1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/ktime.h> 29 #include <linux/module.h> 30 #include <linux/pagemap.h> 31 #include <linux/pci.h> 32 #include <linux/dma-buf.h> 33 34 #include <drm/amdgpu_drm.h> 35 #include <drm/drm_drv.h> 36 #include <drm/drm_exec.h> 37 #include <drm/drm_gem_ttm_helper.h> 38 #include <drm/ttm/ttm_tt.h> 39 #include <drm/drm_syncobj.h> 40 41 #include "amdgpu.h" 42 #include "amdgpu_display.h" 43 #include "amdgpu_dma_buf.h" 44 #include "amdgpu_hmm.h" 45 #include "amdgpu_xgmi.h" 46 #include "amdgpu_vm.h" 47 48 static int 49 amdgpu_gem_add_input_fence(struct drm_file *filp, 50 uint64_t syncobj_handles_array, 51 uint32_t num_syncobj_handles) 52 { 53 struct dma_fence *fence; 54 uint32_t *syncobj_handles; 55 int ret, i; 56 57 if (!num_syncobj_handles) 58 return 0; 59 60 syncobj_handles = memdup_user(u64_to_user_ptr(syncobj_handles_array), 61 size_mul(sizeof(uint32_t), num_syncobj_handles)); 62 if (IS_ERR(syncobj_handles)) 63 return PTR_ERR(syncobj_handles); 64 65 for (i = 0; i < num_syncobj_handles; i++) { 66 67 if (!syncobj_handles[i]) { 68 ret = -EINVAL; 69 goto free_memdup; 70 } 71 72 ret = drm_syncobj_find_fence(filp, syncobj_handles[i], 0, 0, &fence); 73 if (ret) 74 goto free_memdup; 75 76 dma_fence_wait(fence, false); 77 78 /* TODO: optimize async handling */ 79 dma_fence_put(fence); 80 } 81 82 free_memdup: 83 kfree(syncobj_handles); 84 return ret; 85 } 86 87 static int 88 amdgpu_gem_update_timeline_node(struct drm_file *filp, 89 uint32_t syncobj_handle, 90 uint64_t point, 91 struct drm_syncobj **syncobj, 92 struct dma_fence_chain **chain) 93 { 94 if (!syncobj_handle) 95 return 0; 96 97 /* Find the sync object */ 98 *syncobj = drm_syncobj_find(filp, syncobj_handle); 99 if (!*syncobj) 100 return -ENOENT; 101 102 if (!point) 103 return 0; 104 105 /* Allocate the chain node */ 106 *chain = dma_fence_chain_alloc(); 107 if (!*chain) { 108 drm_syncobj_put(*syncobj); 109 return -ENOMEM; 110 } 111 112 return 0; 113 } 114 115 static void 116 amdgpu_gem_update_bo_mapping(struct drm_file *filp, 117 struct amdgpu_bo_va *bo_va, 118 uint32_t operation, 119 uint64_t point, 120 struct dma_fence *fence, 121 struct drm_syncobj *syncobj, 122 struct dma_fence_chain *chain) 123 { 124 struct amdgpu_bo *bo = bo_va ? bo_va->base.bo : NULL; 125 struct amdgpu_fpriv *fpriv = filp->driver_priv; 126 struct amdgpu_vm *vm = &fpriv->vm; 127 struct dma_fence *last_update; 128 129 if (!syncobj) 130 return; 131 132 /* Find the last update fence */ 133 switch (operation) { 134 case AMDGPU_VA_OP_MAP: 135 case AMDGPU_VA_OP_REPLACE: 136 if (bo && (bo->tbo.base.resv == vm->root.bo->tbo.base.resv)) 137 last_update = vm->last_update; 138 else 139 last_update = bo_va->last_pt_update; 140 break; 141 case AMDGPU_VA_OP_UNMAP: 142 case AMDGPU_VA_OP_CLEAR: 143 last_update = fence; 144 break; 145 default: 146 return; 147 } 148 149 /* Add fence to timeline */ 150 if (!point) 151 drm_syncobj_replace_fence(syncobj, last_update); 152 else 153 drm_syncobj_add_point(syncobj, chain, last_update, point); 154 } 155 156 static vm_fault_t amdgpu_gem_fault(struct vm_fault *vmf) 157 { 158 struct ttm_buffer_object *bo = vmf->vma->vm_private_data; 159 struct drm_device *ddev = bo->base.dev; 160 vm_fault_t ret; 161 int idx; 162 163 ret = ttm_bo_vm_reserve(bo, vmf); 164 if (ret) 165 return ret; 166 167 if (drm_dev_enter(ddev, &idx)) { 168 ret = amdgpu_bo_fault_reserve_notify(bo); 169 if (ret) { 170 drm_dev_exit(idx); 171 goto unlock; 172 } 173 174 ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot, 175 TTM_BO_VM_NUM_PREFAULT); 176 177 drm_dev_exit(idx); 178 } else { 179 ret = ttm_bo_vm_dummy_page(vmf, vmf->vma->vm_page_prot); 180 } 181 if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT)) 182 return ret; 183 184 unlock: 185 dma_resv_unlock(bo->base.resv); 186 return ret; 187 } 188 189 static const struct vm_operations_struct amdgpu_gem_vm_ops = { 190 .fault = amdgpu_gem_fault, 191 .open = ttm_bo_vm_open, 192 .close = ttm_bo_vm_close, 193 .access = ttm_bo_vm_access 194 }; 195 196 static void amdgpu_gem_object_free(struct drm_gem_object *gobj) 197 { 198 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(gobj); 199 200 amdgpu_hmm_unregister(aobj); 201 ttm_bo_put(&aobj->tbo); 202 } 203 204 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 205 int alignment, u32 initial_domain, 206 u64 flags, enum ttm_bo_type type, 207 struct dma_resv *resv, 208 struct drm_gem_object **obj, int8_t xcp_id_plus1) 209 { 210 struct amdgpu_bo *bo; 211 struct amdgpu_bo_user *ubo; 212 struct amdgpu_bo_param bp; 213 int r; 214 215 memset(&bp, 0, sizeof(bp)); 216 *obj = NULL; 217 flags |= AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE; 218 219 bp.size = size; 220 bp.byte_align = alignment; 221 bp.type = type; 222 bp.resv = resv; 223 bp.preferred_domain = initial_domain; 224 bp.flags = flags; 225 bp.domain = initial_domain; 226 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 227 bp.xcp_id_plus1 = xcp_id_plus1; 228 229 r = amdgpu_bo_create_user(adev, &bp, &ubo); 230 if (r) 231 return r; 232 233 bo = &ubo->bo; 234 *obj = &bo->tbo.base; 235 236 return 0; 237 } 238 239 void amdgpu_gem_force_release(struct amdgpu_device *adev) 240 { 241 struct drm_device *ddev = adev_to_drm(adev); 242 struct drm_file *file; 243 244 mutex_lock(&ddev->filelist_mutex); 245 246 list_for_each_entry(file, &ddev->filelist, lhead) { 247 struct drm_gem_object *gobj; 248 int handle; 249 250 WARN_ONCE(1, "Still active user space clients!\n"); 251 spin_lock(&file->table_lock); 252 idr_for_each_entry(&file->object_idr, gobj, handle) { 253 WARN_ONCE(1, "And also active allocations!\n"); 254 drm_gem_object_put(gobj); 255 } 256 idr_destroy(&file->object_idr); 257 spin_unlock(&file->table_lock); 258 } 259 260 mutex_unlock(&ddev->filelist_mutex); 261 } 262 263 /* 264 * Call from drm_gem_handle_create which appear in both new and open ioctl 265 * case. 266 */ 267 static int amdgpu_gem_object_open(struct drm_gem_object *obj, 268 struct drm_file *file_priv) 269 { 270 struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj); 271 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 272 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 273 struct amdgpu_vm *vm = &fpriv->vm; 274 struct amdgpu_bo_va *bo_va; 275 struct mm_struct *mm; 276 int r; 277 278 mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm); 279 if (mm && mm != current->mm) 280 return -EPERM; 281 282 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID && 283 !amdgpu_vm_is_bo_always_valid(vm, abo)) 284 return -EPERM; 285 286 r = amdgpu_bo_reserve(abo, false); 287 if (r) 288 return r; 289 290 amdgpu_vm_bo_update_shared(abo); 291 bo_va = amdgpu_vm_bo_find(vm, abo); 292 if (!bo_va) 293 bo_va = amdgpu_vm_bo_add(adev, vm, abo); 294 else 295 ++bo_va->ref_count; 296 297 /* attach gfx eviction fence */ 298 r = amdgpu_eviction_fence_attach(&fpriv->evf_mgr, abo); 299 if (r) { 300 DRM_DEBUG_DRIVER("Failed to attach eviction fence to BO\n"); 301 amdgpu_bo_unreserve(abo); 302 return r; 303 } 304 305 amdgpu_bo_unreserve(abo); 306 307 /* Validate and add eviction fence to DMABuf imports with dynamic 308 * attachment in compute VMs. Re-validation will be done by 309 * amdgpu_vm_validate. Fences are on the reservation shared with the 310 * export, which is currently required to be validated and fenced 311 * already by amdgpu_amdkfd_gpuvm_restore_process_bos. 312 * 313 * Nested locking below for the case that a GEM object is opened in 314 * kfd_mem_export_dmabuf. Since the lock below is only taken for imports, 315 * but not for export, this is a different lock class that cannot lead to 316 * circular lock dependencies. 317 */ 318 if (!vm->is_compute_context || !vm->process_info) 319 return 0; 320 if (!drm_gem_is_imported(obj) || 321 !dma_buf_is_dynamic(obj->import_attach->dmabuf)) 322 return 0; 323 mutex_lock_nested(&vm->process_info->lock, 1); 324 if (!WARN_ON(!vm->process_info->eviction_fence)) { 325 r = amdgpu_amdkfd_bo_validate_and_fence(abo, AMDGPU_GEM_DOMAIN_GTT, 326 &vm->process_info->eviction_fence->base); 327 if (r) { 328 struct amdgpu_task_info *ti = amdgpu_vm_get_task_info_vm(vm); 329 330 dev_warn(adev->dev, "validate_and_fence failed: %d\n", r); 331 if (ti) { 332 dev_warn(adev->dev, "pid %d\n", ti->task.pid); 333 amdgpu_vm_put_task_info(ti); 334 } 335 } 336 } 337 mutex_unlock(&vm->process_info->lock); 338 339 return r; 340 } 341 342 static void amdgpu_gem_object_close(struct drm_gem_object *obj, 343 struct drm_file *file_priv) 344 { 345 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); 346 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 347 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 348 struct amdgpu_vm *vm = &fpriv->vm; 349 350 struct dma_fence *fence = NULL; 351 struct amdgpu_bo_va *bo_va; 352 struct drm_exec exec; 353 long r; 354 355 drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 0); 356 drm_exec_until_all_locked(&exec) { 357 r = drm_exec_prepare_obj(&exec, &bo->tbo.base, 1); 358 drm_exec_retry_on_contention(&exec); 359 if (unlikely(r)) 360 goto out_unlock; 361 362 r = amdgpu_vm_lock_pd(vm, &exec, 0); 363 drm_exec_retry_on_contention(&exec); 364 if (unlikely(r)) 365 goto out_unlock; 366 } 367 368 if (!amdgpu_vm_is_bo_always_valid(vm, bo)) 369 amdgpu_eviction_fence_detach(&fpriv->evf_mgr, bo); 370 371 bo_va = amdgpu_vm_bo_find(vm, bo); 372 if (!bo_va || --bo_va->ref_count) 373 goto out_unlock; 374 375 amdgpu_vm_bo_del(adev, bo_va); 376 amdgpu_vm_bo_update_shared(bo); 377 if (!amdgpu_vm_ready(vm)) 378 goto out_unlock; 379 380 r = amdgpu_vm_clear_freed(adev, vm, &fence); 381 if (unlikely(r < 0)) 382 dev_err(adev->dev, "failed to clear page " 383 "tables on GEM object close (%ld)\n", r); 384 if (r || !fence) 385 goto out_unlock; 386 387 amdgpu_bo_fence(bo, fence, true); 388 dma_fence_put(fence); 389 390 out_unlock: 391 if (r) 392 dev_err(adev->dev, "leaking bo va (%ld)\n", r); 393 drm_exec_fini(&exec); 394 } 395 396 static int amdgpu_gem_object_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma) 397 { 398 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); 399 400 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) 401 return -EPERM; 402 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) 403 return -EPERM; 404 405 /* Workaround for Thunk bug creating PROT_NONE,MAP_PRIVATE mappings 406 * for debugger access to invisible VRAM. Should have used MAP_SHARED 407 * instead. Clearing VM_MAYWRITE prevents the mapping from ever 408 * becoming writable and makes is_cow_mapping(vm_flags) false. 409 */ 410 if (is_cow_mapping(vma->vm_flags) && 411 !(vma->vm_flags & VM_ACCESS_FLAGS)) 412 vm_flags_clear(vma, VM_MAYWRITE); 413 414 return drm_gem_ttm_mmap(obj, vma); 415 } 416 417 const struct drm_gem_object_funcs amdgpu_gem_object_funcs = { 418 .free = amdgpu_gem_object_free, 419 .open = amdgpu_gem_object_open, 420 .close = amdgpu_gem_object_close, 421 .export = amdgpu_gem_prime_export, 422 .vmap = drm_gem_ttm_vmap, 423 .vunmap = drm_gem_ttm_vunmap, 424 .mmap = amdgpu_gem_object_mmap, 425 .vm_ops = &amdgpu_gem_vm_ops, 426 }; 427 428 /* 429 * GEM ioctls. 430 */ 431 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 432 struct drm_file *filp) 433 { 434 struct amdgpu_device *adev = drm_to_adev(dev); 435 struct amdgpu_fpriv *fpriv = filp->driver_priv; 436 struct amdgpu_vm *vm = &fpriv->vm; 437 union drm_amdgpu_gem_create *args = data; 438 uint64_t flags = args->in.domain_flags; 439 uint64_t size = args->in.bo_size; 440 struct dma_resv *resv = NULL; 441 struct drm_gem_object *gobj; 442 uint32_t handle, initial_domain; 443 int r; 444 445 /* reject invalid gem flags */ 446 if (flags & ~AMDGPU_GEM_CREATE_SETTABLE_MASK) 447 return -EINVAL; 448 449 /* reject invalid gem domains */ 450 if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK) 451 return -EINVAL; 452 453 if (!amdgpu_is_tmz(adev) && (flags & AMDGPU_GEM_CREATE_ENCRYPTED)) { 454 DRM_NOTE_ONCE("Cannot allocate secure buffer since TMZ is disabled\n"); 455 return -EINVAL; 456 } 457 458 /* always clear VRAM */ 459 flags |= AMDGPU_GEM_CREATE_VRAM_CLEARED; 460 461 if (args->in.domains & AMDGPU_GEM_DOMAIN_MMIO_REMAP) 462 return -EINVAL; 463 464 /* create a gem object to contain this object in */ 465 if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS | 466 AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { 467 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 468 /* if gds bo is created from user space, it must be 469 * passed to bo list 470 */ 471 DRM_ERROR("GDS bo cannot be per-vm-bo\n"); 472 return -EINVAL; 473 } 474 flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 475 } 476 477 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 478 r = amdgpu_bo_reserve(vm->root.bo, false); 479 if (r) 480 return r; 481 482 resv = vm->root.bo->tbo.base.resv; 483 } 484 485 initial_domain = (u32)(0xffffffff & args->in.domains); 486 retry: 487 r = amdgpu_gem_object_create(adev, size, args->in.alignment, 488 initial_domain, 489 flags, ttm_bo_type_device, resv, &gobj, fpriv->xcp_id + 1); 490 if (r && r != -ERESTARTSYS) { 491 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) { 492 flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 493 goto retry; 494 } 495 496 if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) { 497 initial_domain |= AMDGPU_GEM_DOMAIN_GTT; 498 goto retry; 499 } 500 DRM_DEBUG("Failed to allocate GEM object (%llu, %d, %llu, %d)\n", 501 size, initial_domain, args->in.alignment, r); 502 } 503 504 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 505 if (!r) { 506 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj); 507 508 abo->parent = amdgpu_bo_ref(vm->root.bo); 509 } 510 amdgpu_bo_unreserve(vm->root.bo); 511 } 512 if (r) 513 return r; 514 515 r = drm_gem_handle_create(filp, gobj, &handle); 516 /* drop reference from allocate - handle holds it now */ 517 drm_gem_object_put(gobj); 518 if (r) 519 return r; 520 521 memset(args, 0, sizeof(*args)); 522 args->out.handle = handle; 523 return 0; 524 } 525 526 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 527 struct drm_file *filp) 528 { 529 struct ttm_operation_ctx ctx = { true, false }; 530 struct amdgpu_device *adev = drm_to_adev(dev); 531 struct drm_amdgpu_gem_userptr *args = data; 532 struct amdgpu_fpriv *fpriv = filp->driver_priv; 533 struct drm_gem_object *gobj; 534 struct hmm_range *range; 535 struct amdgpu_bo *bo; 536 uint32_t handle; 537 int r; 538 539 args->addr = untagged_addr(args->addr); 540 541 if (offset_in_page(args->addr | args->size)) 542 return -EINVAL; 543 544 /* reject unknown flag values */ 545 if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY | 546 AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE | 547 AMDGPU_GEM_USERPTR_REGISTER)) 548 return -EINVAL; 549 550 if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) && 551 !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) { 552 553 /* if we want to write to it we must install a MMU notifier */ 554 return -EACCES; 555 } 556 557 /* create a gem object to contain this object in */ 558 r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU, 559 0, ttm_bo_type_device, NULL, &gobj, fpriv->xcp_id + 1); 560 if (r) 561 return r; 562 563 bo = gem_to_amdgpu_bo(gobj); 564 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; 565 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; 566 r = amdgpu_ttm_tt_set_userptr(&bo->tbo, args->addr, args->flags); 567 if (r) 568 goto release_object; 569 570 r = amdgpu_hmm_register(bo, args->addr); 571 if (r) 572 goto release_object; 573 574 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) { 575 r = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages, 576 &range); 577 if (r) 578 goto release_object; 579 580 r = amdgpu_bo_reserve(bo, true); 581 if (r) 582 goto user_pages_done; 583 584 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); 585 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 586 amdgpu_bo_unreserve(bo); 587 if (r) 588 goto user_pages_done; 589 } 590 591 r = drm_gem_handle_create(filp, gobj, &handle); 592 if (r) 593 goto user_pages_done; 594 595 args->handle = handle; 596 597 user_pages_done: 598 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) 599 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, range); 600 601 release_object: 602 drm_gem_object_put(gobj); 603 604 return r; 605 } 606 607 int amdgpu_mode_dumb_mmap(struct drm_file *filp, 608 struct drm_device *dev, 609 uint32_t handle, uint64_t *offset_p) 610 { 611 struct drm_gem_object *gobj; 612 struct amdgpu_bo *robj; 613 614 gobj = drm_gem_object_lookup(filp, handle); 615 if (!gobj) 616 return -ENOENT; 617 618 robj = gem_to_amdgpu_bo(gobj); 619 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) || 620 (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) { 621 drm_gem_object_put(gobj); 622 return -EPERM; 623 } 624 *offset_p = amdgpu_bo_mmap_offset(robj); 625 drm_gem_object_put(gobj); 626 return 0; 627 } 628 629 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 630 struct drm_file *filp) 631 { 632 union drm_amdgpu_gem_mmap *args = data; 633 uint32_t handle = args->in.handle; 634 635 memset(args, 0, sizeof(*args)); 636 return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr); 637 } 638 639 /** 640 * amdgpu_gem_timeout - calculate jiffies timeout from absolute value 641 * 642 * @timeout_ns: timeout in ns 643 * 644 * Calculate the timeout in jiffies from an absolute timeout in ns. 645 */ 646 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns) 647 { 648 unsigned long timeout_jiffies; 649 ktime_t timeout; 650 651 /* clamp timeout if it's to large */ 652 if (((int64_t)timeout_ns) < 0) 653 return MAX_SCHEDULE_TIMEOUT; 654 655 timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get()); 656 if (ktime_to_ns(timeout) < 0) 657 return 0; 658 659 timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout)); 660 /* clamp timeout to avoid unsigned-> signed overflow */ 661 if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT) 662 return MAX_SCHEDULE_TIMEOUT - 1; 663 664 return timeout_jiffies; 665 } 666 667 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 668 struct drm_file *filp) 669 { 670 union drm_amdgpu_gem_wait_idle *args = data; 671 struct drm_gem_object *gobj; 672 struct amdgpu_bo *robj; 673 uint32_t handle = args->in.handle; 674 unsigned long timeout = amdgpu_gem_timeout(args->in.timeout); 675 int r = 0; 676 long ret; 677 678 gobj = drm_gem_object_lookup(filp, handle); 679 if (!gobj) 680 return -ENOENT; 681 682 robj = gem_to_amdgpu_bo(gobj); 683 ret = dma_resv_wait_timeout(robj->tbo.base.resv, DMA_RESV_USAGE_READ, 684 true, timeout); 685 686 /* ret == 0 means not signaled, 687 * ret > 0 means signaled 688 * ret < 0 means interrupted before timeout 689 */ 690 if (ret >= 0) { 691 memset(args, 0, sizeof(*args)); 692 args->out.status = (ret == 0); 693 } else 694 r = ret; 695 696 drm_gem_object_put(gobj); 697 return r; 698 } 699 700 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 701 struct drm_file *filp) 702 { 703 struct drm_amdgpu_gem_metadata *args = data; 704 struct drm_gem_object *gobj; 705 struct amdgpu_bo *robj; 706 int r = -1; 707 708 DRM_DEBUG("%d\n", args->handle); 709 gobj = drm_gem_object_lookup(filp, args->handle); 710 if (gobj == NULL) 711 return -ENOENT; 712 robj = gem_to_amdgpu_bo(gobj); 713 714 r = amdgpu_bo_reserve(robj, false); 715 if (unlikely(r != 0)) 716 goto out; 717 718 if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) { 719 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info); 720 r = amdgpu_bo_get_metadata(robj, args->data.data, 721 sizeof(args->data.data), 722 &args->data.data_size_bytes, 723 &args->data.flags); 724 } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) { 725 if (args->data.data_size_bytes > sizeof(args->data.data)) { 726 r = -EINVAL; 727 goto unreserve; 728 } 729 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info); 730 if (!r) 731 r = amdgpu_bo_set_metadata(robj, args->data.data, 732 args->data.data_size_bytes, 733 args->data.flags); 734 } 735 736 unreserve: 737 amdgpu_bo_unreserve(robj); 738 out: 739 drm_gem_object_put(gobj); 740 return r; 741 } 742 743 /** 744 * amdgpu_gem_va_update_vm -update the bo_va in its VM 745 * 746 * @adev: amdgpu_device pointer 747 * @vm: vm to update 748 * @bo_va: bo_va to update 749 * @operation: map, unmap or clear 750 * 751 * Update the bo_va directly after setting its address. Errors are not 752 * vital here, so they are not reported back to userspace. 753 * 754 * Returns resulting fence if freed BO(s) got cleared from the PT. 755 * otherwise stub fence in case of error. 756 */ 757 static struct dma_fence * 758 amdgpu_gem_va_update_vm(struct amdgpu_device *adev, 759 struct amdgpu_vm *vm, 760 struct amdgpu_bo_va *bo_va, 761 uint32_t operation) 762 { 763 struct dma_fence *fence = dma_fence_get_stub(); 764 int r; 765 766 if (!amdgpu_vm_ready(vm)) 767 return fence; 768 769 r = amdgpu_vm_clear_freed(adev, vm, &fence); 770 if (r) 771 goto error; 772 773 if (operation == AMDGPU_VA_OP_MAP || 774 operation == AMDGPU_VA_OP_REPLACE) { 775 r = amdgpu_vm_bo_update(adev, bo_va, false); 776 if (r) 777 goto error; 778 } 779 780 r = amdgpu_vm_update_pdes(adev, vm, false); 781 782 error: 783 if (r && r != -ERESTARTSYS) 784 DRM_ERROR("Couldn't update BO_VA (%d)\n", r); 785 786 return fence; 787 } 788 789 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 790 struct drm_file *filp) 791 { 792 const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE | 793 AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE | 794 AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK | 795 AMDGPU_VM_PAGE_NOALLOC; 796 const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE | 797 AMDGPU_VM_PAGE_PRT; 798 799 struct drm_amdgpu_gem_va *args = data; 800 struct drm_gem_object *gobj; 801 struct amdgpu_device *adev = drm_to_adev(dev); 802 struct amdgpu_fpriv *fpriv = filp->driver_priv; 803 struct amdgpu_bo *abo; 804 struct amdgpu_bo_va *bo_va; 805 struct drm_syncobj *timeline_syncobj = NULL; 806 struct dma_fence_chain *timeline_chain = NULL; 807 struct dma_fence *fence; 808 struct drm_exec exec; 809 uint64_t vm_size; 810 int r = 0; 811 812 if (args->va_address < AMDGPU_VA_RESERVED_BOTTOM) { 813 dev_dbg(dev->dev, 814 "va_address 0x%llx is in reserved area 0x%llx\n", 815 args->va_address, AMDGPU_VA_RESERVED_BOTTOM); 816 return -EINVAL; 817 } 818 819 if (args->va_address >= AMDGPU_GMC_HOLE_START && 820 args->va_address < AMDGPU_GMC_HOLE_END) { 821 dev_dbg(dev->dev, 822 "va_address 0x%llx is in VA hole 0x%llx-0x%llx\n", 823 args->va_address, AMDGPU_GMC_HOLE_START, 824 AMDGPU_GMC_HOLE_END); 825 return -EINVAL; 826 } 827 828 args->va_address &= AMDGPU_GMC_HOLE_MASK; 829 830 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 831 vm_size -= AMDGPU_VA_RESERVED_TOP; 832 if (args->va_address + args->map_size > vm_size) { 833 dev_dbg(dev->dev, 834 "va_address 0x%llx is in top reserved area 0x%llx\n", 835 args->va_address + args->map_size, vm_size); 836 return -EINVAL; 837 } 838 839 if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) { 840 dev_dbg(dev->dev, "invalid flags combination 0x%08X\n", 841 args->flags); 842 return -EINVAL; 843 } 844 845 switch (args->operation) { 846 case AMDGPU_VA_OP_MAP: 847 case AMDGPU_VA_OP_UNMAP: 848 case AMDGPU_VA_OP_CLEAR: 849 case AMDGPU_VA_OP_REPLACE: 850 break; 851 default: 852 dev_dbg(dev->dev, "unsupported operation %d\n", 853 args->operation); 854 return -EINVAL; 855 } 856 857 if ((args->operation != AMDGPU_VA_OP_CLEAR) && 858 !(args->flags & AMDGPU_VM_PAGE_PRT)) { 859 gobj = drm_gem_object_lookup(filp, args->handle); 860 if (gobj == NULL) 861 return -ENOENT; 862 abo = gem_to_amdgpu_bo(gobj); 863 } else { 864 gobj = NULL; 865 abo = NULL; 866 } 867 868 r = amdgpu_gem_add_input_fence(filp, 869 args->input_fence_syncobj_handles, 870 args->num_syncobj_handles); 871 if (r) 872 goto error_put_gobj; 873 874 drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT | 875 DRM_EXEC_IGNORE_DUPLICATES, 0); 876 drm_exec_until_all_locked(&exec) { 877 if (gobj) { 878 r = drm_exec_lock_obj(&exec, gobj); 879 drm_exec_retry_on_contention(&exec); 880 if (unlikely(r)) 881 goto error; 882 } 883 884 r = amdgpu_vm_lock_pd(&fpriv->vm, &exec, 2); 885 drm_exec_retry_on_contention(&exec); 886 if (unlikely(r)) 887 goto error; 888 } 889 890 if (abo) { 891 bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo); 892 if (!bo_va) { 893 r = -ENOENT; 894 goto error; 895 } 896 } else if (args->operation != AMDGPU_VA_OP_CLEAR) { 897 bo_va = fpriv->prt_va; 898 } else { 899 bo_va = NULL; 900 } 901 902 r = amdgpu_gem_update_timeline_node(filp, 903 args->vm_timeline_syncobj_out, 904 args->vm_timeline_point, 905 &timeline_syncobj, 906 &timeline_chain); 907 if (r) 908 goto error; 909 910 switch (args->operation) { 911 case AMDGPU_VA_OP_MAP: 912 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address, 913 args->offset_in_bo, args->map_size, 914 args->flags); 915 break; 916 case AMDGPU_VA_OP_UNMAP: 917 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address); 918 break; 919 920 case AMDGPU_VA_OP_CLEAR: 921 r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm, 922 args->va_address, 923 args->map_size); 924 break; 925 case AMDGPU_VA_OP_REPLACE: 926 r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address, 927 args->offset_in_bo, args->map_size, 928 args->flags); 929 break; 930 default: 931 break; 932 } 933 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !adev->debug_vm) { 934 fence = amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va, 935 args->operation); 936 937 if (timeline_syncobj) 938 amdgpu_gem_update_bo_mapping(filp, bo_va, 939 args->operation, 940 args->vm_timeline_point, 941 fence, timeline_syncobj, 942 timeline_chain); 943 else 944 dma_fence_put(fence); 945 946 } 947 948 error: 949 drm_exec_fini(&exec); 950 error_put_gobj: 951 drm_gem_object_put(gobj); 952 return r; 953 } 954 955 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 956 struct drm_file *filp) 957 { 958 struct drm_amdgpu_gem_op *args = data; 959 struct drm_gem_object *gobj; 960 struct amdgpu_vm_bo_base *base; 961 struct amdgpu_bo *robj; 962 struct drm_exec exec; 963 struct amdgpu_fpriv *fpriv = filp->driver_priv; 964 int r; 965 966 if (args->padding) 967 return -EINVAL; 968 969 gobj = drm_gem_object_lookup(filp, args->handle); 970 if (!gobj) 971 return -ENOENT; 972 973 robj = gem_to_amdgpu_bo(gobj); 974 975 drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT | 976 DRM_EXEC_IGNORE_DUPLICATES, 0); 977 drm_exec_until_all_locked(&exec) { 978 r = drm_exec_lock_obj(&exec, gobj); 979 drm_exec_retry_on_contention(&exec); 980 if (r) 981 goto out_exec; 982 983 if (args->op == AMDGPU_GEM_OP_GET_MAPPING_INFO) { 984 r = amdgpu_vm_lock_pd(&fpriv->vm, &exec, 0); 985 drm_exec_retry_on_contention(&exec); 986 if (r) 987 goto out_exec; 988 } 989 } 990 991 switch (args->op) { 992 case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: { 993 struct drm_amdgpu_gem_create_in info; 994 void __user *out = u64_to_user_ptr(args->value); 995 996 info.bo_size = robj->tbo.base.size; 997 info.alignment = robj->tbo.page_alignment << PAGE_SHIFT; 998 info.domains = robj->preferred_domains; 999 info.domain_flags = robj->flags; 1000 drm_exec_fini(&exec); 1001 if (copy_to_user(out, &info, sizeof(info))) 1002 r = -EFAULT; 1003 break; 1004 } 1005 case AMDGPU_GEM_OP_SET_PLACEMENT: 1006 if (drm_gem_is_imported(&robj->tbo.base) && 1007 args->value & AMDGPU_GEM_DOMAIN_VRAM) { 1008 r = -EINVAL; 1009 goto out_exec; 1010 } 1011 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) { 1012 r = -EPERM; 1013 goto out_exec; 1014 } 1015 for (base = robj->vm_bo; base; base = base->next) 1016 if (amdgpu_xgmi_same_hive(amdgpu_ttm_adev(robj->tbo.bdev), 1017 amdgpu_ttm_adev(base->vm->root.bo->tbo.bdev))) { 1018 r = -EINVAL; 1019 goto out_exec; 1020 } 1021 1022 1023 robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM | 1024 AMDGPU_GEM_DOMAIN_GTT | 1025 AMDGPU_GEM_DOMAIN_CPU); 1026 robj->allowed_domains = robj->preferred_domains; 1027 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 1028 robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 1029 1030 if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) 1031 amdgpu_vm_bo_invalidate(robj, true); 1032 drm_exec_fini(&exec); 1033 break; 1034 case AMDGPU_GEM_OP_GET_MAPPING_INFO: { 1035 struct amdgpu_bo_va *bo_va = amdgpu_vm_bo_find(&fpriv->vm, robj); 1036 struct drm_amdgpu_gem_vm_entry *vm_entries; 1037 struct amdgpu_bo_va_mapping *mapping; 1038 int num_mappings = 0; 1039 /* 1040 * num_entries is set as an input to the size of the user-allocated array of 1041 * drm_amdgpu_gem_vm_entry stored at args->value. 1042 * num_entries is sent back as output as the number of mappings the bo has. 1043 * If that number is larger than the size of the array, the ioctl must 1044 * be retried. 1045 */ 1046 vm_entries = kvcalloc(args->num_entries, sizeof(*vm_entries), GFP_KERNEL); 1047 if (!vm_entries) 1048 return -ENOMEM; 1049 1050 amdgpu_vm_bo_va_for_each_valid_mapping(bo_va, mapping) { 1051 if (num_mappings < args->num_entries) { 1052 vm_entries[num_mappings].addr = mapping->start * AMDGPU_GPU_PAGE_SIZE; 1053 vm_entries[num_mappings].size = (mapping->last - mapping->start + 1) * AMDGPU_GPU_PAGE_SIZE; 1054 vm_entries[num_mappings].offset = mapping->offset; 1055 vm_entries[num_mappings].flags = mapping->flags; 1056 } 1057 num_mappings += 1; 1058 } 1059 1060 amdgpu_vm_bo_va_for_each_invalid_mapping(bo_va, mapping) { 1061 if (num_mappings < args->num_entries) { 1062 vm_entries[num_mappings].addr = mapping->start * AMDGPU_GPU_PAGE_SIZE; 1063 vm_entries[num_mappings].size = (mapping->last - mapping->start + 1) * AMDGPU_GPU_PAGE_SIZE; 1064 vm_entries[num_mappings].offset = mapping->offset; 1065 vm_entries[num_mappings].flags = mapping->flags; 1066 } 1067 num_mappings += 1; 1068 } 1069 1070 drm_exec_fini(&exec); 1071 1072 if (num_mappings > 0 && num_mappings <= args->num_entries) 1073 if (copy_to_user(u64_to_user_ptr(args->value), vm_entries, num_mappings * sizeof(*vm_entries))) 1074 r = -EFAULT; 1075 1076 args->num_entries = num_mappings; 1077 1078 kvfree(vm_entries); 1079 break; 1080 } 1081 default: 1082 drm_exec_fini(&exec); 1083 r = -EINVAL; 1084 } 1085 1086 drm_gem_object_put(gobj); 1087 return r; 1088 out_exec: 1089 drm_exec_fini(&exec); 1090 drm_gem_object_put(gobj); 1091 return r; 1092 } 1093 1094 /** 1095 * amdgpu_gem_list_handles_ioctl - get information about a process' buffer objects 1096 * 1097 * @dev: drm device pointer 1098 * @data: drm_amdgpu_gem_list_handles 1099 * @filp: drm file pointer 1100 * 1101 * num_entries is set as an input to the size of the entries array. 1102 * num_entries is sent back as output as the number of bos in the process. 1103 * If that number is larger than the size of the array, the ioctl must 1104 * be retried. 1105 * 1106 * Returns: 1107 * 0 for success, -errno for errors. 1108 */ 1109 int amdgpu_gem_list_handles_ioctl(struct drm_device *dev, void *data, 1110 struct drm_file *filp) 1111 { 1112 struct drm_amdgpu_gem_list_handles *args = data; 1113 struct drm_amdgpu_gem_list_handles_entry *bo_entries; 1114 struct drm_gem_object *gobj; 1115 int id, ret = 0; 1116 int bo_index = 0; 1117 int num_bos = 0; 1118 1119 spin_lock(&filp->table_lock); 1120 idr_for_each_entry(&filp->object_idr, gobj, id) 1121 num_bos += 1; 1122 spin_unlock(&filp->table_lock); 1123 1124 if (args->num_entries < num_bos) { 1125 args->num_entries = num_bos; 1126 return 0; 1127 } 1128 1129 if (num_bos == 0) { 1130 args->num_entries = 0; 1131 return 0; 1132 } 1133 1134 bo_entries = kvcalloc(num_bos, sizeof(*bo_entries), GFP_KERNEL); 1135 if (!bo_entries) 1136 return -ENOMEM; 1137 1138 spin_lock(&filp->table_lock); 1139 idr_for_each_entry(&filp->object_idr, gobj, id) { 1140 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj); 1141 struct drm_amdgpu_gem_list_handles_entry *bo_entry; 1142 1143 if (bo_index >= num_bos) { 1144 ret = -EAGAIN; 1145 break; 1146 } 1147 1148 bo_entry = &bo_entries[bo_index]; 1149 1150 bo_entry->size = amdgpu_bo_size(bo); 1151 bo_entry->alloc_flags = bo->flags & AMDGPU_GEM_CREATE_SETTABLE_MASK; 1152 bo_entry->preferred_domains = bo->preferred_domains; 1153 bo_entry->gem_handle = id; 1154 bo_entry->alignment = bo->tbo.page_alignment; 1155 1156 if (bo->tbo.base.import_attach) 1157 bo_entry->flags |= AMDGPU_GEM_LIST_HANDLES_FLAG_IS_IMPORT; 1158 1159 bo_index += 1; 1160 } 1161 spin_unlock(&filp->table_lock); 1162 1163 args->num_entries = bo_index; 1164 1165 if (!ret) 1166 if (copy_to_user(u64_to_user_ptr(args->entries), bo_entries, num_bos * sizeof(*bo_entries))) 1167 ret = -EFAULT; 1168 1169 kvfree(bo_entries); 1170 1171 return ret; 1172 } 1173 1174 static int amdgpu_gem_align_pitch(struct amdgpu_device *adev, 1175 int width, 1176 int cpp, 1177 bool tiled) 1178 { 1179 int aligned = width; 1180 int pitch_mask = 0; 1181 1182 switch (cpp) { 1183 case 1: 1184 pitch_mask = 255; 1185 break; 1186 case 2: 1187 pitch_mask = 127; 1188 break; 1189 case 3: 1190 case 4: 1191 pitch_mask = 63; 1192 break; 1193 } 1194 1195 aligned += pitch_mask; 1196 aligned &= ~pitch_mask; 1197 return aligned * cpp; 1198 } 1199 1200 int amdgpu_mode_dumb_create(struct drm_file *file_priv, 1201 struct drm_device *dev, 1202 struct drm_mode_create_dumb *args) 1203 { 1204 struct amdgpu_device *adev = drm_to_adev(dev); 1205 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1206 struct drm_gem_object *gobj; 1207 uint32_t handle; 1208 u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 1209 AMDGPU_GEM_CREATE_CPU_GTT_USWC | 1210 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 1211 u32 domain; 1212 int r; 1213 1214 /* 1215 * The buffer returned from this function should be cleared, but 1216 * it can only be done if the ring is enabled or we'll fail to 1217 * create the buffer. 1218 */ 1219 if (adev->mman.buffer_funcs_enabled) 1220 flags |= AMDGPU_GEM_CREATE_VRAM_CLEARED; 1221 1222 args->pitch = amdgpu_gem_align_pitch(adev, args->width, 1223 DIV_ROUND_UP(args->bpp, 8), 0); 1224 args->size = (u64)args->pitch * args->height; 1225 args->size = ALIGN(args->size, PAGE_SIZE); 1226 domain = amdgpu_bo_get_preferred_domain(adev, 1227 amdgpu_display_supported_domains(adev, flags)); 1228 r = amdgpu_gem_object_create(adev, args->size, 0, domain, flags, 1229 ttm_bo_type_device, NULL, &gobj, fpriv->xcp_id + 1); 1230 if (r) 1231 return -ENOMEM; 1232 1233 r = drm_gem_handle_create(file_priv, gobj, &handle); 1234 /* drop reference from allocate - handle holds it now */ 1235 drm_gem_object_put(gobj); 1236 if (r) 1237 return r; 1238 1239 args->handle = handle; 1240 return 0; 1241 } 1242 1243 #if defined(CONFIG_DEBUG_FS) 1244 static int amdgpu_debugfs_gem_info_show(struct seq_file *m, void *unused) 1245 { 1246 struct amdgpu_device *adev = m->private; 1247 struct drm_device *dev = adev_to_drm(adev); 1248 struct drm_file *file; 1249 int r; 1250 1251 r = mutex_lock_interruptible(&dev->filelist_mutex); 1252 if (r) 1253 return r; 1254 1255 list_for_each_entry(file, &dev->filelist, lhead) { 1256 struct task_struct *task; 1257 struct drm_gem_object *gobj; 1258 struct pid *pid; 1259 int id; 1260 1261 /* 1262 * Although we have a valid reference on file->pid, that does 1263 * not guarantee that the task_struct who called get_pid() is 1264 * still alive (e.g. get_pid(current) => fork() => exit()). 1265 * Therefore, we need to protect this ->comm access using RCU. 1266 */ 1267 rcu_read_lock(); 1268 pid = rcu_dereference(file->pid); 1269 task = pid_task(pid, PIDTYPE_TGID); 1270 seq_printf(m, "pid %8d command %s:\n", pid_nr(pid), 1271 task ? task->comm : "<unknown>"); 1272 rcu_read_unlock(); 1273 1274 spin_lock(&file->table_lock); 1275 idr_for_each_entry(&file->object_idr, gobj, id) { 1276 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj); 1277 1278 amdgpu_bo_print_info(id, bo, m); 1279 } 1280 spin_unlock(&file->table_lock); 1281 } 1282 1283 mutex_unlock(&dev->filelist_mutex); 1284 return 0; 1285 } 1286 1287 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_gem_info); 1288 1289 #endif 1290 1291 void amdgpu_debugfs_gem_init(struct amdgpu_device *adev) 1292 { 1293 #if defined(CONFIG_DEBUG_FS) 1294 struct drm_minor *minor = adev_to_drm(adev)->primary; 1295 struct dentry *root = minor->debugfs_root; 1296 1297 debugfs_create_file("amdgpu_gem_info", 0444, root, adev, 1298 &amdgpu_debugfs_gem_info_fops); 1299 #endif 1300 } 1301