1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/ktime.h> 29 #include <linux/module.h> 30 #include <linux/pagemap.h> 31 #include <linux/pci.h> 32 #include <linux/dma-buf.h> 33 34 #include <drm/amdgpu_drm.h> 35 #include <drm/drm_drv.h> 36 #include <drm/drm_exec.h> 37 #include <drm/drm_gem_ttm_helper.h> 38 #include <drm/ttm/ttm_tt.h> 39 #include <drm/drm_syncobj.h> 40 41 #include "amdgpu.h" 42 #include "amdgpu_display.h" 43 #include "amdgpu_dma_buf.h" 44 #include "amdgpu_hmm.h" 45 #include "amdgpu_xgmi.h" 46 #include "amdgpu_vm.h" 47 48 static int 49 amdgpu_gem_add_input_fence(struct drm_file *filp, 50 uint64_t syncobj_handles_array, 51 uint32_t num_syncobj_handles) 52 { 53 struct dma_fence *fence; 54 uint32_t *syncobj_handles; 55 int ret, i; 56 57 if (!num_syncobj_handles) 58 return 0; 59 60 syncobj_handles = memdup_user(u64_to_user_ptr(syncobj_handles_array), 61 size_mul(sizeof(uint32_t), num_syncobj_handles)); 62 if (IS_ERR(syncobj_handles)) 63 return PTR_ERR(syncobj_handles); 64 65 for (i = 0; i < num_syncobj_handles; i++) { 66 67 if (!syncobj_handles[i]) { 68 ret = -EINVAL; 69 goto free_memdup; 70 } 71 72 ret = drm_syncobj_find_fence(filp, syncobj_handles[i], 0, 0, &fence); 73 if (ret) 74 goto free_memdup; 75 76 dma_fence_wait(fence, false); 77 78 /* TODO: optimize async handling */ 79 dma_fence_put(fence); 80 } 81 82 free_memdup: 83 kfree(syncobj_handles); 84 return ret; 85 } 86 87 static int 88 amdgpu_gem_update_timeline_node(struct drm_file *filp, 89 uint32_t syncobj_handle, 90 uint64_t point, 91 struct drm_syncobj **syncobj, 92 struct dma_fence_chain **chain) 93 { 94 if (!syncobj_handle) 95 return 0; 96 97 /* Find the sync object */ 98 *syncobj = drm_syncobj_find(filp, syncobj_handle); 99 if (!*syncobj) 100 return -ENOENT; 101 102 if (!point) 103 return 0; 104 105 /* Allocate the chain node */ 106 *chain = dma_fence_chain_alloc(); 107 if (!*chain) { 108 drm_syncobj_put(*syncobj); 109 return -ENOMEM; 110 } 111 112 return 0; 113 } 114 115 static void 116 amdgpu_gem_update_bo_mapping(struct drm_file *filp, 117 struct amdgpu_bo_va *bo_va, 118 uint32_t operation, 119 uint64_t point, 120 struct dma_fence *fence, 121 struct drm_syncobj *syncobj, 122 struct dma_fence_chain *chain) 123 { 124 struct amdgpu_bo *bo = bo_va ? bo_va->base.bo : NULL; 125 struct amdgpu_fpriv *fpriv = filp->driver_priv; 126 struct amdgpu_vm *vm = &fpriv->vm; 127 struct dma_fence *last_update; 128 129 if (!syncobj) 130 return; 131 132 /* Find the last update fence */ 133 switch (operation) { 134 case AMDGPU_VA_OP_MAP: 135 case AMDGPU_VA_OP_REPLACE: 136 if (bo && (bo->tbo.base.resv == vm->root.bo->tbo.base.resv)) 137 last_update = vm->last_update; 138 else 139 last_update = bo_va->last_pt_update; 140 break; 141 case AMDGPU_VA_OP_UNMAP: 142 case AMDGPU_VA_OP_CLEAR: 143 last_update = fence; 144 break; 145 default: 146 return; 147 } 148 149 /* Add fence to timeline */ 150 if (!point) 151 drm_syncobj_replace_fence(syncobj, last_update); 152 else 153 drm_syncobj_add_point(syncobj, chain, last_update, point); 154 } 155 156 static vm_fault_t amdgpu_gem_fault(struct vm_fault *vmf) 157 { 158 struct ttm_buffer_object *bo = vmf->vma->vm_private_data; 159 struct drm_device *ddev = bo->base.dev; 160 vm_fault_t ret; 161 int idx; 162 163 ret = ttm_bo_vm_reserve(bo, vmf); 164 if (ret) 165 return ret; 166 167 if (drm_dev_enter(ddev, &idx)) { 168 ret = amdgpu_bo_fault_reserve_notify(bo); 169 if (ret) { 170 drm_dev_exit(idx); 171 goto unlock; 172 } 173 174 ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot, 175 TTM_BO_VM_NUM_PREFAULT); 176 177 drm_dev_exit(idx); 178 } else { 179 ret = ttm_bo_vm_dummy_page(vmf, vmf->vma->vm_page_prot); 180 } 181 if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT)) 182 return ret; 183 184 unlock: 185 dma_resv_unlock(bo->base.resv); 186 return ret; 187 } 188 189 static const struct vm_operations_struct amdgpu_gem_vm_ops = { 190 .fault = amdgpu_gem_fault, 191 .open = ttm_bo_vm_open, 192 .close = ttm_bo_vm_close, 193 .access = ttm_bo_vm_access 194 }; 195 196 static void amdgpu_gem_object_free(struct drm_gem_object *gobj) 197 { 198 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(gobj); 199 200 amdgpu_hmm_unregister(aobj); 201 ttm_bo_put(&aobj->tbo); 202 } 203 204 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 205 int alignment, u32 initial_domain, 206 u64 flags, enum ttm_bo_type type, 207 struct dma_resv *resv, 208 struct drm_gem_object **obj, int8_t xcp_id_plus1) 209 { 210 struct amdgpu_bo *bo; 211 struct amdgpu_bo_user *ubo; 212 struct amdgpu_bo_param bp; 213 int r; 214 215 memset(&bp, 0, sizeof(bp)); 216 *obj = NULL; 217 flags |= AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE; 218 219 bp.size = size; 220 bp.byte_align = alignment; 221 bp.type = type; 222 bp.resv = resv; 223 bp.preferred_domain = initial_domain; 224 bp.flags = flags; 225 bp.domain = initial_domain; 226 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 227 bp.xcp_id_plus1 = xcp_id_plus1; 228 229 r = amdgpu_bo_create_user(adev, &bp, &ubo); 230 if (r) 231 return r; 232 233 bo = &ubo->bo; 234 *obj = &bo->tbo.base; 235 236 return 0; 237 } 238 239 void amdgpu_gem_force_release(struct amdgpu_device *adev) 240 { 241 struct drm_device *ddev = adev_to_drm(adev); 242 struct drm_file *file; 243 244 mutex_lock(&ddev->filelist_mutex); 245 246 list_for_each_entry(file, &ddev->filelist, lhead) { 247 struct drm_gem_object *gobj; 248 int handle; 249 250 WARN_ONCE(1, "Still active user space clients!\n"); 251 spin_lock(&file->table_lock); 252 idr_for_each_entry(&file->object_idr, gobj, handle) { 253 WARN_ONCE(1, "And also active allocations!\n"); 254 drm_gem_object_put(gobj); 255 } 256 idr_destroy(&file->object_idr); 257 spin_unlock(&file->table_lock); 258 } 259 260 mutex_unlock(&ddev->filelist_mutex); 261 } 262 263 /* 264 * Call from drm_gem_handle_create which appear in both new and open ioctl 265 * case. 266 */ 267 static int amdgpu_gem_object_open(struct drm_gem_object *obj, 268 struct drm_file *file_priv) 269 { 270 struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj); 271 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 272 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 273 struct amdgpu_vm *vm = &fpriv->vm; 274 struct amdgpu_bo_va *bo_va; 275 struct mm_struct *mm; 276 int r; 277 278 mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm); 279 if (mm && mm != current->mm) 280 return -EPERM; 281 282 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID && 283 !amdgpu_vm_is_bo_always_valid(vm, abo)) 284 return -EPERM; 285 286 r = amdgpu_bo_reserve(abo, false); 287 if (r) 288 return r; 289 290 amdgpu_vm_bo_update_shared(abo); 291 bo_va = amdgpu_vm_bo_find(vm, abo); 292 if (!bo_va) 293 bo_va = amdgpu_vm_bo_add(adev, vm, abo); 294 else 295 ++bo_va->ref_count; 296 297 /* attach gfx eviction fence */ 298 r = amdgpu_eviction_fence_attach(&fpriv->evf_mgr, abo); 299 if (r) { 300 DRM_DEBUG_DRIVER("Failed to attach eviction fence to BO\n"); 301 amdgpu_bo_unreserve(abo); 302 return r; 303 } 304 305 amdgpu_bo_unreserve(abo); 306 307 /* Validate and add eviction fence to DMABuf imports with dynamic 308 * attachment in compute VMs. Re-validation will be done by 309 * amdgpu_vm_validate. Fences are on the reservation shared with the 310 * export, which is currently required to be validated and fenced 311 * already by amdgpu_amdkfd_gpuvm_restore_process_bos. 312 * 313 * Nested locking below for the case that a GEM object is opened in 314 * kfd_mem_export_dmabuf. Since the lock below is only taken for imports, 315 * but not for export, this is a different lock class that cannot lead to 316 * circular lock dependencies. 317 */ 318 if (!vm->is_compute_context || !vm->process_info) 319 return 0; 320 if (!drm_gem_is_imported(obj) || !dma_buf_is_dynamic(obj->dma_buf)) 321 return 0; 322 mutex_lock_nested(&vm->process_info->lock, 1); 323 if (!WARN_ON(!vm->process_info->eviction_fence)) { 324 r = amdgpu_amdkfd_bo_validate_and_fence(abo, AMDGPU_GEM_DOMAIN_GTT, 325 &vm->process_info->eviction_fence->base); 326 if (r) { 327 struct amdgpu_task_info *ti = amdgpu_vm_get_task_info_vm(vm); 328 329 dev_warn(adev->dev, "validate_and_fence failed: %d\n", r); 330 if (ti) { 331 dev_warn(adev->dev, "pid %d\n", ti->task.pid); 332 amdgpu_vm_put_task_info(ti); 333 } 334 } 335 } 336 mutex_unlock(&vm->process_info->lock); 337 338 return r; 339 } 340 341 static void amdgpu_gem_object_close(struct drm_gem_object *obj, 342 struct drm_file *file_priv) 343 { 344 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); 345 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 346 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 347 struct amdgpu_vm *vm = &fpriv->vm; 348 349 struct dma_fence *fence = NULL; 350 struct amdgpu_bo_va *bo_va; 351 struct drm_exec exec; 352 long r; 353 354 drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 0); 355 drm_exec_until_all_locked(&exec) { 356 r = drm_exec_prepare_obj(&exec, &bo->tbo.base, 1); 357 drm_exec_retry_on_contention(&exec); 358 if (unlikely(r)) 359 goto out_unlock; 360 361 r = amdgpu_vm_lock_pd(vm, &exec, 0); 362 drm_exec_retry_on_contention(&exec); 363 if (unlikely(r)) 364 goto out_unlock; 365 } 366 367 if (!amdgpu_vm_is_bo_always_valid(vm, bo)) 368 amdgpu_eviction_fence_detach(&fpriv->evf_mgr, bo); 369 370 bo_va = amdgpu_vm_bo_find(vm, bo); 371 if (!bo_va || --bo_va->ref_count) 372 goto out_unlock; 373 374 amdgpu_vm_bo_del(adev, bo_va); 375 amdgpu_vm_bo_update_shared(bo); 376 if (!amdgpu_vm_ready(vm)) 377 goto out_unlock; 378 379 r = amdgpu_vm_clear_freed(adev, vm, &fence); 380 if (unlikely(r < 0)) 381 dev_err(adev->dev, "failed to clear page " 382 "tables on GEM object close (%ld)\n", r); 383 if (r || !fence) 384 goto out_unlock; 385 386 amdgpu_bo_fence(bo, fence, true); 387 dma_fence_put(fence); 388 389 out_unlock: 390 if (r) 391 dev_err(adev->dev, "leaking bo va (%ld)\n", r); 392 drm_exec_fini(&exec); 393 } 394 395 static int amdgpu_gem_object_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma) 396 { 397 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); 398 399 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) 400 return -EPERM; 401 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) 402 return -EPERM; 403 404 /* Workaround for Thunk bug creating PROT_NONE,MAP_PRIVATE mappings 405 * for debugger access to invisible VRAM. Should have used MAP_SHARED 406 * instead. Clearing VM_MAYWRITE prevents the mapping from ever 407 * becoming writable and makes is_cow_mapping(vm_flags) false. 408 */ 409 if (is_cow_mapping(vma->vm_flags) && 410 !(vma->vm_flags & VM_ACCESS_FLAGS)) 411 vm_flags_clear(vma, VM_MAYWRITE); 412 413 return drm_gem_ttm_mmap(obj, vma); 414 } 415 416 const struct drm_gem_object_funcs amdgpu_gem_object_funcs = { 417 .free = amdgpu_gem_object_free, 418 .open = amdgpu_gem_object_open, 419 .close = amdgpu_gem_object_close, 420 .export = amdgpu_gem_prime_export, 421 .vmap = drm_gem_ttm_vmap, 422 .vunmap = drm_gem_ttm_vunmap, 423 .mmap = amdgpu_gem_object_mmap, 424 .vm_ops = &amdgpu_gem_vm_ops, 425 }; 426 427 /* 428 * GEM ioctls. 429 */ 430 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 431 struct drm_file *filp) 432 { 433 struct amdgpu_device *adev = drm_to_adev(dev); 434 struct amdgpu_fpriv *fpriv = filp->driver_priv; 435 struct amdgpu_vm *vm = &fpriv->vm; 436 union drm_amdgpu_gem_create *args = data; 437 uint64_t flags = args->in.domain_flags; 438 uint64_t size = args->in.bo_size; 439 struct dma_resv *resv = NULL; 440 struct drm_gem_object *gobj; 441 uint32_t handle, initial_domain; 442 int r; 443 444 /* reject invalid gem flags */ 445 if (flags & ~AMDGPU_GEM_CREATE_SETTABLE_MASK) 446 return -EINVAL; 447 448 /* reject invalid gem domains */ 449 if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK) 450 return -EINVAL; 451 452 if (!amdgpu_is_tmz(adev) && (flags & AMDGPU_GEM_CREATE_ENCRYPTED)) { 453 DRM_NOTE_ONCE("Cannot allocate secure buffer since TMZ is disabled\n"); 454 return -EINVAL; 455 } 456 457 /* always clear VRAM */ 458 flags |= AMDGPU_GEM_CREATE_VRAM_CLEARED; 459 460 if (args->in.domains & AMDGPU_GEM_DOMAIN_MMIO_REMAP) 461 return -EINVAL; 462 463 /* create a gem object to contain this object in */ 464 if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS | 465 AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { 466 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 467 /* if gds bo is created from user space, it must be 468 * passed to bo list 469 */ 470 DRM_ERROR("GDS bo cannot be per-vm-bo\n"); 471 return -EINVAL; 472 } 473 flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 474 } 475 476 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 477 r = amdgpu_bo_reserve(vm->root.bo, false); 478 if (r) 479 return r; 480 481 resv = vm->root.bo->tbo.base.resv; 482 } 483 484 initial_domain = (u32)(0xffffffff & args->in.domains); 485 retry: 486 r = amdgpu_gem_object_create(adev, size, args->in.alignment, 487 initial_domain, 488 flags, ttm_bo_type_device, resv, &gobj, fpriv->xcp_id + 1); 489 if (r && r != -ERESTARTSYS) { 490 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) { 491 flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 492 goto retry; 493 } 494 495 if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) { 496 initial_domain |= AMDGPU_GEM_DOMAIN_GTT; 497 goto retry; 498 } 499 DRM_DEBUG("Failed to allocate GEM object (%llu, %d, %llu, %d)\n", 500 size, initial_domain, args->in.alignment, r); 501 } 502 503 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 504 if (!r) { 505 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj); 506 507 abo->parent = amdgpu_bo_ref(vm->root.bo); 508 } 509 amdgpu_bo_unreserve(vm->root.bo); 510 } 511 if (r) 512 return r; 513 514 r = drm_gem_handle_create(filp, gobj, &handle); 515 /* drop reference from allocate - handle holds it now */ 516 drm_gem_object_put(gobj); 517 if (r) 518 return r; 519 520 memset(args, 0, sizeof(*args)); 521 args->out.handle = handle; 522 return 0; 523 } 524 525 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 526 struct drm_file *filp) 527 { 528 struct ttm_operation_ctx ctx = { true, false }; 529 struct amdgpu_device *adev = drm_to_adev(dev); 530 struct drm_amdgpu_gem_userptr *args = data; 531 struct amdgpu_fpriv *fpriv = filp->driver_priv; 532 struct drm_gem_object *gobj; 533 struct hmm_range *range; 534 struct amdgpu_bo *bo; 535 uint32_t handle; 536 int r; 537 538 args->addr = untagged_addr(args->addr); 539 540 if (offset_in_page(args->addr | args->size)) 541 return -EINVAL; 542 543 /* reject unknown flag values */ 544 if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY | 545 AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE | 546 AMDGPU_GEM_USERPTR_REGISTER)) 547 return -EINVAL; 548 549 if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) && 550 !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) { 551 552 /* if we want to write to it we must install a MMU notifier */ 553 return -EACCES; 554 } 555 556 /* create a gem object to contain this object in */ 557 r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU, 558 0, ttm_bo_type_device, NULL, &gobj, fpriv->xcp_id + 1); 559 if (r) 560 return r; 561 562 bo = gem_to_amdgpu_bo(gobj); 563 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; 564 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; 565 r = amdgpu_ttm_tt_set_userptr(&bo->tbo, args->addr, args->flags); 566 if (r) 567 goto release_object; 568 569 r = amdgpu_hmm_register(bo, args->addr); 570 if (r) 571 goto release_object; 572 573 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) { 574 r = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages, 575 &range); 576 if (r) 577 goto release_object; 578 579 r = amdgpu_bo_reserve(bo, true); 580 if (r) 581 goto user_pages_done; 582 583 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); 584 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 585 amdgpu_bo_unreserve(bo); 586 if (r) 587 goto user_pages_done; 588 } 589 590 r = drm_gem_handle_create(filp, gobj, &handle); 591 if (r) 592 goto user_pages_done; 593 594 args->handle = handle; 595 596 user_pages_done: 597 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) 598 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, range); 599 600 release_object: 601 drm_gem_object_put(gobj); 602 603 return r; 604 } 605 606 int amdgpu_mode_dumb_mmap(struct drm_file *filp, 607 struct drm_device *dev, 608 uint32_t handle, uint64_t *offset_p) 609 { 610 struct drm_gem_object *gobj; 611 struct amdgpu_bo *robj; 612 613 gobj = drm_gem_object_lookup(filp, handle); 614 if (!gobj) 615 return -ENOENT; 616 617 robj = gem_to_amdgpu_bo(gobj); 618 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) || 619 (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) { 620 drm_gem_object_put(gobj); 621 return -EPERM; 622 } 623 *offset_p = amdgpu_bo_mmap_offset(robj); 624 drm_gem_object_put(gobj); 625 return 0; 626 } 627 628 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 629 struct drm_file *filp) 630 { 631 union drm_amdgpu_gem_mmap *args = data; 632 uint32_t handle = args->in.handle; 633 634 memset(args, 0, sizeof(*args)); 635 return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr); 636 } 637 638 /** 639 * amdgpu_gem_timeout - calculate jiffies timeout from absolute value 640 * 641 * @timeout_ns: timeout in ns 642 * 643 * Calculate the timeout in jiffies from an absolute timeout in ns. 644 */ 645 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns) 646 { 647 unsigned long timeout_jiffies; 648 ktime_t timeout; 649 650 /* clamp timeout if it's to large */ 651 if (((int64_t)timeout_ns) < 0) 652 return MAX_SCHEDULE_TIMEOUT; 653 654 timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get()); 655 if (ktime_to_ns(timeout) < 0) 656 return 0; 657 658 timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout)); 659 /* clamp timeout to avoid unsigned-> signed overflow */ 660 if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT) 661 return MAX_SCHEDULE_TIMEOUT - 1; 662 663 return timeout_jiffies; 664 } 665 666 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 667 struct drm_file *filp) 668 { 669 union drm_amdgpu_gem_wait_idle *args = data; 670 struct drm_gem_object *gobj; 671 struct amdgpu_bo *robj; 672 uint32_t handle = args->in.handle; 673 unsigned long timeout = amdgpu_gem_timeout(args->in.timeout); 674 int r = 0; 675 long ret; 676 677 gobj = drm_gem_object_lookup(filp, handle); 678 if (!gobj) 679 return -ENOENT; 680 681 robj = gem_to_amdgpu_bo(gobj); 682 ret = dma_resv_wait_timeout(robj->tbo.base.resv, DMA_RESV_USAGE_READ, 683 true, timeout); 684 685 /* ret == 0 means not signaled, 686 * ret > 0 means signaled 687 * ret < 0 means interrupted before timeout 688 */ 689 if (ret >= 0) { 690 memset(args, 0, sizeof(*args)); 691 args->out.status = (ret == 0); 692 } else 693 r = ret; 694 695 drm_gem_object_put(gobj); 696 return r; 697 } 698 699 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 700 struct drm_file *filp) 701 { 702 struct drm_amdgpu_gem_metadata *args = data; 703 struct drm_gem_object *gobj; 704 struct amdgpu_bo *robj; 705 int r = -1; 706 707 DRM_DEBUG("%d\n", args->handle); 708 gobj = drm_gem_object_lookup(filp, args->handle); 709 if (gobj == NULL) 710 return -ENOENT; 711 robj = gem_to_amdgpu_bo(gobj); 712 713 r = amdgpu_bo_reserve(robj, false); 714 if (unlikely(r != 0)) 715 goto out; 716 717 if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) { 718 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info); 719 r = amdgpu_bo_get_metadata(robj, args->data.data, 720 sizeof(args->data.data), 721 &args->data.data_size_bytes, 722 &args->data.flags); 723 } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) { 724 if (args->data.data_size_bytes > sizeof(args->data.data)) { 725 r = -EINVAL; 726 goto unreserve; 727 } 728 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info); 729 if (!r) 730 r = amdgpu_bo_set_metadata(robj, args->data.data, 731 args->data.data_size_bytes, 732 args->data.flags); 733 } 734 735 unreserve: 736 amdgpu_bo_unreserve(robj); 737 out: 738 drm_gem_object_put(gobj); 739 return r; 740 } 741 742 /** 743 * amdgpu_gem_va_update_vm -update the bo_va in its VM 744 * 745 * @adev: amdgpu_device pointer 746 * @vm: vm to update 747 * @bo_va: bo_va to update 748 * @operation: map, unmap or clear 749 * 750 * Update the bo_va directly after setting its address. Errors are not 751 * vital here, so they are not reported back to userspace. 752 * 753 * Returns resulting fence if freed BO(s) got cleared from the PT. 754 * otherwise stub fence in case of error. 755 */ 756 static struct dma_fence * 757 amdgpu_gem_va_update_vm(struct amdgpu_device *adev, 758 struct amdgpu_vm *vm, 759 struct amdgpu_bo_va *bo_va, 760 uint32_t operation) 761 { 762 struct dma_fence *fence = dma_fence_get_stub(); 763 int r; 764 765 if (!amdgpu_vm_ready(vm)) 766 return fence; 767 768 r = amdgpu_vm_clear_freed(adev, vm, &fence); 769 if (r) 770 goto error; 771 772 if (operation == AMDGPU_VA_OP_MAP || 773 operation == AMDGPU_VA_OP_REPLACE) { 774 r = amdgpu_vm_bo_update(adev, bo_va, false); 775 if (r) 776 goto error; 777 } 778 779 r = amdgpu_vm_update_pdes(adev, vm, false); 780 781 error: 782 if (r && r != -ERESTARTSYS) 783 DRM_ERROR("Couldn't update BO_VA (%d)\n", r); 784 785 return fence; 786 } 787 788 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 789 struct drm_file *filp) 790 { 791 const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE | 792 AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE | 793 AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK | 794 AMDGPU_VM_PAGE_NOALLOC; 795 const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE | 796 AMDGPU_VM_PAGE_PRT; 797 798 struct drm_amdgpu_gem_va *args = data; 799 struct drm_gem_object *gobj; 800 struct amdgpu_device *adev = drm_to_adev(dev); 801 struct amdgpu_fpriv *fpriv = filp->driver_priv; 802 struct amdgpu_bo *abo; 803 struct amdgpu_bo_va *bo_va; 804 struct drm_syncobj *timeline_syncobj = NULL; 805 struct dma_fence_chain *timeline_chain = NULL; 806 struct dma_fence *fence; 807 struct drm_exec exec; 808 uint64_t vm_size; 809 int r = 0; 810 811 if (args->va_address < AMDGPU_VA_RESERVED_BOTTOM) { 812 dev_dbg(dev->dev, 813 "va_address 0x%llx is in reserved area 0x%llx\n", 814 args->va_address, AMDGPU_VA_RESERVED_BOTTOM); 815 return -EINVAL; 816 } 817 818 if (args->va_address >= AMDGPU_GMC_HOLE_START && 819 args->va_address < AMDGPU_GMC_HOLE_END) { 820 dev_dbg(dev->dev, 821 "va_address 0x%llx is in VA hole 0x%llx-0x%llx\n", 822 args->va_address, AMDGPU_GMC_HOLE_START, 823 AMDGPU_GMC_HOLE_END); 824 return -EINVAL; 825 } 826 827 args->va_address &= AMDGPU_GMC_HOLE_MASK; 828 829 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 830 vm_size -= AMDGPU_VA_RESERVED_TOP; 831 if (args->va_address + args->map_size > vm_size) { 832 dev_dbg(dev->dev, 833 "va_address 0x%llx is in top reserved area 0x%llx\n", 834 args->va_address + args->map_size, vm_size); 835 return -EINVAL; 836 } 837 838 if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) { 839 dev_dbg(dev->dev, "invalid flags combination 0x%08X\n", 840 args->flags); 841 return -EINVAL; 842 } 843 844 switch (args->operation) { 845 case AMDGPU_VA_OP_MAP: 846 case AMDGPU_VA_OP_UNMAP: 847 case AMDGPU_VA_OP_CLEAR: 848 case AMDGPU_VA_OP_REPLACE: 849 break; 850 default: 851 dev_dbg(dev->dev, "unsupported operation %d\n", 852 args->operation); 853 return -EINVAL; 854 } 855 856 if ((args->operation != AMDGPU_VA_OP_CLEAR) && 857 !(args->flags & AMDGPU_VM_PAGE_PRT)) { 858 gobj = drm_gem_object_lookup(filp, args->handle); 859 if (gobj == NULL) 860 return -ENOENT; 861 abo = gem_to_amdgpu_bo(gobj); 862 } else { 863 gobj = NULL; 864 abo = NULL; 865 } 866 867 r = amdgpu_gem_add_input_fence(filp, 868 args->input_fence_syncobj_handles, 869 args->num_syncobj_handles); 870 if (r) 871 goto error_put_gobj; 872 873 drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT | 874 DRM_EXEC_IGNORE_DUPLICATES, 0); 875 drm_exec_until_all_locked(&exec) { 876 if (gobj) { 877 r = drm_exec_lock_obj(&exec, gobj); 878 drm_exec_retry_on_contention(&exec); 879 if (unlikely(r)) 880 goto error; 881 } 882 883 r = amdgpu_vm_lock_pd(&fpriv->vm, &exec, 2); 884 drm_exec_retry_on_contention(&exec); 885 if (unlikely(r)) 886 goto error; 887 } 888 889 if (abo) { 890 bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo); 891 if (!bo_va) { 892 r = -ENOENT; 893 goto error; 894 } 895 } else if (args->operation != AMDGPU_VA_OP_CLEAR) { 896 bo_va = fpriv->prt_va; 897 } else { 898 bo_va = NULL; 899 } 900 901 r = amdgpu_gem_update_timeline_node(filp, 902 args->vm_timeline_syncobj_out, 903 args->vm_timeline_point, 904 &timeline_syncobj, 905 &timeline_chain); 906 if (r) 907 goto error; 908 909 switch (args->operation) { 910 case AMDGPU_VA_OP_MAP: 911 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address, 912 args->offset_in_bo, args->map_size, 913 args->flags); 914 break; 915 case AMDGPU_VA_OP_UNMAP: 916 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address); 917 break; 918 919 case AMDGPU_VA_OP_CLEAR: 920 r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm, 921 args->va_address, 922 args->map_size); 923 break; 924 case AMDGPU_VA_OP_REPLACE: 925 r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address, 926 args->offset_in_bo, args->map_size, 927 args->flags); 928 break; 929 default: 930 break; 931 } 932 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !adev->debug_vm) { 933 fence = amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va, 934 args->operation); 935 936 if (timeline_syncobj) 937 amdgpu_gem_update_bo_mapping(filp, bo_va, 938 args->operation, 939 args->vm_timeline_point, 940 fence, timeline_syncobj, 941 timeline_chain); 942 else 943 dma_fence_put(fence); 944 945 } 946 947 error: 948 drm_exec_fini(&exec); 949 error_put_gobj: 950 drm_gem_object_put(gobj); 951 return r; 952 } 953 954 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 955 struct drm_file *filp) 956 { 957 struct drm_amdgpu_gem_op *args = data; 958 struct drm_gem_object *gobj; 959 struct amdgpu_vm_bo_base *base; 960 struct amdgpu_bo *robj; 961 struct drm_exec exec; 962 struct amdgpu_fpriv *fpriv = filp->driver_priv; 963 int r; 964 965 if (args->padding) 966 return -EINVAL; 967 968 gobj = drm_gem_object_lookup(filp, args->handle); 969 if (!gobj) 970 return -ENOENT; 971 972 robj = gem_to_amdgpu_bo(gobj); 973 974 drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT | 975 DRM_EXEC_IGNORE_DUPLICATES, 0); 976 drm_exec_until_all_locked(&exec) { 977 r = drm_exec_lock_obj(&exec, gobj); 978 drm_exec_retry_on_contention(&exec); 979 if (r) 980 goto out_exec; 981 982 if (args->op == AMDGPU_GEM_OP_GET_MAPPING_INFO) { 983 r = amdgpu_vm_lock_pd(&fpriv->vm, &exec, 0); 984 drm_exec_retry_on_contention(&exec); 985 if (r) 986 goto out_exec; 987 } 988 } 989 990 switch (args->op) { 991 case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: { 992 struct drm_amdgpu_gem_create_in info; 993 void __user *out = u64_to_user_ptr(args->value); 994 995 info.bo_size = robj->tbo.base.size; 996 info.alignment = robj->tbo.page_alignment << PAGE_SHIFT; 997 info.domains = robj->preferred_domains; 998 info.domain_flags = robj->flags; 999 drm_exec_fini(&exec); 1000 if (copy_to_user(out, &info, sizeof(info))) 1001 r = -EFAULT; 1002 break; 1003 } 1004 case AMDGPU_GEM_OP_SET_PLACEMENT: 1005 if (drm_gem_is_imported(&robj->tbo.base) && 1006 args->value & AMDGPU_GEM_DOMAIN_VRAM) { 1007 r = -EINVAL; 1008 goto out_exec; 1009 } 1010 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) { 1011 r = -EPERM; 1012 goto out_exec; 1013 } 1014 for (base = robj->vm_bo; base; base = base->next) 1015 if (amdgpu_xgmi_same_hive(amdgpu_ttm_adev(robj->tbo.bdev), 1016 amdgpu_ttm_adev(base->vm->root.bo->tbo.bdev))) { 1017 r = -EINVAL; 1018 goto out_exec; 1019 } 1020 1021 1022 robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM | 1023 AMDGPU_GEM_DOMAIN_GTT | 1024 AMDGPU_GEM_DOMAIN_CPU); 1025 robj->allowed_domains = robj->preferred_domains; 1026 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 1027 robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 1028 1029 if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) 1030 amdgpu_vm_bo_invalidate(robj, true); 1031 drm_exec_fini(&exec); 1032 break; 1033 case AMDGPU_GEM_OP_GET_MAPPING_INFO: { 1034 struct amdgpu_bo_va *bo_va = amdgpu_vm_bo_find(&fpriv->vm, robj); 1035 struct drm_amdgpu_gem_vm_entry *vm_entries; 1036 struct amdgpu_bo_va_mapping *mapping; 1037 int num_mappings = 0; 1038 /* 1039 * num_entries is set as an input to the size of the user-allocated array of 1040 * drm_amdgpu_gem_vm_entry stored at args->value. 1041 * num_entries is sent back as output as the number of mappings the bo has. 1042 * If that number is larger than the size of the array, the ioctl must 1043 * be retried. 1044 */ 1045 vm_entries = kvcalloc(args->num_entries, sizeof(*vm_entries), GFP_KERNEL); 1046 if (!vm_entries) 1047 return -ENOMEM; 1048 1049 amdgpu_vm_bo_va_for_each_valid_mapping(bo_va, mapping) { 1050 if (num_mappings < args->num_entries) { 1051 vm_entries[num_mappings].addr = mapping->start * AMDGPU_GPU_PAGE_SIZE; 1052 vm_entries[num_mappings].size = (mapping->last - mapping->start + 1) * AMDGPU_GPU_PAGE_SIZE; 1053 vm_entries[num_mappings].offset = mapping->offset; 1054 vm_entries[num_mappings].flags = mapping->flags; 1055 } 1056 num_mappings += 1; 1057 } 1058 1059 amdgpu_vm_bo_va_for_each_invalid_mapping(bo_va, mapping) { 1060 if (num_mappings < args->num_entries) { 1061 vm_entries[num_mappings].addr = mapping->start * AMDGPU_GPU_PAGE_SIZE; 1062 vm_entries[num_mappings].size = (mapping->last - mapping->start + 1) * AMDGPU_GPU_PAGE_SIZE; 1063 vm_entries[num_mappings].offset = mapping->offset; 1064 vm_entries[num_mappings].flags = mapping->flags; 1065 } 1066 num_mappings += 1; 1067 } 1068 1069 drm_exec_fini(&exec); 1070 1071 if (num_mappings > 0 && num_mappings <= args->num_entries) 1072 if (copy_to_user(u64_to_user_ptr(args->value), vm_entries, num_mappings * sizeof(*vm_entries))) 1073 r = -EFAULT; 1074 1075 args->num_entries = num_mappings; 1076 1077 kvfree(vm_entries); 1078 break; 1079 } 1080 default: 1081 drm_exec_fini(&exec); 1082 r = -EINVAL; 1083 } 1084 1085 drm_gem_object_put(gobj); 1086 return r; 1087 out_exec: 1088 drm_exec_fini(&exec); 1089 drm_gem_object_put(gobj); 1090 return r; 1091 } 1092 1093 /** 1094 * amdgpu_gem_list_handles_ioctl - get information about a process' buffer objects 1095 * 1096 * @dev: drm device pointer 1097 * @data: drm_amdgpu_gem_list_handles 1098 * @filp: drm file pointer 1099 * 1100 * num_entries is set as an input to the size of the entries array. 1101 * num_entries is sent back as output as the number of bos in the process. 1102 * If that number is larger than the size of the array, the ioctl must 1103 * be retried. 1104 * 1105 * Returns: 1106 * 0 for success, -errno for errors. 1107 */ 1108 int amdgpu_gem_list_handles_ioctl(struct drm_device *dev, void *data, 1109 struct drm_file *filp) 1110 { 1111 struct drm_amdgpu_gem_list_handles *args = data; 1112 struct drm_amdgpu_gem_list_handles_entry *bo_entries; 1113 struct drm_gem_object *gobj; 1114 int id, ret = 0; 1115 int bo_index = 0; 1116 int num_bos = 0; 1117 1118 spin_lock(&filp->table_lock); 1119 idr_for_each_entry(&filp->object_idr, gobj, id) 1120 num_bos += 1; 1121 spin_unlock(&filp->table_lock); 1122 1123 if (args->num_entries < num_bos) { 1124 args->num_entries = num_bos; 1125 return 0; 1126 } 1127 1128 if (num_bos == 0) { 1129 args->num_entries = 0; 1130 return 0; 1131 } 1132 1133 bo_entries = kvcalloc(num_bos, sizeof(*bo_entries), GFP_KERNEL); 1134 if (!bo_entries) 1135 return -ENOMEM; 1136 1137 spin_lock(&filp->table_lock); 1138 idr_for_each_entry(&filp->object_idr, gobj, id) { 1139 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj); 1140 struct drm_amdgpu_gem_list_handles_entry *bo_entry; 1141 1142 if (bo_index >= num_bos) { 1143 ret = -EAGAIN; 1144 break; 1145 } 1146 1147 bo_entry = &bo_entries[bo_index]; 1148 1149 bo_entry->size = amdgpu_bo_size(bo); 1150 bo_entry->alloc_flags = bo->flags & AMDGPU_GEM_CREATE_SETTABLE_MASK; 1151 bo_entry->preferred_domains = bo->preferred_domains; 1152 bo_entry->gem_handle = id; 1153 bo_entry->alignment = bo->tbo.page_alignment; 1154 1155 if (bo->tbo.base.import_attach) 1156 bo_entry->flags |= AMDGPU_GEM_LIST_HANDLES_FLAG_IS_IMPORT; 1157 1158 bo_index += 1; 1159 } 1160 spin_unlock(&filp->table_lock); 1161 1162 args->num_entries = bo_index; 1163 1164 if (!ret) 1165 if (copy_to_user(u64_to_user_ptr(args->entries), bo_entries, num_bos * sizeof(*bo_entries))) 1166 ret = -EFAULT; 1167 1168 kvfree(bo_entries); 1169 1170 return ret; 1171 } 1172 1173 static int amdgpu_gem_align_pitch(struct amdgpu_device *adev, 1174 int width, 1175 int cpp, 1176 bool tiled) 1177 { 1178 int aligned = width; 1179 int pitch_mask = 0; 1180 1181 switch (cpp) { 1182 case 1: 1183 pitch_mask = 255; 1184 break; 1185 case 2: 1186 pitch_mask = 127; 1187 break; 1188 case 3: 1189 case 4: 1190 pitch_mask = 63; 1191 break; 1192 } 1193 1194 aligned += pitch_mask; 1195 aligned &= ~pitch_mask; 1196 return aligned * cpp; 1197 } 1198 1199 int amdgpu_mode_dumb_create(struct drm_file *file_priv, 1200 struct drm_device *dev, 1201 struct drm_mode_create_dumb *args) 1202 { 1203 struct amdgpu_device *adev = drm_to_adev(dev); 1204 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1205 struct drm_gem_object *gobj; 1206 uint32_t handle; 1207 u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 1208 AMDGPU_GEM_CREATE_CPU_GTT_USWC | 1209 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 1210 u32 domain; 1211 int r; 1212 1213 /* 1214 * The buffer returned from this function should be cleared, but 1215 * it can only be done if the ring is enabled or we'll fail to 1216 * create the buffer. 1217 */ 1218 if (adev->mman.buffer_funcs_enabled) 1219 flags |= AMDGPU_GEM_CREATE_VRAM_CLEARED; 1220 1221 args->pitch = amdgpu_gem_align_pitch(adev, args->width, 1222 DIV_ROUND_UP(args->bpp, 8), 0); 1223 args->size = (u64)args->pitch * args->height; 1224 args->size = ALIGN(args->size, PAGE_SIZE); 1225 domain = amdgpu_bo_get_preferred_domain(adev, 1226 amdgpu_display_supported_domains(adev, flags)); 1227 r = amdgpu_gem_object_create(adev, args->size, 0, domain, flags, 1228 ttm_bo_type_device, NULL, &gobj, fpriv->xcp_id + 1); 1229 if (r) 1230 return -ENOMEM; 1231 1232 r = drm_gem_handle_create(file_priv, gobj, &handle); 1233 /* drop reference from allocate - handle holds it now */ 1234 drm_gem_object_put(gobj); 1235 if (r) 1236 return r; 1237 1238 args->handle = handle; 1239 return 0; 1240 } 1241 1242 #if defined(CONFIG_DEBUG_FS) 1243 static int amdgpu_debugfs_gem_info_show(struct seq_file *m, void *unused) 1244 { 1245 struct amdgpu_device *adev = m->private; 1246 struct drm_device *dev = adev_to_drm(adev); 1247 struct drm_file *file; 1248 int r; 1249 1250 r = mutex_lock_interruptible(&dev->filelist_mutex); 1251 if (r) 1252 return r; 1253 1254 list_for_each_entry(file, &dev->filelist, lhead) { 1255 struct task_struct *task; 1256 struct drm_gem_object *gobj; 1257 struct pid *pid; 1258 int id; 1259 1260 /* 1261 * Although we have a valid reference on file->pid, that does 1262 * not guarantee that the task_struct who called get_pid() is 1263 * still alive (e.g. get_pid(current) => fork() => exit()). 1264 * Therefore, we need to protect this ->comm access using RCU. 1265 */ 1266 rcu_read_lock(); 1267 pid = rcu_dereference(file->pid); 1268 task = pid_task(pid, PIDTYPE_TGID); 1269 seq_printf(m, "pid %8d command %s:\n", pid_nr(pid), 1270 task ? task->comm : "<unknown>"); 1271 rcu_read_unlock(); 1272 1273 spin_lock(&file->table_lock); 1274 idr_for_each_entry(&file->object_idr, gobj, id) { 1275 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj); 1276 1277 amdgpu_bo_print_info(id, bo, m); 1278 } 1279 spin_unlock(&file->table_lock); 1280 } 1281 1282 mutex_unlock(&dev->filelist_mutex); 1283 return 0; 1284 } 1285 1286 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_gem_info); 1287 1288 #endif 1289 1290 void amdgpu_debugfs_gem_init(struct amdgpu_device *adev) 1291 { 1292 #if defined(CONFIG_DEBUG_FS) 1293 struct drm_minor *minor = adev_to_drm(adev)->primary; 1294 struct dentry *root = minor->debugfs_root; 1295 1296 debugfs_create_file("amdgpu_gem_info", 0444, root, adev, 1297 &amdgpu_debugfs_gem_info_fops); 1298 #endif 1299 } 1300