1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <drm/drmP.h> 29 #include <drm/amdgpu_drm.h> 30 #ifdef CONFIG_X86 31 #include <asm/set_memory.h> 32 #endif 33 #include "amdgpu.h" 34 35 /* 36 * GART 37 * The GART (Graphics Aperture Remapping Table) is an aperture 38 * in the GPU's address space. System pages can be mapped into 39 * the aperture and look like contiguous pages from the GPU's 40 * perspective. A page table maps the pages in the aperture 41 * to the actual backing pages in system memory. 42 * 43 * Radeon GPUs support both an internal GART, as described above, 44 * and AGP. AGP works similarly, but the GART table is configured 45 * and maintained by the northbridge rather than the driver. 46 * Radeon hw has a separate AGP aperture that is programmed to 47 * point to the AGP aperture provided by the northbridge and the 48 * requests are passed through to the northbridge aperture. 49 * Both AGP and internal GART can be used at the same time, however 50 * that is not currently supported by the driver. 51 * 52 * This file handles the common internal GART management. 53 */ 54 55 /* 56 * Common GART table functions. 57 */ 58 59 /** 60 * amdgpu_gart_set_defaults - set the default gart_size 61 * 62 * @adev: amdgpu_device pointer 63 * 64 * Set the default gart_size based on parameters and available VRAM. 65 */ 66 void amdgpu_gart_set_defaults(struct amdgpu_device *adev) 67 { 68 adev->mc.gart_size = (uint64_t)amdgpu_gart_size << 20; 69 } 70 71 /** 72 * amdgpu_gart_table_ram_alloc - allocate system ram for gart page table 73 * 74 * @adev: amdgpu_device pointer 75 * 76 * Allocate system memory for GART page table 77 * (r1xx-r3xx, non-pcie r4xx, rs400). These asics require the 78 * gart table to be in system memory. 79 * Returns 0 for success, -ENOMEM for failure. 80 */ 81 int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev) 82 { 83 void *ptr; 84 85 ptr = pci_alloc_consistent(adev->pdev, adev->gart.table_size, 86 &adev->gart.table_addr); 87 if (ptr == NULL) { 88 return -ENOMEM; 89 } 90 #ifdef CONFIG_X86 91 if (0) { 92 set_memory_uc((unsigned long)ptr, 93 adev->gart.table_size >> PAGE_SHIFT); 94 } 95 #endif 96 adev->gart.ptr = ptr; 97 memset((void *)adev->gart.ptr, 0, adev->gart.table_size); 98 return 0; 99 } 100 101 /** 102 * amdgpu_gart_table_ram_free - free system ram for gart page table 103 * 104 * @adev: amdgpu_device pointer 105 * 106 * Free system memory for GART page table 107 * (r1xx-r3xx, non-pcie r4xx, rs400). These asics require the 108 * gart table to be in system memory. 109 */ 110 void amdgpu_gart_table_ram_free(struct amdgpu_device *adev) 111 { 112 if (adev->gart.ptr == NULL) { 113 return; 114 } 115 #ifdef CONFIG_X86 116 if (0) { 117 set_memory_wb((unsigned long)adev->gart.ptr, 118 adev->gart.table_size >> PAGE_SHIFT); 119 } 120 #endif 121 pci_free_consistent(adev->pdev, adev->gart.table_size, 122 (void *)adev->gart.ptr, 123 adev->gart.table_addr); 124 adev->gart.ptr = NULL; 125 adev->gart.table_addr = 0; 126 } 127 128 /** 129 * amdgpu_gart_table_vram_alloc - allocate vram for gart page table 130 * 131 * @adev: amdgpu_device pointer 132 * 133 * Allocate video memory for GART page table 134 * (pcie r4xx, r5xx+). These asics require the 135 * gart table to be in video memory. 136 * Returns 0 for success, error for failure. 137 */ 138 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev) 139 { 140 int r; 141 142 if (adev->gart.robj == NULL) { 143 r = amdgpu_bo_create(adev, adev->gart.table_size, 144 PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, 145 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 146 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, 147 NULL, NULL, 0, &adev->gart.robj); 148 if (r) { 149 return r; 150 } 151 } 152 return 0; 153 } 154 155 /** 156 * amdgpu_gart_table_vram_pin - pin gart page table in vram 157 * 158 * @adev: amdgpu_device pointer 159 * 160 * Pin the GART page table in vram so it will not be moved 161 * by the memory manager (pcie r4xx, r5xx+). These asics require the 162 * gart table to be in video memory. 163 * Returns 0 for success, error for failure. 164 */ 165 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev) 166 { 167 uint64_t gpu_addr; 168 int r; 169 170 r = amdgpu_bo_reserve(adev->gart.robj, false); 171 if (unlikely(r != 0)) 172 return r; 173 r = amdgpu_bo_pin(adev->gart.robj, 174 AMDGPU_GEM_DOMAIN_VRAM, &gpu_addr); 175 if (r) { 176 amdgpu_bo_unreserve(adev->gart.robj); 177 return r; 178 } 179 r = amdgpu_bo_kmap(adev->gart.robj, &adev->gart.ptr); 180 if (r) 181 amdgpu_bo_unpin(adev->gart.robj); 182 amdgpu_bo_unreserve(adev->gart.robj); 183 adev->gart.table_addr = gpu_addr; 184 return r; 185 } 186 187 /** 188 * amdgpu_gart_table_vram_unpin - unpin gart page table in vram 189 * 190 * @adev: amdgpu_device pointer 191 * 192 * Unpin the GART page table in vram (pcie r4xx, r5xx+). 193 * These asics require the gart table to be in video memory. 194 */ 195 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev) 196 { 197 int r; 198 199 if (adev->gart.robj == NULL) { 200 return; 201 } 202 r = amdgpu_bo_reserve(adev->gart.robj, true); 203 if (likely(r == 0)) { 204 amdgpu_bo_kunmap(adev->gart.robj); 205 amdgpu_bo_unpin(adev->gart.robj); 206 amdgpu_bo_unreserve(adev->gart.robj); 207 adev->gart.ptr = NULL; 208 } 209 } 210 211 /** 212 * amdgpu_gart_table_vram_free - free gart page table vram 213 * 214 * @adev: amdgpu_device pointer 215 * 216 * Free the video memory used for the GART page table 217 * (pcie r4xx, r5xx+). These asics require the gart table to 218 * be in video memory. 219 */ 220 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev) 221 { 222 if (adev->gart.robj == NULL) { 223 return; 224 } 225 amdgpu_bo_unref(&adev->gart.robj); 226 } 227 228 /* 229 * Common gart functions. 230 */ 231 /** 232 * amdgpu_gart_unbind - unbind pages from the gart page table 233 * 234 * @adev: amdgpu_device pointer 235 * @offset: offset into the GPU's gart aperture 236 * @pages: number of pages to unbind 237 * 238 * Unbinds the requested pages from the gart page table and 239 * replaces them with the dummy page (all asics). 240 * Returns 0 for success, -EINVAL for failure. 241 */ 242 int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, 243 int pages) 244 { 245 unsigned t; 246 unsigned p; 247 int i, j; 248 u64 page_base; 249 /* Starting from VEGA10, system bit must be 0 to mean invalid. */ 250 uint64_t flags = 0; 251 252 if (!adev->gart.ready) { 253 WARN(1, "trying to unbind memory from uninitialized GART !\n"); 254 return -EINVAL; 255 } 256 257 t = offset / AMDGPU_GPU_PAGE_SIZE; 258 p = t / (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); 259 for (i = 0; i < pages; i++, p++) { 260 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 261 adev->gart.pages[p] = NULL; 262 #endif 263 page_base = adev->dummy_page.addr; 264 if (!adev->gart.ptr) 265 continue; 266 267 for (j = 0; j < (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); j++, t++) { 268 amdgpu_gart_set_pte_pde(adev, adev->gart.ptr, 269 t, page_base, flags); 270 page_base += AMDGPU_GPU_PAGE_SIZE; 271 } 272 } 273 mb(); 274 amdgpu_gart_flush_gpu_tlb(adev, 0); 275 return 0; 276 } 277 278 /** 279 * amdgpu_gart_map - map dma_addresses into GART entries 280 * 281 * @adev: amdgpu_device pointer 282 * @offset: offset into the GPU's gart aperture 283 * @pages: number of pages to bind 284 * @dma_addr: DMA addresses of pages 285 * 286 * Map the dma_addresses into GART entries (all asics). 287 * Returns 0 for success, -EINVAL for failure. 288 */ 289 int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset, 290 int pages, dma_addr_t *dma_addr, uint64_t flags, 291 void *dst) 292 { 293 uint64_t page_base; 294 unsigned i, j, t; 295 296 if (!adev->gart.ready) { 297 WARN(1, "trying to bind memory to uninitialized GART !\n"); 298 return -EINVAL; 299 } 300 301 t = offset / AMDGPU_GPU_PAGE_SIZE; 302 303 for (i = 0; i < pages; i++) { 304 page_base = dma_addr[i]; 305 for (j = 0; j < (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); j++, t++) { 306 amdgpu_gart_set_pte_pde(adev, dst, t, page_base, flags); 307 page_base += AMDGPU_GPU_PAGE_SIZE; 308 } 309 } 310 return 0; 311 } 312 313 /** 314 * amdgpu_gart_bind - bind pages into the gart page table 315 * 316 * @adev: amdgpu_device pointer 317 * @offset: offset into the GPU's gart aperture 318 * @pages: number of pages to bind 319 * @pagelist: pages to bind 320 * @dma_addr: DMA addresses of pages 321 * 322 * Binds the requested pages to the gart page table 323 * (all asics). 324 * Returns 0 for success, -EINVAL for failure. 325 */ 326 int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset, 327 int pages, struct page **pagelist, dma_addr_t *dma_addr, 328 uint64_t flags) 329 { 330 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 331 unsigned i,t,p; 332 #endif 333 int r; 334 335 if (!adev->gart.ready) { 336 WARN(1, "trying to bind memory to uninitialized GART !\n"); 337 return -EINVAL; 338 } 339 340 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 341 t = offset / AMDGPU_GPU_PAGE_SIZE; 342 p = t / (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); 343 for (i = 0; i < pages; i++, p++) 344 adev->gart.pages[p] = pagelist[i]; 345 #endif 346 347 if (adev->gart.ptr) { 348 r = amdgpu_gart_map(adev, offset, pages, dma_addr, flags, 349 adev->gart.ptr); 350 if (r) 351 return r; 352 } 353 354 mb(); 355 amdgpu_gart_flush_gpu_tlb(adev, 0); 356 return 0; 357 } 358 359 /** 360 * amdgpu_gart_init - init the driver info for managing the gart 361 * 362 * @adev: amdgpu_device pointer 363 * 364 * Allocate the dummy page and init the gart driver info (all asics). 365 * Returns 0 for success, error for failure. 366 */ 367 int amdgpu_gart_init(struct amdgpu_device *adev) 368 { 369 int r; 370 371 if (adev->dummy_page.page) 372 return 0; 373 374 /* We need PAGE_SIZE >= AMDGPU_GPU_PAGE_SIZE */ 375 if (PAGE_SIZE < AMDGPU_GPU_PAGE_SIZE) { 376 DRM_ERROR("Page size is smaller than GPU page size!\n"); 377 return -EINVAL; 378 } 379 r = amdgpu_dummy_page_init(adev); 380 if (r) 381 return r; 382 /* Compute table size */ 383 adev->gart.num_cpu_pages = adev->mc.gart_size / PAGE_SIZE; 384 adev->gart.num_gpu_pages = adev->mc.gart_size / AMDGPU_GPU_PAGE_SIZE; 385 DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n", 386 adev->gart.num_cpu_pages, adev->gart.num_gpu_pages); 387 388 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 389 /* Allocate pages table */ 390 adev->gart.pages = vzalloc(sizeof(void *) * adev->gart.num_cpu_pages); 391 if (adev->gart.pages == NULL) { 392 amdgpu_gart_fini(adev); 393 return -ENOMEM; 394 } 395 #endif 396 397 return 0; 398 } 399 400 /** 401 * amdgpu_gart_fini - tear down the driver info for managing the gart 402 * 403 * @adev: amdgpu_device pointer 404 * 405 * Tear down the gart driver info and free the dummy page (all asics). 406 */ 407 void amdgpu_gart_fini(struct amdgpu_device *adev) 408 { 409 if (adev->gart.ready) { 410 /* unbind pages */ 411 amdgpu_gart_unbind(adev, 0, adev->gart.num_cpu_pages); 412 } 413 adev->gart.ready = false; 414 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 415 vfree(adev->gart.pages); 416 adev->gart.pages = NULL; 417 #endif 418 amdgpu_dummy_page_fini(adev); 419 } 420