1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include <linux/pci.h> 30 #include <linux/vmalloc.h> 31 32 #include <drm/amdgpu_drm.h> 33 #ifdef CONFIG_X86 34 #include <asm/set_memory.h> 35 #endif 36 #include "amdgpu.h" 37 #include "amdgpu_reset.h" 38 #include <drm/drm_drv.h> 39 #include <drm/ttm/ttm_tt.h> 40 41 /* 42 * GART 43 * The GART (Graphics Aperture Remapping Table) is an aperture 44 * in the GPU's address space. System pages can be mapped into 45 * the aperture and look like contiguous pages from the GPU's 46 * perspective. A page table maps the pages in the aperture 47 * to the actual backing pages in system memory. 48 * 49 * Radeon GPUs support both an internal GART, as described above, 50 * and AGP. AGP works similarly, but the GART table is configured 51 * and maintained by the northbridge rather than the driver. 52 * Radeon hw has a separate AGP aperture that is programmed to 53 * point to the AGP aperture provided by the northbridge and the 54 * requests are passed through to the northbridge aperture. 55 * Both AGP and internal GART can be used at the same time, however 56 * that is not currently supported by the driver. 57 * 58 * This file handles the common internal GART management. 59 */ 60 61 /* 62 * Common GART table functions. 63 */ 64 65 /** 66 * amdgpu_gart_dummy_page_init - init dummy page used by the driver 67 * 68 * @adev: amdgpu_device pointer 69 * 70 * Allocate the dummy page used by the driver (all asics). 71 * This dummy page is used by the driver as a filler for gart entries 72 * when pages are taken out of the GART 73 * Returns 0 on sucess, -ENOMEM on failure. 74 */ 75 static int amdgpu_gart_dummy_page_init(struct amdgpu_device *adev) 76 { 77 struct page *dummy_page = ttm_glob.dummy_read_page; 78 79 if (adev->dummy_page_addr) 80 return 0; 81 adev->dummy_page_addr = dma_map_page(&adev->pdev->dev, dummy_page, 0, 82 PAGE_SIZE, DMA_BIDIRECTIONAL); 83 if (dma_mapping_error(&adev->pdev->dev, adev->dummy_page_addr)) { 84 dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n"); 85 adev->dummy_page_addr = 0; 86 return -ENOMEM; 87 } 88 return 0; 89 } 90 91 /** 92 * amdgpu_gart_dummy_page_fini - free dummy page used by the driver 93 * 94 * @adev: amdgpu_device pointer 95 * 96 * Frees the dummy page used by the driver (all asics). 97 */ 98 void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev) 99 { 100 if (!adev->dummy_page_addr) 101 return; 102 dma_unmap_page(&adev->pdev->dev, adev->dummy_page_addr, PAGE_SIZE, 103 DMA_BIDIRECTIONAL); 104 adev->dummy_page_addr = 0; 105 } 106 107 /** 108 * amdgpu_gart_table_ram_alloc - allocate system ram for gart page table 109 * 110 * @adev: amdgpu_device pointer 111 * 112 * Allocate system memory for GART page table for ASICs that don't have 113 * dedicated VRAM. 114 * Returns 0 for success, error for failure. 115 */ 116 int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev) 117 { 118 unsigned int order = get_order(adev->gart.table_size); 119 gfp_t gfp_flags = GFP_KERNEL | __GFP_ZERO; 120 struct amdgpu_bo *bo = NULL; 121 struct sg_table *sg = NULL; 122 struct amdgpu_bo_param bp; 123 dma_addr_t dma_addr; 124 struct page *p; 125 unsigned long x; 126 int ret; 127 128 if (adev->gart.bo != NULL) 129 return 0; 130 131 p = alloc_pages(gfp_flags, order); 132 if (!p) 133 return -ENOMEM; 134 135 /* assign pages to this device */ 136 for (x = 0; x < (1UL << order); x++) 137 p[x].mapping = adev->mman.bdev.dev_mapping; 138 139 /* If the hardware does not support UTCL2 snooping of the CPU caches 140 * then set_memory_wc() could be used as a workaround to mark the pages 141 * as write combine memory. 142 */ 143 dma_addr = dma_map_page(&adev->pdev->dev, p, 0, adev->gart.table_size, 144 DMA_BIDIRECTIONAL); 145 if (dma_mapping_error(&adev->pdev->dev, dma_addr)) { 146 dev_err(&adev->pdev->dev, "Failed to DMA MAP the GART BO page\n"); 147 __free_pages(p, order); 148 p = NULL; 149 return -EFAULT; 150 } 151 152 dev_info(adev->dev, "%s dma_addr:%pad\n", __func__, &dma_addr); 153 /* Create SG table */ 154 sg = kmalloc(sizeof(*sg), GFP_KERNEL); 155 if (!sg) { 156 ret = -ENOMEM; 157 goto error; 158 } 159 ret = sg_alloc_table(sg, 1, GFP_KERNEL); 160 if (ret) 161 goto error; 162 163 sg_dma_address(sg->sgl) = dma_addr; 164 sg->sgl->length = adev->gart.table_size; 165 #ifdef CONFIG_NEED_SG_DMA_LENGTH 166 sg->sgl->dma_length = adev->gart.table_size; 167 #endif 168 /* Create SG BO */ 169 memset(&bp, 0, sizeof(bp)); 170 bp.size = adev->gart.table_size; 171 bp.byte_align = PAGE_SIZE; 172 bp.domain = AMDGPU_GEM_DOMAIN_CPU; 173 bp.type = ttm_bo_type_sg; 174 bp.resv = NULL; 175 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 176 bp.flags = 0; 177 ret = amdgpu_bo_create(adev, &bp, &bo); 178 if (ret) 179 goto error; 180 181 bo->tbo.sg = sg; 182 bo->tbo.ttm->sg = sg; 183 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; 184 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; 185 186 ret = amdgpu_bo_reserve(bo, true); 187 if (ret) { 188 dev_err(adev->dev, "(%d) failed to reserve bo for GART system bo\n", ret); 189 goto error; 190 } 191 192 ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT); 193 WARN(ret, "Pinning the GART table failed"); 194 if (ret) 195 goto error_resv; 196 197 adev->gart.bo = bo; 198 adev->gart.ptr = page_to_virt(p); 199 /* Make GART table accessible in VMID0 */ 200 ret = amdgpu_ttm_alloc_gart(&adev->gart.bo->tbo); 201 if (ret) 202 amdgpu_gart_table_ram_free(adev); 203 amdgpu_bo_unreserve(bo); 204 205 return 0; 206 207 error_resv: 208 amdgpu_bo_unreserve(bo); 209 error: 210 amdgpu_bo_unref(&bo); 211 if (sg) { 212 sg_free_table(sg); 213 kfree(sg); 214 } 215 __free_pages(p, order); 216 return ret; 217 } 218 219 /** 220 * amdgpu_gart_table_ram_free - free gart page table system ram 221 * 222 * @adev: amdgpu_device pointer 223 * 224 * Free the system memory used for the GART page tableon ASICs that don't 225 * have dedicated VRAM. 226 */ 227 void amdgpu_gart_table_ram_free(struct amdgpu_device *adev) 228 { 229 unsigned int order = get_order(adev->gart.table_size); 230 struct sg_table *sg = adev->gart.bo->tbo.sg; 231 struct page *p; 232 unsigned long x; 233 int ret; 234 235 ret = amdgpu_bo_reserve(adev->gart.bo, false); 236 if (!ret) { 237 amdgpu_bo_unpin(adev->gart.bo); 238 amdgpu_bo_unreserve(adev->gart.bo); 239 } 240 amdgpu_bo_unref(&adev->gart.bo); 241 sg_free_table(sg); 242 kfree(sg); 243 p = virt_to_page(adev->gart.ptr); 244 for (x = 0; x < (1UL << order); x++) 245 p[x].mapping = NULL; 246 __free_pages(p, order); 247 248 adev->gart.ptr = NULL; 249 } 250 251 /** 252 * amdgpu_gart_table_vram_alloc - allocate vram for gart page table 253 * 254 * @adev: amdgpu_device pointer 255 * 256 * Allocate video memory for GART page table 257 * (pcie r4xx, r5xx+). These asics require the 258 * gart table to be in video memory. 259 * Returns 0 for success, error for failure. 260 */ 261 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev) 262 { 263 if (adev->gart.bo != NULL) 264 return 0; 265 266 return amdgpu_bo_create_kernel(adev, adev->gart.table_size, PAGE_SIZE, 267 AMDGPU_GEM_DOMAIN_VRAM, &adev->gart.bo, 268 NULL, (void *)&adev->gart.ptr); 269 } 270 271 /** 272 * amdgpu_gart_table_vram_free - free gart page table vram 273 * 274 * @adev: amdgpu_device pointer 275 * 276 * Free the video memory used for the GART page table 277 * (pcie r4xx, r5xx+). These asics require the gart table to 278 * be in video memory. 279 */ 280 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev) 281 { 282 amdgpu_bo_free_kernel(&adev->gart.bo, NULL, (void *)&adev->gart.ptr); 283 } 284 285 /* 286 * Common gart functions. 287 */ 288 /** 289 * amdgpu_gart_unbind - unbind pages from the gart page table 290 * 291 * @adev: amdgpu_device pointer 292 * @offset: offset into the GPU's gart aperture 293 * @pages: number of pages to unbind 294 * 295 * Unbinds the requested pages from the gart page table and 296 * replaces them with the dummy page (all asics). 297 * Returns 0 for success, -EINVAL for failure. 298 */ 299 void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, 300 int pages) 301 { 302 unsigned t; 303 unsigned p; 304 int i, j; 305 u64 page_base; 306 /* Starting from VEGA10, system bit must be 0 to mean invalid. */ 307 uint64_t flags = 0; 308 int idx; 309 310 if (!adev->gart.ptr) 311 return; 312 313 if (!drm_dev_enter(adev_to_drm(adev), &idx)) 314 return; 315 316 t = offset / AMDGPU_GPU_PAGE_SIZE; 317 p = t / AMDGPU_GPU_PAGES_IN_CPU_PAGE; 318 for (i = 0; i < pages; i++, p++) { 319 page_base = adev->dummy_page_addr; 320 if (!adev->gart.ptr) 321 continue; 322 323 for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++) { 324 amdgpu_gmc_set_pte_pde(adev, adev->gart.ptr, 325 t, page_base, flags); 326 page_base += AMDGPU_GPU_PAGE_SIZE; 327 } 328 } 329 amdgpu_gart_invalidate_tlb(adev); 330 331 drm_dev_exit(idx); 332 } 333 334 /** 335 * amdgpu_gart_map - map dma_addresses into GART entries 336 * 337 * @adev: amdgpu_device pointer 338 * @offset: offset into the GPU's gart aperture 339 * @pages: number of pages to bind 340 * @dma_addr: DMA addresses of pages 341 * @flags: page table entry flags 342 * @dst: CPU address of the gart table 343 * 344 * Map the dma_addresses into GART entries (all asics). 345 * Returns 0 for success, -EINVAL for failure. 346 */ 347 void amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset, 348 int pages, dma_addr_t *dma_addr, uint64_t flags, 349 void *dst) 350 { 351 uint64_t page_base; 352 unsigned i, j, t; 353 int idx; 354 355 if (!drm_dev_enter(adev_to_drm(adev), &idx)) 356 return; 357 358 t = offset / AMDGPU_GPU_PAGE_SIZE; 359 360 for (i = 0; i < pages; i++) { 361 page_base = dma_addr[i]; 362 for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++) { 363 amdgpu_gmc_set_pte_pde(adev, dst, t, page_base, flags); 364 page_base += AMDGPU_GPU_PAGE_SIZE; 365 } 366 } 367 drm_dev_exit(idx); 368 } 369 370 /** 371 * amdgpu_gart_bind - bind pages into the gart page table 372 * 373 * @adev: amdgpu_device pointer 374 * @offset: offset into the GPU's gart aperture 375 * @pages: number of pages to bind 376 * @dma_addr: DMA addresses of pages 377 * @flags: page table entry flags 378 * 379 * Binds the requested pages to the gart page table 380 * (all asics). 381 * Returns 0 for success, -EINVAL for failure. 382 */ 383 void amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset, 384 int pages, dma_addr_t *dma_addr, 385 uint64_t flags) 386 { 387 if (!adev->gart.ptr) 388 return; 389 390 amdgpu_gart_map(adev, offset, pages, dma_addr, flags, adev->gart.ptr); 391 } 392 393 /** 394 * amdgpu_gart_invalidate_tlb - invalidate gart TLB 395 * 396 * @adev: amdgpu device driver pointer 397 * 398 * Invalidate gart TLB which can be use as a way to flush gart changes 399 * 400 */ 401 void amdgpu_gart_invalidate_tlb(struct amdgpu_device *adev) 402 { 403 int i; 404 405 if (!adev->gart.ptr) 406 return; 407 408 mb(); 409 if (down_read_trylock(&adev->reset_domain->sem)) { 410 amdgpu_device_flush_hdp(adev, NULL); 411 up_read(&adev->reset_domain->sem); 412 } 413 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) 414 amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); 415 } 416 417 /** 418 * amdgpu_gart_init - init the driver info for managing the gart 419 * 420 * @adev: amdgpu_device pointer 421 * 422 * Allocate the dummy page and init the gart driver info (all asics). 423 * Returns 0 for success, error for failure. 424 */ 425 int amdgpu_gart_init(struct amdgpu_device *adev) 426 { 427 int r; 428 429 if (adev->dummy_page_addr) 430 return 0; 431 432 /* We need PAGE_SIZE >= AMDGPU_GPU_PAGE_SIZE */ 433 if (PAGE_SIZE < AMDGPU_GPU_PAGE_SIZE) { 434 DRM_ERROR("Page size is smaller than GPU page size!\n"); 435 return -EINVAL; 436 } 437 r = amdgpu_gart_dummy_page_init(adev); 438 if (r) 439 return r; 440 /* Compute table size */ 441 adev->gart.num_cpu_pages = adev->gmc.gart_size / PAGE_SIZE; 442 adev->gart.num_gpu_pages = adev->gmc.gart_size / AMDGPU_GPU_PAGE_SIZE; 443 DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n", 444 adev->gart.num_cpu_pages, adev->gart.num_gpu_pages); 445 446 return 0; 447 } 448