1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright 2023 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef AMDGPU_EV_FENCE_H_ 26 #define AMDGPU_EV_FENCE_H_ 27 28 #include <linux/dma-fence.h> 29 30 struct amdgpu_eviction_fence { 31 struct dma_fence base; 32 spinlock_t lock; 33 char timeline_name[TASK_COMM_LEN]; 34 struct amdgpu_eviction_fence_mgr *evf_mgr; 35 }; 36 37 struct amdgpu_eviction_fence_mgr { 38 u64 ev_fence_ctx; 39 atomic_t ev_fence_seq; 40 41 /* 42 * Only updated while holding the VM resv lock. 43 * Only signaled while holding the userq mutex. 44 */ 45 struct dma_fence __rcu *ev_fence; 46 struct work_struct suspend_work; 47 bool shutdown; 48 }; 49 50 static inline struct dma_fence * 51 amdgpu_evf_mgr_get_fence(struct amdgpu_eviction_fence_mgr *evf_mgr) 52 { 53 struct dma_fence *ev_fence; 54 55 rcu_read_lock(); 56 ev_fence = dma_fence_get_rcu_safe(&evf_mgr->ev_fence); 57 rcu_read_unlock(); 58 return ev_fence; 59 } 60 61 int amdgpu_evf_mgr_attach_fence(struct amdgpu_eviction_fence_mgr *evf_mgr, 62 struct amdgpu_bo *bo); 63 int amdgpu_evf_mgr_rearm(struct amdgpu_eviction_fence_mgr *evf_mgr, 64 struct drm_exec *exec); 65 void amdgpu_evf_mgr_detach_fence(struct amdgpu_eviction_fence_mgr *evf_mgr, 66 struct amdgpu_bo *bo); 67 void amdgpu_evf_mgr_init(struct amdgpu_eviction_fence_mgr *evf_mgr); 68 void amdgpu_evf_mgr_shutdown(struct amdgpu_eviction_fence_mgr *evf_mgr); 69 void amdgpu_evf_mgr_flush_suspend(struct amdgpu_eviction_fence_mgr *evf_mgr); 70 void amdgpu_evf_mgr_fini(struct amdgpu_eviction_fence_mgr *evf_mgr); 71 72 #endif 73