1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_drv.h> 27 #include <drm/drm_fbdev_generic.h> 28 #include <drm/drm_gem.h> 29 #include <drm/drm_managed.h> 30 #include <drm/drm_pciids.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/drm_vblank.h> 33 34 #include <linux/cc_platform.h> 35 #include <linux/dynamic_debug.h> 36 #include <linux/module.h> 37 #include <linux/mmu_notifier.h> 38 #include <linux/pm_runtime.h> 39 #include <linux/suspend.h> 40 #include <linux/vga_switcheroo.h> 41 42 #include "amdgpu.h" 43 #include "amdgpu_amdkfd.h" 44 #include "amdgpu_dma_buf.h" 45 #include "amdgpu_drv.h" 46 #include "amdgpu_fdinfo.h" 47 #include "amdgpu_irq.h" 48 #include "amdgpu_psp.h" 49 #include "amdgpu_ras.h" 50 #include "amdgpu_reset.h" 51 #include "amdgpu_sched.h" 52 #include "amdgpu_xgmi.h" 53 #include "../amdxcp/amdgpu_xcp_drv.h" 54 55 /* 56 * KMS wrapper. 57 * - 3.0.0 - initial driver 58 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 59 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 60 * at the end of IBs. 61 * - 3.3.0 - Add VM support for UVD on supported hardware. 62 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 63 * - 3.5.0 - Add support for new UVD_NO_OP register. 64 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 65 * - 3.7.0 - Add support for VCE clock list packet 66 * - 3.8.0 - Add support raster config init in the kernel 67 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 68 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 69 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 70 * - 3.12.0 - Add query for double offchip LDS buffers 71 * - 3.13.0 - Add PRT support 72 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 73 * - 3.15.0 - Export more gpu info for gfx9 74 * - 3.16.0 - Add reserved vmid support 75 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 76 * - 3.18.0 - Export gpu always on cu bitmap 77 * - 3.19.0 - Add support for UVD MJPEG decode 78 * - 3.20.0 - Add support for local BOs 79 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 80 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 81 * - 3.23.0 - Add query for VRAM lost counter 82 * - 3.24.0 - Add high priority compute support for gfx9 83 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 84 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 85 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation. 86 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 87 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 88 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 89 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 90 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 91 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 92 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 93 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 94 * - 3.36.0 - Allow reading more status registers on si/cik 95 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 96 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 97 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 98 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 99 * - 3.41.0 - Add video codec query 100 * - 3.42.0 - Add 16bpc fixed point display support 101 * - 3.43.0 - Add device hot plug/unplug support 102 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 103 * - 3.45.0 - Add context ioctl stable pstate interface 104 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm 105 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags 106 * - 3.48.0 - Add IP discovery version info to HW INFO 107 * - 3.49.0 - Add gang submit into CS IOCTL 108 * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock 109 * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock 110 * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl 111 * 3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields: 112 * tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size, 113 * gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi 114 * 3.53.0 - Support for GFX11 CP GFX shadowing 115 * 3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support 116 * - 3.55.0 - Add AMDGPU_INFO_GPUVM_FAULT query 117 * - 3.56.0 - Update IB start address and size alignment for decode and encode 118 */ 119 #define KMS_DRIVER_MAJOR 3 120 #define KMS_DRIVER_MINOR 56 121 #define KMS_DRIVER_PATCHLEVEL 0 122 123 /* 124 * amdgpu.debug module options. Are all disabled by default 125 */ 126 enum AMDGPU_DEBUG_MASK { 127 AMDGPU_DEBUG_VM = BIT(0), 128 AMDGPU_DEBUG_LARGEBAR = BIT(1), 129 AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY = BIT(2), 130 }; 131 132 unsigned int amdgpu_vram_limit = UINT_MAX; 133 int amdgpu_vis_vram_limit; 134 int amdgpu_gart_size = -1; /* auto */ 135 int amdgpu_gtt_size = -1; /* auto */ 136 int amdgpu_moverate = -1; /* auto */ 137 int amdgpu_audio = -1; 138 int amdgpu_disp_priority; 139 int amdgpu_hw_i2c; 140 int amdgpu_pcie_gen2 = -1; 141 int amdgpu_msi = -1; 142 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 143 int amdgpu_dpm = -1; 144 int amdgpu_fw_load_type = -1; 145 int amdgpu_aspm = -1; 146 int amdgpu_runtime_pm = -1; 147 uint amdgpu_ip_block_mask = 0xffffffff; 148 int amdgpu_bapm = -1; 149 int amdgpu_deep_color; 150 int amdgpu_vm_size = -1; 151 int amdgpu_vm_fragment_size = -1; 152 int amdgpu_vm_block_size = -1; 153 int amdgpu_vm_fault_stop; 154 int amdgpu_vm_update_mode = -1; 155 int amdgpu_exp_hw_support; 156 int amdgpu_dc = -1; 157 int amdgpu_sched_jobs = 32; 158 int amdgpu_sched_hw_submission = 2; 159 uint amdgpu_pcie_gen_cap; 160 uint amdgpu_pcie_lane_cap; 161 u64 amdgpu_cg_mask = 0xffffffffffffffff; 162 uint amdgpu_pg_mask = 0xffffffff; 163 uint amdgpu_sdma_phase_quantum = 32; 164 char *amdgpu_disable_cu; 165 char *amdgpu_virtual_display; 166 bool enforce_isolation; 167 /* 168 * OverDrive(bit 14) disabled by default 169 * GFX DCS(bit 19) disabled by default 170 */ 171 uint amdgpu_pp_feature_mask = 0xfff7bfff; 172 uint amdgpu_force_long_training; 173 int amdgpu_lbpw = -1; 174 int amdgpu_compute_multipipe = -1; 175 int amdgpu_gpu_recovery = -1; /* auto */ 176 int amdgpu_emu_mode; 177 uint amdgpu_smu_memory_pool_size; 178 int amdgpu_smu_pptable_id = -1; 179 /* 180 * FBC (bit 0) disabled by default 181 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 182 * - With this, for multiple monitors in sync(e.g. with the same model), 183 * mclk switching will be allowed. And the mclk will be not foced to the 184 * highest. That helps saving some idle power. 185 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 186 * PSR (bit 3) disabled by default 187 * EDP NO POWER SEQUENCING (bit 4) disabled by default 188 */ 189 uint amdgpu_dc_feature_mask = 2; 190 uint amdgpu_dc_debug_mask; 191 uint amdgpu_dc_visual_confirm; 192 int amdgpu_async_gfx_ring = 1; 193 int amdgpu_mcbp = -1; 194 int amdgpu_discovery = -1; 195 int amdgpu_mes; 196 int amdgpu_mes_kiq; 197 int amdgpu_noretry = -1; 198 int amdgpu_force_asic_type = -1; 199 int amdgpu_tmz = -1; /* auto */ 200 int amdgpu_reset_method = -1; /* auto */ 201 int amdgpu_num_kcq = -1; 202 int amdgpu_smartshift_bias; 203 int amdgpu_use_xgmi_p2p = 1; 204 int amdgpu_vcnfw_log; 205 int amdgpu_sg_display = -1; /* auto */ 206 int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE; 207 int amdgpu_umsch_mm; 208 int amdgpu_seamless = -1; /* auto */ 209 uint amdgpu_debug_mask; 210 211 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 212 213 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 214 "DRM_UT_CORE", 215 "DRM_UT_DRIVER", 216 "DRM_UT_KMS", 217 "DRM_UT_PRIME", 218 "DRM_UT_ATOMIC", 219 "DRM_UT_VBL", 220 "DRM_UT_STATE", 221 "DRM_UT_LEASE", 222 "DRM_UT_DP", 223 "DRM_UT_DRMRES"); 224 225 struct amdgpu_mgpu_info mgpu_info = { 226 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 227 .delayed_reset_work = __DELAYED_WORK_INITIALIZER( 228 mgpu_info.delayed_reset_work, 229 amdgpu_drv_delayed_reset_work_handler, 0), 230 }; 231 int amdgpu_ras_enable = -1; 232 uint amdgpu_ras_mask = 0xffffffff; 233 int amdgpu_bad_page_threshold = -1; 234 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 235 .timeout_fatal_disable = false, 236 .period = 0x0, /* default to 0x0 (timeout disable) */ 237 }; 238 239 /** 240 * DOC: vramlimit (int) 241 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 242 */ 243 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 244 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 245 246 /** 247 * DOC: vis_vramlimit (int) 248 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 249 */ 250 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 251 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 252 253 /** 254 * DOC: gartsize (uint) 255 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing. 256 * The default is -1 (The size depends on asic). 257 */ 258 MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)"); 259 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 260 261 /** 262 * DOC: gttsize (int) 263 * Restrict the size of GTT domain (for userspace use) in MiB for testing. 264 * The default is -1 (Use 1/2 RAM, minimum value is 3GB). 265 */ 266 MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)"); 267 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 268 269 /** 270 * DOC: moverate (int) 271 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 272 */ 273 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 274 module_param_named(moverate, amdgpu_moverate, int, 0600); 275 276 /** 277 * DOC: audio (int) 278 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 279 */ 280 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 281 module_param_named(audio, amdgpu_audio, int, 0444); 282 283 /** 284 * DOC: disp_priority (int) 285 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 286 */ 287 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 288 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 289 290 /** 291 * DOC: hw_i2c (int) 292 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 293 */ 294 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 295 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 296 297 /** 298 * DOC: pcie_gen2 (int) 299 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 300 */ 301 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 302 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 303 304 /** 305 * DOC: msi (int) 306 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 307 */ 308 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 309 module_param_named(msi, amdgpu_msi, int, 0444); 310 311 /** 312 * DOC: lockup_timeout (string) 313 * Set GPU scheduler timeout value in ms. 314 * 315 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 316 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 317 * to the default timeout. 318 * 319 * - With one value specified, the setting will apply to all non-compute jobs. 320 * - With multiple values specified, the first one will be for GFX. 321 * The second one is for Compute. The third and fourth ones are 322 * for SDMA and Video. 323 * 324 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 325 * jobs is 10000. The timeout for compute is 60000. 326 */ 327 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 328 "for passthrough or sriov, 10000 for all jobs. 0: keep default value. negative: infinity timeout), format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 329 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 330 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 331 332 /** 333 * DOC: dpm (int) 334 * Override for dynamic power management setting 335 * (0 = disable, 1 = enable) 336 * The default is -1 (auto). 337 */ 338 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 339 module_param_named(dpm, amdgpu_dpm, int, 0444); 340 341 /** 342 * DOC: fw_load_type (int) 343 * Set different firmware loading type for debugging, if supported. 344 * Set to 0 to force direct loading if supported by the ASIC. Set 345 * to -1 to select the default loading mode for the ASIC, as defined 346 * by the driver. The default is -1 (auto). 347 */ 348 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); 349 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 350 351 /** 352 * DOC: aspm (int) 353 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 354 */ 355 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 356 module_param_named(aspm, amdgpu_aspm, int, 0444); 357 358 /** 359 * DOC: runpm (int) 360 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 361 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 362 * Setting the value to 0 disables this functionality. 363 * Setting the value to -2 is auto enabled with power down when displays are attached. 364 */ 365 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto, -2 = autowith displays)"); 366 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 367 368 /** 369 * DOC: ip_block_mask (uint) 370 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 371 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 372 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 373 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 374 */ 375 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 376 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 377 378 /** 379 * DOC: bapm (int) 380 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 381 * The default -1 (auto, enabled) 382 */ 383 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 384 module_param_named(bapm, amdgpu_bapm, int, 0444); 385 386 /** 387 * DOC: deep_color (int) 388 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 389 */ 390 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 391 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 392 393 /** 394 * DOC: vm_size (int) 395 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 396 */ 397 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 398 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 399 400 /** 401 * DOC: vm_fragment_size (int) 402 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 403 */ 404 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 405 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 406 407 /** 408 * DOC: vm_block_size (int) 409 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 410 */ 411 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 412 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 413 414 /** 415 * DOC: vm_fault_stop (int) 416 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 417 */ 418 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 419 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 420 421 /** 422 * DOC: vm_update_mode (int) 423 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 424 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 425 */ 426 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 427 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 428 429 /** 430 * DOC: exp_hw_support (int) 431 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 432 */ 433 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 434 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 435 436 /** 437 * DOC: dc (int) 438 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 439 */ 440 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 441 module_param_named(dc, amdgpu_dc, int, 0444); 442 443 /** 444 * DOC: sched_jobs (int) 445 * Override the max number of jobs supported in the sw queue. The default is 32. 446 */ 447 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 448 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 449 450 /** 451 * DOC: sched_hw_submission (int) 452 * Override the max number of HW submissions. The default is 2. 453 */ 454 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 455 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 456 457 /** 458 * DOC: ppfeaturemask (hexint) 459 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 460 * The default is the current set of stable power features. 461 */ 462 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 463 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 464 465 /** 466 * DOC: forcelongtraining (uint) 467 * Force long memory training in resume. 468 * The default is zero, indicates short training in resume. 469 */ 470 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 471 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 472 473 /** 474 * DOC: pcie_gen_cap (uint) 475 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 476 * The default is 0 (automatic for each asic). 477 */ 478 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 479 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 480 481 /** 482 * DOC: pcie_lane_cap (uint) 483 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 484 * The default is 0 (automatic for each asic). 485 */ 486 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 487 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 488 489 /** 490 * DOC: cg_mask (ullong) 491 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 492 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 493 */ 494 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 495 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 496 497 /** 498 * DOC: pg_mask (uint) 499 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 500 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 501 */ 502 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 503 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 504 505 /** 506 * DOC: sdma_phase_quantum (uint) 507 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 508 */ 509 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 510 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 511 512 /** 513 * DOC: disable_cu (charp) 514 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 515 */ 516 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 517 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 518 519 /** 520 * DOC: virtual_display (charp) 521 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 522 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 523 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 524 * device at 26:00.0. The default is NULL. 525 */ 526 MODULE_PARM_DESC(virtual_display, 527 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 528 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 529 530 /** 531 * DOC: lbpw (int) 532 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 533 */ 534 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 535 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 536 537 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 538 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 539 540 /** 541 * DOC: gpu_recovery (int) 542 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 543 */ 544 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 545 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 546 547 /** 548 * DOC: emu_mode (int) 549 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 550 */ 551 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 552 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 553 554 /** 555 * DOC: ras_enable (int) 556 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 557 */ 558 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 559 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 560 561 /** 562 * DOC: ras_mask (uint) 563 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 564 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 565 */ 566 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 567 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 568 569 /** 570 * DOC: timeout_fatal_disable (bool) 571 * Disable Watchdog timeout fatal error event 572 */ 573 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 574 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 575 576 /** 577 * DOC: timeout_period (uint) 578 * Modify the watchdog timeout max_cycles as (1 << period) 579 */ 580 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 581 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 582 583 /** 584 * DOC: si_support (int) 585 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 586 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 587 * otherwise using amdgpu driver. 588 */ 589 #ifdef CONFIG_DRM_AMDGPU_SI 590 591 #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) 592 int amdgpu_si_support = 0; 593 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 594 #else 595 int amdgpu_si_support = 1; 596 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 597 #endif 598 599 module_param_named(si_support, amdgpu_si_support, int, 0444); 600 #endif 601 602 /** 603 * DOC: cik_support (int) 604 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 605 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 606 * otherwise using amdgpu driver. 607 */ 608 #ifdef CONFIG_DRM_AMDGPU_CIK 609 610 #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) 611 int amdgpu_cik_support = 0; 612 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 613 #else 614 int amdgpu_cik_support = 1; 615 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 616 #endif 617 618 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 619 #endif 620 621 /** 622 * DOC: smu_memory_pool_size (uint) 623 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 624 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 625 */ 626 MODULE_PARM_DESC(smu_memory_pool_size, 627 "reserve gtt for smu debug usage, 0 = disable,0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 628 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 629 630 /** 631 * DOC: async_gfx_ring (int) 632 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 633 */ 634 MODULE_PARM_DESC(async_gfx_ring, 635 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 636 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 637 638 /** 639 * DOC: mcbp (int) 640 * It is used to enable mid command buffer preemption. (0 = disabled, 1 = enabled, -1 auto (default)) 641 */ 642 MODULE_PARM_DESC(mcbp, 643 "Enable Mid-command buffer preemption (0 = disabled, 1 = enabled), -1 = auto (default)"); 644 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 645 646 /** 647 * DOC: discovery (int) 648 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 649 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 650 */ 651 MODULE_PARM_DESC(discovery, 652 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 653 module_param_named(discovery, amdgpu_discovery, int, 0444); 654 655 /** 656 * DOC: mes (int) 657 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 658 * (0 = disabled (default), 1 = enabled) 659 */ 660 MODULE_PARM_DESC(mes, 661 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 662 module_param_named(mes, amdgpu_mes, int, 0444); 663 664 /** 665 * DOC: mes_kiq (int) 666 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq. 667 * (0 = disabled (default), 1 = enabled) 668 */ 669 MODULE_PARM_DESC(mes_kiq, 670 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)"); 671 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444); 672 673 /** 674 * DOC: noretry (int) 675 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 676 * do not support per-process XNACK this also disables retry page faults. 677 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 678 */ 679 MODULE_PARM_DESC(noretry, 680 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 681 module_param_named(noretry, amdgpu_noretry, int, 0644); 682 683 /** 684 * DOC: force_asic_type (int) 685 * A non negative value used to specify the asic type for all supported GPUs. 686 */ 687 MODULE_PARM_DESC(force_asic_type, 688 "A non negative value used to specify the asic type for all supported GPUs"); 689 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 690 691 /** 692 * DOC: use_xgmi_p2p (int) 693 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 694 */ 695 MODULE_PARM_DESC(use_xgmi_p2p, 696 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 697 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 698 699 700 #ifdef CONFIG_HSA_AMD 701 /** 702 * DOC: sched_policy (int) 703 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 704 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 705 * assigns queues to HQDs. 706 */ 707 int sched_policy = KFD_SCHED_POLICY_HWS; 708 module_param(sched_policy, int, 0444); 709 MODULE_PARM_DESC(sched_policy, 710 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 711 712 /** 713 * DOC: hws_max_conc_proc (int) 714 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 715 * number of VMIDs assigned to the HWS, which is also the default. 716 */ 717 int hws_max_conc_proc = -1; 718 module_param(hws_max_conc_proc, int, 0444); 719 MODULE_PARM_DESC(hws_max_conc_proc, 720 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 721 722 /** 723 * DOC: cwsr_enable (int) 724 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 725 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 726 * disables it. 727 */ 728 int cwsr_enable = 1; 729 module_param(cwsr_enable, int, 0444); 730 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 731 732 /** 733 * DOC: max_num_of_queues_per_device (int) 734 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 735 * is 4096. 736 */ 737 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 738 module_param(max_num_of_queues_per_device, int, 0444); 739 MODULE_PARM_DESC(max_num_of_queues_per_device, 740 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 741 742 /** 743 * DOC: send_sigterm (int) 744 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 745 * but just print errors on dmesg. Setting 1 enables sending sigterm. 746 */ 747 int send_sigterm; 748 module_param(send_sigterm, int, 0444); 749 MODULE_PARM_DESC(send_sigterm, 750 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 751 752 /** 753 * DOC: halt_if_hws_hang (int) 754 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 755 * Setting 1 enables halt on hang. 756 */ 757 int halt_if_hws_hang; 758 module_param(halt_if_hws_hang, int, 0644); 759 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 760 761 /** 762 * DOC: hws_gws_support(bool) 763 * Assume that HWS supports GWS barriers regardless of what firmware version 764 * check says. Default value: false (rely on MEC2 firmware version check). 765 */ 766 bool hws_gws_support; 767 module_param(hws_gws_support, bool, 0444); 768 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 769 770 /** 771 * DOC: queue_preemption_timeout_ms (int) 772 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 773 */ 774 int queue_preemption_timeout_ms = 9000; 775 module_param(queue_preemption_timeout_ms, int, 0644); 776 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 777 778 /** 779 * DOC: debug_evictions(bool) 780 * Enable extra debug messages to help determine the cause of evictions 781 */ 782 bool debug_evictions; 783 module_param(debug_evictions, bool, 0644); 784 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 785 786 /** 787 * DOC: no_system_mem_limit(bool) 788 * Disable system memory limit, to support multiple process shared memory 789 */ 790 bool no_system_mem_limit; 791 module_param(no_system_mem_limit, bool, 0644); 792 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 793 794 /** 795 * DOC: no_queue_eviction_on_vm_fault (int) 796 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 797 */ 798 int amdgpu_no_queue_eviction_on_vm_fault; 799 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 800 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 801 #endif 802 803 /** 804 * DOC: mtype_local (int) 805 */ 806 int amdgpu_mtype_local; 807 MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (0 = MTYPE_RW (default), 1 = MTYPE_NC, 2 = MTYPE_CC)"); 808 module_param_named(mtype_local, amdgpu_mtype_local, int, 0444); 809 810 /** 811 * DOC: pcie_p2p (bool) 812 * Enable PCIe P2P (requires large-BAR). Default value: true (on) 813 */ 814 #ifdef CONFIG_HSA_AMD_P2P 815 bool pcie_p2p = true; 816 module_param(pcie_p2p, bool, 0444); 817 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); 818 #endif 819 820 /** 821 * DOC: dcfeaturemask (uint) 822 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 823 * The default is the current set of stable display features. 824 */ 825 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 826 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 827 828 /** 829 * DOC: dcdebugmask (uint) 830 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 831 */ 832 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 833 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 834 835 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)"); 836 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444); 837 838 /** 839 * DOC: abmlevel (uint) 840 * Override the default ABM (Adaptive Backlight Management) level used for DC 841 * enabled hardware. Requires DMCU to be supported and loaded. 842 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 843 * default. Values 1-4 control the maximum allowable brightness reduction via 844 * the ABM algorithm, with 1 being the least reduction and 4 being the most 845 * reduction. 846 * 847 * Defaults to 0, or disabled. Userspace can still override this level later 848 * after boot. 849 */ 850 uint amdgpu_dm_abm_level; 851 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 852 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 853 854 int amdgpu_backlight = -1; 855 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 856 module_param_named(backlight, amdgpu_backlight, bint, 0444); 857 858 /** 859 * DOC: tmz (int) 860 * Trusted Memory Zone (TMZ) is a method to protect data being written 861 * to or read from memory. 862 * 863 * The default value: 0 (off). TODO: change to auto till it is completed. 864 */ 865 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 866 module_param_named(tmz, amdgpu_tmz, int, 0444); 867 868 /** 869 * DOC: reset_method (int) 870 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 871 */ 872 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 873 module_param_named(reset_method, amdgpu_reset_method, int, 0444); 874 875 /** 876 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 877 * threshold value of faulty pages detected by RAS ECC, which may 878 * result in the GPU entering bad status when the number of total 879 * faulty pages by ECC exceeds the threshold value. 880 */ 881 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = driver sets threshold)"); 882 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 883 884 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 885 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 886 887 /** 888 * DOC: vcnfw_log (int) 889 * Enable vcnfw log output for debugging, the default is disabled. 890 */ 891 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 892 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 893 894 /** 895 * DOC: sg_display (int) 896 * Disable S/G (scatter/gather) display (i.e., display from system memory). 897 * This option is only relevant on APUs. Set this option to 0 to disable 898 * S/G display if you experience flickering or other issues under memory 899 * pressure and report the issue. 900 */ 901 MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)"); 902 module_param_named(sg_display, amdgpu_sg_display, int, 0444); 903 904 /** 905 * DOC: umsch_mm (int) 906 * Enable Multi Media User Mode Scheduler. This is a HW scheduling engine for VCN and VPE. 907 * (0 = disabled (default), 1 = enabled) 908 */ 909 MODULE_PARM_DESC(umsch_mm, 910 "Enable Multi Media User Mode Scheduler (0 = disabled (default), 1 = enabled)"); 911 module_param_named(umsch_mm, amdgpu_umsch_mm, int, 0444); 912 913 /** 914 * DOC: smu_pptable_id (int) 915 * Used to override pptable id. id = 0 use VBIOS pptable. 916 * id > 0 use the soft pptable with specicfied id. 917 */ 918 MODULE_PARM_DESC(smu_pptable_id, 919 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 920 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 921 922 /** 923 * DOC: partition_mode (int) 924 * Used to override the default SPX mode. 925 */ 926 MODULE_PARM_DESC( 927 user_partt_mode, 928 "specify partition mode to be used (-2 = AMDGPU_AUTO_COMPUTE_PARTITION_MODE(default value) \ 929 0 = AMDGPU_SPX_PARTITION_MODE, \ 930 1 = AMDGPU_DPX_PARTITION_MODE, \ 931 2 = AMDGPU_TPX_PARTITION_MODE, \ 932 3 = AMDGPU_QPX_PARTITION_MODE, \ 933 4 = AMDGPU_CPX_PARTITION_MODE)"); 934 module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint, 0444); 935 936 937 /** 938 * DOC: enforce_isolation (bool) 939 * enforce process isolation between graphics and compute via using the same reserved vmid. 940 */ 941 module_param(enforce_isolation, bool, 0444); 942 MODULE_PARM_DESC(enforce_isolation, "enforce process isolation between graphics and compute . enforce_isolation = on"); 943 944 /** 945 * DOC: seamless (int) 946 * Seamless boot will keep the image on the screen during the boot process. 947 */ 948 MODULE_PARM_DESC(seamless, "Seamless boot (-1 = auto (default), 0 = disable, 1 = enable)"); 949 module_param_named(seamless, amdgpu_seamless, int, 0444); 950 951 /** 952 * DOC: debug_mask (uint) 953 * Debug options for amdgpu, work as a binary mask with the following options: 954 * 955 * - 0x1: Debug VM handling 956 * - 0x2: Enable simulating large-bar capability on non-large bar system. This 957 * limits the VRAM size reported to ROCm applications to the visible 958 * size, usually 256MB. 959 * - 0x4: Disable GPU soft recovery, always do a full reset 960 */ 961 MODULE_PARM_DESC(debug_mask, "debug options for amdgpu, disabled by default"); 962 module_param_named(debug_mask, amdgpu_debug_mask, uint, 0444); 963 964 /* These devices are not supported by amdgpu. 965 * They are supported by the mach64, r128, radeon drivers 966 */ 967 static const u16 amdgpu_unsupported_pciidlist[] = { 968 /* mach64 */ 969 0x4354, 970 0x4358, 971 0x4554, 972 0x4742, 973 0x4744, 974 0x4749, 975 0x474C, 976 0x474D, 977 0x474E, 978 0x474F, 979 0x4750, 980 0x4751, 981 0x4752, 982 0x4753, 983 0x4754, 984 0x4755, 985 0x4756, 986 0x4757, 987 0x4758, 988 0x4759, 989 0x475A, 990 0x4C42, 991 0x4C44, 992 0x4C47, 993 0x4C49, 994 0x4C4D, 995 0x4C4E, 996 0x4C50, 997 0x4C51, 998 0x4C52, 999 0x4C53, 1000 0x5654, 1001 0x5655, 1002 0x5656, 1003 /* r128 */ 1004 0x4c45, 1005 0x4c46, 1006 0x4d46, 1007 0x4d4c, 1008 0x5041, 1009 0x5042, 1010 0x5043, 1011 0x5044, 1012 0x5045, 1013 0x5046, 1014 0x5047, 1015 0x5048, 1016 0x5049, 1017 0x504A, 1018 0x504B, 1019 0x504C, 1020 0x504D, 1021 0x504E, 1022 0x504F, 1023 0x5050, 1024 0x5051, 1025 0x5052, 1026 0x5053, 1027 0x5054, 1028 0x5055, 1029 0x5056, 1030 0x5057, 1031 0x5058, 1032 0x5245, 1033 0x5246, 1034 0x5247, 1035 0x524b, 1036 0x524c, 1037 0x534d, 1038 0x5446, 1039 0x544C, 1040 0x5452, 1041 /* radeon */ 1042 0x3150, 1043 0x3151, 1044 0x3152, 1045 0x3154, 1046 0x3155, 1047 0x3E50, 1048 0x3E54, 1049 0x4136, 1050 0x4137, 1051 0x4144, 1052 0x4145, 1053 0x4146, 1054 0x4147, 1055 0x4148, 1056 0x4149, 1057 0x414A, 1058 0x414B, 1059 0x4150, 1060 0x4151, 1061 0x4152, 1062 0x4153, 1063 0x4154, 1064 0x4155, 1065 0x4156, 1066 0x4237, 1067 0x4242, 1068 0x4336, 1069 0x4337, 1070 0x4437, 1071 0x4966, 1072 0x4967, 1073 0x4A48, 1074 0x4A49, 1075 0x4A4A, 1076 0x4A4B, 1077 0x4A4C, 1078 0x4A4D, 1079 0x4A4E, 1080 0x4A4F, 1081 0x4A50, 1082 0x4A54, 1083 0x4B48, 1084 0x4B49, 1085 0x4B4A, 1086 0x4B4B, 1087 0x4B4C, 1088 0x4C57, 1089 0x4C58, 1090 0x4C59, 1091 0x4C5A, 1092 0x4C64, 1093 0x4C66, 1094 0x4C67, 1095 0x4E44, 1096 0x4E45, 1097 0x4E46, 1098 0x4E47, 1099 0x4E48, 1100 0x4E49, 1101 0x4E4A, 1102 0x4E4B, 1103 0x4E50, 1104 0x4E51, 1105 0x4E52, 1106 0x4E53, 1107 0x4E54, 1108 0x4E56, 1109 0x5144, 1110 0x5145, 1111 0x5146, 1112 0x5147, 1113 0x5148, 1114 0x514C, 1115 0x514D, 1116 0x5157, 1117 0x5158, 1118 0x5159, 1119 0x515A, 1120 0x515E, 1121 0x5460, 1122 0x5462, 1123 0x5464, 1124 0x5548, 1125 0x5549, 1126 0x554A, 1127 0x554B, 1128 0x554C, 1129 0x554D, 1130 0x554E, 1131 0x554F, 1132 0x5550, 1133 0x5551, 1134 0x5552, 1135 0x5554, 1136 0x564A, 1137 0x564B, 1138 0x564F, 1139 0x5652, 1140 0x5653, 1141 0x5657, 1142 0x5834, 1143 0x5835, 1144 0x5954, 1145 0x5955, 1146 0x5974, 1147 0x5975, 1148 0x5960, 1149 0x5961, 1150 0x5962, 1151 0x5964, 1152 0x5965, 1153 0x5969, 1154 0x5a41, 1155 0x5a42, 1156 0x5a61, 1157 0x5a62, 1158 0x5b60, 1159 0x5b62, 1160 0x5b63, 1161 0x5b64, 1162 0x5b65, 1163 0x5c61, 1164 0x5c63, 1165 0x5d48, 1166 0x5d49, 1167 0x5d4a, 1168 0x5d4c, 1169 0x5d4d, 1170 0x5d4e, 1171 0x5d4f, 1172 0x5d50, 1173 0x5d52, 1174 0x5d57, 1175 0x5e48, 1176 0x5e4a, 1177 0x5e4b, 1178 0x5e4c, 1179 0x5e4d, 1180 0x5e4f, 1181 0x6700, 1182 0x6701, 1183 0x6702, 1184 0x6703, 1185 0x6704, 1186 0x6705, 1187 0x6706, 1188 0x6707, 1189 0x6708, 1190 0x6709, 1191 0x6718, 1192 0x6719, 1193 0x671c, 1194 0x671d, 1195 0x671f, 1196 0x6720, 1197 0x6721, 1198 0x6722, 1199 0x6723, 1200 0x6724, 1201 0x6725, 1202 0x6726, 1203 0x6727, 1204 0x6728, 1205 0x6729, 1206 0x6738, 1207 0x6739, 1208 0x673e, 1209 0x6740, 1210 0x6741, 1211 0x6742, 1212 0x6743, 1213 0x6744, 1214 0x6745, 1215 0x6746, 1216 0x6747, 1217 0x6748, 1218 0x6749, 1219 0x674A, 1220 0x6750, 1221 0x6751, 1222 0x6758, 1223 0x6759, 1224 0x675B, 1225 0x675D, 1226 0x675F, 1227 0x6760, 1228 0x6761, 1229 0x6762, 1230 0x6763, 1231 0x6764, 1232 0x6765, 1233 0x6766, 1234 0x6767, 1235 0x6768, 1236 0x6770, 1237 0x6771, 1238 0x6772, 1239 0x6778, 1240 0x6779, 1241 0x677B, 1242 0x6840, 1243 0x6841, 1244 0x6842, 1245 0x6843, 1246 0x6849, 1247 0x684C, 1248 0x6850, 1249 0x6858, 1250 0x6859, 1251 0x6880, 1252 0x6888, 1253 0x6889, 1254 0x688A, 1255 0x688C, 1256 0x688D, 1257 0x6898, 1258 0x6899, 1259 0x689b, 1260 0x689c, 1261 0x689d, 1262 0x689e, 1263 0x68a0, 1264 0x68a1, 1265 0x68a8, 1266 0x68a9, 1267 0x68b0, 1268 0x68b8, 1269 0x68b9, 1270 0x68ba, 1271 0x68be, 1272 0x68bf, 1273 0x68c0, 1274 0x68c1, 1275 0x68c7, 1276 0x68c8, 1277 0x68c9, 1278 0x68d8, 1279 0x68d9, 1280 0x68da, 1281 0x68de, 1282 0x68e0, 1283 0x68e1, 1284 0x68e4, 1285 0x68e5, 1286 0x68e8, 1287 0x68e9, 1288 0x68f1, 1289 0x68f2, 1290 0x68f8, 1291 0x68f9, 1292 0x68fa, 1293 0x68fe, 1294 0x7100, 1295 0x7101, 1296 0x7102, 1297 0x7103, 1298 0x7104, 1299 0x7105, 1300 0x7106, 1301 0x7108, 1302 0x7109, 1303 0x710A, 1304 0x710B, 1305 0x710C, 1306 0x710E, 1307 0x710F, 1308 0x7140, 1309 0x7141, 1310 0x7142, 1311 0x7143, 1312 0x7144, 1313 0x7145, 1314 0x7146, 1315 0x7147, 1316 0x7149, 1317 0x714A, 1318 0x714B, 1319 0x714C, 1320 0x714D, 1321 0x714E, 1322 0x714F, 1323 0x7151, 1324 0x7152, 1325 0x7153, 1326 0x715E, 1327 0x715F, 1328 0x7180, 1329 0x7181, 1330 0x7183, 1331 0x7186, 1332 0x7187, 1333 0x7188, 1334 0x718A, 1335 0x718B, 1336 0x718C, 1337 0x718D, 1338 0x718F, 1339 0x7193, 1340 0x7196, 1341 0x719B, 1342 0x719F, 1343 0x71C0, 1344 0x71C1, 1345 0x71C2, 1346 0x71C3, 1347 0x71C4, 1348 0x71C5, 1349 0x71C6, 1350 0x71C7, 1351 0x71CD, 1352 0x71CE, 1353 0x71D2, 1354 0x71D4, 1355 0x71D5, 1356 0x71D6, 1357 0x71DA, 1358 0x71DE, 1359 0x7200, 1360 0x7210, 1361 0x7211, 1362 0x7240, 1363 0x7243, 1364 0x7244, 1365 0x7245, 1366 0x7246, 1367 0x7247, 1368 0x7248, 1369 0x7249, 1370 0x724A, 1371 0x724B, 1372 0x724C, 1373 0x724D, 1374 0x724E, 1375 0x724F, 1376 0x7280, 1377 0x7281, 1378 0x7283, 1379 0x7284, 1380 0x7287, 1381 0x7288, 1382 0x7289, 1383 0x728B, 1384 0x728C, 1385 0x7290, 1386 0x7291, 1387 0x7293, 1388 0x7297, 1389 0x7834, 1390 0x7835, 1391 0x791e, 1392 0x791f, 1393 0x793f, 1394 0x7941, 1395 0x7942, 1396 0x796c, 1397 0x796d, 1398 0x796e, 1399 0x796f, 1400 0x9400, 1401 0x9401, 1402 0x9402, 1403 0x9403, 1404 0x9405, 1405 0x940A, 1406 0x940B, 1407 0x940F, 1408 0x94A0, 1409 0x94A1, 1410 0x94A3, 1411 0x94B1, 1412 0x94B3, 1413 0x94B4, 1414 0x94B5, 1415 0x94B9, 1416 0x9440, 1417 0x9441, 1418 0x9442, 1419 0x9443, 1420 0x9444, 1421 0x9446, 1422 0x944A, 1423 0x944B, 1424 0x944C, 1425 0x944E, 1426 0x9450, 1427 0x9452, 1428 0x9456, 1429 0x945A, 1430 0x945B, 1431 0x945E, 1432 0x9460, 1433 0x9462, 1434 0x946A, 1435 0x946B, 1436 0x947A, 1437 0x947B, 1438 0x9480, 1439 0x9487, 1440 0x9488, 1441 0x9489, 1442 0x948A, 1443 0x948F, 1444 0x9490, 1445 0x9491, 1446 0x9495, 1447 0x9498, 1448 0x949C, 1449 0x949E, 1450 0x949F, 1451 0x94C0, 1452 0x94C1, 1453 0x94C3, 1454 0x94C4, 1455 0x94C5, 1456 0x94C6, 1457 0x94C7, 1458 0x94C8, 1459 0x94C9, 1460 0x94CB, 1461 0x94CC, 1462 0x94CD, 1463 0x9500, 1464 0x9501, 1465 0x9504, 1466 0x9505, 1467 0x9506, 1468 0x9507, 1469 0x9508, 1470 0x9509, 1471 0x950F, 1472 0x9511, 1473 0x9515, 1474 0x9517, 1475 0x9519, 1476 0x9540, 1477 0x9541, 1478 0x9542, 1479 0x954E, 1480 0x954F, 1481 0x9552, 1482 0x9553, 1483 0x9555, 1484 0x9557, 1485 0x955f, 1486 0x9580, 1487 0x9581, 1488 0x9583, 1489 0x9586, 1490 0x9587, 1491 0x9588, 1492 0x9589, 1493 0x958A, 1494 0x958B, 1495 0x958C, 1496 0x958D, 1497 0x958E, 1498 0x958F, 1499 0x9590, 1500 0x9591, 1501 0x9593, 1502 0x9595, 1503 0x9596, 1504 0x9597, 1505 0x9598, 1506 0x9599, 1507 0x959B, 1508 0x95C0, 1509 0x95C2, 1510 0x95C4, 1511 0x95C5, 1512 0x95C6, 1513 0x95C7, 1514 0x95C9, 1515 0x95CC, 1516 0x95CD, 1517 0x95CE, 1518 0x95CF, 1519 0x9610, 1520 0x9611, 1521 0x9612, 1522 0x9613, 1523 0x9614, 1524 0x9615, 1525 0x9616, 1526 0x9640, 1527 0x9641, 1528 0x9642, 1529 0x9643, 1530 0x9644, 1531 0x9645, 1532 0x9647, 1533 0x9648, 1534 0x9649, 1535 0x964a, 1536 0x964b, 1537 0x964c, 1538 0x964e, 1539 0x964f, 1540 0x9710, 1541 0x9711, 1542 0x9712, 1543 0x9713, 1544 0x9714, 1545 0x9715, 1546 0x9802, 1547 0x9803, 1548 0x9804, 1549 0x9805, 1550 0x9806, 1551 0x9807, 1552 0x9808, 1553 0x9809, 1554 0x980A, 1555 0x9900, 1556 0x9901, 1557 0x9903, 1558 0x9904, 1559 0x9905, 1560 0x9906, 1561 0x9907, 1562 0x9908, 1563 0x9909, 1564 0x990A, 1565 0x990B, 1566 0x990C, 1567 0x990D, 1568 0x990E, 1569 0x990F, 1570 0x9910, 1571 0x9913, 1572 0x9917, 1573 0x9918, 1574 0x9919, 1575 0x9990, 1576 0x9991, 1577 0x9992, 1578 0x9993, 1579 0x9994, 1580 0x9995, 1581 0x9996, 1582 0x9997, 1583 0x9998, 1584 0x9999, 1585 0x999A, 1586 0x999B, 1587 0x999C, 1588 0x999D, 1589 0x99A0, 1590 0x99A2, 1591 0x99A4, 1592 /* radeon secondary ids */ 1593 0x3171, 1594 0x3e70, 1595 0x4164, 1596 0x4165, 1597 0x4166, 1598 0x4168, 1599 0x4170, 1600 0x4171, 1601 0x4172, 1602 0x4173, 1603 0x496e, 1604 0x4a69, 1605 0x4a6a, 1606 0x4a6b, 1607 0x4a70, 1608 0x4a74, 1609 0x4b69, 1610 0x4b6b, 1611 0x4b6c, 1612 0x4c6e, 1613 0x4e64, 1614 0x4e65, 1615 0x4e66, 1616 0x4e67, 1617 0x4e68, 1618 0x4e69, 1619 0x4e6a, 1620 0x4e71, 1621 0x4f73, 1622 0x5569, 1623 0x556b, 1624 0x556d, 1625 0x556f, 1626 0x5571, 1627 0x5854, 1628 0x5874, 1629 0x5940, 1630 0x5941, 1631 0x5b70, 1632 0x5b72, 1633 0x5b73, 1634 0x5b74, 1635 0x5b75, 1636 0x5d44, 1637 0x5d45, 1638 0x5d6d, 1639 0x5d6f, 1640 0x5d72, 1641 0x5d77, 1642 0x5e6b, 1643 0x5e6d, 1644 0x7120, 1645 0x7124, 1646 0x7129, 1647 0x712e, 1648 0x712f, 1649 0x7162, 1650 0x7163, 1651 0x7166, 1652 0x7167, 1653 0x7172, 1654 0x7173, 1655 0x71a0, 1656 0x71a1, 1657 0x71a3, 1658 0x71a7, 1659 0x71bb, 1660 0x71e0, 1661 0x71e1, 1662 0x71e2, 1663 0x71e6, 1664 0x71e7, 1665 0x71f2, 1666 0x7269, 1667 0x726b, 1668 0x726e, 1669 0x72a0, 1670 0x72a8, 1671 0x72b1, 1672 0x72b3, 1673 0x793f, 1674 }; 1675 1676 static const struct pci_device_id pciidlist[] = { 1677 #ifdef CONFIG_DRM_AMDGPU_SI 1678 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1679 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1680 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1681 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1682 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1683 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1684 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1685 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1686 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1687 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1688 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1689 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1690 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1691 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1692 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1693 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1694 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1695 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1696 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1697 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1698 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1699 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1700 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1701 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1702 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1703 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1704 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1705 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1706 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1707 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1708 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1709 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1710 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1711 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1712 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1713 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1714 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1715 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1716 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1717 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1718 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1719 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1720 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1721 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1722 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1723 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1724 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1725 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1726 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1727 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1728 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1729 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1730 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1731 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1732 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1733 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1734 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1735 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1736 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1737 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1738 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1739 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1740 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1741 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1742 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1743 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1744 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1745 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1746 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1747 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1748 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1749 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1750 #endif 1751 #ifdef CONFIG_DRM_AMDGPU_CIK 1752 /* Kaveri */ 1753 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1754 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1755 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1756 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1757 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1758 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1759 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1760 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1761 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1762 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1763 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1764 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1765 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1766 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1767 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1768 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1769 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1770 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1771 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1772 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1773 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1774 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1775 /* Bonaire */ 1776 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1777 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1778 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1779 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1780 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1781 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1782 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1783 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1784 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1785 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1786 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1787 /* Hawaii */ 1788 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1789 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1790 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1791 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1792 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1793 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1794 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1795 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1796 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1797 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1798 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1799 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1800 /* Kabini */ 1801 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1802 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1803 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1804 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1805 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1806 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1807 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1808 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1809 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1810 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1811 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1812 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1813 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1814 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1815 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1816 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1817 /* mullins */ 1818 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1819 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1820 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1821 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1822 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1823 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1824 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1825 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1826 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1827 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1828 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1829 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1830 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1831 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1832 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1833 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1834 #endif 1835 /* topaz */ 1836 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1837 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1838 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1839 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1840 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1841 /* tonga */ 1842 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1843 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1844 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1845 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1846 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1847 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1848 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1849 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1850 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1851 /* fiji */ 1852 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1853 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1854 /* carrizo */ 1855 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1856 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1857 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1858 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1859 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1860 /* stoney */ 1861 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1862 /* Polaris11 */ 1863 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1864 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1865 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1866 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1867 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1868 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1869 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1870 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1871 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1872 /* Polaris10 */ 1873 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1874 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1875 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1876 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1877 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1878 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1879 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1880 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1881 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1882 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1883 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1884 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1885 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1886 /* Polaris12 */ 1887 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1888 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1889 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1890 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1891 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1892 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1893 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1894 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1895 /* VEGAM */ 1896 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1897 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1898 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1899 /* Vega 10 */ 1900 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1901 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1902 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1903 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1904 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1905 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1906 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1907 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1908 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1909 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1910 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1911 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1912 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1913 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1914 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1915 /* Vega 12 */ 1916 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1917 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1918 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1919 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1920 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1921 /* Vega 20 */ 1922 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1923 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1924 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1925 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1926 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1927 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1928 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1929 /* Raven */ 1930 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1931 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1932 /* Arcturus */ 1933 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1934 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1935 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1936 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1937 /* Navi10 */ 1938 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1939 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1940 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1941 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1942 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1943 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1944 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1945 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1946 /* Navi14 */ 1947 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1948 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1949 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1950 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1951 1952 /* Renoir */ 1953 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1954 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1955 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1956 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1957 1958 /* Navi12 */ 1959 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1960 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1961 1962 /* Sienna_Cichlid */ 1963 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1964 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1965 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1966 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1967 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1968 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1969 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1970 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1971 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1972 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1973 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1974 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1975 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1976 1977 /* Yellow Carp */ 1978 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1979 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1980 1981 /* Navy_Flounder */ 1982 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1983 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1984 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1985 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1986 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1987 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1988 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1989 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1990 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1991 1992 /* DIMGREY_CAVEFISH */ 1993 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1994 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1995 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1996 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1997 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1998 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1999 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2000 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2001 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2002 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2003 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2004 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2005 2006 /* Aldebaran */ 2007 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2008 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2009 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2010 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2011 2012 /* CYAN_SKILLFISH */ 2013 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2014 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2015 2016 /* BEIGE_GOBY */ 2017 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2018 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2019 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2020 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2021 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2022 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2023 2024 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2025 .class = PCI_CLASS_DISPLAY_VGA << 8, 2026 .class_mask = 0xffffff, 2027 .driver_data = CHIP_IP_DISCOVERY }, 2028 2029 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2030 .class = PCI_CLASS_DISPLAY_OTHER << 8, 2031 .class_mask = 0xffffff, 2032 .driver_data = CHIP_IP_DISCOVERY }, 2033 2034 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2035 .class = PCI_CLASS_ACCELERATOR_PROCESSING << 8, 2036 .class_mask = 0xffffff, 2037 .driver_data = CHIP_IP_DISCOVERY }, 2038 2039 {0, 0, 0} 2040 }; 2041 2042 MODULE_DEVICE_TABLE(pci, pciidlist); 2043 2044 static const struct drm_driver amdgpu_kms_driver; 2045 2046 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 2047 { 2048 struct pci_dev *p = NULL; 2049 int i; 2050 2051 /* 0 - GPU 2052 * 1 - audio 2053 * 2 - USB 2054 * 3 - UCSI 2055 */ 2056 for (i = 1; i < 4; i++) { 2057 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 2058 adev->pdev->bus->number, i); 2059 if (p) { 2060 pm_runtime_get_sync(&p->dev); 2061 pm_runtime_mark_last_busy(&p->dev); 2062 pm_runtime_put_autosuspend(&p->dev); 2063 pci_dev_put(p); 2064 } 2065 } 2066 } 2067 2068 static void amdgpu_init_debug_options(struct amdgpu_device *adev) 2069 { 2070 if (amdgpu_debug_mask & AMDGPU_DEBUG_VM) { 2071 pr_info("debug: VM handling debug enabled\n"); 2072 adev->debug_vm = true; 2073 } 2074 2075 if (amdgpu_debug_mask & AMDGPU_DEBUG_LARGEBAR) { 2076 pr_info("debug: enabled simulating large-bar capability on non-large bar system\n"); 2077 adev->debug_largebar = true; 2078 } 2079 2080 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY) { 2081 pr_info("debug: soft reset for GPU recovery disabled\n"); 2082 adev->debug_disable_soft_recovery = true; 2083 } 2084 } 2085 2086 static int amdgpu_pci_probe(struct pci_dev *pdev, 2087 const struct pci_device_id *ent) 2088 { 2089 struct drm_device *ddev; 2090 struct amdgpu_device *adev; 2091 unsigned long flags = ent->driver_data; 2092 int ret, retry = 0, i; 2093 bool supports_atomic = false; 2094 2095 /* skip devices which are owned by radeon */ 2096 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2097 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2098 return -ENODEV; 2099 } 2100 2101 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) 2102 amdgpu_aspm = 0; 2103 2104 if (amdgpu_virtual_display || 2105 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 2106 supports_atomic = true; 2107 2108 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2109 DRM_INFO("This hardware requires experimental hardware support.\n" 2110 "See modparam exp_hw_support\n"); 2111 return -ENODEV; 2112 } 2113 /* differentiate between P10 and P11 asics with the same DID */ 2114 if (pdev->device == 0x67FF && 2115 (pdev->revision == 0xE3 || 2116 pdev->revision == 0xE7 || 2117 pdev->revision == 0xF3 || 2118 pdev->revision == 0xF7)) { 2119 flags &= ~AMD_ASIC_MASK; 2120 flags |= CHIP_POLARIS10; 2121 } 2122 2123 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2124 * however, SME requires an indirect IOMMU mapping because the encryption 2125 * bit is beyond the DMA mask of the chip. 2126 */ 2127 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2128 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2129 dev_info(&pdev->dev, 2130 "SME is not compatible with RAVEN\n"); 2131 return -ENOTSUPP; 2132 } 2133 2134 #ifdef CONFIG_DRM_AMDGPU_SI 2135 if (!amdgpu_si_support) { 2136 switch (flags & AMD_ASIC_MASK) { 2137 case CHIP_TAHITI: 2138 case CHIP_PITCAIRN: 2139 case CHIP_VERDE: 2140 case CHIP_OLAND: 2141 case CHIP_HAINAN: 2142 dev_info(&pdev->dev, 2143 "SI support provided by radeon.\n"); 2144 dev_info(&pdev->dev, 2145 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 2146 ); 2147 return -ENODEV; 2148 } 2149 } 2150 #endif 2151 #ifdef CONFIG_DRM_AMDGPU_CIK 2152 if (!amdgpu_cik_support) { 2153 switch (flags & AMD_ASIC_MASK) { 2154 case CHIP_KAVERI: 2155 case CHIP_BONAIRE: 2156 case CHIP_HAWAII: 2157 case CHIP_KABINI: 2158 case CHIP_MULLINS: 2159 dev_info(&pdev->dev, 2160 "CIK support provided by radeon.\n"); 2161 dev_info(&pdev->dev, 2162 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 2163 ); 2164 return -ENODEV; 2165 } 2166 } 2167 #endif 2168 2169 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2170 if (IS_ERR(adev)) 2171 return PTR_ERR(adev); 2172 2173 adev->dev = &pdev->dev; 2174 adev->pdev = pdev; 2175 ddev = adev_to_drm(adev); 2176 2177 if (!supports_atomic) 2178 ddev->driver_features &= ~DRIVER_ATOMIC; 2179 2180 ret = pci_enable_device(pdev); 2181 if (ret) 2182 return ret; 2183 2184 pci_set_drvdata(pdev, ddev); 2185 2186 ret = amdgpu_driver_load_kms(adev, flags); 2187 if (ret) 2188 goto err_pci; 2189 2190 retry_init: 2191 ret = drm_dev_register(ddev, flags); 2192 if (ret == -EAGAIN && ++retry <= 3) { 2193 DRM_INFO("retry init %d\n", retry); 2194 /* Don't request EX mode too frequently which is attacking */ 2195 msleep(5000); 2196 goto retry_init; 2197 } else if (ret) { 2198 goto err_pci; 2199 } 2200 2201 ret = amdgpu_xcp_dev_register(adev, ent); 2202 if (ret) 2203 goto err_pci; 2204 2205 /* 2206 * 1. don't init fbdev on hw without DCE 2207 * 2. don't init fbdev if there are no connectors 2208 */ 2209 if (adev->mode_info.mode_config_initialized && 2210 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2211 /* select 8 bpp console on low vram cards */ 2212 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2213 drm_fbdev_generic_setup(adev_to_drm(adev), 8); 2214 else 2215 drm_fbdev_generic_setup(adev_to_drm(adev), 32); 2216 } 2217 2218 ret = amdgpu_debugfs_init(adev); 2219 if (ret) 2220 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2221 2222 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2223 /* only need to skip on ATPX */ 2224 if (amdgpu_device_supports_px(ddev)) 2225 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2226 /* we want direct complete for BOCO */ 2227 if (amdgpu_device_supports_boco(ddev)) 2228 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2229 DPM_FLAG_SMART_SUSPEND | 2230 DPM_FLAG_MAY_SKIP_RESUME); 2231 pm_runtime_use_autosuspend(ddev->dev); 2232 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2233 2234 pm_runtime_allow(ddev->dev); 2235 2236 pm_runtime_mark_last_busy(ddev->dev); 2237 pm_runtime_put_autosuspend(ddev->dev); 2238 2239 /* 2240 * For runpm implemented via BACO, PMFW will handle the 2241 * timing for BACO in and out: 2242 * - put ASIC into BACO state only when both video and 2243 * audio functions are in D3 state. 2244 * - pull ASIC out of BACO state when either video or 2245 * audio function is in D0 state. 2246 * Also, at startup, PMFW assumes both functions are in 2247 * D0 state. 2248 * 2249 * So if snd driver was loaded prior to amdgpu driver 2250 * and audio function was put into D3 state, there will 2251 * be no PMFW-aware D-state transition(D0->D3) on runpm 2252 * suspend. Thus the BACO will be not correctly kicked in. 2253 * 2254 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2255 * into D0 state. Then there will be a PMFW-aware D-state 2256 * transition(D0->D3) on runpm suspend. 2257 */ 2258 if (amdgpu_device_supports_baco(ddev) && 2259 !(adev->flags & AMD_IS_APU) && 2260 (adev->asic_type >= CHIP_NAVI10)) 2261 amdgpu_get_secondary_funcs(adev); 2262 } 2263 2264 amdgpu_init_debug_options(adev); 2265 2266 return 0; 2267 2268 err_pci: 2269 pci_disable_device(pdev); 2270 return ret; 2271 } 2272 2273 static void 2274 amdgpu_pci_remove(struct pci_dev *pdev) 2275 { 2276 struct drm_device *dev = pci_get_drvdata(pdev); 2277 struct amdgpu_device *adev = drm_to_adev(dev); 2278 2279 amdgpu_xcp_dev_unplug(adev); 2280 drm_dev_unplug(dev); 2281 2282 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2283 pm_runtime_get_sync(dev->dev); 2284 pm_runtime_forbid(dev->dev); 2285 } 2286 2287 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 2) && 2288 !amdgpu_sriov_vf(adev)) { 2289 bool need_to_reset_gpu = false; 2290 2291 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2292 struct amdgpu_hive_info *hive; 2293 2294 hive = amdgpu_get_xgmi_hive(adev); 2295 if (hive->device_remove_count == 0) 2296 need_to_reset_gpu = true; 2297 hive->device_remove_count++; 2298 amdgpu_put_xgmi_hive(hive); 2299 } else { 2300 need_to_reset_gpu = true; 2301 } 2302 2303 /* Workaround for ASICs need to reset SMU. 2304 * Called only when the first device is removed. 2305 */ 2306 if (need_to_reset_gpu) { 2307 struct amdgpu_reset_context reset_context; 2308 2309 adev->shutdown = true; 2310 memset(&reset_context, 0, sizeof(reset_context)); 2311 reset_context.method = AMD_RESET_METHOD_NONE; 2312 reset_context.reset_req_dev = adev; 2313 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2314 set_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context.flags); 2315 amdgpu_device_gpu_recover(adev, NULL, &reset_context); 2316 } 2317 } 2318 2319 amdgpu_driver_unload_kms(dev); 2320 2321 /* 2322 * Flush any in flight DMA operations from device. 2323 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2324 * StatusTransactions Pending bit. 2325 */ 2326 pci_disable_device(pdev); 2327 pci_wait_for_pending_transaction(pdev); 2328 } 2329 2330 static void 2331 amdgpu_pci_shutdown(struct pci_dev *pdev) 2332 { 2333 struct drm_device *dev = pci_get_drvdata(pdev); 2334 struct amdgpu_device *adev = drm_to_adev(dev); 2335 2336 if (amdgpu_ras_intr_triggered()) 2337 return; 2338 2339 /* if we are running in a VM, make sure the device 2340 * torn down properly on reboot/shutdown. 2341 * unfortunately we can't detect certain 2342 * hypervisors so just do this all the time. 2343 */ 2344 if (!amdgpu_passthrough(adev)) 2345 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2346 amdgpu_device_ip_suspend(adev); 2347 adev->mp1_state = PP_MP1_STATE_NONE; 2348 } 2349 2350 /** 2351 * amdgpu_drv_delayed_reset_work_handler - work handler for reset 2352 * 2353 * @work: work_struct. 2354 */ 2355 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) 2356 { 2357 struct list_head device_list; 2358 struct amdgpu_device *adev; 2359 int i, r; 2360 struct amdgpu_reset_context reset_context; 2361 2362 memset(&reset_context, 0, sizeof(reset_context)); 2363 2364 mutex_lock(&mgpu_info.mutex); 2365 if (mgpu_info.pending_reset == true) { 2366 mutex_unlock(&mgpu_info.mutex); 2367 return; 2368 } 2369 mgpu_info.pending_reset = true; 2370 mutex_unlock(&mgpu_info.mutex); 2371 2372 /* Use a common context, just need to make sure full reset is done */ 2373 reset_context.method = AMD_RESET_METHOD_NONE; 2374 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2375 2376 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2377 adev = mgpu_info.gpu_ins[i].adev; 2378 reset_context.reset_req_dev = adev; 2379 r = amdgpu_device_pre_asic_reset(adev, &reset_context); 2380 if (r) { 2381 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", 2382 r, adev_to_drm(adev)->unique); 2383 } 2384 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) 2385 r = -EALREADY; 2386 } 2387 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2388 adev = mgpu_info.gpu_ins[i].adev; 2389 flush_work(&adev->xgmi_reset_work); 2390 adev->gmc.xgmi.pending_reset = false; 2391 } 2392 2393 /* reset function will rebuild the xgmi hive info , clear it now */ 2394 for (i = 0; i < mgpu_info.num_dgpu; i++) 2395 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); 2396 2397 INIT_LIST_HEAD(&device_list); 2398 2399 for (i = 0; i < mgpu_info.num_dgpu; i++) 2400 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); 2401 2402 /* unregister the GPU first, reset function will add them back */ 2403 list_for_each_entry(adev, &device_list, reset_list) 2404 amdgpu_unregister_gpu_instance(adev); 2405 2406 /* Use a common context, just need to make sure full reset is done */ 2407 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); 2408 r = amdgpu_do_asic_reset(&device_list, &reset_context); 2409 2410 if (r) { 2411 DRM_ERROR("reinit gpus failure"); 2412 return; 2413 } 2414 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2415 adev = mgpu_info.gpu_ins[i].adev; 2416 if (!adev->kfd.init_complete) 2417 amdgpu_amdkfd_device_init(adev); 2418 amdgpu_ttm_set_buffer_funcs_status(adev, true); 2419 } 2420 } 2421 2422 static int amdgpu_pmops_prepare(struct device *dev) 2423 { 2424 struct drm_device *drm_dev = dev_get_drvdata(dev); 2425 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2426 2427 /* Return a positive number here so 2428 * DPM_FLAG_SMART_SUSPEND works properly 2429 */ 2430 if (amdgpu_device_supports_boco(drm_dev) && 2431 pm_runtime_suspended(dev)) 2432 return 1; 2433 2434 /* if we will not support s3 or s2i for the device 2435 * then skip suspend 2436 */ 2437 if (!amdgpu_acpi_is_s0ix_active(adev) && 2438 !amdgpu_acpi_is_s3_active(adev)) 2439 return 1; 2440 2441 return amdgpu_device_prepare(drm_dev); 2442 } 2443 2444 static void amdgpu_pmops_complete(struct device *dev) 2445 { 2446 /* nothing to do */ 2447 } 2448 2449 static int amdgpu_pmops_suspend(struct device *dev) 2450 { 2451 struct drm_device *drm_dev = dev_get_drvdata(dev); 2452 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2453 2454 if (amdgpu_acpi_is_s0ix_active(adev)) 2455 adev->in_s0ix = true; 2456 else if (amdgpu_acpi_is_s3_active(adev)) 2457 adev->in_s3 = true; 2458 if (!adev->in_s0ix && !adev->in_s3) 2459 return 0; 2460 return amdgpu_device_suspend(drm_dev, true); 2461 } 2462 2463 static int amdgpu_pmops_suspend_noirq(struct device *dev) 2464 { 2465 struct drm_device *drm_dev = dev_get_drvdata(dev); 2466 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2467 2468 if (amdgpu_acpi_should_gpu_reset(adev)) 2469 return amdgpu_asic_reset(adev); 2470 2471 return 0; 2472 } 2473 2474 static int amdgpu_pmops_resume(struct device *dev) 2475 { 2476 struct drm_device *drm_dev = dev_get_drvdata(dev); 2477 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2478 int r; 2479 2480 if (!adev->in_s0ix && !adev->in_s3) 2481 return 0; 2482 2483 /* Avoids registers access if device is physically gone */ 2484 if (!pci_device_is_present(adev->pdev)) 2485 adev->no_hw_access = true; 2486 2487 r = amdgpu_device_resume(drm_dev, true); 2488 if (amdgpu_acpi_is_s0ix_active(adev)) 2489 adev->in_s0ix = false; 2490 else 2491 adev->in_s3 = false; 2492 return r; 2493 } 2494 2495 static int amdgpu_pmops_freeze(struct device *dev) 2496 { 2497 struct drm_device *drm_dev = dev_get_drvdata(dev); 2498 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2499 int r; 2500 2501 adev->in_s4 = true; 2502 r = amdgpu_device_suspend(drm_dev, true); 2503 adev->in_s4 = false; 2504 if (r) 2505 return r; 2506 2507 if (amdgpu_acpi_should_gpu_reset(adev)) 2508 return amdgpu_asic_reset(adev); 2509 return 0; 2510 } 2511 2512 static int amdgpu_pmops_thaw(struct device *dev) 2513 { 2514 struct drm_device *drm_dev = dev_get_drvdata(dev); 2515 2516 return amdgpu_device_resume(drm_dev, true); 2517 } 2518 2519 static int amdgpu_pmops_poweroff(struct device *dev) 2520 { 2521 struct drm_device *drm_dev = dev_get_drvdata(dev); 2522 2523 return amdgpu_device_suspend(drm_dev, true); 2524 } 2525 2526 static int amdgpu_pmops_restore(struct device *dev) 2527 { 2528 struct drm_device *drm_dev = dev_get_drvdata(dev); 2529 2530 return amdgpu_device_resume(drm_dev, true); 2531 } 2532 2533 static int amdgpu_runtime_idle_check_display(struct device *dev) 2534 { 2535 struct pci_dev *pdev = to_pci_dev(dev); 2536 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2537 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2538 2539 if (adev->mode_info.num_crtc) { 2540 struct drm_connector *list_connector; 2541 struct drm_connector_list_iter iter; 2542 int ret = 0; 2543 2544 if (amdgpu_runtime_pm != -2) { 2545 /* XXX: Return busy if any displays are connected to avoid 2546 * possible display wakeups after runtime resume due to 2547 * hotplug events in case any displays were connected while 2548 * the GPU was in suspend. Remove this once that is fixed. 2549 */ 2550 mutex_lock(&drm_dev->mode_config.mutex); 2551 drm_connector_list_iter_begin(drm_dev, &iter); 2552 drm_for_each_connector_iter(list_connector, &iter) { 2553 if (list_connector->status == connector_status_connected) { 2554 ret = -EBUSY; 2555 break; 2556 } 2557 } 2558 drm_connector_list_iter_end(&iter); 2559 mutex_unlock(&drm_dev->mode_config.mutex); 2560 2561 if (ret) 2562 return ret; 2563 } 2564 2565 if (adev->dc_enabled) { 2566 struct drm_crtc *crtc; 2567 2568 drm_for_each_crtc(crtc, drm_dev) { 2569 drm_modeset_lock(&crtc->mutex, NULL); 2570 if (crtc->state->active) 2571 ret = -EBUSY; 2572 drm_modeset_unlock(&crtc->mutex); 2573 if (ret < 0) 2574 break; 2575 } 2576 } else { 2577 mutex_lock(&drm_dev->mode_config.mutex); 2578 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2579 2580 drm_connector_list_iter_begin(drm_dev, &iter); 2581 drm_for_each_connector_iter(list_connector, &iter) { 2582 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2583 ret = -EBUSY; 2584 break; 2585 } 2586 } 2587 2588 drm_connector_list_iter_end(&iter); 2589 2590 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2591 mutex_unlock(&drm_dev->mode_config.mutex); 2592 } 2593 if (ret) 2594 return ret; 2595 } 2596 2597 return 0; 2598 } 2599 2600 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2601 { 2602 struct pci_dev *pdev = to_pci_dev(dev); 2603 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2604 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2605 int ret, i; 2606 2607 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2608 pm_runtime_forbid(dev); 2609 return -EBUSY; 2610 } 2611 2612 ret = amdgpu_runtime_idle_check_display(dev); 2613 if (ret) 2614 return ret; 2615 2616 /* wait for all rings to drain before suspending */ 2617 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2618 struct amdgpu_ring *ring = adev->rings[i]; 2619 2620 if (ring && ring->sched.ready) { 2621 ret = amdgpu_fence_wait_empty(ring); 2622 if (ret) 2623 return -EBUSY; 2624 } 2625 } 2626 2627 adev->in_runpm = true; 2628 if (amdgpu_device_supports_px(drm_dev)) 2629 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2630 2631 /* 2632 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2633 * proper cleanups and put itself into a state ready for PNP. That 2634 * can address some random resuming failure observed on BOCO capable 2635 * platforms. 2636 * TODO: this may be also needed for PX capable platform. 2637 */ 2638 if (amdgpu_device_supports_boco(drm_dev)) 2639 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2640 2641 ret = amdgpu_device_prepare(drm_dev); 2642 if (ret) 2643 return ret; 2644 ret = amdgpu_device_suspend(drm_dev, false); 2645 if (ret) { 2646 adev->in_runpm = false; 2647 if (amdgpu_device_supports_boco(drm_dev)) 2648 adev->mp1_state = PP_MP1_STATE_NONE; 2649 return ret; 2650 } 2651 2652 if (amdgpu_device_supports_boco(drm_dev)) 2653 adev->mp1_state = PP_MP1_STATE_NONE; 2654 2655 if (amdgpu_device_supports_px(drm_dev)) { 2656 /* Only need to handle PCI state in the driver for ATPX 2657 * PCI core handles it for _PR3. 2658 */ 2659 amdgpu_device_cache_pci_state(pdev); 2660 pci_disable_device(pdev); 2661 pci_ignore_hotplug(pdev); 2662 pci_set_power_state(pdev, PCI_D3cold); 2663 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2664 } else if (amdgpu_device_supports_boco(drm_dev)) { 2665 /* nothing to do */ 2666 } else if (amdgpu_device_supports_baco(drm_dev)) { 2667 amdgpu_device_baco_enter(drm_dev); 2668 } 2669 2670 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n"); 2671 2672 return 0; 2673 } 2674 2675 static int amdgpu_pmops_runtime_resume(struct device *dev) 2676 { 2677 struct pci_dev *pdev = to_pci_dev(dev); 2678 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2679 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2680 int ret; 2681 2682 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) 2683 return -EINVAL; 2684 2685 /* Avoids registers access if device is physically gone */ 2686 if (!pci_device_is_present(adev->pdev)) 2687 adev->no_hw_access = true; 2688 2689 if (amdgpu_device_supports_px(drm_dev)) { 2690 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2691 2692 /* Only need to handle PCI state in the driver for ATPX 2693 * PCI core handles it for _PR3. 2694 */ 2695 pci_set_power_state(pdev, PCI_D0); 2696 amdgpu_device_load_pci_state(pdev); 2697 ret = pci_enable_device(pdev); 2698 if (ret) 2699 return ret; 2700 pci_set_master(pdev); 2701 } else if (amdgpu_device_supports_boco(drm_dev)) { 2702 /* Only need to handle PCI state in the driver for ATPX 2703 * PCI core handles it for _PR3. 2704 */ 2705 pci_set_master(pdev); 2706 } else if (amdgpu_device_supports_baco(drm_dev)) { 2707 amdgpu_device_baco_exit(drm_dev); 2708 } 2709 ret = amdgpu_device_resume(drm_dev, false); 2710 if (ret) { 2711 if (amdgpu_device_supports_px(drm_dev)) 2712 pci_disable_device(pdev); 2713 return ret; 2714 } 2715 2716 if (amdgpu_device_supports_px(drm_dev)) 2717 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2718 adev->in_runpm = false; 2719 return 0; 2720 } 2721 2722 static int amdgpu_pmops_runtime_idle(struct device *dev) 2723 { 2724 struct drm_device *drm_dev = dev_get_drvdata(dev); 2725 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2726 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 2727 int ret = 1; 2728 2729 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2730 pm_runtime_forbid(dev); 2731 return -EBUSY; 2732 } 2733 2734 ret = amdgpu_runtime_idle_check_display(dev); 2735 2736 pm_runtime_mark_last_busy(dev); 2737 pm_runtime_autosuspend(dev); 2738 return ret; 2739 } 2740 2741 long amdgpu_drm_ioctl(struct file *filp, 2742 unsigned int cmd, unsigned long arg) 2743 { 2744 struct drm_file *file_priv = filp->private_data; 2745 struct drm_device *dev; 2746 long ret; 2747 2748 dev = file_priv->minor->dev; 2749 ret = pm_runtime_get_sync(dev->dev); 2750 if (ret < 0) 2751 goto out; 2752 2753 ret = drm_ioctl(filp, cmd, arg); 2754 2755 pm_runtime_mark_last_busy(dev->dev); 2756 out: 2757 pm_runtime_put_autosuspend(dev->dev); 2758 return ret; 2759 } 2760 2761 static const struct dev_pm_ops amdgpu_pm_ops = { 2762 .prepare = amdgpu_pmops_prepare, 2763 .complete = amdgpu_pmops_complete, 2764 .suspend = amdgpu_pmops_suspend, 2765 .suspend_noirq = amdgpu_pmops_suspend_noirq, 2766 .resume = amdgpu_pmops_resume, 2767 .freeze = amdgpu_pmops_freeze, 2768 .thaw = amdgpu_pmops_thaw, 2769 .poweroff = amdgpu_pmops_poweroff, 2770 .restore = amdgpu_pmops_restore, 2771 .runtime_suspend = amdgpu_pmops_runtime_suspend, 2772 .runtime_resume = amdgpu_pmops_runtime_resume, 2773 .runtime_idle = amdgpu_pmops_runtime_idle, 2774 }; 2775 2776 static int amdgpu_flush(struct file *f, fl_owner_t id) 2777 { 2778 struct drm_file *file_priv = f->private_data; 2779 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2780 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2781 2782 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 2783 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 2784 2785 return timeout >= 0 ? 0 : timeout; 2786 } 2787 2788 static const struct file_operations amdgpu_driver_kms_fops = { 2789 .owner = THIS_MODULE, 2790 .open = drm_open, 2791 .flush = amdgpu_flush, 2792 .release = drm_release, 2793 .unlocked_ioctl = amdgpu_drm_ioctl, 2794 .mmap = drm_gem_mmap, 2795 .poll = drm_poll, 2796 .read = drm_read, 2797 #ifdef CONFIG_COMPAT 2798 .compat_ioctl = amdgpu_kms_compat_ioctl, 2799 #endif 2800 #ifdef CONFIG_PROC_FS 2801 .show_fdinfo = drm_show_fdinfo, 2802 #endif 2803 }; 2804 2805 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 2806 { 2807 struct drm_file *file; 2808 2809 if (!filp) 2810 return -EINVAL; 2811 2812 if (filp->f_op != &amdgpu_driver_kms_fops) 2813 return -EINVAL; 2814 2815 file = filp->private_data; 2816 *fpriv = file->driver_priv; 2817 return 0; 2818 } 2819 2820 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 2821 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2822 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2823 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2824 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 2825 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2826 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2827 /* KMS */ 2828 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2829 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2830 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2831 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2832 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2833 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2834 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2835 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2836 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2837 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2838 }; 2839 2840 static const struct drm_driver amdgpu_kms_driver = { 2841 .driver_features = 2842 DRIVER_ATOMIC | 2843 DRIVER_GEM | 2844 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 2845 DRIVER_SYNCOBJ_TIMELINE, 2846 .open = amdgpu_driver_open_kms, 2847 .postclose = amdgpu_driver_postclose_kms, 2848 .lastclose = amdgpu_driver_lastclose_kms, 2849 .ioctls = amdgpu_ioctls_kms, 2850 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2851 .dumb_create = amdgpu_mode_dumb_create, 2852 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2853 .fops = &amdgpu_driver_kms_fops, 2854 .release = &amdgpu_driver_release_kms, 2855 #ifdef CONFIG_PROC_FS 2856 .show_fdinfo = amdgpu_show_fdinfo, 2857 #endif 2858 2859 .gem_prime_import = amdgpu_gem_prime_import, 2860 2861 .name = DRIVER_NAME, 2862 .desc = DRIVER_DESC, 2863 .date = DRIVER_DATE, 2864 .major = KMS_DRIVER_MAJOR, 2865 .minor = KMS_DRIVER_MINOR, 2866 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2867 }; 2868 2869 const struct drm_driver amdgpu_partition_driver = { 2870 .driver_features = 2871 DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ | 2872 DRIVER_SYNCOBJ_TIMELINE, 2873 .open = amdgpu_driver_open_kms, 2874 .postclose = amdgpu_driver_postclose_kms, 2875 .lastclose = amdgpu_driver_lastclose_kms, 2876 .ioctls = amdgpu_ioctls_kms, 2877 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2878 .dumb_create = amdgpu_mode_dumb_create, 2879 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2880 .fops = &amdgpu_driver_kms_fops, 2881 .release = &amdgpu_driver_release_kms, 2882 2883 .gem_prime_import = amdgpu_gem_prime_import, 2884 2885 .name = DRIVER_NAME, 2886 .desc = DRIVER_DESC, 2887 .date = DRIVER_DATE, 2888 .major = KMS_DRIVER_MAJOR, 2889 .minor = KMS_DRIVER_MINOR, 2890 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2891 }; 2892 2893 static struct pci_error_handlers amdgpu_pci_err_handler = { 2894 .error_detected = amdgpu_pci_error_detected, 2895 .mmio_enabled = amdgpu_pci_mmio_enabled, 2896 .slot_reset = amdgpu_pci_slot_reset, 2897 .resume = amdgpu_pci_resume, 2898 }; 2899 2900 static const struct attribute_group *amdgpu_sysfs_groups[] = { 2901 &amdgpu_vram_mgr_attr_group, 2902 &amdgpu_gtt_mgr_attr_group, 2903 &amdgpu_flash_attr_group, 2904 NULL, 2905 }; 2906 2907 static struct pci_driver amdgpu_kms_pci_driver = { 2908 .name = DRIVER_NAME, 2909 .id_table = pciidlist, 2910 .probe = amdgpu_pci_probe, 2911 .remove = amdgpu_pci_remove, 2912 .shutdown = amdgpu_pci_shutdown, 2913 .driver.pm = &amdgpu_pm_ops, 2914 .err_handler = &amdgpu_pci_err_handler, 2915 .dev_groups = amdgpu_sysfs_groups, 2916 }; 2917 2918 static int __init amdgpu_init(void) 2919 { 2920 int r; 2921 2922 if (drm_firmware_drivers_only()) 2923 return -EINVAL; 2924 2925 r = amdgpu_sync_init(); 2926 if (r) 2927 goto error_sync; 2928 2929 r = amdgpu_fence_slab_init(); 2930 if (r) 2931 goto error_fence; 2932 2933 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 2934 amdgpu_register_atpx_handler(); 2935 amdgpu_acpi_detect(); 2936 2937 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 2938 amdgpu_amdkfd_init(); 2939 2940 /* let modprobe override vga console setting */ 2941 return pci_register_driver(&amdgpu_kms_pci_driver); 2942 2943 error_fence: 2944 amdgpu_sync_fini(); 2945 2946 error_sync: 2947 return r; 2948 } 2949 2950 static void __exit amdgpu_exit(void) 2951 { 2952 amdgpu_amdkfd_fini(); 2953 pci_unregister_driver(&amdgpu_kms_pci_driver); 2954 amdgpu_unregister_atpx_handler(); 2955 amdgpu_acpi_release(); 2956 amdgpu_sync_fini(); 2957 amdgpu_fence_slab_fini(); 2958 mmu_notifier_synchronize(); 2959 amdgpu_xcp_drv_release(); 2960 } 2961 2962 module_init(amdgpu_init); 2963 module_exit(amdgpu_exit); 2964 2965 MODULE_AUTHOR(DRIVER_AUTHOR); 2966 MODULE_DESCRIPTION(DRIVER_DESC); 2967 MODULE_LICENSE("GPL and additional rights"); 2968