1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_drv.h> 27 #include <drm/drm_fbdev_generic.h> 28 #include <drm/drm_gem.h> 29 #include <drm/drm_managed.h> 30 #include <drm/drm_pciids.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/drm_vblank.h> 33 34 #include <linux/cc_platform.h> 35 #include <linux/dynamic_debug.h> 36 #include <linux/module.h> 37 #include <linux/mmu_notifier.h> 38 #include <linux/pm_runtime.h> 39 #include <linux/suspend.h> 40 #include <linux/vga_switcheroo.h> 41 42 #include "amdgpu.h" 43 #include "amdgpu_amdkfd.h" 44 #include "amdgpu_dma_buf.h" 45 #include "amdgpu_drv.h" 46 #include "amdgpu_fdinfo.h" 47 #include "amdgpu_irq.h" 48 #include "amdgpu_psp.h" 49 #include "amdgpu_ras.h" 50 #include "amdgpu_reset.h" 51 #include "amdgpu_sched.h" 52 #include "amdgpu_xgmi.h" 53 #include "../amdxcp/amdgpu_xcp_drv.h" 54 55 /* 56 * KMS wrapper. 57 * - 3.0.0 - initial driver 58 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 59 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 60 * at the end of IBs. 61 * - 3.3.0 - Add VM support for UVD on supported hardware. 62 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 63 * - 3.5.0 - Add support for new UVD_NO_OP register. 64 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 65 * - 3.7.0 - Add support for VCE clock list packet 66 * - 3.8.0 - Add support raster config init in the kernel 67 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 68 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 69 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 70 * - 3.12.0 - Add query for double offchip LDS buffers 71 * - 3.13.0 - Add PRT support 72 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 73 * - 3.15.0 - Export more gpu info for gfx9 74 * - 3.16.0 - Add reserved vmid support 75 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 76 * - 3.18.0 - Export gpu always on cu bitmap 77 * - 3.19.0 - Add support for UVD MJPEG decode 78 * - 3.20.0 - Add support for local BOs 79 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 80 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 81 * - 3.23.0 - Add query for VRAM lost counter 82 * - 3.24.0 - Add high priority compute support for gfx9 83 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 84 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 85 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation. 86 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 87 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 88 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 89 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 90 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 91 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 92 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 93 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 94 * - 3.36.0 - Allow reading more status registers on si/cik 95 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 96 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 97 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 98 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 99 * - 3.41.0 - Add video codec query 100 * - 3.42.0 - Add 16bpc fixed point display support 101 * - 3.43.0 - Add device hot plug/unplug support 102 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 103 * - 3.45.0 - Add context ioctl stable pstate interface 104 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm 105 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags 106 * - 3.48.0 - Add IP discovery version info to HW INFO 107 * - 3.49.0 - Add gang submit into CS IOCTL 108 * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock 109 * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock 110 * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl 111 * 3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields: 112 * tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size, 113 * gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi 114 * 3.53.0 - Support for GFX11 CP GFX shadowing 115 * 3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support 116 * - 3.55.0 - Add AMDGPU_INFO_GPUVM_FAULT query 117 * - 3.56.0 - Update IB start address and size alignment for decode and encode 118 * - 3.57.0 - Compute tunneling on GFX10+ 119 */ 120 #define KMS_DRIVER_MAJOR 3 121 #define KMS_DRIVER_MINOR 57 122 #define KMS_DRIVER_PATCHLEVEL 0 123 124 /* 125 * amdgpu.debug module options. Are all disabled by default 126 */ 127 enum AMDGPU_DEBUG_MASK { 128 AMDGPU_DEBUG_VM = BIT(0), 129 AMDGPU_DEBUG_LARGEBAR = BIT(1), 130 AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY = BIT(2), 131 AMDGPU_DEBUG_USE_VRAM_FW_BUF = BIT(3), 132 }; 133 134 unsigned int amdgpu_vram_limit = UINT_MAX; 135 int amdgpu_vis_vram_limit; 136 int amdgpu_gart_size = -1; /* auto */ 137 int amdgpu_gtt_size = -1; /* auto */ 138 int amdgpu_moverate = -1; /* auto */ 139 int amdgpu_audio = -1; 140 int amdgpu_disp_priority; 141 int amdgpu_hw_i2c; 142 int amdgpu_pcie_gen2 = -1; 143 int amdgpu_msi = -1; 144 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 145 int amdgpu_dpm = -1; 146 int amdgpu_fw_load_type = -1; 147 int amdgpu_aspm = -1; 148 int amdgpu_runtime_pm = -1; 149 uint amdgpu_ip_block_mask = 0xffffffff; 150 int amdgpu_bapm = -1; 151 int amdgpu_deep_color; 152 int amdgpu_vm_size = -1; 153 int amdgpu_vm_fragment_size = -1; 154 int amdgpu_vm_block_size = -1; 155 int amdgpu_vm_fault_stop; 156 int amdgpu_vm_update_mode = -1; 157 int amdgpu_exp_hw_support; 158 int amdgpu_dc = -1; 159 int amdgpu_sched_jobs = 32; 160 int amdgpu_sched_hw_submission = 2; 161 uint amdgpu_pcie_gen_cap; 162 uint amdgpu_pcie_lane_cap; 163 u64 amdgpu_cg_mask = 0xffffffffffffffff; 164 uint amdgpu_pg_mask = 0xffffffff; 165 uint amdgpu_sdma_phase_quantum = 32; 166 char *amdgpu_disable_cu; 167 char *amdgpu_virtual_display; 168 bool enforce_isolation; 169 /* 170 * OverDrive(bit 14) disabled by default 171 * GFX DCS(bit 19) disabled by default 172 */ 173 uint amdgpu_pp_feature_mask = 0xfff7bfff; 174 uint amdgpu_force_long_training; 175 int amdgpu_lbpw = -1; 176 int amdgpu_compute_multipipe = -1; 177 int amdgpu_gpu_recovery = -1; /* auto */ 178 int amdgpu_emu_mode; 179 uint amdgpu_smu_memory_pool_size; 180 int amdgpu_smu_pptable_id = -1; 181 /* 182 * FBC (bit 0) disabled by default 183 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 184 * - With this, for multiple monitors in sync(e.g. with the same model), 185 * mclk switching will be allowed. And the mclk will be not foced to the 186 * highest. That helps saving some idle power. 187 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 188 * PSR (bit 3) disabled by default 189 * EDP NO POWER SEQUENCING (bit 4) disabled by default 190 */ 191 uint amdgpu_dc_feature_mask = 2; 192 uint amdgpu_dc_debug_mask; 193 uint amdgpu_dc_visual_confirm; 194 int amdgpu_async_gfx_ring = 1; 195 int amdgpu_mcbp = -1; 196 int amdgpu_discovery = -1; 197 int amdgpu_mes; 198 int amdgpu_mes_log_enable = 0; 199 int amdgpu_mes_kiq; 200 int amdgpu_uni_mes; 201 int amdgpu_noretry = -1; 202 int amdgpu_force_asic_type = -1; 203 int amdgpu_tmz = -1; /* auto */ 204 uint amdgpu_freesync_vid_mode; 205 int amdgpu_reset_method = -1; /* auto */ 206 int amdgpu_num_kcq = -1; 207 int amdgpu_smartshift_bias; 208 int amdgpu_use_xgmi_p2p = 1; 209 int amdgpu_vcnfw_log; 210 int amdgpu_sg_display = -1; /* auto */ 211 int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE; 212 int amdgpu_umsch_mm; 213 int amdgpu_seamless = -1; /* auto */ 214 uint amdgpu_debug_mask; 215 int amdgpu_agp = -1; /* auto */ 216 int amdgpu_wbrf = -1; 217 int amdgpu_damage_clips = -1; /* auto */ 218 int amdgpu_umsch_mm_fwlog; 219 220 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 221 222 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 223 "DRM_UT_CORE", 224 "DRM_UT_DRIVER", 225 "DRM_UT_KMS", 226 "DRM_UT_PRIME", 227 "DRM_UT_ATOMIC", 228 "DRM_UT_VBL", 229 "DRM_UT_STATE", 230 "DRM_UT_LEASE", 231 "DRM_UT_DP", 232 "DRM_UT_DRMRES"); 233 234 struct amdgpu_mgpu_info mgpu_info = { 235 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 236 .delayed_reset_work = __DELAYED_WORK_INITIALIZER( 237 mgpu_info.delayed_reset_work, 238 amdgpu_drv_delayed_reset_work_handler, 0), 239 }; 240 int amdgpu_ras_enable = -1; 241 uint amdgpu_ras_mask = 0xffffffff; 242 int amdgpu_bad_page_threshold = -1; 243 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 244 .timeout_fatal_disable = false, 245 .period = 0x0, /* default to 0x0 (timeout disable) */ 246 }; 247 248 /** 249 * DOC: vramlimit (int) 250 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 251 */ 252 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 253 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 254 255 /** 256 * DOC: vis_vramlimit (int) 257 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 258 */ 259 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 260 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 261 262 /** 263 * DOC: gartsize (uint) 264 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing. 265 * The default is -1 (The size depends on asic). 266 */ 267 MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)"); 268 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 269 270 /** 271 * DOC: gttsize (int) 272 * Restrict the size of GTT domain (for userspace use) in MiB for testing. 273 * The default is -1 (Use 1/2 RAM, minimum value is 3GB). 274 */ 275 MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)"); 276 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 277 278 /** 279 * DOC: moverate (int) 280 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 281 */ 282 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 283 module_param_named(moverate, amdgpu_moverate, int, 0600); 284 285 /** 286 * DOC: audio (int) 287 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 288 */ 289 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 290 module_param_named(audio, amdgpu_audio, int, 0444); 291 292 /** 293 * DOC: disp_priority (int) 294 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 295 */ 296 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 297 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 298 299 /** 300 * DOC: hw_i2c (int) 301 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 302 */ 303 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 304 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 305 306 /** 307 * DOC: pcie_gen2 (int) 308 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 309 */ 310 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 311 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 312 313 /** 314 * DOC: msi (int) 315 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 316 */ 317 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 318 module_param_named(msi, amdgpu_msi, int, 0444); 319 320 /** 321 * DOC: lockup_timeout (string) 322 * Set GPU scheduler timeout value in ms. 323 * 324 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 325 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 326 * to the default timeout. 327 * 328 * - With one value specified, the setting will apply to all non-compute jobs. 329 * - With multiple values specified, the first one will be for GFX. 330 * The second one is for Compute. The third and fourth ones are 331 * for SDMA and Video. 332 * 333 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 334 * jobs is 10000. The timeout for compute is 60000. 335 */ 336 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 337 "for passthrough or sriov, 10000 for all jobs. 0: keep default value. negative: infinity timeout), format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 338 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 339 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 340 341 /** 342 * DOC: dpm (int) 343 * Override for dynamic power management setting 344 * (0 = disable, 1 = enable) 345 * The default is -1 (auto). 346 */ 347 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 348 module_param_named(dpm, amdgpu_dpm, int, 0444); 349 350 /** 351 * DOC: fw_load_type (int) 352 * Set different firmware loading type for debugging, if supported. 353 * Set to 0 to force direct loading if supported by the ASIC. Set 354 * to -1 to select the default loading mode for the ASIC, as defined 355 * by the driver. The default is -1 (auto). 356 */ 357 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); 358 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 359 360 /** 361 * DOC: aspm (int) 362 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 363 */ 364 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 365 module_param_named(aspm, amdgpu_aspm, int, 0444); 366 367 /** 368 * DOC: runpm (int) 369 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 370 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 371 * Setting the value to 0 disables this functionality. 372 * Setting the value to -2 is auto enabled with power down when displays are attached. 373 */ 374 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto, -2 = auto with displays)"); 375 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 376 377 /** 378 * DOC: ip_block_mask (uint) 379 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 380 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 381 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 382 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 383 */ 384 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 385 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 386 387 /** 388 * DOC: bapm (int) 389 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 390 * The default -1 (auto, enabled) 391 */ 392 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 393 module_param_named(bapm, amdgpu_bapm, int, 0444); 394 395 /** 396 * DOC: deep_color (int) 397 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 398 */ 399 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 400 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 401 402 /** 403 * DOC: vm_size (int) 404 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 405 */ 406 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 407 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 408 409 /** 410 * DOC: vm_fragment_size (int) 411 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 412 */ 413 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 414 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 415 416 /** 417 * DOC: vm_block_size (int) 418 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 419 */ 420 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 421 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 422 423 /** 424 * DOC: vm_fault_stop (int) 425 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 426 */ 427 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 428 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 429 430 /** 431 * DOC: vm_update_mode (int) 432 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 433 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 434 */ 435 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 436 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 437 438 /** 439 * DOC: exp_hw_support (int) 440 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 441 */ 442 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 443 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 444 445 /** 446 * DOC: dc (int) 447 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 448 */ 449 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 450 module_param_named(dc, amdgpu_dc, int, 0444); 451 452 /** 453 * DOC: sched_jobs (int) 454 * Override the max number of jobs supported in the sw queue. The default is 32. 455 */ 456 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 457 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 458 459 /** 460 * DOC: sched_hw_submission (int) 461 * Override the max number of HW submissions. The default is 2. 462 */ 463 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 464 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 465 466 /** 467 * DOC: ppfeaturemask (hexint) 468 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 469 * The default is the current set of stable power features. 470 */ 471 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 472 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 473 474 /** 475 * DOC: forcelongtraining (uint) 476 * Force long memory training in resume. 477 * The default is zero, indicates short training in resume. 478 */ 479 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 480 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 481 482 /** 483 * DOC: pcie_gen_cap (uint) 484 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 485 * The default is 0 (automatic for each asic). 486 */ 487 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 488 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 489 490 /** 491 * DOC: pcie_lane_cap (uint) 492 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 493 * The default is 0 (automatic for each asic). 494 */ 495 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 496 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 497 498 /** 499 * DOC: cg_mask (ullong) 500 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 501 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 502 */ 503 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 504 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 505 506 /** 507 * DOC: pg_mask (uint) 508 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 509 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 510 */ 511 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 512 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 513 514 /** 515 * DOC: sdma_phase_quantum (uint) 516 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 517 */ 518 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 519 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 520 521 /** 522 * DOC: disable_cu (charp) 523 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 524 */ 525 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 526 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 527 528 /** 529 * DOC: virtual_display (charp) 530 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 531 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 532 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 533 * device at 26:00.0. The default is NULL. 534 */ 535 MODULE_PARM_DESC(virtual_display, 536 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 537 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 538 539 /** 540 * DOC: lbpw (int) 541 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 542 */ 543 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 544 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 545 546 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 547 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 548 549 /** 550 * DOC: gpu_recovery (int) 551 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 552 */ 553 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 554 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 555 556 /** 557 * DOC: emu_mode (int) 558 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 559 */ 560 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 561 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 562 563 /** 564 * DOC: ras_enable (int) 565 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 566 */ 567 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 568 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 569 570 /** 571 * DOC: ras_mask (uint) 572 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 573 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 574 */ 575 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 576 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 577 578 /** 579 * DOC: timeout_fatal_disable (bool) 580 * Disable Watchdog timeout fatal error event 581 */ 582 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 583 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 584 585 /** 586 * DOC: timeout_period (uint) 587 * Modify the watchdog timeout max_cycles as (1 << period) 588 */ 589 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 590 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 591 592 /** 593 * DOC: si_support (int) 594 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 595 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 596 * otherwise using amdgpu driver. 597 */ 598 #ifdef CONFIG_DRM_AMDGPU_SI 599 600 #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) 601 int amdgpu_si_support; 602 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 603 #else 604 int amdgpu_si_support = 1; 605 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 606 #endif 607 608 module_param_named(si_support, amdgpu_si_support, int, 0444); 609 #endif 610 611 /** 612 * DOC: cik_support (int) 613 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 614 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 615 * otherwise using amdgpu driver. 616 */ 617 #ifdef CONFIG_DRM_AMDGPU_CIK 618 619 #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) 620 int amdgpu_cik_support; 621 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 622 #else 623 int amdgpu_cik_support = 1; 624 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 625 #endif 626 627 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 628 #endif 629 630 /** 631 * DOC: smu_memory_pool_size (uint) 632 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 633 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 634 */ 635 MODULE_PARM_DESC(smu_memory_pool_size, 636 "reserve gtt for smu debug usage, 0 = disable,0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 637 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 638 639 /** 640 * DOC: async_gfx_ring (int) 641 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 642 */ 643 MODULE_PARM_DESC(async_gfx_ring, 644 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 645 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 646 647 /** 648 * DOC: mcbp (int) 649 * It is used to enable mid command buffer preemption. (0 = disabled, 1 = enabled, -1 auto (default)) 650 */ 651 MODULE_PARM_DESC(mcbp, 652 "Enable Mid-command buffer preemption (0 = disabled, 1 = enabled), -1 = auto (default)"); 653 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 654 655 /** 656 * DOC: discovery (int) 657 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 658 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 659 */ 660 MODULE_PARM_DESC(discovery, 661 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 662 module_param_named(discovery, amdgpu_discovery, int, 0444); 663 664 /** 665 * DOC: mes (int) 666 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 667 * (0 = disabled (default), 1 = enabled) 668 */ 669 MODULE_PARM_DESC(mes, 670 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 671 module_param_named(mes, amdgpu_mes, int, 0444); 672 673 /** 674 * DOC: mes_log_enable (int) 675 * Enable Micro Engine Scheduler log. This is used to enable/disable MES internal log. 676 * (0 = disabled (default), 1 = enabled) 677 */ 678 MODULE_PARM_DESC(mes_log_enable, 679 "Enable Micro Engine Scheduler log (0 = disabled (default), 1 = enabled)"); 680 module_param_named(mes_log_enable, amdgpu_mes_log_enable, int, 0444); 681 682 /** 683 * DOC: mes_kiq (int) 684 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq. 685 * (0 = disabled (default), 1 = enabled) 686 */ 687 MODULE_PARM_DESC(mes_kiq, 688 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)"); 689 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444); 690 691 /** 692 * DOC: uni_mes (int) 693 * Enable Unified Micro Engine Scheduler. This is a new engine pipe for unified scheduler. 694 * (0 = disabled (default), 1 = enabled) 695 */ 696 MODULE_PARM_DESC(uni_mes, 697 "Enable Unified Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 698 module_param_named(uni_mes, amdgpu_uni_mes, int, 0444); 699 700 /** 701 * DOC: noretry (int) 702 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 703 * do not support per-process XNACK this also disables retry page faults. 704 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 705 */ 706 MODULE_PARM_DESC(noretry, 707 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 708 module_param_named(noretry, amdgpu_noretry, int, 0644); 709 710 /** 711 * DOC: force_asic_type (int) 712 * A non negative value used to specify the asic type for all supported GPUs. 713 */ 714 MODULE_PARM_DESC(force_asic_type, 715 "A non negative value used to specify the asic type for all supported GPUs"); 716 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 717 718 /** 719 * DOC: use_xgmi_p2p (int) 720 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 721 */ 722 MODULE_PARM_DESC(use_xgmi_p2p, 723 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 724 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 725 726 727 #ifdef CONFIG_HSA_AMD 728 /** 729 * DOC: sched_policy (int) 730 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 731 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 732 * assigns queues to HQDs. 733 */ 734 int sched_policy = KFD_SCHED_POLICY_HWS; 735 module_param(sched_policy, int, 0444); 736 MODULE_PARM_DESC(sched_policy, 737 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 738 739 /** 740 * DOC: hws_max_conc_proc (int) 741 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 742 * number of VMIDs assigned to the HWS, which is also the default. 743 */ 744 int hws_max_conc_proc = -1; 745 module_param(hws_max_conc_proc, int, 0444); 746 MODULE_PARM_DESC(hws_max_conc_proc, 747 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 748 749 /** 750 * DOC: cwsr_enable (int) 751 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 752 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 753 * disables it. 754 */ 755 int cwsr_enable = 1; 756 module_param(cwsr_enable, int, 0444); 757 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 758 759 /** 760 * DOC: max_num_of_queues_per_device (int) 761 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 762 * is 4096. 763 */ 764 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 765 module_param(max_num_of_queues_per_device, int, 0444); 766 MODULE_PARM_DESC(max_num_of_queues_per_device, 767 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 768 769 /** 770 * DOC: send_sigterm (int) 771 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 772 * but just print errors on dmesg. Setting 1 enables sending sigterm. 773 */ 774 int send_sigterm; 775 module_param(send_sigterm, int, 0444); 776 MODULE_PARM_DESC(send_sigterm, 777 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 778 779 /** 780 * DOC: halt_if_hws_hang (int) 781 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 782 * Setting 1 enables halt on hang. 783 */ 784 int halt_if_hws_hang; 785 module_param(halt_if_hws_hang, int, 0644); 786 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 787 788 /** 789 * DOC: hws_gws_support(bool) 790 * Assume that HWS supports GWS barriers regardless of what firmware version 791 * check says. Default value: false (rely on MEC2 firmware version check). 792 */ 793 bool hws_gws_support; 794 module_param(hws_gws_support, bool, 0444); 795 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 796 797 /** 798 * DOC: queue_preemption_timeout_ms (int) 799 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 800 */ 801 int queue_preemption_timeout_ms = 9000; 802 module_param(queue_preemption_timeout_ms, int, 0644); 803 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 804 805 /** 806 * DOC: debug_evictions(bool) 807 * Enable extra debug messages to help determine the cause of evictions 808 */ 809 bool debug_evictions; 810 module_param(debug_evictions, bool, 0644); 811 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 812 813 /** 814 * DOC: no_system_mem_limit(bool) 815 * Disable system memory limit, to support multiple process shared memory 816 */ 817 bool no_system_mem_limit; 818 module_param(no_system_mem_limit, bool, 0644); 819 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 820 821 /** 822 * DOC: no_queue_eviction_on_vm_fault (int) 823 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 824 */ 825 int amdgpu_no_queue_eviction_on_vm_fault; 826 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 827 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 828 #endif 829 830 /** 831 * DOC: mtype_local (int) 832 */ 833 int amdgpu_mtype_local; 834 MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (0 = MTYPE_RW (default), 1 = MTYPE_NC, 2 = MTYPE_CC)"); 835 module_param_named(mtype_local, amdgpu_mtype_local, int, 0444); 836 837 /** 838 * DOC: pcie_p2p (bool) 839 * Enable PCIe P2P (requires large-BAR). Default value: true (on) 840 */ 841 #ifdef CONFIG_HSA_AMD_P2P 842 bool pcie_p2p = true; 843 module_param(pcie_p2p, bool, 0444); 844 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); 845 #endif 846 847 /** 848 * DOC: dcfeaturemask (uint) 849 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 850 * The default is the current set of stable display features. 851 */ 852 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 853 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 854 855 /** 856 * DOC: dcdebugmask (uint) 857 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 858 */ 859 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 860 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 861 862 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)"); 863 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444); 864 865 /** 866 * DOC: abmlevel (uint) 867 * Override the default ABM (Adaptive Backlight Management) level used for DC 868 * enabled hardware. Requires DMCU to be supported and loaded. 869 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 870 * default. Values 1-4 control the maximum allowable brightness reduction via 871 * the ABM algorithm, with 1 being the least reduction and 4 being the most 872 * reduction. 873 * 874 * Defaults to -1, or disabled. Userspace can only override this level after 875 * boot if it's set to auto. 876 */ 877 int amdgpu_dm_abm_level = -1; 878 MODULE_PARM_DESC(abmlevel, 879 "ABM level (0 = off, 1-4 = backlight reduction level, -1 auto (default))"); 880 module_param_named(abmlevel, amdgpu_dm_abm_level, int, 0444); 881 882 int amdgpu_backlight = -1; 883 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 884 module_param_named(backlight, amdgpu_backlight, bint, 0444); 885 886 /** 887 * DOC: damageclips (int) 888 * Enable or disable damage clips support. If damage clips support is disabled, 889 * we will force full frame updates, irrespective of what user space sends to 890 * us. 891 * 892 * Defaults to -1 (where it is enabled unless a PSR-SU display is detected). 893 */ 894 MODULE_PARM_DESC(damageclips, 895 "Damage clips support (0 = disable, 1 = enable, -1 auto (default))"); 896 module_param_named(damageclips, amdgpu_damage_clips, int, 0444); 897 898 /** 899 * DOC: tmz (int) 900 * Trusted Memory Zone (TMZ) is a method to protect data being written 901 * to or read from memory. 902 * 903 * The default value: 0 (off). TODO: change to auto till it is completed. 904 */ 905 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 906 module_param_named(tmz, amdgpu_tmz, int, 0444); 907 908 /** 909 * DOC: freesync_video (uint) 910 * Enable the optimization to adjust front porch timing to achieve seamless 911 * mode change experience when setting a freesync supported mode for which full 912 * modeset is not needed. 913 * 914 * The Display Core will add a set of modes derived from the base FreeSync 915 * video mode into the corresponding connector's mode list based on commonly 916 * used refresh rates and VRR range of the connected display, when users enable 917 * this feature. From the userspace perspective, they can see a seamless mode 918 * change experience when the change between different refresh rates under the 919 * same resolution. Additionally, userspace applications such as Video playback 920 * can read this modeset list and change the refresh rate based on the video 921 * frame rate. Finally, the userspace can also derive an appropriate mode for a 922 * particular refresh rate based on the FreeSync Mode and add it to the 923 * connector's mode list. 924 * 925 * Note: This is an experimental feature. 926 * 927 * The default value: 0 (off). 928 */ 929 MODULE_PARM_DESC( 930 freesync_video, 931 "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)"); 932 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); 933 934 /** 935 * DOC: reset_method (int) 936 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 937 */ 938 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 939 module_param_named(reset_method, amdgpu_reset_method, int, 0644); 940 941 /** 942 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 943 * threshold value of faulty pages detected by RAS ECC, which may 944 * result in the GPU entering bad status when the number of total 945 * faulty pages by ECC exceeds the threshold value. 946 */ 947 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = driver sets threshold)"); 948 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 949 950 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 951 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 952 953 /** 954 * DOC: vcnfw_log (int) 955 * Enable vcnfw log output for debugging, the default is disabled. 956 */ 957 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 958 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 959 960 /** 961 * DOC: sg_display (int) 962 * Disable S/G (scatter/gather) display (i.e., display from system memory). 963 * This option is only relevant on APUs. Set this option to 0 to disable 964 * S/G display if you experience flickering or other issues under memory 965 * pressure and report the issue. 966 */ 967 MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)"); 968 module_param_named(sg_display, amdgpu_sg_display, int, 0444); 969 970 /** 971 * DOC: umsch_mm (int) 972 * Enable Multi Media User Mode Scheduler. This is a HW scheduling engine for VCN and VPE. 973 * (0 = disabled (default), 1 = enabled) 974 */ 975 MODULE_PARM_DESC(umsch_mm, 976 "Enable Multi Media User Mode Scheduler (0 = disabled (default), 1 = enabled)"); 977 module_param_named(umsch_mm, amdgpu_umsch_mm, int, 0444); 978 979 /** 980 * DOC: umsch_mm_fwlog (int) 981 * Enable umschfw log output for debugging, the default is disabled. 982 */ 983 MODULE_PARM_DESC(umsch_mm_fwlog, "Enable umschfw log(0 = disable (default value), 1 = enable)"); 984 module_param_named(umsch_mm_fwlog, amdgpu_umsch_mm_fwlog, int, 0444); 985 986 /** 987 * DOC: smu_pptable_id (int) 988 * Used to override pptable id. id = 0 use VBIOS pptable. 989 * id > 0 use the soft pptable with specicfied id. 990 */ 991 MODULE_PARM_DESC(smu_pptable_id, 992 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 993 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 994 995 /** 996 * DOC: partition_mode (int) 997 * Used to override the default SPX mode. 998 */ 999 MODULE_PARM_DESC( 1000 user_partt_mode, 1001 "specify partition mode to be used (-2 = AMDGPU_AUTO_COMPUTE_PARTITION_MODE(default value) \ 1002 0 = AMDGPU_SPX_PARTITION_MODE, \ 1003 1 = AMDGPU_DPX_PARTITION_MODE, \ 1004 2 = AMDGPU_TPX_PARTITION_MODE, \ 1005 3 = AMDGPU_QPX_PARTITION_MODE, \ 1006 4 = AMDGPU_CPX_PARTITION_MODE)"); 1007 module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint, 0444); 1008 1009 1010 /** 1011 * DOC: enforce_isolation (bool) 1012 * enforce process isolation between graphics and compute via using the same reserved vmid. 1013 */ 1014 module_param(enforce_isolation, bool, 0444); 1015 MODULE_PARM_DESC(enforce_isolation, "enforce process isolation between graphics and compute . enforce_isolation = on"); 1016 1017 /** 1018 * DOC: seamless (int) 1019 * Seamless boot will keep the image on the screen during the boot process. 1020 */ 1021 MODULE_PARM_DESC(seamless, "Seamless boot (-1 = auto (default), 0 = disable, 1 = enable)"); 1022 module_param_named(seamless, amdgpu_seamless, int, 0444); 1023 1024 /** 1025 * DOC: debug_mask (uint) 1026 * Debug options for amdgpu, work as a binary mask with the following options: 1027 * 1028 * - 0x1: Debug VM handling 1029 * - 0x2: Enable simulating large-bar capability on non-large bar system. This 1030 * limits the VRAM size reported to ROCm applications to the visible 1031 * size, usually 256MB. 1032 * - 0x4: Disable GPU soft recovery, always do a full reset 1033 */ 1034 MODULE_PARM_DESC(debug_mask, "debug options for amdgpu, disabled by default"); 1035 module_param_named(debug_mask, amdgpu_debug_mask, uint, 0444); 1036 1037 /** 1038 * DOC: agp (int) 1039 * Enable the AGP aperture. This provides an aperture in the GPU's internal 1040 * address space for direct access to system memory. Note that these accesses 1041 * are non-snooped, so they are only used for access to uncached memory. 1042 */ 1043 MODULE_PARM_DESC(agp, "AGP (-1 = auto (default), 0 = disable, 1 = enable)"); 1044 module_param_named(agp, amdgpu_agp, int, 0444); 1045 1046 /** 1047 * DOC: wbrf (int) 1048 * Enable Wifi RFI interference mitigation feature. 1049 * Due to electrical and mechanical constraints there may be likely interference of 1050 * relatively high-powered harmonics of the (G-)DDR memory clocks with local radio 1051 * module frequency bands used by Wifi 6/6e/7. To mitigate the possible RFI interference, 1052 * with this feature enabled, PMFW will use either “shadowed P-State” or “P-State” based 1053 * on active list of frequencies in-use (to be avoided) as part of initial setting or 1054 * P-state transition. However, there may be potential performance impact with this 1055 * feature enabled. 1056 * (0 = disabled, 1 = enabled, -1 = auto (default setting, will be enabled if supported)) 1057 */ 1058 MODULE_PARM_DESC(wbrf, 1059 "Enable Wifi RFI interference mitigation (0 = disabled, 1 = enabled, -1 = auto(default)"); 1060 module_param_named(wbrf, amdgpu_wbrf, int, 0444); 1061 1062 /* These devices are not supported by amdgpu. 1063 * They are supported by the mach64, r128, radeon drivers 1064 */ 1065 static const u16 amdgpu_unsupported_pciidlist[] = { 1066 /* mach64 */ 1067 0x4354, 1068 0x4358, 1069 0x4554, 1070 0x4742, 1071 0x4744, 1072 0x4749, 1073 0x474C, 1074 0x474D, 1075 0x474E, 1076 0x474F, 1077 0x4750, 1078 0x4751, 1079 0x4752, 1080 0x4753, 1081 0x4754, 1082 0x4755, 1083 0x4756, 1084 0x4757, 1085 0x4758, 1086 0x4759, 1087 0x475A, 1088 0x4C42, 1089 0x4C44, 1090 0x4C47, 1091 0x4C49, 1092 0x4C4D, 1093 0x4C4E, 1094 0x4C50, 1095 0x4C51, 1096 0x4C52, 1097 0x4C53, 1098 0x5654, 1099 0x5655, 1100 0x5656, 1101 /* r128 */ 1102 0x4c45, 1103 0x4c46, 1104 0x4d46, 1105 0x4d4c, 1106 0x5041, 1107 0x5042, 1108 0x5043, 1109 0x5044, 1110 0x5045, 1111 0x5046, 1112 0x5047, 1113 0x5048, 1114 0x5049, 1115 0x504A, 1116 0x504B, 1117 0x504C, 1118 0x504D, 1119 0x504E, 1120 0x504F, 1121 0x5050, 1122 0x5051, 1123 0x5052, 1124 0x5053, 1125 0x5054, 1126 0x5055, 1127 0x5056, 1128 0x5057, 1129 0x5058, 1130 0x5245, 1131 0x5246, 1132 0x5247, 1133 0x524b, 1134 0x524c, 1135 0x534d, 1136 0x5446, 1137 0x544C, 1138 0x5452, 1139 /* radeon */ 1140 0x3150, 1141 0x3151, 1142 0x3152, 1143 0x3154, 1144 0x3155, 1145 0x3E50, 1146 0x3E54, 1147 0x4136, 1148 0x4137, 1149 0x4144, 1150 0x4145, 1151 0x4146, 1152 0x4147, 1153 0x4148, 1154 0x4149, 1155 0x414A, 1156 0x414B, 1157 0x4150, 1158 0x4151, 1159 0x4152, 1160 0x4153, 1161 0x4154, 1162 0x4155, 1163 0x4156, 1164 0x4237, 1165 0x4242, 1166 0x4336, 1167 0x4337, 1168 0x4437, 1169 0x4966, 1170 0x4967, 1171 0x4A48, 1172 0x4A49, 1173 0x4A4A, 1174 0x4A4B, 1175 0x4A4C, 1176 0x4A4D, 1177 0x4A4E, 1178 0x4A4F, 1179 0x4A50, 1180 0x4A54, 1181 0x4B48, 1182 0x4B49, 1183 0x4B4A, 1184 0x4B4B, 1185 0x4B4C, 1186 0x4C57, 1187 0x4C58, 1188 0x4C59, 1189 0x4C5A, 1190 0x4C64, 1191 0x4C66, 1192 0x4C67, 1193 0x4E44, 1194 0x4E45, 1195 0x4E46, 1196 0x4E47, 1197 0x4E48, 1198 0x4E49, 1199 0x4E4A, 1200 0x4E4B, 1201 0x4E50, 1202 0x4E51, 1203 0x4E52, 1204 0x4E53, 1205 0x4E54, 1206 0x4E56, 1207 0x5144, 1208 0x5145, 1209 0x5146, 1210 0x5147, 1211 0x5148, 1212 0x514C, 1213 0x514D, 1214 0x5157, 1215 0x5158, 1216 0x5159, 1217 0x515A, 1218 0x515E, 1219 0x5460, 1220 0x5462, 1221 0x5464, 1222 0x5548, 1223 0x5549, 1224 0x554A, 1225 0x554B, 1226 0x554C, 1227 0x554D, 1228 0x554E, 1229 0x554F, 1230 0x5550, 1231 0x5551, 1232 0x5552, 1233 0x5554, 1234 0x564A, 1235 0x564B, 1236 0x564F, 1237 0x5652, 1238 0x5653, 1239 0x5657, 1240 0x5834, 1241 0x5835, 1242 0x5954, 1243 0x5955, 1244 0x5974, 1245 0x5975, 1246 0x5960, 1247 0x5961, 1248 0x5962, 1249 0x5964, 1250 0x5965, 1251 0x5969, 1252 0x5a41, 1253 0x5a42, 1254 0x5a61, 1255 0x5a62, 1256 0x5b60, 1257 0x5b62, 1258 0x5b63, 1259 0x5b64, 1260 0x5b65, 1261 0x5c61, 1262 0x5c63, 1263 0x5d48, 1264 0x5d49, 1265 0x5d4a, 1266 0x5d4c, 1267 0x5d4d, 1268 0x5d4e, 1269 0x5d4f, 1270 0x5d50, 1271 0x5d52, 1272 0x5d57, 1273 0x5e48, 1274 0x5e4a, 1275 0x5e4b, 1276 0x5e4c, 1277 0x5e4d, 1278 0x5e4f, 1279 0x6700, 1280 0x6701, 1281 0x6702, 1282 0x6703, 1283 0x6704, 1284 0x6705, 1285 0x6706, 1286 0x6707, 1287 0x6708, 1288 0x6709, 1289 0x6718, 1290 0x6719, 1291 0x671c, 1292 0x671d, 1293 0x671f, 1294 0x6720, 1295 0x6721, 1296 0x6722, 1297 0x6723, 1298 0x6724, 1299 0x6725, 1300 0x6726, 1301 0x6727, 1302 0x6728, 1303 0x6729, 1304 0x6738, 1305 0x6739, 1306 0x673e, 1307 0x6740, 1308 0x6741, 1309 0x6742, 1310 0x6743, 1311 0x6744, 1312 0x6745, 1313 0x6746, 1314 0x6747, 1315 0x6748, 1316 0x6749, 1317 0x674A, 1318 0x6750, 1319 0x6751, 1320 0x6758, 1321 0x6759, 1322 0x675B, 1323 0x675D, 1324 0x675F, 1325 0x6760, 1326 0x6761, 1327 0x6762, 1328 0x6763, 1329 0x6764, 1330 0x6765, 1331 0x6766, 1332 0x6767, 1333 0x6768, 1334 0x6770, 1335 0x6771, 1336 0x6772, 1337 0x6778, 1338 0x6779, 1339 0x677B, 1340 0x6840, 1341 0x6841, 1342 0x6842, 1343 0x6843, 1344 0x6849, 1345 0x684C, 1346 0x6850, 1347 0x6858, 1348 0x6859, 1349 0x6880, 1350 0x6888, 1351 0x6889, 1352 0x688A, 1353 0x688C, 1354 0x688D, 1355 0x6898, 1356 0x6899, 1357 0x689b, 1358 0x689c, 1359 0x689d, 1360 0x689e, 1361 0x68a0, 1362 0x68a1, 1363 0x68a8, 1364 0x68a9, 1365 0x68b0, 1366 0x68b8, 1367 0x68b9, 1368 0x68ba, 1369 0x68be, 1370 0x68bf, 1371 0x68c0, 1372 0x68c1, 1373 0x68c7, 1374 0x68c8, 1375 0x68c9, 1376 0x68d8, 1377 0x68d9, 1378 0x68da, 1379 0x68de, 1380 0x68e0, 1381 0x68e1, 1382 0x68e4, 1383 0x68e5, 1384 0x68e8, 1385 0x68e9, 1386 0x68f1, 1387 0x68f2, 1388 0x68f8, 1389 0x68f9, 1390 0x68fa, 1391 0x68fe, 1392 0x7100, 1393 0x7101, 1394 0x7102, 1395 0x7103, 1396 0x7104, 1397 0x7105, 1398 0x7106, 1399 0x7108, 1400 0x7109, 1401 0x710A, 1402 0x710B, 1403 0x710C, 1404 0x710E, 1405 0x710F, 1406 0x7140, 1407 0x7141, 1408 0x7142, 1409 0x7143, 1410 0x7144, 1411 0x7145, 1412 0x7146, 1413 0x7147, 1414 0x7149, 1415 0x714A, 1416 0x714B, 1417 0x714C, 1418 0x714D, 1419 0x714E, 1420 0x714F, 1421 0x7151, 1422 0x7152, 1423 0x7153, 1424 0x715E, 1425 0x715F, 1426 0x7180, 1427 0x7181, 1428 0x7183, 1429 0x7186, 1430 0x7187, 1431 0x7188, 1432 0x718A, 1433 0x718B, 1434 0x718C, 1435 0x718D, 1436 0x718F, 1437 0x7193, 1438 0x7196, 1439 0x719B, 1440 0x719F, 1441 0x71C0, 1442 0x71C1, 1443 0x71C2, 1444 0x71C3, 1445 0x71C4, 1446 0x71C5, 1447 0x71C6, 1448 0x71C7, 1449 0x71CD, 1450 0x71CE, 1451 0x71D2, 1452 0x71D4, 1453 0x71D5, 1454 0x71D6, 1455 0x71DA, 1456 0x71DE, 1457 0x7200, 1458 0x7210, 1459 0x7211, 1460 0x7240, 1461 0x7243, 1462 0x7244, 1463 0x7245, 1464 0x7246, 1465 0x7247, 1466 0x7248, 1467 0x7249, 1468 0x724A, 1469 0x724B, 1470 0x724C, 1471 0x724D, 1472 0x724E, 1473 0x724F, 1474 0x7280, 1475 0x7281, 1476 0x7283, 1477 0x7284, 1478 0x7287, 1479 0x7288, 1480 0x7289, 1481 0x728B, 1482 0x728C, 1483 0x7290, 1484 0x7291, 1485 0x7293, 1486 0x7297, 1487 0x7834, 1488 0x7835, 1489 0x791e, 1490 0x791f, 1491 0x793f, 1492 0x7941, 1493 0x7942, 1494 0x796c, 1495 0x796d, 1496 0x796e, 1497 0x796f, 1498 0x9400, 1499 0x9401, 1500 0x9402, 1501 0x9403, 1502 0x9405, 1503 0x940A, 1504 0x940B, 1505 0x940F, 1506 0x94A0, 1507 0x94A1, 1508 0x94A3, 1509 0x94B1, 1510 0x94B3, 1511 0x94B4, 1512 0x94B5, 1513 0x94B9, 1514 0x9440, 1515 0x9441, 1516 0x9442, 1517 0x9443, 1518 0x9444, 1519 0x9446, 1520 0x944A, 1521 0x944B, 1522 0x944C, 1523 0x944E, 1524 0x9450, 1525 0x9452, 1526 0x9456, 1527 0x945A, 1528 0x945B, 1529 0x945E, 1530 0x9460, 1531 0x9462, 1532 0x946A, 1533 0x946B, 1534 0x947A, 1535 0x947B, 1536 0x9480, 1537 0x9487, 1538 0x9488, 1539 0x9489, 1540 0x948A, 1541 0x948F, 1542 0x9490, 1543 0x9491, 1544 0x9495, 1545 0x9498, 1546 0x949C, 1547 0x949E, 1548 0x949F, 1549 0x94C0, 1550 0x94C1, 1551 0x94C3, 1552 0x94C4, 1553 0x94C5, 1554 0x94C6, 1555 0x94C7, 1556 0x94C8, 1557 0x94C9, 1558 0x94CB, 1559 0x94CC, 1560 0x94CD, 1561 0x9500, 1562 0x9501, 1563 0x9504, 1564 0x9505, 1565 0x9506, 1566 0x9507, 1567 0x9508, 1568 0x9509, 1569 0x950F, 1570 0x9511, 1571 0x9515, 1572 0x9517, 1573 0x9519, 1574 0x9540, 1575 0x9541, 1576 0x9542, 1577 0x954E, 1578 0x954F, 1579 0x9552, 1580 0x9553, 1581 0x9555, 1582 0x9557, 1583 0x955f, 1584 0x9580, 1585 0x9581, 1586 0x9583, 1587 0x9586, 1588 0x9587, 1589 0x9588, 1590 0x9589, 1591 0x958A, 1592 0x958B, 1593 0x958C, 1594 0x958D, 1595 0x958E, 1596 0x958F, 1597 0x9590, 1598 0x9591, 1599 0x9593, 1600 0x9595, 1601 0x9596, 1602 0x9597, 1603 0x9598, 1604 0x9599, 1605 0x959B, 1606 0x95C0, 1607 0x95C2, 1608 0x95C4, 1609 0x95C5, 1610 0x95C6, 1611 0x95C7, 1612 0x95C9, 1613 0x95CC, 1614 0x95CD, 1615 0x95CE, 1616 0x95CF, 1617 0x9610, 1618 0x9611, 1619 0x9612, 1620 0x9613, 1621 0x9614, 1622 0x9615, 1623 0x9616, 1624 0x9640, 1625 0x9641, 1626 0x9642, 1627 0x9643, 1628 0x9644, 1629 0x9645, 1630 0x9647, 1631 0x9648, 1632 0x9649, 1633 0x964a, 1634 0x964b, 1635 0x964c, 1636 0x964e, 1637 0x964f, 1638 0x9710, 1639 0x9711, 1640 0x9712, 1641 0x9713, 1642 0x9714, 1643 0x9715, 1644 0x9802, 1645 0x9803, 1646 0x9804, 1647 0x9805, 1648 0x9806, 1649 0x9807, 1650 0x9808, 1651 0x9809, 1652 0x980A, 1653 0x9900, 1654 0x9901, 1655 0x9903, 1656 0x9904, 1657 0x9905, 1658 0x9906, 1659 0x9907, 1660 0x9908, 1661 0x9909, 1662 0x990A, 1663 0x990B, 1664 0x990C, 1665 0x990D, 1666 0x990E, 1667 0x990F, 1668 0x9910, 1669 0x9913, 1670 0x9917, 1671 0x9918, 1672 0x9919, 1673 0x9990, 1674 0x9991, 1675 0x9992, 1676 0x9993, 1677 0x9994, 1678 0x9995, 1679 0x9996, 1680 0x9997, 1681 0x9998, 1682 0x9999, 1683 0x999A, 1684 0x999B, 1685 0x999C, 1686 0x999D, 1687 0x99A0, 1688 0x99A2, 1689 0x99A4, 1690 /* radeon secondary ids */ 1691 0x3171, 1692 0x3e70, 1693 0x4164, 1694 0x4165, 1695 0x4166, 1696 0x4168, 1697 0x4170, 1698 0x4171, 1699 0x4172, 1700 0x4173, 1701 0x496e, 1702 0x4a69, 1703 0x4a6a, 1704 0x4a6b, 1705 0x4a70, 1706 0x4a74, 1707 0x4b69, 1708 0x4b6b, 1709 0x4b6c, 1710 0x4c6e, 1711 0x4e64, 1712 0x4e65, 1713 0x4e66, 1714 0x4e67, 1715 0x4e68, 1716 0x4e69, 1717 0x4e6a, 1718 0x4e71, 1719 0x4f73, 1720 0x5569, 1721 0x556b, 1722 0x556d, 1723 0x556f, 1724 0x5571, 1725 0x5854, 1726 0x5874, 1727 0x5940, 1728 0x5941, 1729 0x5b70, 1730 0x5b72, 1731 0x5b73, 1732 0x5b74, 1733 0x5b75, 1734 0x5d44, 1735 0x5d45, 1736 0x5d6d, 1737 0x5d6f, 1738 0x5d72, 1739 0x5d77, 1740 0x5e6b, 1741 0x5e6d, 1742 0x7120, 1743 0x7124, 1744 0x7129, 1745 0x712e, 1746 0x712f, 1747 0x7162, 1748 0x7163, 1749 0x7166, 1750 0x7167, 1751 0x7172, 1752 0x7173, 1753 0x71a0, 1754 0x71a1, 1755 0x71a3, 1756 0x71a7, 1757 0x71bb, 1758 0x71e0, 1759 0x71e1, 1760 0x71e2, 1761 0x71e6, 1762 0x71e7, 1763 0x71f2, 1764 0x7269, 1765 0x726b, 1766 0x726e, 1767 0x72a0, 1768 0x72a8, 1769 0x72b1, 1770 0x72b3, 1771 0x793f, 1772 }; 1773 1774 static const struct pci_device_id pciidlist[] = { 1775 #ifdef CONFIG_DRM_AMDGPU_SI 1776 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1777 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1778 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1779 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1780 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1781 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1782 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1783 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1784 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1785 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1786 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1787 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1788 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1789 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1790 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1791 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1792 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1793 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1794 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1795 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1796 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1797 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1798 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1799 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1800 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1801 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1802 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1803 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1804 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1805 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1806 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1807 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1808 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1809 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1810 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1811 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1812 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1813 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1814 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1815 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1816 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1817 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1818 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1819 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1820 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1821 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1822 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1823 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1824 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1825 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1826 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1827 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1828 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1829 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1830 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1831 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1832 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1833 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1834 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1835 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1836 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1837 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1838 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1839 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1840 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1841 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1842 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1843 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1844 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1845 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1846 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1847 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1848 #endif 1849 #ifdef CONFIG_DRM_AMDGPU_CIK 1850 /* Kaveri */ 1851 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1852 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1853 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1854 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1855 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1856 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1857 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1858 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1859 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1860 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1861 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1862 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1863 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1864 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1865 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1866 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1867 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1868 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1869 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1870 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1871 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1872 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1873 /* Bonaire */ 1874 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1875 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1876 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1877 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1878 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1879 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1880 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1881 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1882 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1883 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1884 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1885 /* Hawaii */ 1886 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1887 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1888 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1889 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1890 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1891 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1892 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1893 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1894 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1895 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1896 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1897 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1898 /* Kabini */ 1899 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1900 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1901 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1902 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1903 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1904 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1905 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1906 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1907 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1908 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1909 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1910 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1911 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1912 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1913 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1914 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1915 /* mullins */ 1916 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1917 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1918 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1919 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1920 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1921 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1922 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1923 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1924 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1925 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1926 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1927 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1928 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1929 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1930 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1931 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1932 #endif 1933 /* topaz */ 1934 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1935 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1936 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1937 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1938 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1939 /* tonga */ 1940 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1941 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1942 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1943 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1944 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1945 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1946 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1947 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1948 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1949 /* fiji */ 1950 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1951 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1952 /* carrizo */ 1953 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1954 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1955 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1956 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1957 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1958 /* stoney */ 1959 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1960 /* Polaris11 */ 1961 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1962 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1963 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1964 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1965 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1966 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1967 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1968 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1969 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1970 /* Polaris10 */ 1971 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1972 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1973 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1974 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1975 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1976 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1977 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1978 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1979 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1980 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1981 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1982 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1983 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1984 /* Polaris12 */ 1985 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1986 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1987 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1988 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1989 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1990 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1991 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1992 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1993 /* VEGAM */ 1994 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1995 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1996 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1997 /* Vega 10 */ 1998 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1999 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2000 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2001 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2002 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2003 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2004 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2005 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2006 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2007 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2008 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2009 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2010 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2011 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2012 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2013 /* Vega 12 */ 2014 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2015 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2016 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2017 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2018 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2019 /* Vega 20 */ 2020 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2021 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2022 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2023 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2024 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2025 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2026 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2027 /* Raven */ 2028 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 2029 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 2030 /* Arcturus */ 2031 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2032 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2033 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2034 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2035 /* Navi10 */ 2036 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2037 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2038 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2039 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2040 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2041 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2042 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2043 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2044 /* Navi14 */ 2045 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2046 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2047 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2048 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2049 2050 /* Renoir */ 2051 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2052 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2053 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2054 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2055 2056 /* Navi12 */ 2057 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 2058 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 2059 2060 /* Sienna_Cichlid */ 2061 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2062 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2063 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2064 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2065 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2066 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2067 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2068 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2069 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2070 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2071 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2072 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2073 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2074 2075 /* Yellow Carp */ 2076 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 2077 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 2078 2079 /* Navy_Flounder */ 2080 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2081 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2082 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2083 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2084 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2085 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2086 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2087 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2088 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2089 2090 /* DIMGREY_CAVEFISH */ 2091 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2092 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2093 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2094 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2095 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2096 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2097 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2098 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2099 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2100 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2101 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2102 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2103 2104 /* Aldebaran */ 2105 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2106 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2107 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2108 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2109 2110 /* CYAN_SKILLFISH */ 2111 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2112 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2113 2114 /* BEIGE_GOBY */ 2115 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2116 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2117 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2118 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2119 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2120 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2121 2122 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2123 .class = PCI_CLASS_DISPLAY_VGA << 8, 2124 .class_mask = 0xffffff, 2125 .driver_data = CHIP_IP_DISCOVERY }, 2126 2127 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2128 .class = PCI_CLASS_DISPLAY_OTHER << 8, 2129 .class_mask = 0xffffff, 2130 .driver_data = CHIP_IP_DISCOVERY }, 2131 2132 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2133 .class = PCI_CLASS_ACCELERATOR_PROCESSING << 8, 2134 .class_mask = 0xffffff, 2135 .driver_data = CHIP_IP_DISCOVERY }, 2136 2137 {0, 0, 0} 2138 }; 2139 2140 MODULE_DEVICE_TABLE(pci, pciidlist); 2141 2142 static const struct amdgpu_asic_type_quirk asic_type_quirks[] = { 2143 /* differentiate between P10 and P11 asics with the same DID */ 2144 {0x67FF, 0xE3, CHIP_POLARIS10}, 2145 {0x67FF, 0xE7, CHIP_POLARIS10}, 2146 {0x67FF, 0xF3, CHIP_POLARIS10}, 2147 {0x67FF, 0xF7, CHIP_POLARIS10}, 2148 }; 2149 2150 static const struct drm_driver amdgpu_kms_driver; 2151 2152 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 2153 { 2154 struct pci_dev *p = NULL; 2155 int i; 2156 2157 /* 0 - GPU 2158 * 1 - audio 2159 * 2 - USB 2160 * 3 - UCSI 2161 */ 2162 for (i = 1; i < 4; i++) { 2163 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 2164 adev->pdev->bus->number, i); 2165 if (p) { 2166 pm_runtime_get_sync(&p->dev); 2167 pm_runtime_mark_last_busy(&p->dev); 2168 pm_runtime_put_autosuspend(&p->dev); 2169 pci_dev_put(p); 2170 } 2171 } 2172 } 2173 2174 static void amdgpu_init_debug_options(struct amdgpu_device *adev) 2175 { 2176 if (amdgpu_debug_mask & AMDGPU_DEBUG_VM) { 2177 pr_info("debug: VM handling debug enabled\n"); 2178 adev->debug_vm = true; 2179 } 2180 2181 if (amdgpu_debug_mask & AMDGPU_DEBUG_LARGEBAR) { 2182 pr_info("debug: enabled simulating large-bar capability on non-large bar system\n"); 2183 adev->debug_largebar = true; 2184 } 2185 2186 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY) { 2187 pr_info("debug: soft reset for GPU recovery disabled\n"); 2188 adev->debug_disable_soft_recovery = true; 2189 } 2190 2191 if (amdgpu_debug_mask & AMDGPU_DEBUG_USE_VRAM_FW_BUF) { 2192 pr_info("debug: place fw in vram for frontdoor loading\n"); 2193 adev->debug_use_vram_fw_buf = true; 2194 } 2195 } 2196 2197 static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long flags) 2198 { 2199 int i; 2200 2201 for (i = 0; i < ARRAY_SIZE(asic_type_quirks); i++) { 2202 if (pdev->device == asic_type_quirks[i].device && 2203 pdev->revision == asic_type_quirks[i].revision) { 2204 flags &= ~AMD_ASIC_MASK; 2205 flags |= asic_type_quirks[i].type; 2206 break; 2207 } 2208 } 2209 2210 return flags; 2211 } 2212 2213 static int amdgpu_pci_probe(struct pci_dev *pdev, 2214 const struct pci_device_id *ent) 2215 { 2216 struct drm_device *ddev; 2217 struct amdgpu_device *adev; 2218 unsigned long flags = ent->driver_data; 2219 int ret, retry = 0, i; 2220 bool supports_atomic = false; 2221 2222 /* skip devices which are owned by radeon */ 2223 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2224 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2225 return -ENODEV; 2226 } 2227 2228 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) 2229 amdgpu_aspm = 0; 2230 2231 if (amdgpu_virtual_display || 2232 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 2233 supports_atomic = true; 2234 2235 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2236 DRM_INFO("This hardware requires experimental hardware support.\n" 2237 "See modparam exp_hw_support\n"); 2238 return -ENODEV; 2239 } 2240 2241 flags = amdgpu_fix_asic_type(pdev, flags); 2242 2243 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2244 * however, SME requires an indirect IOMMU mapping because the encryption 2245 * bit is beyond the DMA mask of the chip. 2246 */ 2247 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2248 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2249 dev_info(&pdev->dev, 2250 "SME is not compatible with RAVEN\n"); 2251 return -ENOTSUPP; 2252 } 2253 2254 #ifdef CONFIG_DRM_AMDGPU_SI 2255 if (!amdgpu_si_support) { 2256 switch (flags & AMD_ASIC_MASK) { 2257 case CHIP_TAHITI: 2258 case CHIP_PITCAIRN: 2259 case CHIP_VERDE: 2260 case CHIP_OLAND: 2261 case CHIP_HAINAN: 2262 dev_info(&pdev->dev, 2263 "SI support provided by radeon.\n"); 2264 dev_info(&pdev->dev, 2265 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 2266 ); 2267 return -ENODEV; 2268 } 2269 } 2270 #endif 2271 #ifdef CONFIG_DRM_AMDGPU_CIK 2272 if (!amdgpu_cik_support) { 2273 switch (flags & AMD_ASIC_MASK) { 2274 case CHIP_KAVERI: 2275 case CHIP_BONAIRE: 2276 case CHIP_HAWAII: 2277 case CHIP_KABINI: 2278 case CHIP_MULLINS: 2279 dev_info(&pdev->dev, 2280 "CIK support provided by radeon.\n"); 2281 dev_info(&pdev->dev, 2282 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 2283 ); 2284 return -ENODEV; 2285 } 2286 } 2287 #endif 2288 2289 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2290 if (IS_ERR(adev)) 2291 return PTR_ERR(adev); 2292 2293 adev->dev = &pdev->dev; 2294 adev->pdev = pdev; 2295 ddev = adev_to_drm(adev); 2296 2297 if (!supports_atomic) 2298 ddev->driver_features &= ~DRIVER_ATOMIC; 2299 2300 ret = pci_enable_device(pdev); 2301 if (ret) 2302 return ret; 2303 2304 pci_set_drvdata(pdev, ddev); 2305 2306 amdgpu_init_debug_options(adev); 2307 2308 ret = amdgpu_driver_load_kms(adev, flags); 2309 if (ret) 2310 goto err_pci; 2311 2312 retry_init: 2313 ret = drm_dev_register(ddev, flags); 2314 if (ret == -EAGAIN && ++retry <= 3) { 2315 DRM_INFO("retry init %d\n", retry); 2316 /* Don't request EX mode too frequently which is attacking */ 2317 msleep(5000); 2318 goto retry_init; 2319 } else if (ret) { 2320 goto err_pci; 2321 } 2322 2323 ret = amdgpu_xcp_dev_register(adev, ent); 2324 if (ret) 2325 goto err_pci; 2326 2327 ret = amdgpu_amdkfd_drm_client_create(adev); 2328 if (ret) 2329 goto err_pci; 2330 2331 /* 2332 * 1. don't init fbdev on hw without DCE 2333 * 2. don't init fbdev if there are no connectors 2334 */ 2335 if (adev->mode_info.mode_config_initialized && 2336 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2337 /* select 8 bpp console on low vram cards */ 2338 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2339 drm_fbdev_generic_setup(adev_to_drm(adev), 8); 2340 else 2341 drm_fbdev_generic_setup(adev_to_drm(adev), 32); 2342 } 2343 2344 ret = amdgpu_debugfs_init(adev); 2345 if (ret) 2346 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2347 2348 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2349 /* only need to skip on ATPX */ 2350 if (amdgpu_device_supports_px(ddev)) 2351 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2352 /* we want direct complete for BOCO */ 2353 if (amdgpu_device_supports_boco(ddev)) 2354 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2355 DPM_FLAG_SMART_SUSPEND | 2356 DPM_FLAG_MAY_SKIP_RESUME); 2357 pm_runtime_use_autosuspend(ddev->dev); 2358 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2359 2360 pm_runtime_allow(ddev->dev); 2361 2362 pm_runtime_mark_last_busy(ddev->dev); 2363 pm_runtime_put_autosuspend(ddev->dev); 2364 2365 pci_wake_from_d3(pdev, TRUE); 2366 2367 /* 2368 * For runpm implemented via BACO, PMFW will handle the 2369 * timing for BACO in and out: 2370 * - put ASIC into BACO state only when both video and 2371 * audio functions are in D3 state. 2372 * - pull ASIC out of BACO state when either video or 2373 * audio function is in D0 state. 2374 * Also, at startup, PMFW assumes both functions are in 2375 * D0 state. 2376 * 2377 * So if snd driver was loaded prior to amdgpu driver 2378 * and audio function was put into D3 state, there will 2379 * be no PMFW-aware D-state transition(D0->D3) on runpm 2380 * suspend. Thus the BACO will be not correctly kicked in. 2381 * 2382 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2383 * into D0 state. Then there will be a PMFW-aware D-state 2384 * transition(D0->D3) on runpm suspend. 2385 */ 2386 if (amdgpu_device_supports_baco(ddev) && 2387 !(adev->flags & AMD_IS_APU) && 2388 (adev->asic_type >= CHIP_NAVI10)) 2389 amdgpu_get_secondary_funcs(adev); 2390 } 2391 2392 return 0; 2393 2394 err_pci: 2395 pci_disable_device(pdev); 2396 return ret; 2397 } 2398 2399 static void 2400 amdgpu_pci_remove(struct pci_dev *pdev) 2401 { 2402 struct drm_device *dev = pci_get_drvdata(pdev); 2403 struct amdgpu_device *adev = drm_to_adev(dev); 2404 2405 amdgpu_xcp_dev_unplug(adev); 2406 drm_dev_unplug(dev); 2407 2408 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2409 pm_runtime_get_sync(dev->dev); 2410 pm_runtime_forbid(dev->dev); 2411 } 2412 2413 amdgpu_driver_unload_kms(dev); 2414 2415 /* 2416 * Flush any in flight DMA operations from device. 2417 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2418 * StatusTransactions Pending bit. 2419 */ 2420 pci_disable_device(pdev); 2421 pci_wait_for_pending_transaction(pdev); 2422 } 2423 2424 static void 2425 amdgpu_pci_shutdown(struct pci_dev *pdev) 2426 { 2427 struct drm_device *dev = pci_get_drvdata(pdev); 2428 struct amdgpu_device *adev = drm_to_adev(dev); 2429 2430 if (amdgpu_ras_intr_triggered()) 2431 return; 2432 2433 /* if we are running in a VM, make sure the device 2434 * torn down properly on reboot/shutdown. 2435 * unfortunately we can't detect certain 2436 * hypervisors so just do this all the time. 2437 */ 2438 if (!amdgpu_passthrough(adev)) 2439 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2440 amdgpu_device_ip_suspend(adev); 2441 adev->mp1_state = PP_MP1_STATE_NONE; 2442 } 2443 2444 /** 2445 * amdgpu_drv_delayed_reset_work_handler - work handler for reset 2446 * 2447 * @work: work_struct. 2448 */ 2449 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) 2450 { 2451 struct list_head device_list; 2452 struct amdgpu_device *adev; 2453 int i, r; 2454 struct amdgpu_reset_context reset_context; 2455 2456 memset(&reset_context, 0, sizeof(reset_context)); 2457 2458 mutex_lock(&mgpu_info.mutex); 2459 if (mgpu_info.pending_reset == true) { 2460 mutex_unlock(&mgpu_info.mutex); 2461 return; 2462 } 2463 mgpu_info.pending_reset = true; 2464 mutex_unlock(&mgpu_info.mutex); 2465 2466 /* Use a common context, just need to make sure full reset is done */ 2467 reset_context.method = AMD_RESET_METHOD_NONE; 2468 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2469 2470 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2471 adev = mgpu_info.gpu_ins[i].adev; 2472 reset_context.reset_req_dev = adev; 2473 r = amdgpu_device_pre_asic_reset(adev, &reset_context); 2474 if (r) { 2475 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", 2476 r, adev_to_drm(adev)->unique); 2477 } 2478 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) 2479 r = -EALREADY; 2480 } 2481 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2482 adev = mgpu_info.gpu_ins[i].adev; 2483 flush_work(&adev->xgmi_reset_work); 2484 adev->gmc.xgmi.pending_reset = false; 2485 } 2486 2487 /* reset function will rebuild the xgmi hive info , clear it now */ 2488 for (i = 0; i < mgpu_info.num_dgpu; i++) 2489 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); 2490 2491 INIT_LIST_HEAD(&device_list); 2492 2493 for (i = 0; i < mgpu_info.num_dgpu; i++) 2494 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); 2495 2496 /* unregister the GPU first, reset function will add them back */ 2497 list_for_each_entry(adev, &device_list, reset_list) 2498 amdgpu_unregister_gpu_instance(adev); 2499 2500 /* Use a common context, just need to make sure full reset is done */ 2501 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); 2502 set_bit(AMDGPU_SKIP_COREDUMP, &reset_context.flags); 2503 r = amdgpu_do_asic_reset(&device_list, &reset_context); 2504 2505 if (r) { 2506 DRM_ERROR("reinit gpus failure"); 2507 return; 2508 } 2509 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2510 adev = mgpu_info.gpu_ins[i].adev; 2511 if (!adev->kfd.init_complete) { 2512 kgd2kfd_init_zone_device(adev); 2513 amdgpu_amdkfd_device_init(adev); 2514 amdgpu_amdkfd_drm_client_create(adev); 2515 } 2516 amdgpu_ttm_set_buffer_funcs_status(adev, true); 2517 } 2518 } 2519 2520 static int amdgpu_pmops_prepare(struct device *dev) 2521 { 2522 struct drm_device *drm_dev = dev_get_drvdata(dev); 2523 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2524 2525 /* Return a positive number here so 2526 * DPM_FLAG_SMART_SUSPEND works properly 2527 */ 2528 if (amdgpu_device_supports_boco(drm_dev) && 2529 pm_runtime_suspended(dev)) 2530 return 1; 2531 2532 /* if we will not support s3 or s2i for the device 2533 * then skip suspend 2534 */ 2535 if (!amdgpu_acpi_is_s0ix_active(adev) && 2536 !amdgpu_acpi_is_s3_active(adev)) 2537 return 1; 2538 2539 return amdgpu_device_prepare(drm_dev); 2540 } 2541 2542 static void amdgpu_pmops_complete(struct device *dev) 2543 { 2544 /* nothing to do */ 2545 } 2546 2547 static int amdgpu_pmops_suspend(struct device *dev) 2548 { 2549 struct drm_device *drm_dev = dev_get_drvdata(dev); 2550 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2551 2552 adev->suspend_complete = false; 2553 if (amdgpu_acpi_is_s0ix_active(adev)) 2554 adev->in_s0ix = true; 2555 else if (amdgpu_acpi_is_s3_active(adev)) 2556 adev->in_s3 = true; 2557 if (!adev->in_s0ix && !adev->in_s3) 2558 return 0; 2559 return amdgpu_device_suspend(drm_dev, true); 2560 } 2561 2562 static int amdgpu_pmops_suspend_noirq(struct device *dev) 2563 { 2564 struct drm_device *drm_dev = dev_get_drvdata(dev); 2565 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2566 2567 adev->suspend_complete = true; 2568 if (amdgpu_acpi_should_gpu_reset(adev)) 2569 return amdgpu_asic_reset(adev); 2570 2571 return 0; 2572 } 2573 2574 static int amdgpu_pmops_resume(struct device *dev) 2575 { 2576 struct drm_device *drm_dev = dev_get_drvdata(dev); 2577 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2578 int r; 2579 2580 if (!adev->in_s0ix && !adev->in_s3) 2581 return 0; 2582 2583 /* Avoids registers access if device is physically gone */ 2584 if (!pci_device_is_present(adev->pdev)) 2585 adev->no_hw_access = true; 2586 2587 r = amdgpu_device_resume(drm_dev, true); 2588 if (amdgpu_acpi_is_s0ix_active(adev)) 2589 adev->in_s0ix = false; 2590 else 2591 adev->in_s3 = false; 2592 return r; 2593 } 2594 2595 static int amdgpu_pmops_freeze(struct device *dev) 2596 { 2597 struct drm_device *drm_dev = dev_get_drvdata(dev); 2598 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2599 int r; 2600 2601 adev->in_s4 = true; 2602 r = amdgpu_device_suspend(drm_dev, true); 2603 adev->in_s4 = false; 2604 if (r) 2605 return r; 2606 2607 if (amdgpu_acpi_should_gpu_reset(adev)) 2608 return amdgpu_asic_reset(adev); 2609 return 0; 2610 } 2611 2612 static int amdgpu_pmops_thaw(struct device *dev) 2613 { 2614 struct drm_device *drm_dev = dev_get_drvdata(dev); 2615 2616 return amdgpu_device_resume(drm_dev, true); 2617 } 2618 2619 static int amdgpu_pmops_poweroff(struct device *dev) 2620 { 2621 struct drm_device *drm_dev = dev_get_drvdata(dev); 2622 2623 return amdgpu_device_suspend(drm_dev, true); 2624 } 2625 2626 static int amdgpu_pmops_restore(struct device *dev) 2627 { 2628 struct drm_device *drm_dev = dev_get_drvdata(dev); 2629 2630 return amdgpu_device_resume(drm_dev, true); 2631 } 2632 2633 static int amdgpu_runtime_idle_check_display(struct device *dev) 2634 { 2635 struct pci_dev *pdev = to_pci_dev(dev); 2636 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2637 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2638 2639 if (adev->mode_info.num_crtc) { 2640 struct drm_connector *list_connector; 2641 struct drm_connector_list_iter iter; 2642 int ret = 0; 2643 2644 if (amdgpu_runtime_pm != -2) { 2645 /* XXX: Return busy if any displays are connected to avoid 2646 * possible display wakeups after runtime resume due to 2647 * hotplug events in case any displays were connected while 2648 * the GPU was in suspend. Remove this once that is fixed. 2649 */ 2650 mutex_lock(&drm_dev->mode_config.mutex); 2651 drm_connector_list_iter_begin(drm_dev, &iter); 2652 drm_for_each_connector_iter(list_connector, &iter) { 2653 if (list_connector->status == connector_status_connected) { 2654 ret = -EBUSY; 2655 break; 2656 } 2657 } 2658 drm_connector_list_iter_end(&iter); 2659 mutex_unlock(&drm_dev->mode_config.mutex); 2660 2661 if (ret) 2662 return ret; 2663 } 2664 2665 if (adev->dc_enabled) { 2666 struct drm_crtc *crtc; 2667 2668 drm_for_each_crtc(crtc, drm_dev) { 2669 drm_modeset_lock(&crtc->mutex, NULL); 2670 if (crtc->state->active) 2671 ret = -EBUSY; 2672 drm_modeset_unlock(&crtc->mutex); 2673 if (ret < 0) 2674 break; 2675 } 2676 } else { 2677 mutex_lock(&drm_dev->mode_config.mutex); 2678 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2679 2680 drm_connector_list_iter_begin(drm_dev, &iter); 2681 drm_for_each_connector_iter(list_connector, &iter) { 2682 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2683 ret = -EBUSY; 2684 break; 2685 } 2686 } 2687 2688 drm_connector_list_iter_end(&iter); 2689 2690 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2691 mutex_unlock(&drm_dev->mode_config.mutex); 2692 } 2693 if (ret) 2694 return ret; 2695 } 2696 2697 return 0; 2698 } 2699 2700 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2701 { 2702 struct pci_dev *pdev = to_pci_dev(dev); 2703 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2704 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2705 int ret, i; 2706 2707 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2708 pm_runtime_forbid(dev); 2709 return -EBUSY; 2710 } 2711 2712 ret = amdgpu_runtime_idle_check_display(dev); 2713 if (ret) 2714 return ret; 2715 2716 /* wait for all rings to drain before suspending */ 2717 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2718 struct amdgpu_ring *ring = adev->rings[i]; 2719 2720 if (ring && ring->sched.ready) { 2721 ret = amdgpu_fence_wait_empty(ring); 2722 if (ret) 2723 return -EBUSY; 2724 } 2725 } 2726 2727 adev->in_runpm = true; 2728 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2729 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2730 2731 /* 2732 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2733 * proper cleanups and put itself into a state ready for PNP. That 2734 * can address some random resuming failure observed on BOCO capable 2735 * platforms. 2736 * TODO: this may be also needed for PX capable platform. 2737 */ 2738 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2739 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2740 2741 ret = amdgpu_device_prepare(drm_dev); 2742 if (ret) 2743 return ret; 2744 ret = amdgpu_device_suspend(drm_dev, false); 2745 if (ret) { 2746 adev->in_runpm = false; 2747 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2748 adev->mp1_state = PP_MP1_STATE_NONE; 2749 return ret; 2750 } 2751 2752 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2753 adev->mp1_state = PP_MP1_STATE_NONE; 2754 2755 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) { 2756 /* Only need to handle PCI state in the driver for ATPX 2757 * PCI core handles it for _PR3. 2758 */ 2759 amdgpu_device_cache_pci_state(pdev); 2760 pci_disable_device(pdev); 2761 pci_ignore_hotplug(pdev); 2762 pci_set_power_state(pdev, PCI_D3cold); 2763 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2764 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) { 2765 /* nothing to do */ 2766 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2767 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) { 2768 amdgpu_device_baco_enter(drm_dev); 2769 } 2770 2771 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n"); 2772 2773 return 0; 2774 } 2775 2776 static int amdgpu_pmops_runtime_resume(struct device *dev) 2777 { 2778 struct pci_dev *pdev = to_pci_dev(dev); 2779 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2780 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2781 int ret; 2782 2783 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) 2784 return -EINVAL; 2785 2786 /* Avoids registers access if device is physically gone */ 2787 if (!pci_device_is_present(adev->pdev)) 2788 adev->no_hw_access = true; 2789 2790 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) { 2791 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2792 2793 /* Only need to handle PCI state in the driver for ATPX 2794 * PCI core handles it for _PR3. 2795 */ 2796 pci_set_power_state(pdev, PCI_D0); 2797 amdgpu_device_load_pci_state(pdev); 2798 ret = pci_enable_device(pdev); 2799 if (ret) 2800 return ret; 2801 pci_set_master(pdev); 2802 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) { 2803 /* Only need to handle PCI state in the driver for ATPX 2804 * PCI core handles it for _PR3. 2805 */ 2806 pci_set_master(pdev); 2807 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2808 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) { 2809 amdgpu_device_baco_exit(drm_dev); 2810 } 2811 ret = amdgpu_device_resume(drm_dev, false); 2812 if (ret) { 2813 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2814 pci_disable_device(pdev); 2815 return ret; 2816 } 2817 2818 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2819 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2820 adev->in_runpm = false; 2821 return 0; 2822 } 2823 2824 static int amdgpu_pmops_runtime_idle(struct device *dev) 2825 { 2826 struct drm_device *drm_dev = dev_get_drvdata(dev); 2827 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2828 int ret; 2829 2830 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2831 pm_runtime_forbid(dev); 2832 return -EBUSY; 2833 } 2834 2835 ret = amdgpu_runtime_idle_check_display(dev); 2836 2837 pm_runtime_mark_last_busy(dev); 2838 pm_runtime_autosuspend(dev); 2839 return ret; 2840 } 2841 2842 long amdgpu_drm_ioctl(struct file *filp, 2843 unsigned int cmd, unsigned long arg) 2844 { 2845 struct drm_file *file_priv = filp->private_data; 2846 struct drm_device *dev; 2847 long ret; 2848 2849 dev = file_priv->minor->dev; 2850 ret = pm_runtime_get_sync(dev->dev); 2851 if (ret < 0) 2852 goto out; 2853 2854 ret = drm_ioctl(filp, cmd, arg); 2855 2856 pm_runtime_mark_last_busy(dev->dev); 2857 out: 2858 pm_runtime_put_autosuspend(dev->dev); 2859 return ret; 2860 } 2861 2862 static const struct dev_pm_ops amdgpu_pm_ops = { 2863 .prepare = amdgpu_pmops_prepare, 2864 .complete = amdgpu_pmops_complete, 2865 .suspend = amdgpu_pmops_suspend, 2866 .suspend_noirq = amdgpu_pmops_suspend_noirq, 2867 .resume = amdgpu_pmops_resume, 2868 .freeze = amdgpu_pmops_freeze, 2869 .thaw = amdgpu_pmops_thaw, 2870 .poweroff = amdgpu_pmops_poweroff, 2871 .restore = amdgpu_pmops_restore, 2872 .runtime_suspend = amdgpu_pmops_runtime_suspend, 2873 .runtime_resume = amdgpu_pmops_runtime_resume, 2874 .runtime_idle = amdgpu_pmops_runtime_idle, 2875 }; 2876 2877 static int amdgpu_flush(struct file *f, fl_owner_t id) 2878 { 2879 struct drm_file *file_priv = f->private_data; 2880 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2881 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2882 2883 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 2884 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 2885 2886 return timeout >= 0 ? 0 : timeout; 2887 } 2888 2889 static const struct file_operations amdgpu_driver_kms_fops = { 2890 .owner = THIS_MODULE, 2891 .open = drm_open, 2892 .flush = amdgpu_flush, 2893 .release = drm_release, 2894 .unlocked_ioctl = amdgpu_drm_ioctl, 2895 .mmap = drm_gem_mmap, 2896 .poll = drm_poll, 2897 .read = drm_read, 2898 #ifdef CONFIG_COMPAT 2899 .compat_ioctl = amdgpu_kms_compat_ioctl, 2900 #endif 2901 #ifdef CONFIG_PROC_FS 2902 .show_fdinfo = drm_show_fdinfo, 2903 #endif 2904 }; 2905 2906 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 2907 { 2908 struct drm_file *file; 2909 2910 if (!filp) 2911 return -EINVAL; 2912 2913 if (filp->f_op != &amdgpu_driver_kms_fops) 2914 return -EINVAL; 2915 2916 file = filp->private_data; 2917 *fpriv = file->driver_priv; 2918 return 0; 2919 } 2920 2921 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 2922 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2923 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2924 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2925 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 2926 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2927 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2928 /* KMS */ 2929 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2930 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2931 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2932 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2933 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2934 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2935 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2936 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2937 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2938 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2939 }; 2940 2941 static const struct drm_driver amdgpu_kms_driver = { 2942 .driver_features = 2943 DRIVER_ATOMIC | 2944 DRIVER_GEM | 2945 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 2946 DRIVER_SYNCOBJ_TIMELINE, 2947 .open = amdgpu_driver_open_kms, 2948 .postclose = amdgpu_driver_postclose_kms, 2949 .lastclose = amdgpu_driver_lastclose_kms, 2950 .ioctls = amdgpu_ioctls_kms, 2951 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2952 .dumb_create = amdgpu_mode_dumb_create, 2953 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2954 .fops = &amdgpu_driver_kms_fops, 2955 .release = &amdgpu_driver_release_kms, 2956 #ifdef CONFIG_PROC_FS 2957 .show_fdinfo = amdgpu_show_fdinfo, 2958 #endif 2959 2960 .gem_prime_import = amdgpu_gem_prime_import, 2961 2962 .name = DRIVER_NAME, 2963 .desc = DRIVER_DESC, 2964 .date = DRIVER_DATE, 2965 .major = KMS_DRIVER_MAJOR, 2966 .minor = KMS_DRIVER_MINOR, 2967 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2968 }; 2969 2970 const struct drm_driver amdgpu_partition_driver = { 2971 .driver_features = 2972 DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ | 2973 DRIVER_SYNCOBJ_TIMELINE, 2974 .open = amdgpu_driver_open_kms, 2975 .postclose = amdgpu_driver_postclose_kms, 2976 .lastclose = amdgpu_driver_lastclose_kms, 2977 .ioctls = amdgpu_ioctls_kms, 2978 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2979 .dumb_create = amdgpu_mode_dumb_create, 2980 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2981 .fops = &amdgpu_driver_kms_fops, 2982 .release = &amdgpu_driver_release_kms, 2983 2984 .gem_prime_import = amdgpu_gem_prime_import, 2985 2986 .name = DRIVER_NAME, 2987 .desc = DRIVER_DESC, 2988 .date = DRIVER_DATE, 2989 .major = KMS_DRIVER_MAJOR, 2990 .minor = KMS_DRIVER_MINOR, 2991 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2992 }; 2993 2994 static struct pci_error_handlers amdgpu_pci_err_handler = { 2995 .error_detected = amdgpu_pci_error_detected, 2996 .mmio_enabled = amdgpu_pci_mmio_enabled, 2997 .slot_reset = amdgpu_pci_slot_reset, 2998 .resume = amdgpu_pci_resume, 2999 }; 3000 3001 static const struct attribute_group *amdgpu_sysfs_groups[] = { 3002 &amdgpu_vram_mgr_attr_group, 3003 &amdgpu_gtt_mgr_attr_group, 3004 &amdgpu_flash_attr_group, 3005 NULL, 3006 }; 3007 3008 static struct pci_driver amdgpu_kms_pci_driver = { 3009 .name = DRIVER_NAME, 3010 .id_table = pciidlist, 3011 .probe = amdgpu_pci_probe, 3012 .remove = amdgpu_pci_remove, 3013 .shutdown = amdgpu_pci_shutdown, 3014 .driver.pm = &amdgpu_pm_ops, 3015 .err_handler = &amdgpu_pci_err_handler, 3016 .dev_groups = amdgpu_sysfs_groups, 3017 }; 3018 3019 static int __init amdgpu_init(void) 3020 { 3021 int r; 3022 3023 if (drm_firmware_drivers_only()) 3024 return -EINVAL; 3025 3026 r = amdgpu_sync_init(); 3027 if (r) 3028 goto error_sync; 3029 3030 r = amdgpu_fence_slab_init(); 3031 if (r) 3032 goto error_fence; 3033 3034 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 3035 amdgpu_register_atpx_handler(); 3036 amdgpu_acpi_detect(); 3037 3038 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 3039 amdgpu_amdkfd_init(); 3040 3041 /* let modprobe override vga console setting */ 3042 return pci_register_driver(&amdgpu_kms_pci_driver); 3043 3044 error_fence: 3045 amdgpu_sync_fini(); 3046 3047 error_sync: 3048 return r; 3049 } 3050 3051 static void __exit amdgpu_exit(void) 3052 { 3053 amdgpu_amdkfd_fini(); 3054 pci_unregister_driver(&amdgpu_kms_pci_driver); 3055 amdgpu_unregister_atpx_handler(); 3056 amdgpu_acpi_release(); 3057 amdgpu_sync_fini(); 3058 amdgpu_fence_slab_fini(); 3059 mmu_notifier_synchronize(); 3060 amdgpu_xcp_drv_release(); 3061 } 3062 3063 module_init(amdgpu_init); 3064 module_exit(amdgpu_exit); 3065 3066 MODULE_AUTHOR(DRIVER_AUTHOR); 3067 MODULE_DESCRIPTION(DRIVER_DESC); 3068 MODULE_LICENSE("GPL and additional rights"); 3069