1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_drv.h> 27 #include <drm/drm_fbdev_generic.h> 28 #include <drm/drm_gem.h> 29 #include <drm/drm_managed.h> 30 #include <drm/drm_pciids.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/drm_vblank.h> 33 34 #include <linux/cc_platform.h> 35 #include <linux/dynamic_debug.h> 36 #include <linux/module.h> 37 #include <linux/mmu_notifier.h> 38 #include <linux/pm_runtime.h> 39 #include <linux/suspend.h> 40 #include <linux/vga_switcheroo.h> 41 42 #include "amdgpu.h" 43 #include "amdgpu_amdkfd.h" 44 #include "amdgpu_dma_buf.h" 45 #include "amdgpu_drv.h" 46 #include "amdgpu_fdinfo.h" 47 #include "amdgpu_irq.h" 48 #include "amdgpu_psp.h" 49 #include "amdgpu_ras.h" 50 #include "amdgpu_reset.h" 51 #include "amdgpu_sched.h" 52 #include "amdgpu_xgmi.h" 53 #include "../amdxcp/amdgpu_xcp_drv.h" 54 55 /* 56 * KMS wrapper. 57 * - 3.0.0 - initial driver 58 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 59 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 60 * at the end of IBs. 61 * - 3.3.0 - Add VM support for UVD on supported hardware. 62 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 63 * - 3.5.0 - Add support for new UVD_NO_OP register. 64 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 65 * - 3.7.0 - Add support for VCE clock list packet 66 * - 3.8.0 - Add support raster config init in the kernel 67 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 68 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 69 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 70 * - 3.12.0 - Add query for double offchip LDS buffers 71 * - 3.13.0 - Add PRT support 72 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 73 * - 3.15.0 - Export more gpu info for gfx9 74 * - 3.16.0 - Add reserved vmid support 75 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 76 * - 3.18.0 - Export gpu always on cu bitmap 77 * - 3.19.0 - Add support for UVD MJPEG decode 78 * - 3.20.0 - Add support for local BOs 79 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 80 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 81 * - 3.23.0 - Add query for VRAM lost counter 82 * - 3.24.0 - Add high priority compute support for gfx9 83 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 84 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 85 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation. 86 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 87 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 88 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 89 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 90 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 91 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 92 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 93 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 94 * - 3.36.0 - Allow reading more status registers on si/cik 95 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 96 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 97 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 98 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 99 * - 3.41.0 - Add video codec query 100 * - 3.42.0 - Add 16bpc fixed point display support 101 * - 3.43.0 - Add device hot plug/unplug support 102 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 103 * - 3.45.0 - Add context ioctl stable pstate interface 104 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm 105 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags 106 * - 3.48.0 - Add IP discovery version info to HW INFO 107 * - 3.49.0 - Add gang submit into CS IOCTL 108 * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock 109 * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock 110 * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl 111 * 3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields: 112 * tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size, 113 * gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi 114 * 3.53.0 - Support for GFX11 CP GFX shadowing 115 * 3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support 116 * - 3.55.0 - Add AMDGPU_INFO_GPUVM_FAULT query 117 * - 3.56.0 - Update IB start address and size alignment for decode and encode 118 * - 3.57.0 - Compute tunneling on GFX10+ 119 */ 120 #define KMS_DRIVER_MAJOR 3 121 #define KMS_DRIVER_MINOR 57 122 #define KMS_DRIVER_PATCHLEVEL 0 123 124 /* 125 * amdgpu.debug module options. Are all disabled by default 126 */ 127 enum AMDGPU_DEBUG_MASK { 128 AMDGPU_DEBUG_VM = BIT(0), 129 AMDGPU_DEBUG_LARGEBAR = BIT(1), 130 AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY = BIT(2), 131 AMDGPU_DEBUG_USE_VRAM_FW_BUF = BIT(3), 132 }; 133 134 unsigned int amdgpu_vram_limit = UINT_MAX; 135 int amdgpu_vis_vram_limit; 136 int amdgpu_gart_size = -1; /* auto */ 137 int amdgpu_gtt_size = -1; /* auto */ 138 int amdgpu_moverate = -1; /* auto */ 139 int amdgpu_audio = -1; 140 int amdgpu_disp_priority; 141 int amdgpu_hw_i2c; 142 int amdgpu_pcie_gen2 = -1; 143 int amdgpu_msi = -1; 144 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 145 int amdgpu_dpm = -1; 146 int amdgpu_fw_load_type = -1; 147 int amdgpu_aspm = -1; 148 int amdgpu_runtime_pm = -1; 149 uint amdgpu_ip_block_mask = 0xffffffff; 150 int amdgpu_bapm = -1; 151 int amdgpu_deep_color; 152 int amdgpu_vm_size = -1; 153 int amdgpu_vm_fragment_size = -1; 154 int amdgpu_vm_block_size = -1; 155 int amdgpu_vm_fault_stop; 156 int amdgpu_vm_update_mode = -1; 157 int amdgpu_exp_hw_support; 158 int amdgpu_dc = -1; 159 int amdgpu_sched_jobs = 32; 160 int amdgpu_sched_hw_submission = 2; 161 uint amdgpu_pcie_gen_cap; 162 uint amdgpu_pcie_lane_cap; 163 u64 amdgpu_cg_mask = 0xffffffffffffffff; 164 uint amdgpu_pg_mask = 0xffffffff; 165 uint amdgpu_sdma_phase_quantum = 32; 166 char *amdgpu_disable_cu; 167 char *amdgpu_virtual_display; 168 bool enforce_isolation; 169 /* 170 * OverDrive(bit 14) disabled by default 171 * GFX DCS(bit 19) disabled by default 172 */ 173 uint amdgpu_pp_feature_mask = 0xfff7bfff; 174 uint amdgpu_force_long_training; 175 int amdgpu_lbpw = -1; 176 int amdgpu_compute_multipipe = -1; 177 int amdgpu_gpu_recovery = -1; /* auto */ 178 int amdgpu_emu_mode; 179 uint amdgpu_smu_memory_pool_size; 180 int amdgpu_smu_pptable_id = -1; 181 /* 182 * FBC (bit 0) disabled by default 183 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 184 * - With this, for multiple monitors in sync(e.g. with the same model), 185 * mclk switching will be allowed. And the mclk will be not foced to the 186 * highest. That helps saving some idle power. 187 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 188 * PSR (bit 3) disabled by default 189 * EDP NO POWER SEQUENCING (bit 4) disabled by default 190 */ 191 uint amdgpu_dc_feature_mask = 2; 192 uint amdgpu_dc_debug_mask; 193 uint amdgpu_dc_visual_confirm; 194 int amdgpu_async_gfx_ring = 1; 195 int amdgpu_mcbp = -1; 196 int amdgpu_discovery = -1; 197 int amdgpu_mes; 198 int amdgpu_mes_kiq; 199 int amdgpu_noretry = -1; 200 int amdgpu_force_asic_type = -1; 201 int amdgpu_tmz = -1; /* auto */ 202 uint amdgpu_freesync_vid_mode; 203 int amdgpu_reset_method = -1; /* auto */ 204 int amdgpu_num_kcq = -1; 205 int amdgpu_smartshift_bias; 206 int amdgpu_use_xgmi_p2p = 1; 207 int amdgpu_vcnfw_log; 208 int amdgpu_sg_display = -1; /* auto */ 209 int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE; 210 int amdgpu_umsch_mm; 211 int amdgpu_seamless = -1; /* auto */ 212 uint amdgpu_debug_mask; 213 int amdgpu_agp = -1; /* auto */ 214 int amdgpu_wbrf = -1; 215 int amdgpu_damage_clips = -1; /* auto */ 216 217 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 218 219 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 220 "DRM_UT_CORE", 221 "DRM_UT_DRIVER", 222 "DRM_UT_KMS", 223 "DRM_UT_PRIME", 224 "DRM_UT_ATOMIC", 225 "DRM_UT_VBL", 226 "DRM_UT_STATE", 227 "DRM_UT_LEASE", 228 "DRM_UT_DP", 229 "DRM_UT_DRMRES"); 230 231 struct amdgpu_mgpu_info mgpu_info = { 232 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 233 .delayed_reset_work = __DELAYED_WORK_INITIALIZER( 234 mgpu_info.delayed_reset_work, 235 amdgpu_drv_delayed_reset_work_handler, 0), 236 }; 237 int amdgpu_ras_enable = -1; 238 uint amdgpu_ras_mask = 0xffffffff; 239 int amdgpu_bad_page_threshold = -1; 240 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 241 .timeout_fatal_disable = false, 242 .period = 0x0, /* default to 0x0 (timeout disable) */ 243 }; 244 245 /** 246 * DOC: vramlimit (int) 247 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 248 */ 249 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 250 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 251 252 /** 253 * DOC: vis_vramlimit (int) 254 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 255 */ 256 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 257 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 258 259 /** 260 * DOC: gartsize (uint) 261 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing. 262 * The default is -1 (The size depends on asic). 263 */ 264 MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)"); 265 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 266 267 /** 268 * DOC: gttsize (int) 269 * Restrict the size of GTT domain (for userspace use) in MiB for testing. 270 * The default is -1 (Use 1/2 RAM, minimum value is 3GB). 271 */ 272 MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)"); 273 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 274 275 /** 276 * DOC: moverate (int) 277 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 278 */ 279 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 280 module_param_named(moverate, amdgpu_moverate, int, 0600); 281 282 /** 283 * DOC: audio (int) 284 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 285 */ 286 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 287 module_param_named(audio, amdgpu_audio, int, 0444); 288 289 /** 290 * DOC: disp_priority (int) 291 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 292 */ 293 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 294 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 295 296 /** 297 * DOC: hw_i2c (int) 298 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 299 */ 300 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 301 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 302 303 /** 304 * DOC: pcie_gen2 (int) 305 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 306 */ 307 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 308 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 309 310 /** 311 * DOC: msi (int) 312 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 313 */ 314 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 315 module_param_named(msi, amdgpu_msi, int, 0444); 316 317 /** 318 * DOC: lockup_timeout (string) 319 * Set GPU scheduler timeout value in ms. 320 * 321 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 322 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 323 * to the default timeout. 324 * 325 * - With one value specified, the setting will apply to all non-compute jobs. 326 * - With multiple values specified, the first one will be for GFX. 327 * The second one is for Compute. The third and fourth ones are 328 * for SDMA and Video. 329 * 330 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 331 * jobs is 10000. The timeout for compute is 60000. 332 */ 333 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 334 "for passthrough or sriov, 10000 for all jobs. 0: keep default value. negative: infinity timeout), format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 335 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 336 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 337 338 /** 339 * DOC: dpm (int) 340 * Override for dynamic power management setting 341 * (0 = disable, 1 = enable) 342 * The default is -1 (auto). 343 */ 344 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 345 module_param_named(dpm, amdgpu_dpm, int, 0444); 346 347 /** 348 * DOC: fw_load_type (int) 349 * Set different firmware loading type for debugging, if supported. 350 * Set to 0 to force direct loading if supported by the ASIC. Set 351 * to -1 to select the default loading mode for the ASIC, as defined 352 * by the driver. The default is -1 (auto). 353 */ 354 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); 355 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 356 357 /** 358 * DOC: aspm (int) 359 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 360 */ 361 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 362 module_param_named(aspm, amdgpu_aspm, int, 0444); 363 364 /** 365 * DOC: runpm (int) 366 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 367 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 368 * Setting the value to 0 disables this functionality. 369 * Setting the value to -2 is auto enabled with power down when displays are attached. 370 */ 371 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto, -2 = auto with displays)"); 372 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 373 374 /** 375 * DOC: ip_block_mask (uint) 376 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 377 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 378 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 379 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 380 */ 381 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 382 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 383 384 /** 385 * DOC: bapm (int) 386 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 387 * The default -1 (auto, enabled) 388 */ 389 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 390 module_param_named(bapm, amdgpu_bapm, int, 0444); 391 392 /** 393 * DOC: deep_color (int) 394 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 395 */ 396 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 397 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 398 399 /** 400 * DOC: vm_size (int) 401 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 402 */ 403 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 404 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 405 406 /** 407 * DOC: vm_fragment_size (int) 408 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 409 */ 410 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 411 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 412 413 /** 414 * DOC: vm_block_size (int) 415 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 416 */ 417 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 418 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 419 420 /** 421 * DOC: vm_fault_stop (int) 422 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 423 */ 424 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 425 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 426 427 /** 428 * DOC: vm_update_mode (int) 429 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 430 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 431 */ 432 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 433 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 434 435 /** 436 * DOC: exp_hw_support (int) 437 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 438 */ 439 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 440 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 441 442 /** 443 * DOC: dc (int) 444 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 445 */ 446 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 447 module_param_named(dc, amdgpu_dc, int, 0444); 448 449 /** 450 * DOC: sched_jobs (int) 451 * Override the max number of jobs supported in the sw queue. The default is 32. 452 */ 453 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 454 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 455 456 /** 457 * DOC: sched_hw_submission (int) 458 * Override the max number of HW submissions. The default is 2. 459 */ 460 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 461 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 462 463 /** 464 * DOC: ppfeaturemask (hexint) 465 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 466 * The default is the current set of stable power features. 467 */ 468 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 469 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 470 471 /** 472 * DOC: forcelongtraining (uint) 473 * Force long memory training in resume. 474 * The default is zero, indicates short training in resume. 475 */ 476 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 477 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 478 479 /** 480 * DOC: pcie_gen_cap (uint) 481 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 482 * The default is 0 (automatic for each asic). 483 */ 484 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 485 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 486 487 /** 488 * DOC: pcie_lane_cap (uint) 489 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 490 * The default is 0 (automatic for each asic). 491 */ 492 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 493 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 494 495 /** 496 * DOC: cg_mask (ullong) 497 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 498 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 499 */ 500 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 501 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 502 503 /** 504 * DOC: pg_mask (uint) 505 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 506 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 507 */ 508 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 509 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 510 511 /** 512 * DOC: sdma_phase_quantum (uint) 513 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 514 */ 515 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 516 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 517 518 /** 519 * DOC: disable_cu (charp) 520 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 521 */ 522 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 523 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 524 525 /** 526 * DOC: virtual_display (charp) 527 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 528 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 529 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 530 * device at 26:00.0. The default is NULL. 531 */ 532 MODULE_PARM_DESC(virtual_display, 533 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 534 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 535 536 /** 537 * DOC: lbpw (int) 538 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 539 */ 540 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 541 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 542 543 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 544 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 545 546 /** 547 * DOC: gpu_recovery (int) 548 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 549 */ 550 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 551 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 552 553 /** 554 * DOC: emu_mode (int) 555 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 556 */ 557 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 558 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 559 560 /** 561 * DOC: ras_enable (int) 562 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 563 */ 564 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 565 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 566 567 /** 568 * DOC: ras_mask (uint) 569 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 570 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 571 */ 572 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 573 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 574 575 /** 576 * DOC: timeout_fatal_disable (bool) 577 * Disable Watchdog timeout fatal error event 578 */ 579 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 580 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 581 582 /** 583 * DOC: timeout_period (uint) 584 * Modify the watchdog timeout max_cycles as (1 << period) 585 */ 586 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 587 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 588 589 /** 590 * DOC: si_support (int) 591 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 592 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 593 * otherwise using amdgpu driver. 594 */ 595 #ifdef CONFIG_DRM_AMDGPU_SI 596 597 #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) 598 int amdgpu_si_support; 599 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 600 #else 601 int amdgpu_si_support = 1; 602 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 603 #endif 604 605 module_param_named(si_support, amdgpu_si_support, int, 0444); 606 #endif 607 608 /** 609 * DOC: cik_support (int) 610 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 611 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 612 * otherwise using amdgpu driver. 613 */ 614 #ifdef CONFIG_DRM_AMDGPU_CIK 615 616 #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) 617 int amdgpu_cik_support; 618 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 619 #else 620 int amdgpu_cik_support = 1; 621 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 622 #endif 623 624 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 625 #endif 626 627 /** 628 * DOC: smu_memory_pool_size (uint) 629 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 630 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 631 */ 632 MODULE_PARM_DESC(smu_memory_pool_size, 633 "reserve gtt for smu debug usage, 0 = disable,0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 634 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 635 636 /** 637 * DOC: async_gfx_ring (int) 638 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 639 */ 640 MODULE_PARM_DESC(async_gfx_ring, 641 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 642 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 643 644 /** 645 * DOC: mcbp (int) 646 * It is used to enable mid command buffer preemption. (0 = disabled, 1 = enabled, -1 auto (default)) 647 */ 648 MODULE_PARM_DESC(mcbp, 649 "Enable Mid-command buffer preemption (0 = disabled, 1 = enabled), -1 = auto (default)"); 650 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 651 652 /** 653 * DOC: discovery (int) 654 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 655 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 656 */ 657 MODULE_PARM_DESC(discovery, 658 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 659 module_param_named(discovery, amdgpu_discovery, int, 0444); 660 661 /** 662 * DOC: mes (int) 663 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 664 * (0 = disabled (default), 1 = enabled) 665 */ 666 MODULE_PARM_DESC(mes, 667 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 668 module_param_named(mes, amdgpu_mes, int, 0444); 669 670 /** 671 * DOC: mes_kiq (int) 672 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq. 673 * (0 = disabled (default), 1 = enabled) 674 */ 675 MODULE_PARM_DESC(mes_kiq, 676 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)"); 677 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444); 678 679 /** 680 * DOC: noretry (int) 681 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 682 * do not support per-process XNACK this also disables retry page faults. 683 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 684 */ 685 MODULE_PARM_DESC(noretry, 686 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 687 module_param_named(noretry, amdgpu_noretry, int, 0644); 688 689 /** 690 * DOC: force_asic_type (int) 691 * A non negative value used to specify the asic type for all supported GPUs. 692 */ 693 MODULE_PARM_DESC(force_asic_type, 694 "A non negative value used to specify the asic type for all supported GPUs"); 695 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 696 697 /** 698 * DOC: use_xgmi_p2p (int) 699 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 700 */ 701 MODULE_PARM_DESC(use_xgmi_p2p, 702 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 703 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 704 705 706 #ifdef CONFIG_HSA_AMD 707 /** 708 * DOC: sched_policy (int) 709 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 710 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 711 * assigns queues to HQDs. 712 */ 713 int sched_policy = KFD_SCHED_POLICY_HWS; 714 module_param(sched_policy, int, 0444); 715 MODULE_PARM_DESC(sched_policy, 716 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 717 718 /** 719 * DOC: hws_max_conc_proc (int) 720 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 721 * number of VMIDs assigned to the HWS, which is also the default. 722 */ 723 int hws_max_conc_proc = -1; 724 module_param(hws_max_conc_proc, int, 0444); 725 MODULE_PARM_DESC(hws_max_conc_proc, 726 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 727 728 /** 729 * DOC: cwsr_enable (int) 730 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 731 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 732 * disables it. 733 */ 734 int cwsr_enable = 1; 735 module_param(cwsr_enable, int, 0444); 736 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 737 738 /** 739 * DOC: max_num_of_queues_per_device (int) 740 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 741 * is 4096. 742 */ 743 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 744 module_param(max_num_of_queues_per_device, int, 0444); 745 MODULE_PARM_DESC(max_num_of_queues_per_device, 746 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 747 748 /** 749 * DOC: send_sigterm (int) 750 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 751 * but just print errors on dmesg. Setting 1 enables sending sigterm. 752 */ 753 int send_sigterm; 754 module_param(send_sigterm, int, 0444); 755 MODULE_PARM_DESC(send_sigterm, 756 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 757 758 /** 759 * DOC: halt_if_hws_hang (int) 760 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 761 * Setting 1 enables halt on hang. 762 */ 763 int halt_if_hws_hang; 764 module_param(halt_if_hws_hang, int, 0644); 765 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 766 767 /** 768 * DOC: hws_gws_support(bool) 769 * Assume that HWS supports GWS barriers regardless of what firmware version 770 * check says. Default value: false (rely on MEC2 firmware version check). 771 */ 772 bool hws_gws_support; 773 module_param(hws_gws_support, bool, 0444); 774 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 775 776 /** 777 * DOC: queue_preemption_timeout_ms (int) 778 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 779 */ 780 int queue_preemption_timeout_ms = 9000; 781 module_param(queue_preemption_timeout_ms, int, 0644); 782 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 783 784 /** 785 * DOC: debug_evictions(bool) 786 * Enable extra debug messages to help determine the cause of evictions 787 */ 788 bool debug_evictions; 789 module_param(debug_evictions, bool, 0644); 790 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 791 792 /** 793 * DOC: no_system_mem_limit(bool) 794 * Disable system memory limit, to support multiple process shared memory 795 */ 796 bool no_system_mem_limit; 797 module_param(no_system_mem_limit, bool, 0644); 798 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 799 800 /** 801 * DOC: no_queue_eviction_on_vm_fault (int) 802 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 803 */ 804 int amdgpu_no_queue_eviction_on_vm_fault; 805 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 806 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 807 #endif 808 809 /** 810 * DOC: mtype_local (int) 811 */ 812 int amdgpu_mtype_local; 813 MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (0 = MTYPE_RW (default), 1 = MTYPE_NC, 2 = MTYPE_CC)"); 814 module_param_named(mtype_local, amdgpu_mtype_local, int, 0444); 815 816 /** 817 * DOC: pcie_p2p (bool) 818 * Enable PCIe P2P (requires large-BAR). Default value: true (on) 819 */ 820 #ifdef CONFIG_HSA_AMD_P2P 821 bool pcie_p2p = true; 822 module_param(pcie_p2p, bool, 0444); 823 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); 824 #endif 825 826 /** 827 * DOC: dcfeaturemask (uint) 828 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 829 * The default is the current set of stable display features. 830 */ 831 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 832 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 833 834 /** 835 * DOC: dcdebugmask (uint) 836 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 837 */ 838 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 839 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 840 841 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)"); 842 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444); 843 844 /** 845 * DOC: abmlevel (uint) 846 * Override the default ABM (Adaptive Backlight Management) level used for DC 847 * enabled hardware. Requires DMCU to be supported and loaded. 848 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 849 * default. Values 1-4 control the maximum allowable brightness reduction via 850 * the ABM algorithm, with 1 being the least reduction and 4 being the most 851 * reduction. 852 * 853 * Defaults to -1, or disabled. Userspace can only override this level after 854 * boot if it's set to auto. 855 */ 856 int amdgpu_dm_abm_level = -1; 857 MODULE_PARM_DESC(abmlevel, 858 "ABM level (0 = off, 1-4 = backlight reduction level, -1 auto (default))"); 859 module_param_named(abmlevel, amdgpu_dm_abm_level, int, 0444); 860 861 int amdgpu_backlight = -1; 862 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 863 module_param_named(backlight, amdgpu_backlight, bint, 0444); 864 865 /** 866 * DOC: damageclips (int) 867 * Enable or disable damage clips support. If damage clips support is disabled, 868 * we will force full frame updates, irrespective of what user space sends to 869 * us. 870 * 871 * Defaults to -1 (where it is enabled unless a PSR-SU display is detected). 872 */ 873 MODULE_PARM_DESC(damageclips, 874 "Damage clips support (0 = disable, 1 = enable, -1 auto (default))"); 875 module_param_named(damageclips, amdgpu_damage_clips, int, 0444); 876 877 /** 878 * DOC: tmz (int) 879 * Trusted Memory Zone (TMZ) is a method to protect data being written 880 * to or read from memory. 881 * 882 * The default value: 0 (off). TODO: change to auto till it is completed. 883 */ 884 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 885 module_param_named(tmz, amdgpu_tmz, int, 0444); 886 887 /** 888 * DOC: freesync_video (uint) 889 * Enable the optimization to adjust front porch timing to achieve seamless 890 * mode change experience when setting a freesync supported mode for which full 891 * modeset is not needed. 892 * 893 * The Display Core will add a set of modes derived from the base FreeSync 894 * video mode into the corresponding connector's mode list based on commonly 895 * used refresh rates and VRR range of the connected display, when users enable 896 * this feature. From the userspace perspective, they can see a seamless mode 897 * change experience when the change between different refresh rates under the 898 * same resolution. Additionally, userspace applications such as Video playback 899 * can read this modeset list and change the refresh rate based on the video 900 * frame rate. Finally, the userspace can also derive an appropriate mode for a 901 * particular refresh rate based on the FreeSync Mode and add it to the 902 * connector's mode list. 903 * 904 * Note: This is an experimental feature. 905 * 906 * The default value: 0 (off). 907 */ 908 MODULE_PARM_DESC( 909 freesync_video, 910 "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)"); 911 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); 912 913 /** 914 * DOC: reset_method (int) 915 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 916 */ 917 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 918 module_param_named(reset_method, amdgpu_reset_method, int, 0444); 919 920 /** 921 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 922 * threshold value of faulty pages detected by RAS ECC, which may 923 * result in the GPU entering bad status when the number of total 924 * faulty pages by ECC exceeds the threshold value. 925 */ 926 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = driver sets threshold)"); 927 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 928 929 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 930 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 931 932 /** 933 * DOC: vcnfw_log (int) 934 * Enable vcnfw log output for debugging, the default is disabled. 935 */ 936 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 937 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 938 939 /** 940 * DOC: sg_display (int) 941 * Disable S/G (scatter/gather) display (i.e., display from system memory). 942 * This option is only relevant on APUs. Set this option to 0 to disable 943 * S/G display if you experience flickering or other issues under memory 944 * pressure and report the issue. 945 */ 946 MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)"); 947 module_param_named(sg_display, amdgpu_sg_display, int, 0444); 948 949 /** 950 * DOC: umsch_mm (int) 951 * Enable Multi Media User Mode Scheduler. This is a HW scheduling engine for VCN and VPE. 952 * (0 = disabled (default), 1 = enabled) 953 */ 954 MODULE_PARM_DESC(umsch_mm, 955 "Enable Multi Media User Mode Scheduler (0 = disabled (default), 1 = enabled)"); 956 module_param_named(umsch_mm, amdgpu_umsch_mm, int, 0444); 957 958 /** 959 * DOC: smu_pptable_id (int) 960 * Used to override pptable id. id = 0 use VBIOS pptable. 961 * id > 0 use the soft pptable with specicfied id. 962 */ 963 MODULE_PARM_DESC(smu_pptable_id, 964 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 965 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 966 967 /** 968 * DOC: partition_mode (int) 969 * Used to override the default SPX mode. 970 */ 971 MODULE_PARM_DESC( 972 user_partt_mode, 973 "specify partition mode to be used (-2 = AMDGPU_AUTO_COMPUTE_PARTITION_MODE(default value) \ 974 0 = AMDGPU_SPX_PARTITION_MODE, \ 975 1 = AMDGPU_DPX_PARTITION_MODE, \ 976 2 = AMDGPU_TPX_PARTITION_MODE, \ 977 3 = AMDGPU_QPX_PARTITION_MODE, \ 978 4 = AMDGPU_CPX_PARTITION_MODE)"); 979 module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint, 0444); 980 981 982 /** 983 * DOC: enforce_isolation (bool) 984 * enforce process isolation between graphics and compute via using the same reserved vmid. 985 */ 986 module_param(enforce_isolation, bool, 0444); 987 MODULE_PARM_DESC(enforce_isolation, "enforce process isolation between graphics and compute . enforce_isolation = on"); 988 989 /** 990 * DOC: seamless (int) 991 * Seamless boot will keep the image on the screen during the boot process. 992 */ 993 MODULE_PARM_DESC(seamless, "Seamless boot (-1 = auto (default), 0 = disable, 1 = enable)"); 994 module_param_named(seamless, amdgpu_seamless, int, 0444); 995 996 /** 997 * DOC: debug_mask (uint) 998 * Debug options for amdgpu, work as a binary mask with the following options: 999 * 1000 * - 0x1: Debug VM handling 1001 * - 0x2: Enable simulating large-bar capability on non-large bar system. This 1002 * limits the VRAM size reported to ROCm applications to the visible 1003 * size, usually 256MB. 1004 * - 0x4: Disable GPU soft recovery, always do a full reset 1005 */ 1006 MODULE_PARM_DESC(debug_mask, "debug options for amdgpu, disabled by default"); 1007 module_param_named(debug_mask, amdgpu_debug_mask, uint, 0444); 1008 1009 /** 1010 * DOC: agp (int) 1011 * Enable the AGP aperture. This provides an aperture in the GPU's internal 1012 * address space for direct access to system memory. Note that these accesses 1013 * are non-snooped, so they are only used for access to uncached memory. 1014 */ 1015 MODULE_PARM_DESC(agp, "AGP (-1 = auto (default), 0 = disable, 1 = enable)"); 1016 module_param_named(agp, amdgpu_agp, int, 0444); 1017 1018 /** 1019 * DOC: wbrf (int) 1020 * Enable Wifi RFI interference mitigation feature. 1021 * Due to electrical and mechanical constraints there may be likely interference of 1022 * relatively high-powered harmonics of the (G-)DDR memory clocks with local radio 1023 * module frequency bands used by Wifi 6/6e/7. To mitigate the possible RFI interference, 1024 * with this feature enabled, PMFW will use either “shadowed P-State” or “P-State” based 1025 * on active list of frequencies in-use (to be avoided) as part of initial setting or 1026 * P-state transition. However, there may be potential performance impact with this 1027 * feature enabled. 1028 * (0 = disabled, 1 = enabled, -1 = auto (default setting, will be enabled if supported)) 1029 */ 1030 MODULE_PARM_DESC(wbrf, 1031 "Enable Wifi RFI interference mitigation (0 = disabled, 1 = enabled, -1 = auto(default)"); 1032 module_param_named(wbrf, amdgpu_wbrf, int, 0444); 1033 1034 /* These devices are not supported by amdgpu. 1035 * They are supported by the mach64, r128, radeon drivers 1036 */ 1037 static const u16 amdgpu_unsupported_pciidlist[] = { 1038 /* mach64 */ 1039 0x4354, 1040 0x4358, 1041 0x4554, 1042 0x4742, 1043 0x4744, 1044 0x4749, 1045 0x474C, 1046 0x474D, 1047 0x474E, 1048 0x474F, 1049 0x4750, 1050 0x4751, 1051 0x4752, 1052 0x4753, 1053 0x4754, 1054 0x4755, 1055 0x4756, 1056 0x4757, 1057 0x4758, 1058 0x4759, 1059 0x475A, 1060 0x4C42, 1061 0x4C44, 1062 0x4C47, 1063 0x4C49, 1064 0x4C4D, 1065 0x4C4E, 1066 0x4C50, 1067 0x4C51, 1068 0x4C52, 1069 0x4C53, 1070 0x5654, 1071 0x5655, 1072 0x5656, 1073 /* r128 */ 1074 0x4c45, 1075 0x4c46, 1076 0x4d46, 1077 0x4d4c, 1078 0x5041, 1079 0x5042, 1080 0x5043, 1081 0x5044, 1082 0x5045, 1083 0x5046, 1084 0x5047, 1085 0x5048, 1086 0x5049, 1087 0x504A, 1088 0x504B, 1089 0x504C, 1090 0x504D, 1091 0x504E, 1092 0x504F, 1093 0x5050, 1094 0x5051, 1095 0x5052, 1096 0x5053, 1097 0x5054, 1098 0x5055, 1099 0x5056, 1100 0x5057, 1101 0x5058, 1102 0x5245, 1103 0x5246, 1104 0x5247, 1105 0x524b, 1106 0x524c, 1107 0x534d, 1108 0x5446, 1109 0x544C, 1110 0x5452, 1111 /* radeon */ 1112 0x3150, 1113 0x3151, 1114 0x3152, 1115 0x3154, 1116 0x3155, 1117 0x3E50, 1118 0x3E54, 1119 0x4136, 1120 0x4137, 1121 0x4144, 1122 0x4145, 1123 0x4146, 1124 0x4147, 1125 0x4148, 1126 0x4149, 1127 0x414A, 1128 0x414B, 1129 0x4150, 1130 0x4151, 1131 0x4152, 1132 0x4153, 1133 0x4154, 1134 0x4155, 1135 0x4156, 1136 0x4237, 1137 0x4242, 1138 0x4336, 1139 0x4337, 1140 0x4437, 1141 0x4966, 1142 0x4967, 1143 0x4A48, 1144 0x4A49, 1145 0x4A4A, 1146 0x4A4B, 1147 0x4A4C, 1148 0x4A4D, 1149 0x4A4E, 1150 0x4A4F, 1151 0x4A50, 1152 0x4A54, 1153 0x4B48, 1154 0x4B49, 1155 0x4B4A, 1156 0x4B4B, 1157 0x4B4C, 1158 0x4C57, 1159 0x4C58, 1160 0x4C59, 1161 0x4C5A, 1162 0x4C64, 1163 0x4C66, 1164 0x4C67, 1165 0x4E44, 1166 0x4E45, 1167 0x4E46, 1168 0x4E47, 1169 0x4E48, 1170 0x4E49, 1171 0x4E4A, 1172 0x4E4B, 1173 0x4E50, 1174 0x4E51, 1175 0x4E52, 1176 0x4E53, 1177 0x4E54, 1178 0x4E56, 1179 0x5144, 1180 0x5145, 1181 0x5146, 1182 0x5147, 1183 0x5148, 1184 0x514C, 1185 0x514D, 1186 0x5157, 1187 0x5158, 1188 0x5159, 1189 0x515A, 1190 0x515E, 1191 0x5460, 1192 0x5462, 1193 0x5464, 1194 0x5548, 1195 0x5549, 1196 0x554A, 1197 0x554B, 1198 0x554C, 1199 0x554D, 1200 0x554E, 1201 0x554F, 1202 0x5550, 1203 0x5551, 1204 0x5552, 1205 0x5554, 1206 0x564A, 1207 0x564B, 1208 0x564F, 1209 0x5652, 1210 0x5653, 1211 0x5657, 1212 0x5834, 1213 0x5835, 1214 0x5954, 1215 0x5955, 1216 0x5974, 1217 0x5975, 1218 0x5960, 1219 0x5961, 1220 0x5962, 1221 0x5964, 1222 0x5965, 1223 0x5969, 1224 0x5a41, 1225 0x5a42, 1226 0x5a61, 1227 0x5a62, 1228 0x5b60, 1229 0x5b62, 1230 0x5b63, 1231 0x5b64, 1232 0x5b65, 1233 0x5c61, 1234 0x5c63, 1235 0x5d48, 1236 0x5d49, 1237 0x5d4a, 1238 0x5d4c, 1239 0x5d4d, 1240 0x5d4e, 1241 0x5d4f, 1242 0x5d50, 1243 0x5d52, 1244 0x5d57, 1245 0x5e48, 1246 0x5e4a, 1247 0x5e4b, 1248 0x5e4c, 1249 0x5e4d, 1250 0x5e4f, 1251 0x6700, 1252 0x6701, 1253 0x6702, 1254 0x6703, 1255 0x6704, 1256 0x6705, 1257 0x6706, 1258 0x6707, 1259 0x6708, 1260 0x6709, 1261 0x6718, 1262 0x6719, 1263 0x671c, 1264 0x671d, 1265 0x671f, 1266 0x6720, 1267 0x6721, 1268 0x6722, 1269 0x6723, 1270 0x6724, 1271 0x6725, 1272 0x6726, 1273 0x6727, 1274 0x6728, 1275 0x6729, 1276 0x6738, 1277 0x6739, 1278 0x673e, 1279 0x6740, 1280 0x6741, 1281 0x6742, 1282 0x6743, 1283 0x6744, 1284 0x6745, 1285 0x6746, 1286 0x6747, 1287 0x6748, 1288 0x6749, 1289 0x674A, 1290 0x6750, 1291 0x6751, 1292 0x6758, 1293 0x6759, 1294 0x675B, 1295 0x675D, 1296 0x675F, 1297 0x6760, 1298 0x6761, 1299 0x6762, 1300 0x6763, 1301 0x6764, 1302 0x6765, 1303 0x6766, 1304 0x6767, 1305 0x6768, 1306 0x6770, 1307 0x6771, 1308 0x6772, 1309 0x6778, 1310 0x6779, 1311 0x677B, 1312 0x6840, 1313 0x6841, 1314 0x6842, 1315 0x6843, 1316 0x6849, 1317 0x684C, 1318 0x6850, 1319 0x6858, 1320 0x6859, 1321 0x6880, 1322 0x6888, 1323 0x6889, 1324 0x688A, 1325 0x688C, 1326 0x688D, 1327 0x6898, 1328 0x6899, 1329 0x689b, 1330 0x689c, 1331 0x689d, 1332 0x689e, 1333 0x68a0, 1334 0x68a1, 1335 0x68a8, 1336 0x68a9, 1337 0x68b0, 1338 0x68b8, 1339 0x68b9, 1340 0x68ba, 1341 0x68be, 1342 0x68bf, 1343 0x68c0, 1344 0x68c1, 1345 0x68c7, 1346 0x68c8, 1347 0x68c9, 1348 0x68d8, 1349 0x68d9, 1350 0x68da, 1351 0x68de, 1352 0x68e0, 1353 0x68e1, 1354 0x68e4, 1355 0x68e5, 1356 0x68e8, 1357 0x68e9, 1358 0x68f1, 1359 0x68f2, 1360 0x68f8, 1361 0x68f9, 1362 0x68fa, 1363 0x68fe, 1364 0x7100, 1365 0x7101, 1366 0x7102, 1367 0x7103, 1368 0x7104, 1369 0x7105, 1370 0x7106, 1371 0x7108, 1372 0x7109, 1373 0x710A, 1374 0x710B, 1375 0x710C, 1376 0x710E, 1377 0x710F, 1378 0x7140, 1379 0x7141, 1380 0x7142, 1381 0x7143, 1382 0x7144, 1383 0x7145, 1384 0x7146, 1385 0x7147, 1386 0x7149, 1387 0x714A, 1388 0x714B, 1389 0x714C, 1390 0x714D, 1391 0x714E, 1392 0x714F, 1393 0x7151, 1394 0x7152, 1395 0x7153, 1396 0x715E, 1397 0x715F, 1398 0x7180, 1399 0x7181, 1400 0x7183, 1401 0x7186, 1402 0x7187, 1403 0x7188, 1404 0x718A, 1405 0x718B, 1406 0x718C, 1407 0x718D, 1408 0x718F, 1409 0x7193, 1410 0x7196, 1411 0x719B, 1412 0x719F, 1413 0x71C0, 1414 0x71C1, 1415 0x71C2, 1416 0x71C3, 1417 0x71C4, 1418 0x71C5, 1419 0x71C6, 1420 0x71C7, 1421 0x71CD, 1422 0x71CE, 1423 0x71D2, 1424 0x71D4, 1425 0x71D5, 1426 0x71D6, 1427 0x71DA, 1428 0x71DE, 1429 0x7200, 1430 0x7210, 1431 0x7211, 1432 0x7240, 1433 0x7243, 1434 0x7244, 1435 0x7245, 1436 0x7246, 1437 0x7247, 1438 0x7248, 1439 0x7249, 1440 0x724A, 1441 0x724B, 1442 0x724C, 1443 0x724D, 1444 0x724E, 1445 0x724F, 1446 0x7280, 1447 0x7281, 1448 0x7283, 1449 0x7284, 1450 0x7287, 1451 0x7288, 1452 0x7289, 1453 0x728B, 1454 0x728C, 1455 0x7290, 1456 0x7291, 1457 0x7293, 1458 0x7297, 1459 0x7834, 1460 0x7835, 1461 0x791e, 1462 0x791f, 1463 0x793f, 1464 0x7941, 1465 0x7942, 1466 0x796c, 1467 0x796d, 1468 0x796e, 1469 0x796f, 1470 0x9400, 1471 0x9401, 1472 0x9402, 1473 0x9403, 1474 0x9405, 1475 0x940A, 1476 0x940B, 1477 0x940F, 1478 0x94A0, 1479 0x94A1, 1480 0x94A3, 1481 0x94B1, 1482 0x94B3, 1483 0x94B4, 1484 0x94B5, 1485 0x94B9, 1486 0x9440, 1487 0x9441, 1488 0x9442, 1489 0x9443, 1490 0x9444, 1491 0x9446, 1492 0x944A, 1493 0x944B, 1494 0x944C, 1495 0x944E, 1496 0x9450, 1497 0x9452, 1498 0x9456, 1499 0x945A, 1500 0x945B, 1501 0x945E, 1502 0x9460, 1503 0x9462, 1504 0x946A, 1505 0x946B, 1506 0x947A, 1507 0x947B, 1508 0x9480, 1509 0x9487, 1510 0x9488, 1511 0x9489, 1512 0x948A, 1513 0x948F, 1514 0x9490, 1515 0x9491, 1516 0x9495, 1517 0x9498, 1518 0x949C, 1519 0x949E, 1520 0x949F, 1521 0x94C0, 1522 0x94C1, 1523 0x94C3, 1524 0x94C4, 1525 0x94C5, 1526 0x94C6, 1527 0x94C7, 1528 0x94C8, 1529 0x94C9, 1530 0x94CB, 1531 0x94CC, 1532 0x94CD, 1533 0x9500, 1534 0x9501, 1535 0x9504, 1536 0x9505, 1537 0x9506, 1538 0x9507, 1539 0x9508, 1540 0x9509, 1541 0x950F, 1542 0x9511, 1543 0x9515, 1544 0x9517, 1545 0x9519, 1546 0x9540, 1547 0x9541, 1548 0x9542, 1549 0x954E, 1550 0x954F, 1551 0x9552, 1552 0x9553, 1553 0x9555, 1554 0x9557, 1555 0x955f, 1556 0x9580, 1557 0x9581, 1558 0x9583, 1559 0x9586, 1560 0x9587, 1561 0x9588, 1562 0x9589, 1563 0x958A, 1564 0x958B, 1565 0x958C, 1566 0x958D, 1567 0x958E, 1568 0x958F, 1569 0x9590, 1570 0x9591, 1571 0x9593, 1572 0x9595, 1573 0x9596, 1574 0x9597, 1575 0x9598, 1576 0x9599, 1577 0x959B, 1578 0x95C0, 1579 0x95C2, 1580 0x95C4, 1581 0x95C5, 1582 0x95C6, 1583 0x95C7, 1584 0x95C9, 1585 0x95CC, 1586 0x95CD, 1587 0x95CE, 1588 0x95CF, 1589 0x9610, 1590 0x9611, 1591 0x9612, 1592 0x9613, 1593 0x9614, 1594 0x9615, 1595 0x9616, 1596 0x9640, 1597 0x9641, 1598 0x9642, 1599 0x9643, 1600 0x9644, 1601 0x9645, 1602 0x9647, 1603 0x9648, 1604 0x9649, 1605 0x964a, 1606 0x964b, 1607 0x964c, 1608 0x964e, 1609 0x964f, 1610 0x9710, 1611 0x9711, 1612 0x9712, 1613 0x9713, 1614 0x9714, 1615 0x9715, 1616 0x9802, 1617 0x9803, 1618 0x9804, 1619 0x9805, 1620 0x9806, 1621 0x9807, 1622 0x9808, 1623 0x9809, 1624 0x980A, 1625 0x9900, 1626 0x9901, 1627 0x9903, 1628 0x9904, 1629 0x9905, 1630 0x9906, 1631 0x9907, 1632 0x9908, 1633 0x9909, 1634 0x990A, 1635 0x990B, 1636 0x990C, 1637 0x990D, 1638 0x990E, 1639 0x990F, 1640 0x9910, 1641 0x9913, 1642 0x9917, 1643 0x9918, 1644 0x9919, 1645 0x9990, 1646 0x9991, 1647 0x9992, 1648 0x9993, 1649 0x9994, 1650 0x9995, 1651 0x9996, 1652 0x9997, 1653 0x9998, 1654 0x9999, 1655 0x999A, 1656 0x999B, 1657 0x999C, 1658 0x999D, 1659 0x99A0, 1660 0x99A2, 1661 0x99A4, 1662 /* radeon secondary ids */ 1663 0x3171, 1664 0x3e70, 1665 0x4164, 1666 0x4165, 1667 0x4166, 1668 0x4168, 1669 0x4170, 1670 0x4171, 1671 0x4172, 1672 0x4173, 1673 0x496e, 1674 0x4a69, 1675 0x4a6a, 1676 0x4a6b, 1677 0x4a70, 1678 0x4a74, 1679 0x4b69, 1680 0x4b6b, 1681 0x4b6c, 1682 0x4c6e, 1683 0x4e64, 1684 0x4e65, 1685 0x4e66, 1686 0x4e67, 1687 0x4e68, 1688 0x4e69, 1689 0x4e6a, 1690 0x4e71, 1691 0x4f73, 1692 0x5569, 1693 0x556b, 1694 0x556d, 1695 0x556f, 1696 0x5571, 1697 0x5854, 1698 0x5874, 1699 0x5940, 1700 0x5941, 1701 0x5b70, 1702 0x5b72, 1703 0x5b73, 1704 0x5b74, 1705 0x5b75, 1706 0x5d44, 1707 0x5d45, 1708 0x5d6d, 1709 0x5d6f, 1710 0x5d72, 1711 0x5d77, 1712 0x5e6b, 1713 0x5e6d, 1714 0x7120, 1715 0x7124, 1716 0x7129, 1717 0x712e, 1718 0x712f, 1719 0x7162, 1720 0x7163, 1721 0x7166, 1722 0x7167, 1723 0x7172, 1724 0x7173, 1725 0x71a0, 1726 0x71a1, 1727 0x71a3, 1728 0x71a7, 1729 0x71bb, 1730 0x71e0, 1731 0x71e1, 1732 0x71e2, 1733 0x71e6, 1734 0x71e7, 1735 0x71f2, 1736 0x7269, 1737 0x726b, 1738 0x726e, 1739 0x72a0, 1740 0x72a8, 1741 0x72b1, 1742 0x72b3, 1743 0x793f, 1744 }; 1745 1746 static const struct pci_device_id pciidlist[] = { 1747 #ifdef CONFIG_DRM_AMDGPU_SI 1748 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1749 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1750 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1751 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1752 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1753 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1754 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1755 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1756 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1757 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1758 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1759 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1760 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1761 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1762 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1763 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1764 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1765 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1766 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1767 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1768 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1769 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1770 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1771 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1772 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1773 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1774 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1775 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1776 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1777 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1778 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1779 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1780 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1781 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1782 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1783 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1784 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1785 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1786 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1787 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1788 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1789 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1790 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1791 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1792 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1793 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1794 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1795 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1796 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1797 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1798 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1799 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1800 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1801 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1802 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1803 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1804 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1805 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1806 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1807 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1808 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1809 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1810 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1811 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1812 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1813 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1814 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1815 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1816 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1817 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1818 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1819 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1820 #endif 1821 #ifdef CONFIG_DRM_AMDGPU_CIK 1822 /* Kaveri */ 1823 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1824 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1825 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1826 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1827 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1828 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1829 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1830 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1831 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1832 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1833 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1834 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1835 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1836 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1837 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1838 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1839 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1840 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1841 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1842 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1843 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1844 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1845 /* Bonaire */ 1846 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1847 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1848 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1849 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1850 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1851 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1852 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1853 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1854 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1855 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1856 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1857 /* Hawaii */ 1858 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1859 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1860 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1861 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1862 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1863 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1864 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1865 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1866 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1867 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1868 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1869 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1870 /* Kabini */ 1871 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1872 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1873 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1874 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1875 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1876 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1877 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1878 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1879 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1880 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1881 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1882 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1883 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1884 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1885 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1886 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1887 /* mullins */ 1888 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1889 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1890 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1891 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1892 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1893 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1894 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1895 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1896 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1897 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1898 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1899 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1900 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1901 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1902 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1903 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1904 #endif 1905 /* topaz */ 1906 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1907 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1908 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1909 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1910 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1911 /* tonga */ 1912 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1913 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1914 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1915 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1916 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1917 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1918 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1919 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1920 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1921 /* fiji */ 1922 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1923 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1924 /* carrizo */ 1925 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1926 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1927 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1928 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1929 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1930 /* stoney */ 1931 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1932 /* Polaris11 */ 1933 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1934 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1935 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1936 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1937 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1938 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1939 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1940 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1941 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1942 /* Polaris10 */ 1943 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1944 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1945 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1946 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1947 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1948 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1949 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1950 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1951 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1952 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1953 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1954 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1955 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1956 /* Polaris12 */ 1957 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1958 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1959 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1960 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1961 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1962 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1963 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1964 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1965 /* VEGAM */ 1966 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1967 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1968 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1969 /* Vega 10 */ 1970 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1971 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1972 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1973 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1974 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1975 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1976 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1977 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1978 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1979 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1980 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1981 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1982 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1983 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1984 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1985 /* Vega 12 */ 1986 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1987 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1988 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1989 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1990 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1991 /* Vega 20 */ 1992 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1993 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1994 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1995 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1996 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1997 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1998 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1999 /* Raven */ 2000 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 2001 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 2002 /* Arcturus */ 2003 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2004 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2005 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2006 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2007 /* Navi10 */ 2008 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2009 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2010 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2011 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2012 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2013 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2014 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2015 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2016 /* Navi14 */ 2017 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2018 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2019 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2020 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2021 2022 /* Renoir */ 2023 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2024 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2025 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2026 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2027 2028 /* Navi12 */ 2029 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 2030 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 2031 2032 /* Sienna_Cichlid */ 2033 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2034 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2035 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2036 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2037 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2038 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2039 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2040 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2041 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2042 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2043 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2044 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2045 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2046 2047 /* Yellow Carp */ 2048 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 2049 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 2050 2051 /* Navy_Flounder */ 2052 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2053 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2054 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2055 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2056 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2057 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2058 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2059 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2060 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2061 2062 /* DIMGREY_CAVEFISH */ 2063 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2064 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2065 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2066 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2067 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2068 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2069 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2070 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2071 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2072 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2073 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2074 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2075 2076 /* Aldebaran */ 2077 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2078 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2079 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2080 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2081 2082 /* CYAN_SKILLFISH */ 2083 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2084 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2085 2086 /* BEIGE_GOBY */ 2087 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2088 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2089 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2090 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2091 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2092 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2093 2094 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2095 .class = PCI_CLASS_DISPLAY_VGA << 8, 2096 .class_mask = 0xffffff, 2097 .driver_data = CHIP_IP_DISCOVERY }, 2098 2099 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2100 .class = PCI_CLASS_DISPLAY_OTHER << 8, 2101 .class_mask = 0xffffff, 2102 .driver_data = CHIP_IP_DISCOVERY }, 2103 2104 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2105 .class = PCI_CLASS_ACCELERATOR_PROCESSING << 8, 2106 .class_mask = 0xffffff, 2107 .driver_data = CHIP_IP_DISCOVERY }, 2108 2109 {0, 0, 0} 2110 }; 2111 2112 MODULE_DEVICE_TABLE(pci, pciidlist); 2113 2114 static const struct amdgpu_asic_type_quirk asic_type_quirks[] = { 2115 /* differentiate between P10 and P11 asics with the same DID */ 2116 {0x67FF, 0xE3, CHIP_POLARIS10}, 2117 {0x67FF, 0xE7, CHIP_POLARIS10}, 2118 {0x67FF, 0xF3, CHIP_POLARIS10}, 2119 {0x67FF, 0xF7, CHIP_POLARIS10}, 2120 }; 2121 2122 static const struct drm_driver amdgpu_kms_driver; 2123 2124 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 2125 { 2126 struct pci_dev *p = NULL; 2127 int i; 2128 2129 /* 0 - GPU 2130 * 1 - audio 2131 * 2 - USB 2132 * 3 - UCSI 2133 */ 2134 for (i = 1; i < 4; i++) { 2135 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 2136 adev->pdev->bus->number, i); 2137 if (p) { 2138 pm_runtime_get_sync(&p->dev); 2139 pm_runtime_mark_last_busy(&p->dev); 2140 pm_runtime_put_autosuspend(&p->dev); 2141 pci_dev_put(p); 2142 } 2143 } 2144 } 2145 2146 static void amdgpu_init_debug_options(struct amdgpu_device *adev) 2147 { 2148 if (amdgpu_debug_mask & AMDGPU_DEBUG_VM) { 2149 pr_info("debug: VM handling debug enabled\n"); 2150 adev->debug_vm = true; 2151 } 2152 2153 if (amdgpu_debug_mask & AMDGPU_DEBUG_LARGEBAR) { 2154 pr_info("debug: enabled simulating large-bar capability on non-large bar system\n"); 2155 adev->debug_largebar = true; 2156 } 2157 2158 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY) { 2159 pr_info("debug: soft reset for GPU recovery disabled\n"); 2160 adev->debug_disable_soft_recovery = true; 2161 } 2162 2163 if (amdgpu_debug_mask & AMDGPU_DEBUG_USE_VRAM_FW_BUF) { 2164 pr_info("debug: place fw in vram for frontdoor loading\n"); 2165 adev->debug_use_vram_fw_buf = true; 2166 } 2167 } 2168 2169 static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long flags) 2170 { 2171 int i; 2172 2173 for (i = 0; i < ARRAY_SIZE(asic_type_quirks); i++) { 2174 if (pdev->device == asic_type_quirks[i].device && 2175 pdev->revision == asic_type_quirks[i].revision) { 2176 flags &= ~AMD_ASIC_MASK; 2177 flags |= asic_type_quirks[i].type; 2178 break; 2179 } 2180 } 2181 2182 return flags; 2183 } 2184 2185 static int amdgpu_pci_probe(struct pci_dev *pdev, 2186 const struct pci_device_id *ent) 2187 { 2188 struct drm_device *ddev; 2189 struct amdgpu_device *adev; 2190 unsigned long flags = ent->driver_data; 2191 int ret, retry = 0, i; 2192 bool supports_atomic = false; 2193 2194 /* skip devices which are owned by radeon */ 2195 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2196 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2197 return -ENODEV; 2198 } 2199 2200 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) 2201 amdgpu_aspm = 0; 2202 2203 if (amdgpu_virtual_display || 2204 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 2205 supports_atomic = true; 2206 2207 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2208 DRM_INFO("This hardware requires experimental hardware support.\n" 2209 "See modparam exp_hw_support\n"); 2210 return -ENODEV; 2211 } 2212 2213 flags = amdgpu_fix_asic_type(pdev, flags); 2214 2215 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2216 * however, SME requires an indirect IOMMU mapping because the encryption 2217 * bit is beyond the DMA mask of the chip. 2218 */ 2219 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2220 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2221 dev_info(&pdev->dev, 2222 "SME is not compatible with RAVEN\n"); 2223 return -ENOTSUPP; 2224 } 2225 2226 #ifdef CONFIG_DRM_AMDGPU_SI 2227 if (!amdgpu_si_support) { 2228 switch (flags & AMD_ASIC_MASK) { 2229 case CHIP_TAHITI: 2230 case CHIP_PITCAIRN: 2231 case CHIP_VERDE: 2232 case CHIP_OLAND: 2233 case CHIP_HAINAN: 2234 dev_info(&pdev->dev, 2235 "SI support provided by radeon.\n"); 2236 dev_info(&pdev->dev, 2237 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 2238 ); 2239 return -ENODEV; 2240 } 2241 } 2242 #endif 2243 #ifdef CONFIG_DRM_AMDGPU_CIK 2244 if (!amdgpu_cik_support) { 2245 switch (flags & AMD_ASIC_MASK) { 2246 case CHIP_KAVERI: 2247 case CHIP_BONAIRE: 2248 case CHIP_HAWAII: 2249 case CHIP_KABINI: 2250 case CHIP_MULLINS: 2251 dev_info(&pdev->dev, 2252 "CIK support provided by radeon.\n"); 2253 dev_info(&pdev->dev, 2254 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 2255 ); 2256 return -ENODEV; 2257 } 2258 } 2259 #endif 2260 2261 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2262 if (IS_ERR(adev)) 2263 return PTR_ERR(adev); 2264 2265 adev->dev = &pdev->dev; 2266 adev->pdev = pdev; 2267 ddev = adev_to_drm(adev); 2268 2269 if (!supports_atomic) 2270 ddev->driver_features &= ~DRIVER_ATOMIC; 2271 2272 ret = pci_enable_device(pdev); 2273 if (ret) 2274 return ret; 2275 2276 pci_set_drvdata(pdev, ddev); 2277 2278 amdgpu_init_debug_options(adev); 2279 2280 ret = amdgpu_driver_load_kms(adev, flags); 2281 if (ret) 2282 goto err_pci; 2283 2284 retry_init: 2285 ret = drm_dev_register(ddev, flags); 2286 if (ret == -EAGAIN && ++retry <= 3) { 2287 DRM_INFO("retry init %d\n", retry); 2288 /* Don't request EX mode too frequently which is attacking */ 2289 msleep(5000); 2290 goto retry_init; 2291 } else if (ret) { 2292 goto err_pci; 2293 } 2294 2295 ret = amdgpu_xcp_dev_register(adev, ent); 2296 if (ret) 2297 goto err_pci; 2298 2299 ret = amdgpu_amdkfd_drm_client_create(adev); 2300 if (ret) 2301 goto err_pci; 2302 2303 /* 2304 * 1. don't init fbdev on hw without DCE 2305 * 2. don't init fbdev if there are no connectors 2306 */ 2307 if (adev->mode_info.mode_config_initialized && 2308 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2309 /* select 8 bpp console on low vram cards */ 2310 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2311 drm_fbdev_generic_setup(adev_to_drm(adev), 8); 2312 else 2313 drm_fbdev_generic_setup(adev_to_drm(adev), 32); 2314 } 2315 2316 ret = amdgpu_debugfs_init(adev); 2317 if (ret) 2318 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2319 2320 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2321 /* only need to skip on ATPX */ 2322 if (amdgpu_device_supports_px(ddev)) 2323 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2324 /* we want direct complete for BOCO */ 2325 if (amdgpu_device_supports_boco(ddev)) 2326 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2327 DPM_FLAG_SMART_SUSPEND | 2328 DPM_FLAG_MAY_SKIP_RESUME); 2329 pm_runtime_use_autosuspend(ddev->dev); 2330 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2331 2332 pm_runtime_allow(ddev->dev); 2333 2334 pm_runtime_mark_last_busy(ddev->dev); 2335 pm_runtime_put_autosuspend(ddev->dev); 2336 2337 pci_wake_from_d3(pdev, TRUE); 2338 2339 /* 2340 * For runpm implemented via BACO, PMFW will handle the 2341 * timing for BACO in and out: 2342 * - put ASIC into BACO state only when both video and 2343 * audio functions are in D3 state. 2344 * - pull ASIC out of BACO state when either video or 2345 * audio function is in D0 state. 2346 * Also, at startup, PMFW assumes both functions are in 2347 * D0 state. 2348 * 2349 * So if snd driver was loaded prior to amdgpu driver 2350 * and audio function was put into D3 state, there will 2351 * be no PMFW-aware D-state transition(D0->D3) on runpm 2352 * suspend. Thus the BACO will be not correctly kicked in. 2353 * 2354 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2355 * into D0 state. Then there will be a PMFW-aware D-state 2356 * transition(D0->D3) on runpm suspend. 2357 */ 2358 if (amdgpu_device_supports_baco(ddev) && 2359 !(adev->flags & AMD_IS_APU) && 2360 (adev->asic_type >= CHIP_NAVI10)) 2361 amdgpu_get_secondary_funcs(adev); 2362 } 2363 2364 return 0; 2365 2366 err_pci: 2367 pci_disable_device(pdev); 2368 return ret; 2369 } 2370 2371 static void 2372 amdgpu_pci_remove(struct pci_dev *pdev) 2373 { 2374 struct drm_device *dev = pci_get_drvdata(pdev); 2375 struct amdgpu_device *adev = drm_to_adev(dev); 2376 2377 amdgpu_xcp_dev_unplug(adev); 2378 drm_dev_unplug(dev); 2379 2380 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2381 pm_runtime_get_sync(dev->dev); 2382 pm_runtime_forbid(dev->dev); 2383 } 2384 2385 amdgpu_driver_unload_kms(dev); 2386 2387 /* 2388 * Flush any in flight DMA operations from device. 2389 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2390 * StatusTransactions Pending bit. 2391 */ 2392 pci_disable_device(pdev); 2393 pci_wait_for_pending_transaction(pdev); 2394 } 2395 2396 static void 2397 amdgpu_pci_shutdown(struct pci_dev *pdev) 2398 { 2399 struct drm_device *dev = pci_get_drvdata(pdev); 2400 struct amdgpu_device *adev = drm_to_adev(dev); 2401 2402 if (amdgpu_ras_intr_triggered()) 2403 return; 2404 2405 /* if we are running in a VM, make sure the device 2406 * torn down properly on reboot/shutdown. 2407 * unfortunately we can't detect certain 2408 * hypervisors so just do this all the time. 2409 */ 2410 if (!amdgpu_passthrough(adev)) 2411 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2412 amdgpu_device_ip_suspend(adev); 2413 adev->mp1_state = PP_MP1_STATE_NONE; 2414 } 2415 2416 /** 2417 * amdgpu_drv_delayed_reset_work_handler - work handler for reset 2418 * 2419 * @work: work_struct. 2420 */ 2421 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) 2422 { 2423 struct list_head device_list; 2424 struct amdgpu_device *adev; 2425 int i, r; 2426 struct amdgpu_reset_context reset_context; 2427 2428 memset(&reset_context, 0, sizeof(reset_context)); 2429 2430 mutex_lock(&mgpu_info.mutex); 2431 if (mgpu_info.pending_reset == true) { 2432 mutex_unlock(&mgpu_info.mutex); 2433 return; 2434 } 2435 mgpu_info.pending_reset = true; 2436 mutex_unlock(&mgpu_info.mutex); 2437 2438 /* Use a common context, just need to make sure full reset is done */ 2439 reset_context.method = AMD_RESET_METHOD_NONE; 2440 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2441 2442 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2443 adev = mgpu_info.gpu_ins[i].adev; 2444 reset_context.reset_req_dev = adev; 2445 r = amdgpu_device_pre_asic_reset(adev, &reset_context); 2446 if (r) { 2447 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", 2448 r, adev_to_drm(adev)->unique); 2449 } 2450 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) 2451 r = -EALREADY; 2452 } 2453 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2454 adev = mgpu_info.gpu_ins[i].adev; 2455 flush_work(&adev->xgmi_reset_work); 2456 adev->gmc.xgmi.pending_reset = false; 2457 } 2458 2459 /* reset function will rebuild the xgmi hive info , clear it now */ 2460 for (i = 0; i < mgpu_info.num_dgpu; i++) 2461 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); 2462 2463 INIT_LIST_HEAD(&device_list); 2464 2465 for (i = 0; i < mgpu_info.num_dgpu; i++) 2466 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); 2467 2468 /* unregister the GPU first, reset function will add them back */ 2469 list_for_each_entry(adev, &device_list, reset_list) 2470 amdgpu_unregister_gpu_instance(adev); 2471 2472 /* Use a common context, just need to make sure full reset is done */ 2473 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); 2474 r = amdgpu_do_asic_reset(&device_list, &reset_context); 2475 2476 if (r) { 2477 DRM_ERROR("reinit gpus failure"); 2478 return; 2479 } 2480 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2481 adev = mgpu_info.gpu_ins[i].adev; 2482 if (!adev->kfd.init_complete) 2483 amdgpu_amdkfd_device_init(adev); 2484 amdgpu_ttm_set_buffer_funcs_status(adev, true); 2485 } 2486 } 2487 2488 static int amdgpu_pmops_prepare(struct device *dev) 2489 { 2490 struct drm_device *drm_dev = dev_get_drvdata(dev); 2491 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2492 2493 /* Return a positive number here so 2494 * DPM_FLAG_SMART_SUSPEND works properly 2495 */ 2496 if (amdgpu_device_supports_boco(drm_dev) && 2497 pm_runtime_suspended(dev)) 2498 return 1; 2499 2500 /* if we will not support s3 or s2i for the device 2501 * then skip suspend 2502 */ 2503 if (!amdgpu_acpi_is_s0ix_active(adev) && 2504 !amdgpu_acpi_is_s3_active(adev)) 2505 return 1; 2506 2507 return amdgpu_device_prepare(drm_dev); 2508 } 2509 2510 static void amdgpu_pmops_complete(struct device *dev) 2511 { 2512 /* nothing to do */ 2513 } 2514 2515 static int amdgpu_pmops_suspend(struct device *dev) 2516 { 2517 struct drm_device *drm_dev = dev_get_drvdata(dev); 2518 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2519 2520 adev->suspend_complete = false; 2521 if (amdgpu_acpi_is_s0ix_active(adev)) 2522 adev->in_s0ix = true; 2523 else if (amdgpu_acpi_is_s3_active(adev)) 2524 adev->in_s3 = true; 2525 if (!adev->in_s0ix && !adev->in_s3) 2526 return 0; 2527 return amdgpu_device_suspend(drm_dev, true); 2528 } 2529 2530 static int amdgpu_pmops_suspend_noirq(struct device *dev) 2531 { 2532 struct drm_device *drm_dev = dev_get_drvdata(dev); 2533 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2534 2535 adev->suspend_complete = true; 2536 if (amdgpu_acpi_should_gpu_reset(adev)) 2537 return amdgpu_asic_reset(adev); 2538 2539 return 0; 2540 } 2541 2542 static int amdgpu_pmops_resume(struct device *dev) 2543 { 2544 struct drm_device *drm_dev = dev_get_drvdata(dev); 2545 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2546 int r; 2547 2548 if (!adev->in_s0ix && !adev->in_s3) 2549 return 0; 2550 2551 /* Avoids registers access if device is physically gone */ 2552 if (!pci_device_is_present(adev->pdev)) 2553 adev->no_hw_access = true; 2554 2555 r = amdgpu_device_resume(drm_dev, true); 2556 if (amdgpu_acpi_is_s0ix_active(adev)) 2557 adev->in_s0ix = false; 2558 else 2559 adev->in_s3 = false; 2560 return r; 2561 } 2562 2563 static int amdgpu_pmops_freeze(struct device *dev) 2564 { 2565 struct drm_device *drm_dev = dev_get_drvdata(dev); 2566 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2567 int r; 2568 2569 adev->in_s4 = true; 2570 r = amdgpu_device_suspend(drm_dev, true); 2571 adev->in_s4 = false; 2572 if (r) 2573 return r; 2574 2575 if (amdgpu_acpi_should_gpu_reset(adev)) 2576 return amdgpu_asic_reset(adev); 2577 return 0; 2578 } 2579 2580 static int amdgpu_pmops_thaw(struct device *dev) 2581 { 2582 struct drm_device *drm_dev = dev_get_drvdata(dev); 2583 2584 return amdgpu_device_resume(drm_dev, true); 2585 } 2586 2587 static int amdgpu_pmops_poweroff(struct device *dev) 2588 { 2589 struct drm_device *drm_dev = dev_get_drvdata(dev); 2590 2591 return amdgpu_device_suspend(drm_dev, true); 2592 } 2593 2594 static int amdgpu_pmops_restore(struct device *dev) 2595 { 2596 struct drm_device *drm_dev = dev_get_drvdata(dev); 2597 2598 return amdgpu_device_resume(drm_dev, true); 2599 } 2600 2601 static int amdgpu_runtime_idle_check_display(struct device *dev) 2602 { 2603 struct pci_dev *pdev = to_pci_dev(dev); 2604 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2605 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2606 2607 if (adev->mode_info.num_crtc) { 2608 struct drm_connector *list_connector; 2609 struct drm_connector_list_iter iter; 2610 int ret = 0; 2611 2612 if (amdgpu_runtime_pm != -2) { 2613 /* XXX: Return busy if any displays are connected to avoid 2614 * possible display wakeups after runtime resume due to 2615 * hotplug events in case any displays were connected while 2616 * the GPU was in suspend. Remove this once that is fixed. 2617 */ 2618 mutex_lock(&drm_dev->mode_config.mutex); 2619 drm_connector_list_iter_begin(drm_dev, &iter); 2620 drm_for_each_connector_iter(list_connector, &iter) { 2621 if (list_connector->status == connector_status_connected) { 2622 ret = -EBUSY; 2623 break; 2624 } 2625 } 2626 drm_connector_list_iter_end(&iter); 2627 mutex_unlock(&drm_dev->mode_config.mutex); 2628 2629 if (ret) 2630 return ret; 2631 } 2632 2633 if (adev->dc_enabled) { 2634 struct drm_crtc *crtc; 2635 2636 drm_for_each_crtc(crtc, drm_dev) { 2637 drm_modeset_lock(&crtc->mutex, NULL); 2638 if (crtc->state->active) 2639 ret = -EBUSY; 2640 drm_modeset_unlock(&crtc->mutex); 2641 if (ret < 0) 2642 break; 2643 } 2644 } else { 2645 mutex_lock(&drm_dev->mode_config.mutex); 2646 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2647 2648 drm_connector_list_iter_begin(drm_dev, &iter); 2649 drm_for_each_connector_iter(list_connector, &iter) { 2650 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2651 ret = -EBUSY; 2652 break; 2653 } 2654 } 2655 2656 drm_connector_list_iter_end(&iter); 2657 2658 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2659 mutex_unlock(&drm_dev->mode_config.mutex); 2660 } 2661 if (ret) 2662 return ret; 2663 } 2664 2665 return 0; 2666 } 2667 2668 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2669 { 2670 struct pci_dev *pdev = to_pci_dev(dev); 2671 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2672 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2673 int ret, i; 2674 2675 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2676 pm_runtime_forbid(dev); 2677 return -EBUSY; 2678 } 2679 2680 ret = amdgpu_runtime_idle_check_display(dev); 2681 if (ret) 2682 return ret; 2683 2684 /* wait for all rings to drain before suspending */ 2685 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2686 struct amdgpu_ring *ring = adev->rings[i]; 2687 2688 if (ring && ring->sched.ready) { 2689 ret = amdgpu_fence_wait_empty(ring); 2690 if (ret) 2691 return -EBUSY; 2692 } 2693 } 2694 2695 adev->in_runpm = true; 2696 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2697 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2698 2699 /* 2700 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2701 * proper cleanups and put itself into a state ready for PNP. That 2702 * can address some random resuming failure observed on BOCO capable 2703 * platforms. 2704 * TODO: this may be also needed for PX capable platform. 2705 */ 2706 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2707 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2708 2709 ret = amdgpu_device_prepare(drm_dev); 2710 if (ret) 2711 return ret; 2712 ret = amdgpu_device_suspend(drm_dev, false); 2713 if (ret) { 2714 adev->in_runpm = false; 2715 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2716 adev->mp1_state = PP_MP1_STATE_NONE; 2717 return ret; 2718 } 2719 2720 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2721 adev->mp1_state = PP_MP1_STATE_NONE; 2722 2723 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) { 2724 /* Only need to handle PCI state in the driver for ATPX 2725 * PCI core handles it for _PR3. 2726 */ 2727 amdgpu_device_cache_pci_state(pdev); 2728 pci_disable_device(pdev); 2729 pci_ignore_hotplug(pdev); 2730 pci_set_power_state(pdev, PCI_D3cold); 2731 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2732 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) { 2733 /* nothing to do */ 2734 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) { 2735 amdgpu_device_baco_enter(drm_dev); 2736 } 2737 2738 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n"); 2739 2740 return 0; 2741 } 2742 2743 static int amdgpu_pmops_runtime_resume(struct device *dev) 2744 { 2745 struct pci_dev *pdev = to_pci_dev(dev); 2746 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2747 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2748 int ret; 2749 2750 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) 2751 return -EINVAL; 2752 2753 /* Avoids registers access if device is physically gone */ 2754 if (!pci_device_is_present(adev->pdev)) 2755 adev->no_hw_access = true; 2756 2757 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) { 2758 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2759 2760 /* Only need to handle PCI state in the driver for ATPX 2761 * PCI core handles it for _PR3. 2762 */ 2763 pci_set_power_state(pdev, PCI_D0); 2764 amdgpu_device_load_pci_state(pdev); 2765 ret = pci_enable_device(pdev); 2766 if (ret) 2767 return ret; 2768 pci_set_master(pdev); 2769 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) { 2770 /* Only need to handle PCI state in the driver for ATPX 2771 * PCI core handles it for _PR3. 2772 */ 2773 pci_set_master(pdev); 2774 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) { 2775 amdgpu_device_baco_exit(drm_dev); 2776 } 2777 ret = amdgpu_device_resume(drm_dev, false); 2778 if (ret) { 2779 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2780 pci_disable_device(pdev); 2781 return ret; 2782 } 2783 2784 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2785 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2786 adev->in_runpm = false; 2787 return 0; 2788 } 2789 2790 static int amdgpu_pmops_runtime_idle(struct device *dev) 2791 { 2792 struct drm_device *drm_dev = dev_get_drvdata(dev); 2793 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2794 int ret; 2795 2796 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2797 pm_runtime_forbid(dev); 2798 return -EBUSY; 2799 } 2800 2801 ret = amdgpu_runtime_idle_check_display(dev); 2802 2803 pm_runtime_mark_last_busy(dev); 2804 pm_runtime_autosuspend(dev); 2805 return ret; 2806 } 2807 2808 long amdgpu_drm_ioctl(struct file *filp, 2809 unsigned int cmd, unsigned long arg) 2810 { 2811 struct drm_file *file_priv = filp->private_data; 2812 struct drm_device *dev; 2813 long ret; 2814 2815 dev = file_priv->minor->dev; 2816 ret = pm_runtime_get_sync(dev->dev); 2817 if (ret < 0) 2818 goto out; 2819 2820 ret = drm_ioctl(filp, cmd, arg); 2821 2822 pm_runtime_mark_last_busy(dev->dev); 2823 out: 2824 pm_runtime_put_autosuspend(dev->dev); 2825 return ret; 2826 } 2827 2828 static const struct dev_pm_ops amdgpu_pm_ops = { 2829 .prepare = amdgpu_pmops_prepare, 2830 .complete = amdgpu_pmops_complete, 2831 .suspend = amdgpu_pmops_suspend, 2832 .suspend_noirq = amdgpu_pmops_suspend_noirq, 2833 .resume = amdgpu_pmops_resume, 2834 .freeze = amdgpu_pmops_freeze, 2835 .thaw = amdgpu_pmops_thaw, 2836 .poweroff = amdgpu_pmops_poweroff, 2837 .restore = amdgpu_pmops_restore, 2838 .runtime_suspend = amdgpu_pmops_runtime_suspend, 2839 .runtime_resume = amdgpu_pmops_runtime_resume, 2840 .runtime_idle = amdgpu_pmops_runtime_idle, 2841 }; 2842 2843 static int amdgpu_flush(struct file *f, fl_owner_t id) 2844 { 2845 struct drm_file *file_priv = f->private_data; 2846 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2847 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2848 2849 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 2850 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 2851 2852 return timeout >= 0 ? 0 : timeout; 2853 } 2854 2855 static const struct file_operations amdgpu_driver_kms_fops = { 2856 .owner = THIS_MODULE, 2857 .open = drm_open, 2858 .flush = amdgpu_flush, 2859 .release = drm_release, 2860 .unlocked_ioctl = amdgpu_drm_ioctl, 2861 .mmap = drm_gem_mmap, 2862 .poll = drm_poll, 2863 .read = drm_read, 2864 #ifdef CONFIG_COMPAT 2865 .compat_ioctl = amdgpu_kms_compat_ioctl, 2866 #endif 2867 #ifdef CONFIG_PROC_FS 2868 .show_fdinfo = drm_show_fdinfo, 2869 #endif 2870 }; 2871 2872 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 2873 { 2874 struct drm_file *file; 2875 2876 if (!filp) 2877 return -EINVAL; 2878 2879 if (filp->f_op != &amdgpu_driver_kms_fops) 2880 return -EINVAL; 2881 2882 file = filp->private_data; 2883 *fpriv = file->driver_priv; 2884 return 0; 2885 } 2886 2887 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 2888 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2889 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2890 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2891 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 2892 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2893 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2894 /* KMS */ 2895 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2896 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2897 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2898 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2899 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2900 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2901 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2902 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2903 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2904 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2905 }; 2906 2907 static const struct drm_driver amdgpu_kms_driver = { 2908 .driver_features = 2909 DRIVER_ATOMIC | 2910 DRIVER_GEM | 2911 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 2912 DRIVER_SYNCOBJ_TIMELINE, 2913 .open = amdgpu_driver_open_kms, 2914 .postclose = amdgpu_driver_postclose_kms, 2915 .lastclose = amdgpu_driver_lastclose_kms, 2916 .ioctls = amdgpu_ioctls_kms, 2917 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2918 .dumb_create = amdgpu_mode_dumb_create, 2919 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2920 .fops = &amdgpu_driver_kms_fops, 2921 .release = &amdgpu_driver_release_kms, 2922 #ifdef CONFIG_PROC_FS 2923 .show_fdinfo = amdgpu_show_fdinfo, 2924 #endif 2925 2926 .gem_prime_import = amdgpu_gem_prime_import, 2927 2928 .name = DRIVER_NAME, 2929 .desc = DRIVER_DESC, 2930 .date = DRIVER_DATE, 2931 .major = KMS_DRIVER_MAJOR, 2932 .minor = KMS_DRIVER_MINOR, 2933 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2934 }; 2935 2936 const struct drm_driver amdgpu_partition_driver = { 2937 .driver_features = 2938 DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ | 2939 DRIVER_SYNCOBJ_TIMELINE, 2940 .open = amdgpu_driver_open_kms, 2941 .postclose = amdgpu_driver_postclose_kms, 2942 .lastclose = amdgpu_driver_lastclose_kms, 2943 .ioctls = amdgpu_ioctls_kms, 2944 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2945 .dumb_create = amdgpu_mode_dumb_create, 2946 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2947 .fops = &amdgpu_driver_kms_fops, 2948 .release = &amdgpu_driver_release_kms, 2949 2950 .gem_prime_import = amdgpu_gem_prime_import, 2951 2952 .name = DRIVER_NAME, 2953 .desc = DRIVER_DESC, 2954 .date = DRIVER_DATE, 2955 .major = KMS_DRIVER_MAJOR, 2956 .minor = KMS_DRIVER_MINOR, 2957 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2958 }; 2959 2960 static struct pci_error_handlers amdgpu_pci_err_handler = { 2961 .error_detected = amdgpu_pci_error_detected, 2962 .mmio_enabled = amdgpu_pci_mmio_enabled, 2963 .slot_reset = amdgpu_pci_slot_reset, 2964 .resume = amdgpu_pci_resume, 2965 }; 2966 2967 static const struct attribute_group *amdgpu_sysfs_groups[] = { 2968 &amdgpu_vram_mgr_attr_group, 2969 &amdgpu_gtt_mgr_attr_group, 2970 &amdgpu_flash_attr_group, 2971 NULL, 2972 }; 2973 2974 static struct pci_driver amdgpu_kms_pci_driver = { 2975 .name = DRIVER_NAME, 2976 .id_table = pciidlist, 2977 .probe = amdgpu_pci_probe, 2978 .remove = amdgpu_pci_remove, 2979 .shutdown = amdgpu_pci_shutdown, 2980 .driver.pm = &amdgpu_pm_ops, 2981 .err_handler = &amdgpu_pci_err_handler, 2982 .dev_groups = amdgpu_sysfs_groups, 2983 }; 2984 2985 static int __init amdgpu_init(void) 2986 { 2987 int r; 2988 2989 if (drm_firmware_drivers_only()) 2990 return -EINVAL; 2991 2992 r = amdgpu_sync_init(); 2993 if (r) 2994 goto error_sync; 2995 2996 r = amdgpu_fence_slab_init(); 2997 if (r) 2998 goto error_fence; 2999 3000 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 3001 amdgpu_register_atpx_handler(); 3002 amdgpu_acpi_detect(); 3003 3004 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 3005 amdgpu_amdkfd_init(); 3006 3007 /* let modprobe override vga console setting */ 3008 return pci_register_driver(&amdgpu_kms_pci_driver); 3009 3010 error_fence: 3011 amdgpu_sync_fini(); 3012 3013 error_sync: 3014 return r; 3015 } 3016 3017 static void __exit amdgpu_exit(void) 3018 { 3019 amdgpu_amdkfd_fini(); 3020 pci_unregister_driver(&amdgpu_kms_pci_driver); 3021 amdgpu_unregister_atpx_handler(); 3022 amdgpu_acpi_release(); 3023 amdgpu_sync_fini(); 3024 amdgpu_fence_slab_fini(); 3025 mmu_notifier_synchronize(); 3026 amdgpu_xcp_drv_release(); 3027 } 3028 3029 module_init(amdgpu_init); 3030 module_exit(amdgpu_exit); 3031 3032 MODULE_AUTHOR(DRIVER_AUTHOR); 3033 MODULE_DESCRIPTION(DRIVER_DESC); 3034 MODULE_LICENSE("GPL and additional rights"); 3035