1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_client_setup.h> 27 #include <drm/drm_drv.h> 28 #include <drm/drm_fbdev_ttm.h> 29 #include <drm/drm_gem.h> 30 #include <drm/drm_managed.h> 31 #include <drm/drm_pciids.h> 32 #include <drm/drm_probe_helper.h> 33 #include <drm/drm_vblank.h> 34 35 #include <linux/cc_platform.h> 36 #include <linux/dynamic_debug.h> 37 #include <linux/module.h> 38 #include <linux/mmu_notifier.h> 39 #include <linux/pm_runtime.h> 40 #include <linux/suspend.h> 41 #include <linux/vga_switcheroo.h> 42 43 #include "amdgpu.h" 44 #include "amdgpu_amdkfd.h" 45 #include "amdgpu_dma_buf.h" 46 #include "amdgpu_drv.h" 47 #include "amdgpu_fdinfo.h" 48 #include "amdgpu_irq.h" 49 #include "amdgpu_psp.h" 50 #include "amdgpu_ras.h" 51 #include "amdgpu_reset.h" 52 #include "amdgpu_sched.h" 53 #include "amdgpu_xgmi.h" 54 #include "../amdxcp/amdgpu_xcp_drv.h" 55 56 /* 57 * KMS wrapper. 58 * - 3.0.0 - initial driver 59 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 60 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 61 * at the end of IBs. 62 * - 3.3.0 - Add VM support for UVD on supported hardware. 63 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 64 * - 3.5.0 - Add support for new UVD_NO_OP register. 65 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 66 * - 3.7.0 - Add support for VCE clock list packet 67 * - 3.8.0 - Add support raster config init in the kernel 68 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 69 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 70 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 71 * - 3.12.0 - Add query for double offchip LDS buffers 72 * - 3.13.0 - Add PRT support 73 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 74 * - 3.15.0 - Export more gpu info for gfx9 75 * - 3.16.0 - Add reserved vmid support 76 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 77 * - 3.18.0 - Export gpu always on cu bitmap 78 * - 3.19.0 - Add support for UVD MJPEG decode 79 * - 3.20.0 - Add support for local BOs 80 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 81 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 82 * - 3.23.0 - Add query for VRAM lost counter 83 * - 3.24.0 - Add high priority compute support for gfx9 84 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 85 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 86 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation. 87 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 88 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 89 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 90 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 91 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 92 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 93 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 94 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 95 * - 3.36.0 - Allow reading more status registers on si/cik 96 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 97 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 98 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 99 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 100 * - 3.41.0 - Add video codec query 101 * - 3.42.0 - Add 16bpc fixed point display support 102 * - 3.43.0 - Add device hot plug/unplug support 103 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 104 * - 3.45.0 - Add context ioctl stable pstate interface 105 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm 106 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags 107 * - 3.48.0 - Add IP discovery version info to HW INFO 108 * - 3.49.0 - Add gang submit into CS IOCTL 109 * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock 110 * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock 111 * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl 112 * 3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields: 113 * tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size, 114 * gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi 115 * 3.53.0 - Support for GFX11 CP GFX shadowing 116 * 3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support 117 * - 3.55.0 - Add AMDGPU_INFO_GPUVM_FAULT query 118 * - 3.56.0 - Update IB start address and size alignment for decode and encode 119 * - 3.57.0 - Compute tunneling on GFX10+ 120 * - 3.58.0 - Add GFX12 DCC support 121 * - 3.59.0 - Cleared VRAM 122 */ 123 #define KMS_DRIVER_MAJOR 3 124 #define KMS_DRIVER_MINOR 59 125 #define KMS_DRIVER_PATCHLEVEL 0 126 127 /* 128 * amdgpu.debug module options. Are all disabled by default 129 */ 130 enum AMDGPU_DEBUG_MASK { 131 AMDGPU_DEBUG_VM = BIT(0), 132 AMDGPU_DEBUG_LARGEBAR = BIT(1), 133 AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY = BIT(2), 134 AMDGPU_DEBUG_USE_VRAM_FW_BUF = BIT(3), 135 AMDGPU_DEBUG_ENABLE_RAS_ACA = BIT(4), 136 AMDGPU_DEBUG_ENABLE_EXP_RESETS = BIT(5), 137 }; 138 139 unsigned int amdgpu_vram_limit = UINT_MAX; 140 int amdgpu_vis_vram_limit; 141 int amdgpu_gart_size = -1; /* auto */ 142 int amdgpu_gtt_size = -1; /* auto */ 143 int amdgpu_moverate = -1; /* auto */ 144 int amdgpu_audio = -1; 145 int amdgpu_disp_priority; 146 int amdgpu_hw_i2c; 147 int amdgpu_pcie_gen2 = -1; 148 int amdgpu_msi = -1; 149 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 150 int amdgpu_dpm = -1; 151 int amdgpu_fw_load_type = -1; 152 int amdgpu_aspm = -1; 153 int amdgpu_runtime_pm = -1; 154 uint amdgpu_ip_block_mask = 0xffffffff; 155 int amdgpu_bapm = -1; 156 int amdgpu_deep_color; 157 int amdgpu_vm_size = -1; 158 int amdgpu_vm_fragment_size = -1; 159 int amdgpu_vm_block_size = -1; 160 int amdgpu_vm_fault_stop; 161 int amdgpu_vm_update_mode = -1; 162 int amdgpu_exp_hw_support; 163 int amdgpu_dc = -1; 164 int amdgpu_sched_jobs = 32; 165 int amdgpu_sched_hw_submission = 2; 166 uint amdgpu_pcie_gen_cap; 167 uint amdgpu_pcie_lane_cap; 168 u64 amdgpu_cg_mask = 0xffffffffffffffff; 169 uint amdgpu_pg_mask = 0xffffffff; 170 uint amdgpu_sdma_phase_quantum = 32; 171 char *amdgpu_disable_cu; 172 char *amdgpu_virtual_display; 173 bool enforce_isolation; 174 175 /* Specifies the default granularity for SVM, used in buffer 176 * migration and restoration of backing memory when handling 177 * recoverable page faults. 178 * 179 * The value is given as log(numPages(buffer)); for a 2 MiB 180 * buffer it computes to be 9 181 */ 182 uint amdgpu_svm_default_granularity = 9; 183 184 /* 185 * OverDrive(bit 14) disabled by default 186 * GFX DCS(bit 19) disabled by default 187 */ 188 uint amdgpu_pp_feature_mask = 0xfff7bfff; 189 uint amdgpu_force_long_training; 190 int amdgpu_lbpw = -1; 191 int amdgpu_compute_multipipe = -1; 192 int amdgpu_gpu_recovery = -1; /* auto */ 193 int amdgpu_emu_mode; 194 uint amdgpu_smu_memory_pool_size; 195 int amdgpu_smu_pptable_id = -1; 196 /* 197 * FBC (bit 0) disabled by default 198 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 199 * - With this, for multiple monitors in sync(e.g. with the same model), 200 * mclk switching will be allowed. And the mclk will be not foced to the 201 * highest. That helps saving some idle power. 202 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 203 * PSR (bit 3) disabled by default 204 * EDP NO POWER SEQUENCING (bit 4) disabled by default 205 */ 206 uint amdgpu_dc_feature_mask = 2; 207 uint amdgpu_dc_debug_mask; 208 uint amdgpu_dc_visual_confirm; 209 int amdgpu_async_gfx_ring = 1; 210 int amdgpu_mcbp = -1; 211 int amdgpu_discovery = -1; 212 int amdgpu_mes; 213 int amdgpu_mes_log_enable = 0; 214 int amdgpu_mes_kiq; 215 int amdgpu_uni_mes = 1; 216 int amdgpu_noretry = -1; 217 int amdgpu_force_asic_type = -1; 218 int amdgpu_tmz = -1; /* auto */ 219 uint amdgpu_freesync_vid_mode; 220 int amdgpu_reset_method = -1; /* auto */ 221 int amdgpu_num_kcq = -1; 222 int amdgpu_smartshift_bias; 223 int amdgpu_use_xgmi_p2p = 1; 224 int amdgpu_vcnfw_log; 225 int amdgpu_sg_display = -1; /* auto */ 226 int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE; 227 int amdgpu_umsch_mm; 228 int amdgpu_seamless = -1; /* auto */ 229 uint amdgpu_debug_mask; 230 int amdgpu_agp = -1; /* auto */ 231 int amdgpu_wbrf = -1; 232 int amdgpu_damage_clips = -1; /* auto */ 233 int amdgpu_umsch_mm_fwlog; 234 235 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 236 237 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 238 "DRM_UT_CORE", 239 "DRM_UT_DRIVER", 240 "DRM_UT_KMS", 241 "DRM_UT_PRIME", 242 "DRM_UT_ATOMIC", 243 "DRM_UT_VBL", 244 "DRM_UT_STATE", 245 "DRM_UT_LEASE", 246 "DRM_UT_DP", 247 "DRM_UT_DRMRES"); 248 249 struct amdgpu_mgpu_info mgpu_info = { 250 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 251 .delayed_reset_work = __DELAYED_WORK_INITIALIZER( 252 mgpu_info.delayed_reset_work, 253 amdgpu_drv_delayed_reset_work_handler, 0), 254 }; 255 int amdgpu_ras_enable = -1; 256 uint amdgpu_ras_mask = 0xffffffff; 257 int amdgpu_bad_page_threshold = -1; 258 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 259 .timeout_fatal_disable = false, 260 .period = 0x0, /* default to 0x0 (timeout disable) */ 261 }; 262 263 /** 264 * DOC: vramlimit (int) 265 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 266 */ 267 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 268 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 269 270 /** 271 * DOC: vis_vramlimit (int) 272 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 273 */ 274 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 275 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 276 277 /** 278 * DOC: gartsize (uint) 279 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing. 280 * The default is -1 (The size depends on asic). 281 */ 282 MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)"); 283 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 284 285 /** 286 * DOC: gttsize (int) 287 * Restrict the size of GTT domain (for userspace use) in MiB for testing. 288 * The default is -1 (Use 1/2 RAM, minimum value is 3GB). 289 */ 290 MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)"); 291 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 292 293 /** 294 * DOC: moverate (int) 295 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 296 */ 297 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 298 module_param_named(moverate, amdgpu_moverate, int, 0600); 299 300 /** 301 * DOC: audio (int) 302 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 303 */ 304 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 305 module_param_named(audio, amdgpu_audio, int, 0444); 306 307 /** 308 * DOC: disp_priority (int) 309 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 310 */ 311 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 312 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 313 314 /** 315 * DOC: hw_i2c (int) 316 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 317 */ 318 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 319 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 320 321 /** 322 * DOC: pcie_gen2 (int) 323 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 324 */ 325 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 326 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 327 328 /** 329 * DOC: msi (int) 330 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 331 */ 332 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 333 module_param_named(msi, amdgpu_msi, int, 0444); 334 335 /** 336 * DOC: svm_default_granularity (uint) 337 * Used in buffer migration and handling of recoverable page faults 338 */ 339 MODULE_PARM_DESC(svm_default_granularity, "SVM's default granularity in log(2^Pages), default 9 = 2^9 = 2 MiB"); 340 module_param_named(svm_default_granularity, amdgpu_svm_default_granularity, uint, 0644); 341 342 /** 343 * DOC: lockup_timeout (string) 344 * Set GPU scheduler timeout value in ms. 345 * 346 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 347 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 348 * to the default timeout. 349 * 350 * - With one value specified, the setting will apply to all non-compute jobs. 351 * - With multiple values specified, the first one will be for GFX. 352 * The second one is for Compute. The third and fourth ones are 353 * for SDMA and Video. 354 * 355 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 356 * jobs is 10000. The timeout for compute is 60000. 357 */ 358 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 359 "for passthrough or sriov, 10000 for all jobs. 0: keep default value. negative: infinity timeout), format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 360 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 361 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 362 363 /** 364 * DOC: dpm (int) 365 * Override for dynamic power management setting 366 * (0 = disable, 1 = enable) 367 * The default is -1 (auto). 368 */ 369 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 370 module_param_named(dpm, amdgpu_dpm, int, 0444); 371 372 /** 373 * DOC: fw_load_type (int) 374 * Set different firmware loading type for debugging, if supported. 375 * Set to 0 to force direct loading if supported by the ASIC. Set 376 * to -1 to select the default loading mode for the ASIC, as defined 377 * by the driver. The default is -1 (auto). 378 */ 379 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); 380 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 381 382 /** 383 * DOC: aspm (int) 384 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 385 */ 386 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 387 module_param_named(aspm, amdgpu_aspm, int, 0444); 388 389 /** 390 * DOC: runpm (int) 391 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 392 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 393 * Setting the value to 0 disables this functionality. 394 * Setting the value to -2 is auto enabled with power down when displays are attached. 395 */ 396 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto, -2 = auto with displays)"); 397 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 398 399 /** 400 * DOC: ip_block_mask (uint) 401 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 402 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 403 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 404 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 405 */ 406 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 407 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 408 409 /** 410 * DOC: bapm (int) 411 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 412 * The default -1 (auto, enabled) 413 */ 414 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 415 module_param_named(bapm, amdgpu_bapm, int, 0444); 416 417 /** 418 * DOC: deep_color (int) 419 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 420 */ 421 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 422 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 423 424 /** 425 * DOC: vm_size (int) 426 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 427 */ 428 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 429 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 430 431 /** 432 * DOC: vm_fragment_size (int) 433 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 434 */ 435 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 436 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 437 438 /** 439 * DOC: vm_block_size (int) 440 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 441 */ 442 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 443 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 444 445 /** 446 * DOC: vm_fault_stop (int) 447 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 448 */ 449 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 450 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 451 452 /** 453 * DOC: vm_update_mode (int) 454 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 455 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 456 */ 457 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 458 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 459 460 /** 461 * DOC: exp_hw_support (int) 462 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 463 */ 464 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 465 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 466 467 /** 468 * DOC: dc (int) 469 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 470 */ 471 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 472 module_param_named(dc, amdgpu_dc, int, 0444); 473 474 /** 475 * DOC: sched_jobs (int) 476 * Override the max number of jobs supported in the sw queue. The default is 32. 477 */ 478 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 479 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 480 481 /** 482 * DOC: sched_hw_submission (int) 483 * Override the max number of HW submissions. The default is 2. 484 */ 485 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 486 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 487 488 /** 489 * DOC: ppfeaturemask (hexint) 490 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 491 * The default is the current set of stable power features. 492 */ 493 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 494 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 495 496 /** 497 * DOC: forcelongtraining (uint) 498 * Force long memory training in resume. 499 * The default is zero, indicates short training in resume. 500 */ 501 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 502 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 503 504 /** 505 * DOC: pcie_gen_cap (uint) 506 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 507 * The default is 0 (automatic for each asic). 508 */ 509 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 510 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 511 512 /** 513 * DOC: pcie_lane_cap (uint) 514 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 515 * The default is 0 (automatic for each asic). 516 */ 517 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 518 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 519 520 /** 521 * DOC: cg_mask (ullong) 522 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 523 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 524 */ 525 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 526 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 527 528 /** 529 * DOC: pg_mask (uint) 530 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 531 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 532 */ 533 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 534 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 535 536 /** 537 * DOC: sdma_phase_quantum (uint) 538 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 539 */ 540 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 541 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 542 543 /** 544 * DOC: disable_cu (charp) 545 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 546 */ 547 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 548 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 549 550 /** 551 * DOC: virtual_display (charp) 552 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 553 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 554 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 555 * device at 26:00.0. The default is NULL. 556 */ 557 MODULE_PARM_DESC(virtual_display, 558 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 559 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 560 561 /** 562 * DOC: lbpw (int) 563 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 564 */ 565 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 566 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 567 568 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 569 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 570 571 /** 572 * DOC: gpu_recovery (int) 573 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 574 */ 575 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 576 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 577 578 /** 579 * DOC: emu_mode (int) 580 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 581 */ 582 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 583 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 584 585 /** 586 * DOC: ras_enable (int) 587 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 588 */ 589 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 590 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 591 592 /** 593 * DOC: ras_mask (uint) 594 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 595 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 596 */ 597 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 598 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 599 600 /** 601 * DOC: timeout_fatal_disable (bool) 602 * Disable Watchdog timeout fatal error event 603 */ 604 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 605 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 606 607 /** 608 * DOC: timeout_period (uint) 609 * Modify the watchdog timeout max_cycles as (1 << period) 610 */ 611 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 612 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 613 614 /** 615 * DOC: si_support (int) 616 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 617 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 618 * otherwise using amdgpu driver. 619 */ 620 #ifdef CONFIG_DRM_AMDGPU_SI 621 622 #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) 623 int amdgpu_si_support; 624 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 625 #else 626 int amdgpu_si_support = 1; 627 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 628 #endif 629 630 module_param_named(si_support, amdgpu_si_support, int, 0444); 631 #endif 632 633 /** 634 * DOC: cik_support (int) 635 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 636 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 637 * otherwise using amdgpu driver. 638 */ 639 #ifdef CONFIG_DRM_AMDGPU_CIK 640 641 #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) 642 int amdgpu_cik_support; 643 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 644 #else 645 int amdgpu_cik_support = 1; 646 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 647 #endif 648 649 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 650 #endif 651 652 /** 653 * DOC: smu_memory_pool_size (uint) 654 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 655 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 656 */ 657 MODULE_PARM_DESC(smu_memory_pool_size, 658 "reserve gtt for smu debug usage, 0 = disable,0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 659 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 660 661 /** 662 * DOC: async_gfx_ring (int) 663 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 664 */ 665 MODULE_PARM_DESC(async_gfx_ring, 666 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 667 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 668 669 /** 670 * DOC: mcbp (int) 671 * It is used to enable mid command buffer preemption. (0 = disabled, 1 = enabled, -1 auto (default)) 672 */ 673 MODULE_PARM_DESC(mcbp, 674 "Enable Mid-command buffer preemption (0 = disabled, 1 = enabled), -1 = auto (default)"); 675 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 676 677 /** 678 * DOC: discovery (int) 679 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 680 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 681 */ 682 MODULE_PARM_DESC(discovery, 683 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 684 module_param_named(discovery, amdgpu_discovery, int, 0444); 685 686 /** 687 * DOC: mes (int) 688 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 689 * (0 = disabled (default), 1 = enabled) 690 */ 691 MODULE_PARM_DESC(mes, 692 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 693 module_param_named(mes, amdgpu_mes, int, 0444); 694 695 /** 696 * DOC: mes_log_enable (int) 697 * Enable Micro Engine Scheduler log. This is used to enable/disable MES internal log. 698 * (0 = disabled (default), 1 = enabled) 699 */ 700 MODULE_PARM_DESC(mes_log_enable, 701 "Enable Micro Engine Scheduler log (0 = disabled (default), 1 = enabled)"); 702 module_param_named(mes_log_enable, amdgpu_mes_log_enable, int, 0444); 703 704 /** 705 * DOC: mes_kiq (int) 706 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq. 707 * (0 = disabled (default), 1 = enabled) 708 */ 709 MODULE_PARM_DESC(mes_kiq, 710 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)"); 711 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444); 712 713 /** 714 * DOC: uni_mes (int) 715 * Enable Unified Micro Engine Scheduler. This is a new engine pipe for unified scheduler. 716 * (0 = disabled (default), 1 = enabled) 717 */ 718 MODULE_PARM_DESC(uni_mes, 719 "Enable Unified Micro Engine Scheduler (0 = disabled, 1 = enabled(default)"); 720 module_param_named(uni_mes, amdgpu_uni_mes, int, 0444); 721 722 /** 723 * DOC: noretry (int) 724 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 725 * do not support per-process XNACK this also disables retry page faults. 726 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 727 */ 728 MODULE_PARM_DESC(noretry, 729 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 730 module_param_named(noretry, amdgpu_noretry, int, 0644); 731 732 /** 733 * DOC: force_asic_type (int) 734 * A non negative value used to specify the asic type for all supported GPUs. 735 */ 736 MODULE_PARM_DESC(force_asic_type, 737 "A non negative value used to specify the asic type for all supported GPUs"); 738 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 739 740 /** 741 * DOC: use_xgmi_p2p (int) 742 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 743 */ 744 MODULE_PARM_DESC(use_xgmi_p2p, 745 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 746 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 747 748 749 #ifdef CONFIG_HSA_AMD 750 /** 751 * DOC: sched_policy (int) 752 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 753 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 754 * assigns queues to HQDs. 755 */ 756 int sched_policy = KFD_SCHED_POLICY_HWS; 757 module_param(sched_policy, int, 0444); 758 MODULE_PARM_DESC(sched_policy, 759 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 760 761 /** 762 * DOC: hws_max_conc_proc (int) 763 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 764 * number of VMIDs assigned to the HWS, which is also the default. 765 */ 766 int hws_max_conc_proc = -1; 767 module_param(hws_max_conc_proc, int, 0444); 768 MODULE_PARM_DESC(hws_max_conc_proc, 769 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 770 771 /** 772 * DOC: cwsr_enable (int) 773 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 774 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 775 * disables it. 776 */ 777 int cwsr_enable = 1; 778 module_param(cwsr_enable, int, 0444); 779 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 780 781 /** 782 * DOC: max_num_of_queues_per_device (int) 783 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 784 * is 4096. 785 */ 786 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 787 module_param(max_num_of_queues_per_device, int, 0444); 788 MODULE_PARM_DESC(max_num_of_queues_per_device, 789 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 790 791 /** 792 * DOC: send_sigterm (int) 793 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 794 * but just print errors on dmesg. Setting 1 enables sending sigterm. 795 */ 796 int send_sigterm; 797 module_param(send_sigterm, int, 0444); 798 MODULE_PARM_DESC(send_sigterm, 799 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 800 801 /** 802 * DOC: halt_if_hws_hang (int) 803 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 804 * Setting 1 enables halt on hang. 805 */ 806 int halt_if_hws_hang; 807 module_param(halt_if_hws_hang, int, 0644); 808 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 809 810 /** 811 * DOC: hws_gws_support(bool) 812 * Assume that HWS supports GWS barriers regardless of what firmware version 813 * check says. Default value: false (rely on MEC2 firmware version check). 814 */ 815 bool hws_gws_support; 816 module_param(hws_gws_support, bool, 0444); 817 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 818 819 /** 820 * DOC: queue_preemption_timeout_ms (int) 821 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 822 */ 823 int queue_preemption_timeout_ms = 9000; 824 module_param(queue_preemption_timeout_ms, int, 0644); 825 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 826 827 /** 828 * DOC: debug_evictions(bool) 829 * Enable extra debug messages to help determine the cause of evictions 830 */ 831 bool debug_evictions; 832 module_param(debug_evictions, bool, 0644); 833 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 834 835 /** 836 * DOC: no_system_mem_limit(bool) 837 * Disable system memory limit, to support multiple process shared memory 838 */ 839 bool no_system_mem_limit; 840 module_param(no_system_mem_limit, bool, 0644); 841 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 842 843 /** 844 * DOC: no_queue_eviction_on_vm_fault (int) 845 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 846 */ 847 int amdgpu_no_queue_eviction_on_vm_fault; 848 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 849 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 850 #endif 851 852 /** 853 * DOC: mtype_local (int) 854 */ 855 int amdgpu_mtype_local; 856 MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (0 = MTYPE_RW (default), 1 = MTYPE_NC, 2 = MTYPE_CC)"); 857 module_param_named(mtype_local, amdgpu_mtype_local, int, 0444); 858 859 /** 860 * DOC: pcie_p2p (bool) 861 * Enable PCIe P2P (requires large-BAR). Default value: true (on) 862 */ 863 #ifdef CONFIG_HSA_AMD_P2P 864 bool pcie_p2p = true; 865 module_param(pcie_p2p, bool, 0444); 866 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); 867 #endif 868 869 /** 870 * DOC: dcfeaturemask (uint) 871 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 872 * The default is the current set of stable display features. 873 */ 874 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 875 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 876 877 /** 878 * DOC: dcdebugmask (uint) 879 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 880 */ 881 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 882 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 883 884 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)"); 885 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444); 886 887 /** 888 * DOC: abmlevel (uint) 889 * Override the default ABM (Adaptive Backlight Management) level used for DC 890 * enabled hardware. Requires DMCU to be supported and loaded. 891 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 892 * default. Values 1-4 control the maximum allowable brightness reduction via 893 * the ABM algorithm, with 1 being the least reduction and 4 being the most 894 * reduction. 895 * 896 * Defaults to -1, or disabled. Userspace can only override this level after 897 * boot if it's set to auto. 898 */ 899 int amdgpu_dm_abm_level = -1; 900 MODULE_PARM_DESC(abmlevel, 901 "ABM level (0 = off, 1-4 = backlight reduction level, -1 auto (default))"); 902 module_param_named(abmlevel, amdgpu_dm_abm_level, int, 0444); 903 904 int amdgpu_backlight = -1; 905 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 906 module_param_named(backlight, amdgpu_backlight, bint, 0444); 907 908 /** 909 * DOC: damageclips (int) 910 * Enable or disable damage clips support. If damage clips support is disabled, 911 * we will force full frame updates, irrespective of what user space sends to 912 * us. 913 * 914 * Defaults to -1 (where it is enabled unless a PSR-SU display is detected). 915 */ 916 MODULE_PARM_DESC(damageclips, 917 "Damage clips support (0 = disable, 1 = enable, -1 auto (default))"); 918 module_param_named(damageclips, amdgpu_damage_clips, int, 0444); 919 920 /** 921 * DOC: tmz (int) 922 * Trusted Memory Zone (TMZ) is a method to protect data being written 923 * to or read from memory. 924 * 925 * The default value: 0 (off). TODO: change to auto till it is completed. 926 */ 927 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 928 module_param_named(tmz, amdgpu_tmz, int, 0444); 929 930 /** 931 * DOC: freesync_video (uint) 932 * Enable the optimization to adjust front porch timing to achieve seamless 933 * mode change experience when setting a freesync supported mode for which full 934 * modeset is not needed. 935 * 936 * The Display Core will add a set of modes derived from the base FreeSync 937 * video mode into the corresponding connector's mode list based on commonly 938 * used refresh rates and VRR range of the connected display, when users enable 939 * this feature. From the userspace perspective, they can see a seamless mode 940 * change experience when the change between different refresh rates under the 941 * same resolution. Additionally, userspace applications such as Video playback 942 * can read this modeset list and change the refresh rate based on the video 943 * frame rate. Finally, the userspace can also derive an appropriate mode for a 944 * particular refresh rate based on the FreeSync Mode and add it to the 945 * connector's mode list. 946 * 947 * Note: This is an experimental feature. 948 * 949 * The default value: 0 (off). 950 */ 951 MODULE_PARM_DESC( 952 freesync_video, 953 "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)"); 954 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); 955 956 /** 957 * DOC: reset_method (int) 958 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 959 */ 960 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 961 module_param_named(reset_method, amdgpu_reset_method, int, 0644); 962 963 /** 964 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 965 * threshold value of faulty pages detected by RAS ECC, which may 966 * result in the GPU entering bad status when the number of total 967 * faulty pages by ECC exceeds the threshold value. 968 */ 969 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = driver sets threshold)"); 970 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 971 972 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 973 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 974 975 /** 976 * DOC: vcnfw_log (int) 977 * Enable vcnfw log output for debugging, the default is disabled. 978 */ 979 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 980 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 981 982 /** 983 * DOC: sg_display (int) 984 * Disable S/G (scatter/gather) display (i.e., display from system memory). 985 * This option is only relevant on APUs. Set this option to 0 to disable 986 * S/G display if you experience flickering or other issues under memory 987 * pressure and report the issue. 988 */ 989 MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)"); 990 module_param_named(sg_display, amdgpu_sg_display, int, 0444); 991 992 /** 993 * DOC: umsch_mm (int) 994 * Enable Multi Media User Mode Scheduler. This is a HW scheduling engine for VCN and VPE. 995 * (0 = disabled (default), 1 = enabled) 996 */ 997 MODULE_PARM_DESC(umsch_mm, 998 "Enable Multi Media User Mode Scheduler (0 = disabled (default), 1 = enabled)"); 999 module_param_named(umsch_mm, amdgpu_umsch_mm, int, 0444); 1000 1001 /** 1002 * DOC: umsch_mm_fwlog (int) 1003 * Enable umschfw log output for debugging, the default is disabled. 1004 */ 1005 MODULE_PARM_DESC(umsch_mm_fwlog, "Enable umschfw log(0 = disable (default value), 1 = enable)"); 1006 module_param_named(umsch_mm_fwlog, amdgpu_umsch_mm_fwlog, int, 0444); 1007 1008 /** 1009 * DOC: smu_pptable_id (int) 1010 * Used to override pptable id. id = 0 use VBIOS pptable. 1011 * id > 0 use the soft pptable with specicfied id. 1012 */ 1013 MODULE_PARM_DESC(smu_pptable_id, 1014 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 1015 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 1016 1017 /** 1018 * DOC: partition_mode (int) 1019 * Used to override the default SPX mode. 1020 */ 1021 MODULE_PARM_DESC( 1022 user_partt_mode, 1023 "specify partition mode to be used (-2 = AMDGPU_AUTO_COMPUTE_PARTITION_MODE(default value) \ 1024 0 = AMDGPU_SPX_PARTITION_MODE, \ 1025 1 = AMDGPU_DPX_PARTITION_MODE, \ 1026 2 = AMDGPU_TPX_PARTITION_MODE, \ 1027 3 = AMDGPU_QPX_PARTITION_MODE, \ 1028 4 = AMDGPU_CPX_PARTITION_MODE)"); 1029 module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint, 0444); 1030 1031 1032 /** 1033 * DOC: enforce_isolation (bool) 1034 * enforce process isolation between graphics and compute via using the same reserved vmid. 1035 */ 1036 module_param(enforce_isolation, bool, 0444); 1037 MODULE_PARM_DESC(enforce_isolation, "enforce process isolation between graphics and compute . enforce_isolation = on"); 1038 1039 /** 1040 * DOC: seamless (int) 1041 * Seamless boot will keep the image on the screen during the boot process. 1042 */ 1043 MODULE_PARM_DESC(seamless, "Seamless boot (-1 = auto (default), 0 = disable, 1 = enable)"); 1044 module_param_named(seamless, amdgpu_seamless, int, 0444); 1045 1046 /** 1047 * DOC: debug_mask (uint) 1048 * Debug options for amdgpu, work as a binary mask with the following options: 1049 * 1050 * - 0x1: Debug VM handling 1051 * - 0x2: Enable simulating large-bar capability on non-large bar system. This 1052 * limits the VRAM size reported to ROCm applications to the visible 1053 * size, usually 256MB. 1054 * - 0x4: Disable GPU soft recovery, always do a full reset 1055 */ 1056 MODULE_PARM_DESC(debug_mask, "debug options for amdgpu, disabled by default"); 1057 module_param_named(debug_mask, amdgpu_debug_mask, uint, 0444); 1058 1059 /** 1060 * DOC: agp (int) 1061 * Enable the AGP aperture. This provides an aperture in the GPU's internal 1062 * address space for direct access to system memory. Note that these accesses 1063 * are non-snooped, so they are only used for access to uncached memory. 1064 */ 1065 MODULE_PARM_DESC(agp, "AGP (-1 = auto (default), 0 = disable, 1 = enable)"); 1066 module_param_named(agp, amdgpu_agp, int, 0444); 1067 1068 /** 1069 * DOC: wbrf (int) 1070 * Enable Wifi RFI interference mitigation feature. 1071 * Due to electrical and mechanical constraints there may be likely interference of 1072 * relatively high-powered harmonics of the (G-)DDR memory clocks with local radio 1073 * module frequency bands used by Wifi 6/6e/7. To mitigate the possible RFI interference, 1074 * with this feature enabled, PMFW will use either “shadowed P-State” or “P-State” based 1075 * on active list of frequencies in-use (to be avoided) as part of initial setting or 1076 * P-state transition. However, there may be potential performance impact with this 1077 * feature enabled. 1078 * (0 = disabled, 1 = enabled, -1 = auto (default setting, will be enabled if supported)) 1079 */ 1080 MODULE_PARM_DESC(wbrf, 1081 "Enable Wifi RFI interference mitigation (0 = disabled, 1 = enabled, -1 = auto(default)"); 1082 module_param_named(wbrf, amdgpu_wbrf, int, 0444); 1083 1084 /* These devices are not supported by amdgpu. 1085 * They are supported by the mach64, r128, radeon drivers 1086 */ 1087 static const u16 amdgpu_unsupported_pciidlist[] = { 1088 /* mach64 */ 1089 0x4354, 1090 0x4358, 1091 0x4554, 1092 0x4742, 1093 0x4744, 1094 0x4749, 1095 0x474C, 1096 0x474D, 1097 0x474E, 1098 0x474F, 1099 0x4750, 1100 0x4751, 1101 0x4752, 1102 0x4753, 1103 0x4754, 1104 0x4755, 1105 0x4756, 1106 0x4757, 1107 0x4758, 1108 0x4759, 1109 0x475A, 1110 0x4C42, 1111 0x4C44, 1112 0x4C47, 1113 0x4C49, 1114 0x4C4D, 1115 0x4C4E, 1116 0x4C50, 1117 0x4C51, 1118 0x4C52, 1119 0x4C53, 1120 0x5654, 1121 0x5655, 1122 0x5656, 1123 /* r128 */ 1124 0x4c45, 1125 0x4c46, 1126 0x4d46, 1127 0x4d4c, 1128 0x5041, 1129 0x5042, 1130 0x5043, 1131 0x5044, 1132 0x5045, 1133 0x5046, 1134 0x5047, 1135 0x5048, 1136 0x5049, 1137 0x504A, 1138 0x504B, 1139 0x504C, 1140 0x504D, 1141 0x504E, 1142 0x504F, 1143 0x5050, 1144 0x5051, 1145 0x5052, 1146 0x5053, 1147 0x5054, 1148 0x5055, 1149 0x5056, 1150 0x5057, 1151 0x5058, 1152 0x5245, 1153 0x5246, 1154 0x5247, 1155 0x524b, 1156 0x524c, 1157 0x534d, 1158 0x5446, 1159 0x544C, 1160 0x5452, 1161 /* radeon */ 1162 0x3150, 1163 0x3151, 1164 0x3152, 1165 0x3154, 1166 0x3155, 1167 0x3E50, 1168 0x3E54, 1169 0x4136, 1170 0x4137, 1171 0x4144, 1172 0x4145, 1173 0x4146, 1174 0x4147, 1175 0x4148, 1176 0x4149, 1177 0x414A, 1178 0x414B, 1179 0x4150, 1180 0x4151, 1181 0x4152, 1182 0x4153, 1183 0x4154, 1184 0x4155, 1185 0x4156, 1186 0x4237, 1187 0x4242, 1188 0x4336, 1189 0x4337, 1190 0x4437, 1191 0x4966, 1192 0x4967, 1193 0x4A48, 1194 0x4A49, 1195 0x4A4A, 1196 0x4A4B, 1197 0x4A4C, 1198 0x4A4D, 1199 0x4A4E, 1200 0x4A4F, 1201 0x4A50, 1202 0x4A54, 1203 0x4B48, 1204 0x4B49, 1205 0x4B4A, 1206 0x4B4B, 1207 0x4B4C, 1208 0x4C57, 1209 0x4C58, 1210 0x4C59, 1211 0x4C5A, 1212 0x4C64, 1213 0x4C66, 1214 0x4C67, 1215 0x4E44, 1216 0x4E45, 1217 0x4E46, 1218 0x4E47, 1219 0x4E48, 1220 0x4E49, 1221 0x4E4A, 1222 0x4E4B, 1223 0x4E50, 1224 0x4E51, 1225 0x4E52, 1226 0x4E53, 1227 0x4E54, 1228 0x4E56, 1229 0x5144, 1230 0x5145, 1231 0x5146, 1232 0x5147, 1233 0x5148, 1234 0x514C, 1235 0x514D, 1236 0x5157, 1237 0x5158, 1238 0x5159, 1239 0x515A, 1240 0x515E, 1241 0x5460, 1242 0x5462, 1243 0x5464, 1244 0x5548, 1245 0x5549, 1246 0x554A, 1247 0x554B, 1248 0x554C, 1249 0x554D, 1250 0x554E, 1251 0x554F, 1252 0x5550, 1253 0x5551, 1254 0x5552, 1255 0x5554, 1256 0x564A, 1257 0x564B, 1258 0x564F, 1259 0x5652, 1260 0x5653, 1261 0x5657, 1262 0x5834, 1263 0x5835, 1264 0x5954, 1265 0x5955, 1266 0x5974, 1267 0x5975, 1268 0x5960, 1269 0x5961, 1270 0x5962, 1271 0x5964, 1272 0x5965, 1273 0x5969, 1274 0x5a41, 1275 0x5a42, 1276 0x5a61, 1277 0x5a62, 1278 0x5b60, 1279 0x5b62, 1280 0x5b63, 1281 0x5b64, 1282 0x5b65, 1283 0x5c61, 1284 0x5c63, 1285 0x5d48, 1286 0x5d49, 1287 0x5d4a, 1288 0x5d4c, 1289 0x5d4d, 1290 0x5d4e, 1291 0x5d4f, 1292 0x5d50, 1293 0x5d52, 1294 0x5d57, 1295 0x5e48, 1296 0x5e4a, 1297 0x5e4b, 1298 0x5e4c, 1299 0x5e4d, 1300 0x5e4f, 1301 0x6700, 1302 0x6701, 1303 0x6702, 1304 0x6703, 1305 0x6704, 1306 0x6705, 1307 0x6706, 1308 0x6707, 1309 0x6708, 1310 0x6709, 1311 0x6718, 1312 0x6719, 1313 0x671c, 1314 0x671d, 1315 0x671f, 1316 0x6720, 1317 0x6721, 1318 0x6722, 1319 0x6723, 1320 0x6724, 1321 0x6725, 1322 0x6726, 1323 0x6727, 1324 0x6728, 1325 0x6729, 1326 0x6738, 1327 0x6739, 1328 0x673e, 1329 0x6740, 1330 0x6741, 1331 0x6742, 1332 0x6743, 1333 0x6744, 1334 0x6745, 1335 0x6746, 1336 0x6747, 1337 0x6748, 1338 0x6749, 1339 0x674A, 1340 0x6750, 1341 0x6751, 1342 0x6758, 1343 0x6759, 1344 0x675B, 1345 0x675D, 1346 0x675F, 1347 0x6760, 1348 0x6761, 1349 0x6762, 1350 0x6763, 1351 0x6764, 1352 0x6765, 1353 0x6766, 1354 0x6767, 1355 0x6768, 1356 0x6770, 1357 0x6771, 1358 0x6772, 1359 0x6778, 1360 0x6779, 1361 0x677B, 1362 0x6840, 1363 0x6841, 1364 0x6842, 1365 0x6843, 1366 0x6849, 1367 0x684C, 1368 0x6850, 1369 0x6858, 1370 0x6859, 1371 0x6880, 1372 0x6888, 1373 0x6889, 1374 0x688A, 1375 0x688C, 1376 0x688D, 1377 0x6898, 1378 0x6899, 1379 0x689b, 1380 0x689c, 1381 0x689d, 1382 0x689e, 1383 0x68a0, 1384 0x68a1, 1385 0x68a8, 1386 0x68a9, 1387 0x68b0, 1388 0x68b8, 1389 0x68b9, 1390 0x68ba, 1391 0x68be, 1392 0x68bf, 1393 0x68c0, 1394 0x68c1, 1395 0x68c7, 1396 0x68c8, 1397 0x68c9, 1398 0x68d8, 1399 0x68d9, 1400 0x68da, 1401 0x68de, 1402 0x68e0, 1403 0x68e1, 1404 0x68e4, 1405 0x68e5, 1406 0x68e8, 1407 0x68e9, 1408 0x68f1, 1409 0x68f2, 1410 0x68f8, 1411 0x68f9, 1412 0x68fa, 1413 0x68fe, 1414 0x7100, 1415 0x7101, 1416 0x7102, 1417 0x7103, 1418 0x7104, 1419 0x7105, 1420 0x7106, 1421 0x7108, 1422 0x7109, 1423 0x710A, 1424 0x710B, 1425 0x710C, 1426 0x710E, 1427 0x710F, 1428 0x7140, 1429 0x7141, 1430 0x7142, 1431 0x7143, 1432 0x7144, 1433 0x7145, 1434 0x7146, 1435 0x7147, 1436 0x7149, 1437 0x714A, 1438 0x714B, 1439 0x714C, 1440 0x714D, 1441 0x714E, 1442 0x714F, 1443 0x7151, 1444 0x7152, 1445 0x7153, 1446 0x715E, 1447 0x715F, 1448 0x7180, 1449 0x7181, 1450 0x7183, 1451 0x7186, 1452 0x7187, 1453 0x7188, 1454 0x718A, 1455 0x718B, 1456 0x718C, 1457 0x718D, 1458 0x718F, 1459 0x7193, 1460 0x7196, 1461 0x719B, 1462 0x719F, 1463 0x71C0, 1464 0x71C1, 1465 0x71C2, 1466 0x71C3, 1467 0x71C4, 1468 0x71C5, 1469 0x71C6, 1470 0x71C7, 1471 0x71CD, 1472 0x71CE, 1473 0x71D2, 1474 0x71D4, 1475 0x71D5, 1476 0x71D6, 1477 0x71DA, 1478 0x71DE, 1479 0x7200, 1480 0x7210, 1481 0x7211, 1482 0x7240, 1483 0x7243, 1484 0x7244, 1485 0x7245, 1486 0x7246, 1487 0x7247, 1488 0x7248, 1489 0x7249, 1490 0x724A, 1491 0x724B, 1492 0x724C, 1493 0x724D, 1494 0x724E, 1495 0x724F, 1496 0x7280, 1497 0x7281, 1498 0x7283, 1499 0x7284, 1500 0x7287, 1501 0x7288, 1502 0x7289, 1503 0x728B, 1504 0x728C, 1505 0x7290, 1506 0x7291, 1507 0x7293, 1508 0x7297, 1509 0x7834, 1510 0x7835, 1511 0x791e, 1512 0x791f, 1513 0x793f, 1514 0x7941, 1515 0x7942, 1516 0x796c, 1517 0x796d, 1518 0x796e, 1519 0x796f, 1520 0x9400, 1521 0x9401, 1522 0x9402, 1523 0x9403, 1524 0x9405, 1525 0x940A, 1526 0x940B, 1527 0x940F, 1528 0x94A0, 1529 0x94A1, 1530 0x94A3, 1531 0x94B1, 1532 0x94B3, 1533 0x94B4, 1534 0x94B5, 1535 0x94B9, 1536 0x9440, 1537 0x9441, 1538 0x9442, 1539 0x9443, 1540 0x9444, 1541 0x9446, 1542 0x944A, 1543 0x944B, 1544 0x944C, 1545 0x944E, 1546 0x9450, 1547 0x9452, 1548 0x9456, 1549 0x945A, 1550 0x945B, 1551 0x945E, 1552 0x9460, 1553 0x9462, 1554 0x946A, 1555 0x946B, 1556 0x947A, 1557 0x947B, 1558 0x9480, 1559 0x9487, 1560 0x9488, 1561 0x9489, 1562 0x948A, 1563 0x948F, 1564 0x9490, 1565 0x9491, 1566 0x9495, 1567 0x9498, 1568 0x949C, 1569 0x949E, 1570 0x949F, 1571 0x94C0, 1572 0x94C1, 1573 0x94C3, 1574 0x94C4, 1575 0x94C5, 1576 0x94C6, 1577 0x94C7, 1578 0x94C8, 1579 0x94C9, 1580 0x94CB, 1581 0x94CC, 1582 0x94CD, 1583 0x9500, 1584 0x9501, 1585 0x9504, 1586 0x9505, 1587 0x9506, 1588 0x9507, 1589 0x9508, 1590 0x9509, 1591 0x950F, 1592 0x9511, 1593 0x9515, 1594 0x9517, 1595 0x9519, 1596 0x9540, 1597 0x9541, 1598 0x9542, 1599 0x954E, 1600 0x954F, 1601 0x9552, 1602 0x9553, 1603 0x9555, 1604 0x9557, 1605 0x955f, 1606 0x9580, 1607 0x9581, 1608 0x9583, 1609 0x9586, 1610 0x9587, 1611 0x9588, 1612 0x9589, 1613 0x958A, 1614 0x958B, 1615 0x958C, 1616 0x958D, 1617 0x958E, 1618 0x958F, 1619 0x9590, 1620 0x9591, 1621 0x9593, 1622 0x9595, 1623 0x9596, 1624 0x9597, 1625 0x9598, 1626 0x9599, 1627 0x959B, 1628 0x95C0, 1629 0x95C2, 1630 0x95C4, 1631 0x95C5, 1632 0x95C6, 1633 0x95C7, 1634 0x95C9, 1635 0x95CC, 1636 0x95CD, 1637 0x95CE, 1638 0x95CF, 1639 0x9610, 1640 0x9611, 1641 0x9612, 1642 0x9613, 1643 0x9614, 1644 0x9615, 1645 0x9616, 1646 0x9640, 1647 0x9641, 1648 0x9642, 1649 0x9643, 1650 0x9644, 1651 0x9645, 1652 0x9647, 1653 0x9648, 1654 0x9649, 1655 0x964a, 1656 0x964b, 1657 0x964c, 1658 0x964e, 1659 0x964f, 1660 0x9710, 1661 0x9711, 1662 0x9712, 1663 0x9713, 1664 0x9714, 1665 0x9715, 1666 0x9802, 1667 0x9803, 1668 0x9804, 1669 0x9805, 1670 0x9806, 1671 0x9807, 1672 0x9808, 1673 0x9809, 1674 0x980A, 1675 0x9900, 1676 0x9901, 1677 0x9903, 1678 0x9904, 1679 0x9905, 1680 0x9906, 1681 0x9907, 1682 0x9908, 1683 0x9909, 1684 0x990A, 1685 0x990B, 1686 0x990C, 1687 0x990D, 1688 0x990E, 1689 0x990F, 1690 0x9910, 1691 0x9913, 1692 0x9917, 1693 0x9918, 1694 0x9919, 1695 0x9990, 1696 0x9991, 1697 0x9992, 1698 0x9993, 1699 0x9994, 1700 0x9995, 1701 0x9996, 1702 0x9997, 1703 0x9998, 1704 0x9999, 1705 0x999A, 1706 0x999B, 1707 0x999C, 1708 0x999D, 1709 0x99A0, 1710 0x99A2, 1711 0x99A4, 1712 /* radeon secondary ids */ 1713 0x3171, 1714 0x3e70, 1715 0x4164, 1716 0x4165, 1717 0x4166, 1718 0x4168, 1719 0x4170, 1720 0x4171, 1721 0x4172, 1722 0x4173, 1723 0x496e, 1724 0x4a69, 1725 0x4a6a, 1726 0x4a6b, 1727 0x4a70, 1728 0x4a74, 1729 0x4b69, 1730 0x4b6b, 1731 0x4b6c, 1732 0x4c6e, 1733 0x4e64, 1734 0x4e65, 1735 0x4e66, 1736 0x4e67, 1737 0x4e68, 1738 0x4e69, 1739 0x4e6a, 1740 0x4e71, 1741 0x4f73, 1742 0x5569, 1743 0x556b, 1744 0x556d, 1745 0x556f, 1746 0x5571, 1747 0x5854, 1748 0x5874, 1749 0x5940, 1750 0x5941, 1751 0x5b70, 1752 0x5b72, 1753 0x5b73, 1754 0x5b74, 1755 0x5b75, 1756 0x5d44, 1757 0x5d45, 1758 0x5d6d, 1759 0x5d6f, 1760 0x5d72, 1761 0x5d77, 1762 0x5e6b, 1763 0x5e6d, 1764 0x7120, 1765 0x7124, 1766 0x7129, 1767 0x712e, 1768 0x712f, 1769 0x7162, 1770 0x7163, 1771 0x7166, 1772 0x7167, 1773 0x7172, 1774 0x7173, 1775 0x71a0, 1776 0x71a1, 1777 0x71a3, 1778 0x71a7, 1779 0x71bb, 1780 0x71e0, 1781 0x71e1, 1782 0x71e2, 1783 0x71e6, 1784 0x71e7, 1785 0x71f2, 1786 0x7269, 1787 0x726b, 1788 0x726e, 1789 0x72a0, 1790 0x72a8, 1791 0x72b1, 1792 0x72b3, 1793 0x793f, 1794 }; 1795 1796 static const struct pci_device_id pciidlist[] = { 1797 #ifdef CONFIG_DRM_AMDGPU_SI 1798 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1799 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1800 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1801 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1802 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1803 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1804 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1805 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1806 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1807 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1808 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1809 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1810 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1811 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1812 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1813 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1814 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1815 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1816 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1817 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1818 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1819 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1820 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1821 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1822 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1823 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1824 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1825 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1826 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1827 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1828 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1829 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1830 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1831 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1832 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1833 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1834 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1835 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1836 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1837 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1838 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1839 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1840 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1841 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1842 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1843 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1844 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1845 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1846 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1847 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1848 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1849 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1850 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1851 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1852 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1853 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1854 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1855 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1856 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1857 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1858 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1859 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1860 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1861 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1862 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1863 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1864 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1865 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1866 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1867 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1868 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1869 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1870 #endif 1871 #ifdef CONFIG_DRM_AMDGPU_CIK 1872 /* Kaveri */ 1873 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1874 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1875 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1876 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1877 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1878 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1879 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1880 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1881 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1882 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1883 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1884 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1885 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1886 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1887 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1888 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1889 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1890 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1891 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1892 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1893 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1894 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1895 /* Bonaire */ 1896 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1897 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1898 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1899 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1900 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1901 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1902 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1903 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1904 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1905 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1906 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1907 /* Hawaii */ 1908 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1909 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1910 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1911 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1912 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1913 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1914 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1915 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1916 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1917 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1918 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1919 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1920 /* Kabini */ 1921 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1922 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1923 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1924 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1925 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1926 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1927 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1928 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1929 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1930 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1931 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1932 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1933 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1934 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1935 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1936 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1937 /* mullins */ 1938 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1939 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1940 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1941 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1942 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1943 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1944 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1945 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1946 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1947 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1948 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1949 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1950 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1951 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1952 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1953 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1954 #endif 1955 /* topaz */ 1956 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1957 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1958 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1959 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1960 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1961 /* tonga */ 1962 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1963 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1964 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1965 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1966 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1967 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1968 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1969 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1970 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1971 /* fiji */ 1972 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1973 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1974 /* carrizo */ 1975 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1976 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1977 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1978 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1979 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1980 /* stoney */ 1981 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1982 /* Polaris11 */ 1983 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1984 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1985 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1986 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1987 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1988 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1989 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1990 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1991 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1992 /* Polaris10 */ 1993 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1994 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1995 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1996 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1997 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1998 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1999 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2000 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2001 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2002 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2003 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2004 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2005 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2006 /* Polaris12 */ 2007 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2008 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2009 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2010 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2011 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2012 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2013 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2014 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2015 /* VEGAM */ 2016 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 2017 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 2018 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 2019 /* Vega 10 */ 2020 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2021 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2022 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2023 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2024 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2025 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2026 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2027 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2028 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2029 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2030 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2031 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2032 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2033 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2034 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2035 /* Vega 12 */ 2036 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2037 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2038 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2039 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2040 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2041 /* Vega 20 */ 2042 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2043 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2044 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2045 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2046 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2047 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2048 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2049 /* Raven */ 2050 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 2051 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 2052 /* Arcturus */ 2053 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2054 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2055 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2056 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2057 /* Navi10 */ 2058 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2059 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2060 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2061 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2062 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2063 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2064 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2065 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2066 /* Navi14 */ 2067 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2068 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2069 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2070 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2071 2072 /* Renoir */ 2073 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2074 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2075 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2076 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2077 2078 /* Navi12 */ 2079 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 2080 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 2081 2082 /* Sienna_Cichlid */ 2083 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2084 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2085 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2086 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2087 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2088 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2089 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2090 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2091 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2092 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2093 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2094 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2095 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2096 2097 /* Yellow Carp */ 2098 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 2099 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 2100 2101 /* Navy_Flounder */ 2102 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2103 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2104 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2105 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2106 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2107 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2108 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2109 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2110 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2111 2112 /* DIMGREY_CAVEFISH */ 2113 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2114 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2115 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2116 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2117 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2118 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2119 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2120 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2121 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2122 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2123 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2124 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2125 2126 /* Aldebaran */ 2127 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2128 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2129 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2130 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2131 2132 /* CYAN_SKILLFISH */ 2133 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2134 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2135 2136 /* BEIGE_GOBY */ 2137 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2138 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2139 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2140 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2141 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2142 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2143 2144 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2145 .class = PCI_CLASS_DISPLAY_VGA << 8, 2146 .class_mask = 0xffffff, 2147 .driver_data = CHIP_IP_DISCOVERY }, 2148 2149 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2150 .class = PCI_CLASS_DISPLAY_OTHER << 8, 2151 .class_mask = 0xffffff, 2152 .driver_data = CHIP_IP_DISCOVERY }, 2153 2154 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2155 .class = PCI_CLASS_ACCELERATOR_PROCESSING << 8, 2156 .class_mask = 0xffffff, 2157 .driver_data = CHIP_IP_DISCOVERY }, 2158 2159 {0, 0, 0} 2160 }; 2161 2162 MODULE_DEVICE_TABLE(pci, pciidlist); 2163 2164 static const struct amdgpu_asic_type_quirk asic_type_quirks[] = { 2165 /* differentiate between P10 and P11 asics with the same DID */ 2166 {0x67FF, 0xE3, CHIP_POLARIS10}, 2167 {0x67FF, 0xE7, CHIP_POLARIS10}, 2168 {0x67FF, 0xF3, CHIP_POLARIS10}, 2169 {0x67FF, 0xF7, CHIP_POLARIS10}, 2170 }; 2171 2172 static const struct drm_driver amdgpu_kms_driver; 2173 2174 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 2175 { 2176 struct pci_dev *p = NULL; 2177 int i; 2178 2179 /* 0 - GPU 2180 * 1 - audio 2181 * 2 - USB 2182 * 3 - UCSI 2183 */ 2184 for (i = 1; i < 4; i++) { 2185 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 2186 adev->pdev->bus->number, i); 2187 if (p) { 2188 pm_runtime_get_sync(&p->dev); 2189 pm_runtime_mark_last_busy(&p->dev); 2190 pm_runtime_put_autosuspend(&p->dev); 2191 pci_dev_put(p); 2192 } 2193 } 2194 } 2195 2196 static void amdgpu_init_debug_options(struct amdgpu_device *adev) 2197 { 2198 if (amdgpu_debug_mask & AMDGPU_DEBUG_VM) { 2199 pr_info("debug: VM handling debug enabled\n"); 2200 adev->debug_vm = true; 2201 } 2202 2203 if (amdgpu_debug_mask & AMDGPU_DEBUG_LARGEBAR) { 2204 pr_info("debug: enabled simulating large-bar capability on non-large bar system\n"); 2205 adev->debug_largebar = true; 2206 } 2207 2208 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY) { 2209 pr_info("debug: soft reset for GPU recovery disabled\n"); 2210 adev->debug_disable_soft_recovery = true; 2211 } 2212 2213 if (amdgpu_debug_mask & AMDGPU_DEBUG_USE_VRAM_FW_BUF) { 2214 pr_info("debug: place fw in vram for frontdoor loading\n"); 2215 adev->debug_use_vram_fw_buf = true; 2216 } 2217 2218 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_RAS_ACA) { 2219 pr_info("debug: enable RAS ACA\n"); 2220 adev->debug_enable_ras_aca = true; 2221 } 2222 2223 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_EXP_RESETS) { 2224 pr_info("debug: enable experimental reset features\n"); 2225 adev->debug_exp_resets = true; 2226 } 2227 } 2228 2229 static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long flags) 2230 { 2231 int i; 2232 2233 for (i = 0; i < ARRAY_SIZE(asic_type_quirks); i++) { 2234 if (pdev->device == asic_type_quirks[i].device && 2235 pdev->revision == asic_type_quirks[i].revision) { 2236 flags &= ~AMD_ASIC_MASK; 2237 flags |= asic_type_quirks[i].type; 2238 break; 2239 } 2240 } 2241 2242 return flags; 2243 } 2244 2245 static int amdgpu_pci_probe(struct pci_dev *pdev, 2246 const struct pci_device_id *ent) 2247 { 2248 struct drm_device *ddev; 2249 struct amdgpu_device *adev; 2250 unsigned long flags = ent->driver_data; 2251 int ret, retry = 0, i; 2252 bool supports_atomic = false; 2253 2254 /* skip devices which are owned by radeon */ 2255 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2256 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2257 return -ENODEV; 2258 } 2259 2260 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) 2261 amdgpu_aspm = 0; 2262 2263 if (amdgpu_virtual_display || 2264 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 2265 supports_atomic = true; 2266 2267 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2268 DRM_INFO("This hardware requires experimental hardware support.\n" 2269 "See modparam exp_hw_support\n"); 2270 return -ENODEV; 2271 } 2272 2273 flags = amdgpu_fix_asic_type(pdev, flags); 2274 2275 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2276 * however, SME requires an indirect IOMMU mapping because the encryption 2277 * bit is beyond the DMA mask of the chip. 2278 */ 2279 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2280 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2281 dev_info(&pdev->dev, 2282 "SME is not compatible with RAVEN\n"); 2283 return -ENOTSUPP; 2284 } 2285 2286 #ifdef CONFIG_DRM_AMDGPU_SI 2287 if (!amdgpu_si_support) { 2288 switch (flags & AMD_ASIC_MASK) { 2289 case CHIP_TAHITI: 2290 case CHIP_PITCAIRN: 2291 case CHIP_VERDE: 2292 case CHIP_OLAND: 2293 case CHIP_HAINAN: 2294 dev_info(&pdev->dev, 2295 "SI support provided by radeon.\n"); 2296 dev_info(&pdev->dev, 2297 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 2298 ); 2299 return -ENODEV; 2300 } 2301 } 2302 #endif 2303 #ifdef CONFIG_DRM_AMDGPU_CIK 2304 if (!amdgpu_cik_support) { 2305 switch (flags & AMD_ASIC_MASK) { 2306 case CHIP_KAVERI: 2307 case CHIP_BONAIRE: 2308 case CHIP_HAWAII: 2309 case CHIP_KABINI: 2310 case CHIP_MULLINS: 2311 dev_info(&pdev->dev, 2312 "CIK support provided by radeon.\n"); 2313 dev_info(&pdev->dev, 2314 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 2315 ); 2316 return -ENODEV; 2317 } 2318 } 2319 #endif 2320 2321 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2322 if (IS_ERR(adev)) 2323 return PTR_ERR(adev); 2324 2325 adev->dev = &pdev->dev; 2326 adev->pdev = pdev; 2327 ddev = adev_to_drm(adev); 2328 2329 if (!supports_atomic) 2330 ddev->driver_features &= ~DRIVER_ATOMIC; 2331 2332 ret = pci_enable_device(pdev); 2333 if (ret) 2334 return ret; 2335 2336 pci_set_drvdata(pdev, ddev); 2337 2338 amdgpu_init_debug_options(adev); 2339 2340 ret = amdgpu_driver_load_kms(adev, flags); 2341 if (ret) 2342 goto err_pci; 2343 2344 retry_init: 2345 ret = drm_dev_register(ddev, flags); 2346 if (ret == -EAGAIN && ++retry <= 3) { 2347 DRM_INFO("retry init %d\n", retry); 2348 /* Don't request EX mode too frequently which is attacking */ 2349 msleep(5000); 2350 goto retry_init; 2351 } else if (ret) { 2352 goto err_pci; 2353 } 2354 2355 ret = amdgpu_xcp_dev_register(adev, ent); 2356 if (ret) 2357 goto err_pci; 2358 2359 ret = amdgpu_amdkfd_drm_client_create(adev); 2360 if (ret) 2361 goto err_pci; 2362 2363 /* 2364 * 1. don't init fbdev on hw without DCE 2365 * 2. don't init fbdev if there are no connectors 2366 */ 2367 if (adev->mode_info.mode_config_initialized && 2368 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2369 const struct drm_format_info *format; 2370 2371 /* select 8 bpp console on low vram cards */ 2372 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2373 format = drm_format_info(DRM_FORMAT_C8); 2374 else 2375 format = NULL; 2376 2377 drm_client_setup(adev_to_drm(adev), format); 2378 } 2379 2380 ret = amdgpu_debugfs_init(adev); 2381 if (ret) 2382 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2383 2384 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2385 /* only need to skip on ATPX */ 2386 if (amdgpu_device_supports_px(ddev)) 2387 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2388 /* we want direct complete for BOCO */ 2389 if (amdgpu_device_supports_boco(ddev)) 2390 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2391 DPM_FLAG_SMART_SUSPEND | 2392 DPM_FLAG_MAY_SKIP_RESUME); 2393 pm_runtime_use_autosuspend(ddev->dev); 2394 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2395 2396 pm_runtime_allow(ddev->dev); 2397 2398 pm_runtime_mark_last_busy(ddev->dev); 2399 pm_runtime_put_autosuspend(ddev->dev); 2400 2401 pci_wake_from_d3(pdev, TRUE); 2402 2403 /* 2404 * For runpm implemented via BACO, PMFW will handle the 2405 * timing for BACO in and out: 2406 * - put ASIC into BACO state only when both video and 2407 * audio functions are in D3 state. 2408 * - pull ASIC out of BACO state when either video or 2409 * audio function is in D0 state. 2410 * Also, at startup, PMFW assumes both functions are in 2411 * D0 state. 2412 * 2413 * So if snd driver was loaded prior to amdgpu driver 2414 * and audio function was put into D3 state, there will 2415 * be no PMFW-aware D-state transition(D0->D3) on runpm 2416 * suspend. Thus the BACO will be not correctly kicked in. 2417 * 2418 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2419 * into D0 state. Then there will be a PMFW-aware D-state 2420 * transition(D0->D3) on runpm suspend. 2421 */ 2422 if (amdgpu_device_supports_baco(ddev) && 2423 !(adev->flags & AMD_IS_APU) && 2424 (adev->asic_type >= CHIP_NAVI10)) 2425 amdgpu_get_secondary_funcs(adev); 2426 } 2427 2428 return 0; 2429 2430 err_pci: 2431 pci_disable_device(pdev); 2432 return ret; 2433 } 2434 2435 static void 2436 amdgpu_pci_remove(struct pci_dev *pdev) 2437 { 2438 struct drm_device *dev = pci_get_drvdata(pdev); 2439 struct amdgpu_device *adev = drm_to_adev(dev); 2440 2441 amdgpu_xcp_dev_unplug(adev); 2442 drm_dev_unplug(dev); 2443 2444 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2445 pm_runtime_get_sync(dev->dev); 2446 pm_runtime_forbid(dev->dev); 2447 } 2448 2449 amdgpu_driver_unload_kms(dev); 2450 2451 /* 2452 * Flush any in flight DMA operations from device. 2453 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2454 * StatusTransactions Pending bit. 2455 */ 2456 pci_disable_device(pdev); 2457 pci_wait_for_pending_transaction(pdev); 2458 } 2459 2460 static void 2461 amdgpu_pci_shutdown(struct pci_dev *pdev) 2462 { 2463 struct drm_device *dev = pci_get_drvdata(pdev); 2464 struct amdgpu_device *adev = drm_to_adev(dev); 2465 2466 if (amdgpu_ras_intr_triggered()) 2467 return; 2468 2469 /* if we are running in a VM, make sure the device 2470 * torn down properly on reboot/shutdown. 2471 * unfortunately we can't detect certain 2472 * hypervisors so just do this all the time. 2473 */ 2474 if (!amdgpu_passthrough(adev)) 2475 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2476 amdgpu_device_ip_suspend(adev); 2477 adev->mp1_state = PP_MP1_STATE_NONE; 2478 } 2479 2480 /** 2481 * amdgpu_drv_delayed_reset_work_handler - work handler for reset 2482 * 2483 * @work: work_struct. 2484 */ 2485 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) 2486 { 2487 struct list_head device_list; 2488 struct amdgpu_device *adev; 2489 int i, r; 2490 struct amdgpu_reset_context reset_context; 2491 2492 memset(&reset_context, 0, sizeof(reset_context)); 2493 2494 mutex_lock(&mgpu_info.mutex); 2495 if (mgpu_info.pending_reset == true) { 2496 mutex_unlock(&mgpu_info.mutex); 2497 return; 2498 } 2499 mgpu_info.pending_reset = true; 2500 mutex_unlock(&mgpu_info.mutex); 2501 2502 /* Use a common context, just need to make sure full reset is done */ 2503 reset_context.method = AMD_RESET_METHOD_NONE; 2504 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2505 2506 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2507 adev = mgpu_info.gpu_ins[i].adev; 2508 reset_context.reset_req_dev = adev; 2509 r = amdgpu_device_pre_asic_reset(adev, &reset_context); 2510 if (r) { 2511 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", 2512 r, adev_to_drm(adev)->unique); 2513 } 2514 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) 2515 r = -EALREADY; 2516 } 2517 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2518 adev = mgpu_info.gpu_ins[i].adev; 2519 flush_work(&adev->xgmi_reset_work); 2520 adev->gmc.xgmi.pending_reset = false; 2521 } 2522 2523 /* reset function will rebuild the xgmi hive info , clear it now */ 2524 for (i = 0; i < mgpu_info.num_dgpu; i++) 2525 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); 2526 2527 INIT_LIST_HEAD(&device_list); 2528 2529 for (i = 0; i < mgpu_info.num_dgpu; i++) 2530 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); 2531 2532 /* unregister the GPU first, reset function will add them back */ 2533 list_for_each_entry(adev, &device_list, reset_list) 2534 amdgpu_unregister_gpu_instance(adev); 2535 2536 /* Use a common context, just need to make sure full reset is done */ 2537 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); 2538 set_bit(AMDGPU_SKIP_COREDUMP, &reset_context.flags); 2539 r = amdgpu_do_asic_reset(&device_list, &reset_context); 2540 2541 if (r) { 2542 DRM_ERROR("reinit gpus failure"); 2543 return; 2544 } 2545 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2546 adev = mgpu_info.gpu_ins[i].adev; 2547 if (!adev->kfd.init_complete) { 2548 kgd2kfd_init_zone_device(adev); 2549 amdgpu_amdkfd_device_init(adev); 2550 amdgpu_amdkfd_drm_client_create(adev); 2551 } 2552 amdgpu_ttm_set_buffer_funcs_status(adev, true); 2553 } 2554 } 2555 2556 static int amdgpu_pmops_prepare(struct device *dev) 2557 { 2558 struct drm_device *drm_dev = dev_get_drvdata(dev); 2559 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2560 2561 /* Return a positive number here so 2562 * DPM_FLAG_SMART_SUSPEND works properly 2563 */ 2564 if (amdgpu_device_supports_boco(drm_dev) && 2565 pm_runtime_suspended(dev)) 2566 return 1; 2567 2568 /* if we will not support s3 or s2i for the device 2569 * then skip suspend 2570 */ 2571 if (!amdgpu_acpi_is_s0ix_active(adev) && 2572 !amdgpu_acpi_is_s3_active(adev)) 2573 return 1; 2574 2575 return amdgpu_device_prepare(drm_dev); 2576 } 2577 2578 static void amdgpu_pmops_complete(struct device *dev) 2579 { 2580 /* nothing to do */ 2581 } 2582 2583 static int amdgpu_pmops_suspend(struct device *dev) 2584 { 2585 struct drm_device *drm_dev = dev_get_drvdata(dev); 2586 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2587 2588 adev->suspend_complete = false; 2589 if (amdgpu_acpi_is_s0ix_active(adev)) 2590 adev->in_s0ix = true; 2591 else if (amdgpu_acpi_is_s3_active(adev)) 2592 adev->in_s3 = true; 2593 if (!adev->in_s0ix && !adev->in_s3) 2594 return 0; 2595 return amdgpu_device_suspend(drm_dev, true); 2596 } 2597 2598 static int amdgpu_pmops_suspend_noirq(struct device *dev) 2599 { 2600 struct drm_device *drm_dev = dev_get_drvdata(dev); 2601 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2602 2603 adev->suspend_complete = true; 2604 if (amdgpu_acpi_should_gpu_reset(adev)) 2605 return amdgpu_asic_reset(adev); 2606 2607 return 0; 2608 } 2609 2610 static int amdgpu_pmops_resume(struct device *dev) 2611 { 2612 struct drm_device *drm_dev = dev_get_drvdata(dev); 2613 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2614 int r; 2615 2616 if (!adev->in_s0ix && !adev->in_s3) 2617 return 0; 2618 2619 /* Avoids registers access if device is physically gone */ 2620 if (!pci_device_is_present(adev->pdev)) 2621 adev->no_hw_access = true; 2622 2623 r = amdgpu_device_resume(drm_dev, true); 2624 if (amdgpu_acpi_is_s0ix_active(adev)) 2625 adev->in_s0ix = false; 2626 else 2627 adev->in_s3 = false; 2628 return r; 2629 } 2630 2631 static int amdgpu_pmops_freeze(struct device *dev) 2632 { 2633 struct drm_device *drm_dev = dev_get_drvdata(dev); 2634 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2635 int r; 2636 2637 adev->in_s4 = true; 2638 r = amdgpu_device_suspend(drm_dev, true); 2639 adev->in_s4 = false; 2640 if (r) 2641 return r; 2642 2643 if (amdgpu_acpi_should_gpu_reset(adev)) 2644 return amdgpu_asic_reset(adev); 2645 return 0; 2646 } 2647 2648 static int amdgpu_pmops_thaw(struct device *dev) 2649 { 2650 struct drm_device *drm_dev = dev_get_drvdata(dev); 2651 2652 return amdgpu_device_resume(drm_dev, true); 2653 } 2654 2655 static int amdgpu_pmops_poweroff(struct device *dev) 2656 { 2657 struct drm_device *drm_dev = dev_get_drvdata(dev); 2658 2659 return amdgpu_device_suspend(drm_dev, true); 2660 } 2661 2662 static int amdgpu_pmops_restore(struct device *dev) 2663 { 2664 struct drm_device *drm_dev = dev_get_drvdata(dev); 2665 2666 return amdgpu_device_resume(drm_dev, true); 2667 } 2668 2669 static int amdgpu_runtime_idle_check_display(struct device *dev) 2670 { 2671 struct pci_dev *pdev = to_pci_dev(dev); 2672 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2673 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2674 2675 if (adev->mode_info.num_crtc) { 2676 struct drm_connector *list_connector; 2677 struct drm_connector_list_iter iter; 2678 int ret = 0; 2679 2680 if (amdgpu_runtime_pm != -2) { 2681 /* XXX: Return busy if any displays are connected to avoid 2682 * possible display wakeups after runtime resume due to 2683 * hotplug events in case any displays were connected while 2684 * the GPU was in suspend. Remove this once that is fixed. 2685 */ 2686 mutex_lock(&drm_dev->mode_config.mutex); 2687 drm_connector_list_iter_begin(drm_dev, &iter); 2688 drm_for_each_connector_iter(list_connector, &iter) { 2689 if (list_connector->status == connector_status_connected) { 2690 ret = -EBUSY; 2691 break; 2692 } 2693 } 2694 drm_connector_list_iter_end(&iter); 2695 mutex_unlock(&drm_dev->mode_config.mutex); 2696 2697 if (ret) 2698 return ret; 2699 } 2700 2701 if (adev->dc_enabled) { 2702 struct drm_crtc *crtc; 2703 2704 drm_for_each_crtc(crtc, drm_dev) { 2705 drm_modeset_lock(&crtc->mutex, NULL); 2706 if (crtc->state->active) 2707 ret = -EBUSY; 2708 drm_modeset_unlock(&crtc->mutex); 2709 if (ret < 0) 2710 break; 2711 } 2712 } else { 2713 mutex_lock(&drm_dev->mode_config.mutex); 2714 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2715 2716 drm_connector_list_iter_begin(drm_dev, &iter); 2717 drm_for_each_connector_iter(list_connector, &iter) { 2718 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2719 ret = -EBUSY; 2720 break; 2721 } 2722 } 2723 2724 drm_connector_list_iter_end(&iter); 2725 2726 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2727 mutex_unlock(&drm_dev->mode_config.mutex); 2728 } 2729 if (ret) 2730 return ret; 2731 } 2732 2733 return 0; 2734 } 2735 2736 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2737 { 2738 struct pci_dev *pdev = to_pci_dev(dev); 2739 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2740 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2741 int ret, i; 2742 2743 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2744 pm_runtime_forbid(dev); 2745 return -EBUSY; 2746 } 2747 2748 ret = amdgpu_runtime_idle_check_display(dev); 2749 if (ret) 2750 return ret; 2751 2752 /* wait for all rings to drain before suspending */ 2753 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2754 struct amdgpu_ring *ring = adev->rings[i]; 2755 2756 if (ring && ring->sched.ready) { 2757 ret = amdgpu_fence_wait_empty(ring); 2758 if (ret) 2759 return -EBUSY; 2760 } 2761 } 2762 2763 adev->in_runpm = true; 2764 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2765 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2766 2767 /* 2768 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2769 * proper cleanups and put itself into a state ready for PNP. That 2770 * can address some random resuming failure observed on BOCO capable 2771 * platforms. 2772 * TODO: this may be also needed for PX capable platform. 2773 */ 2774 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2775 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2776 2777 ret = amdgpu_device_prepare(drm_dev); 2778 if (ret) 2779 return ret; 2780 ret = amdgpu_device_suspend(drm_dev, false); 2781 if (ret) { 2782 adev->in_runpm = false; 2783 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2784 adev->mp1_state = PP_MP1_STATE_NONE; 2785 return ret; 2786 } 2787 2788 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2789 adev->mp1_state = PP_MP1_STATE_NONE; 2790 2791 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) { 2792 /* Only need to handle PCI state in the driver for ATPX 2793 * PCI core handles it for _PR3. 2794 */ 2795 amdgpu_device_cache_pci_state(pdev); 2796 pci_disable_device(pdev); 2797 pci_ignore_hotplug(pdev); 2798 pci_set_power_state(pdev, PCI_D3cold); 2799 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2800 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) { 2801 /* nothing to do */ 2802 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2803 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) { 2804 amdgpu_device_baco_enter(drm_dev); 2805 } 2806 2807 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n"); 2808 2809 return 0; 2810 } 2811 2812 static int amdgpu_pmops_runtime_resume(struct device *dev) 2813 { 2814 struct pci_dev *pdev = to_pci_dev(dev); 2815 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2816 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2817 int ret; 2818 2819 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) 2820 return -EINVAL; 2821 2822 /* Avoids registers access if device is physically gone */ 2823 if (!pci_device_is_present(adev->pdev)) 2824 adev->no_hw_access = true; 2825 2826 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) { 2827 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2828 2829 /* Only need to handle PCI state in the driver for ATPX 2830 * PCI core handles it for _PR3. 2831 */ 2832 pci_set_power_state(pdev, PCI_D0); 2833 amdgpu_device_load_pci_state(pdev); 2834 ret = pci_enable_device(pdev); 2835 if (ret) 2836 return ret; 2837 pci_set_master(pdev); 2838 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) { 2839 /* Only need to handle PCI state in the driver for ATPX 2840 * PCI core handles it for _PR3. 2841 */ 2842 pci_set_master(pdev); 2843 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2844 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) { 2845 amdgpu_device_baco_exit(drm_dev); 2846 } 2847 ret = amdgpu_device_resume(drm_dev, false); 2848 if (ret) { 2849 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2850 pci_disable_device(pdev); 2851 return ret; 2852 } 2853 2854 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2855 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2856 adev->in_runpm = false; 2857 return 0; 2858 } 2859 2860 static int amdgpu_pmops_runtime_idle(struct device *dev) 2861 { 2862 struct drm_device *drm_dev = dev_get_drvdata(dev); 2863 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2864 int ret; 2865 2866 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2867 pm_runtime_forbid(dev); 2868 return -EBUSY; 2869 } 2870 2871 ret = amdgpu_runtime_idle_check_display(dev); 2872 2873 pm_runtime_mark_last_busy(dev); 2874 pm_runtime_autosuspend(dev); 2875 return ret; 2876 } 2877 2878 long amdgpu_drm_ioctl(struct file *filp, 2879 unsigned int cmd, unsigned long arg) 2880 { 2881 struct drm_file *file_priv = filp->private_data; 2882 struct drm_device *dev; 2883 long ret; 2884 2885 dev = file_priv->minor->dev; 2886 ret = pm_runtime_get_sync(dev->dev); 2887 if (ret < 0) 2888 goto out; 2889 2890 ret = drm_ioctl(filp, cmd, arg); 2891 2892 pm_runtime_mark_last_busy(dev->dev); 2893 out: 2894 pm_runtime_put_autosuspend(dev->dev); 2895 return ret; 2896 } 2897 2898 static const struct dev_pm_ops amdgpu_pm_ops = { 2899 .prepare = amdgpu_pmops_prepare, 2900 .complete = amdgpu_pmops_complete, 2901 .suspend = amdgpu_pmops_suspend, 2902 .suspend_noirq = amdgpu_pmops_suspend_noirq, 2903 .resume = amdgpu_pmops_resume, 2904 .freeze = amdgpu_pmops_freeze, 2905 .thaw = amdgpu_pmops_thaw, 2906 .poweroff = amdgpu_pmops_poweroff, 2907 .restore = amdgpu_pmops_restore, 2908 .runtime_suspend = amdgpu_pmops_runtime_suspend, 2909 .runtime_resume = amdgpu_pmops_runtime_resume, 2910 .runtime_idle = amdgpu_pmops_runtime_idle, 2911 }; 2912 2913 static int amdgpu_flush(struct file *f, fl_owner_t id) 2914 { 2915 struct drm_file *file_priv = f->private_data; 2916 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2917 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2918 2919 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 2920 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 2921 2922 return timeout >= 0 ? 0 : timeout; 2923 } 2924 2925 static const struct file_operations amdgpu_driver_kms_fops = { 2926 .owner = THIS_MODULE, 2927 .open = drm_open, 2928 .flush = amdgpu_flush, 2929 .release = drm_release, 2930 .unlocked_ioctl = amdgpu_drm_ioctl, 2931 .mmap = drm_gem_mmap, 2932 .poll = drm_poll, 2933 .read = drm_read, 2934 #ifdef CONFIG_COMPAT 2935 .compat_ioctl = amdgpu_kms_compat_ioctl, 2936 #endif 2937 #ifdef CONFIG_PROC_FS 2938 .show_fdinfo = drm_show_fdinfo, 2939 #endif 2940 .fop_flags = FOP_UNSIGNED_OFFSET, 2941 }; 2942 2943 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 2944 { 2945 struct drm_file *file; 2946 2947 if (!filp) 2948 return -EINVAL; 2949 2950 if (filp->f_op != &amdgpu_driver_kms_fops) 2951 return -EINVAL; 2952 2953 file = filp->private_data; 2954 *fpriv = file->driver_priv; 2955 return 0; 2956 } 2957 2958 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 2959 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2960 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2961 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2962 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 2963 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2964 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2965 /* KMS */ 2966 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2967 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2968 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2969 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2970 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2971 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2972 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2973 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2974 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2975 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2976 }; 2977 2978 static const struct drm_driver amdgpu_kms_driver = { 2979 .driver_features = 2980 DRIVER_ATOMIC | 2981 DRIVER_GEM | 2982 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 2983 DRIVER_SYNCOBJ_TIMELINE, 2984 .open = amdgpu_driver_open_kms, 2985 .postclose = amdgpu_driver_postclose_kms, 2986 .ioctls = amdgpu_ioctls_kms, 2987 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2988 .dumb_create = amdgpu_mode_dumb_create, 2989 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2990 DRM_FBDEV_TTM_DRIVER_OPS, 2991 .fops = &amdgpu_driver_kms_fops, 2992 .release = &amdgpu_driver_release_kms, 2993 #ifdef CONFIG_PROC_FS 2994 .show_fdinfo = amdgpu_show_fdinfo, 2995 #endif 2996 2997 .gem_prime_import = amdgpu_gem_prime_import, 2998 2999 .name = DRIVER_NAME, 3000 .desc = DRIVER_DESC, 3001 .date = DRIVER_DATE, 3002 .major = KMS_DRIVER_MAJOR, 3003 .minor = KMS_DRIVER_MINOR, 3004 .patchlevel = KMS_DRIVER_PATCHLEVEL, 3005 }; 3006 3007 const struct drm_driver amdgpu_partition_driver = { 3008 .driver_features = 3009 DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ | 3010 DRIVER_SYNCOBJ_TIMELINE, 3011 .open = amdgpu_driver_open_kms, 3012 .postclose = amdgpu_driver_postclose_kms, 3013 .ioctls = amdgpu_ioctls_kms, 3014 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 3015 .dumb_create = amdgpu_mode_dumb_create, 3016 .dumb_map_offset = amdgpu_mode_dumb_mmap, 3017 DRM_FBDEV_TTM_DRIVER_OPS, 3018 .fops = &amdgpu_driver_kms_fops, 3019 .release = &amdgpu_driver_release_kms, 3020 3021 .gem_prime_import = amdgpu_gem_prime_import, 3022 3023 .name = DRIVER_NAME, 3024 .desc = DRIVER_DESC, 3025 .date = DRIVER_DATE, 3026 .major = KMS_DRIVER_MAJOR, 3027 .minor = KMS_DRIVER_MINOR, 3028 .patchlevel = KMS_DRIVER_PATCHLEVEL, 3029 }; 3030 3031 static struct pci_error_handlers amdgpu_pci_err_handler = { 3032 .error_detected = amdgpu_pci_error_detected, 3033 .mmio_enabled = amdgpu_pci_mmio_enabled, 3034 .slot_reset = amdgpu_pci_slot_reset, 3035 .resume = amdgpu_pci_resume, 3036 }; 3037 3038 static const struct attribute_group *amdgpu_sysfs_groups[] = { 3039 &amdgpu_vram_mgr_attr_group, 3040 &amdgpu_gtt_mgr_attr_group, 3041 &amdgpu_flash_attr_group, 3042 NULL, 3043 }; 3044 3045 static struct pci_driver amdgpu_kms_pci_driver = { 3046 .name = DRIVER_NAME, 3047 .id_table = pciidlist, 3048 .probe = amdgpu_pci_probe, 3049 .remove = amdgpu_pci_remove, 3050 .shutdown = amdgpu_pci_shutdown, 3051 .driver.pm = &amdgpu_pm_ops, 3052 .err_handler = &amdgpu_pci_err_handler, 3053 .dev_groups = amdgpu_sysfs_groups, 3054 }; 3055 3056 static int __init amdgpu_init(void) 3057 { 3058 int r; 3059 3060 if (drm_firmware_drivers_only()) 3061 return -EINVAL; 3062 3063 r = amdgpu_sync_init(); 3064 if (r) 3065 goto error_sync; 3066 3067 r = amdgpu_fence_slab_init(); 3068 if (r) 3069 goto error_fence; 3070 3071 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 3072 amdgpu_register_atpx_handler(); 3073 amdgpu_acpi_detect(); 3074 3075 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 3076 amdgpu_amdkfd_init(); 3077 3078 /* let modprobe override vga console setting */ 3079 return pci_register_driver(&amdgpu_kms_pci_driver); 3080 3081 error_fence: 3082 amdgpu_sync_fini(); 3083 3084 error_sync: 3085 return r; 3086 } 3087 3088 static void __exit amdgpu_exit(void) 3089 { 3090 amdgpu_amdkfd_fini(); 3091 pci_unregister_driver(&amdgpu_kms_pci_driver); 3092 amdgpu_unregister_atpx_handler(); 3093 amdgpu_acpi_release(); 3094 amdgpu_sync_fini(); 3095 amdgpu_fence_slab_fini(); 3096 mmu_notifier_synchronize(); 3097 amdgpu_xcp_drv_release(); 3098 } 3099 3100 module_init(amdgpu_init); 3101 module_exit(amdgpu_exit); 3102 3103 MODULE_AUTHOR(DRIVER_AUTHOR); 3104 MODULE_DESCRIPTION(DRIVER_DESC); 3105 MODULE_LICENSE("GPL and additional rights"); 3106