1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/clients/drm_client_setup.h> 27 #include <drm/drm_drv.h> 28 #include <drm/drm_fbdev_ttm.h> 29 #include <drm/drm_gem.h> 30 #include <drm/drm_managed.h> 31 #include <drm/drm_pciids.h> 32 #include <drm/drm_probe_helper.h> 33 #include <drm/drm_vblank.h> 34 35 #include <linux/cc_platform.h> 36 #include <linux/dynamic_debug.h> 37 #include <linux/module.h> 38 #include <linux/mmu_notifier.h> 39 #include <linux/pm_runtime.h> 40 #include <linux/suspend.h> 41 #include <linux/vga_switcheroo.h> 42 43 #include "amdgpu.h" 44 #include "amdgpu_amdkfd.h" 45 #include "amdgpu_dma_buf.h" 46 #include "amdgpu_drv.h" 47 #include "amdgpu_fdinfo.h" 48 #include "amdgpu_irq.h" 49 #include "amdgpu_psp.h" 50 #include "amdgpu_ras.h" 51 #include "amdgpu_reset.h" 52 #include "amdgpu_sched.h" 53 #include "amdgpu_xgmi.h" 54 #include "../amdxcp/amdgpu_xcp_drv.h" 55 56 /* 57 * KMS wrapper. 58 * - 3.0.0 - initial driver 59 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 60 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 61 * at the end of IBs. 62 * - 3.3.0 - Add VM support for UVD on supported hardware. 63 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 64 * - 3.5.0 - Add support for new UVD_NO_OP register. 65 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 66 * - 3.7.0 - Add support for VCE clock list packet 67 * - 3.8.0 - Add support raster config init in the kernel 68 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 69 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 70 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 71 * - 3.12.0 - Add query for double offchip LDS buffers 72 * - 3.13.0 - Add PRT support 73 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 74 * - 3.15.0 - Export more gpu info for gfx9 75 * - 3.16.0 - Add reserved vmid support 76 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 77 * - 3.18.0 - Export gpu always on cu bitmap 78 * - 3.19.0 - Add support for UVD MJPEG decode 79 * - 3.20.0 - Add support for local BOs 80 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 81 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 82 * - 3.23.0 - Add query for VRAM lost counter 83 * - 3.24.0 - Add high priority compute support for gfx9 84 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 85 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 86 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation. 87 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 88 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 89 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 90 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 91 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 92 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 93 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 94 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 95 * - 3.36.0 - Allow reading more status registers on si/cik 96 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 97 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 98 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 99 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 100 * - 3.41.0 - Add video codec query 101 * - 3.42.0 - Add 16bpc fixed point display support 102 * - 3.43.0 - Add device hot plug/unplug support 103 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 104 * - 3.45.0 - Add context ioctl stable pstate interface 105 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm 106 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags 107 * - 3.48.0 - Add IP discovery version info to HW INFO 108 * - 3.49.0 - Add gang submit into CS IOCTL 109 * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock 110 * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock 111 * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl 112 * 3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields: 113 * tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size, 114 * gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi 115 * 3.53.0 - Support for GFX11 CP GFX shadowing 116 * 3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support 117 * - 3.55.0 - Add AMDGPU_INFO_GPUVM_FAULT query 118 * - 3.56.0 - Update IB start address and size alignment for decode and encode 119 * - 3.57.0 - Compute tunneling on GFX10+ 120 * - 3.58.0 - Add GFX12 DCC support 121 * - 3.59.0 - Cleared VRAM 122 * - 3.60.0 - Add AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE (Vulkan requirement) 123 * - 3.61.0 - Contains fix for RV/PCO compute queues 124 * - 3.62.0 - Add AMDGPU_IDS_FLAGS_MODE_PF, AMDGPU_IDS_FLAGS_MODE_VF & AMDGPU_IDS_FLAGS_MODE_PT 125 * - 3.63.0 - GFX12 display DCC supports 256B max compressed block size 126 */ 127 #define KMS_DRIVER_MAJOR 3 128 #define KMS_DRIVER_MINOR 63 129 #define KMS_DRIVER_PATCHLEVEL 0 130 131 /* 132 * amdgpu.debug module options. Are all disabled by default 133 */ 134 enum AMDGPU_DEBUG_MASK { 135 AMDGPU_DEBUG_VM = BIT(0), 136 AMDGPU_DEBUG_LARGEBAR = BIT(1), 137 AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY = BIT(2), 138 AMDGPU_DEBUG_USE_VRAM_FW_BUF = BIT(3), 139 AMDGPU_DEBUG_ENABLE_RAS_ACA = BIT(4), 140 AMDGPU_DEBUG_ENABLE_EXP_RESETS = BIT(5), 141 AMDGPU_DEBUG_DISABLE_GPU_RING_RESET = BIT(6), 142 AMDGPU_DEBUG_SMU_POOL = BIT(7), 143 }; 144 145 unsigned int amdgpu_vram_limit = UINT_MAX; 146 int amdgpu_vis_vram_limit; 147 int amdgpu_gart_size = -1; /* auto */ 148 int amdgpu_gtt_size = -1; /* auto */ 149 int amdgpu_moverate = -1; /* auto */ 150 int amdgpu_audio = -1; 151 int amdgpu_disp_priority; 152 int amdgpu_hw_i2c; 153 int amdgpu_pcie_gen2 = -1; 154 int amdgpu_msi = -1; 155 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 156 int amdgpu_dpm = -1; 157 int amdgpu_fw_load_type = -1; 158 int amdgpu_aspm = -1; 159 int amdgpu_runtime_pm = -1; 160 uint amdgpu_ip_block_mask = 0xffffffff; 161 int amdgpu_bapm = -1; 162 int amdgpu_deep_color; 163 int amdgpu_vm_size = -1; 164 int amdgpu_vm_fragment_size = -1; 165 int amdgpu_vm_block_size = -1; 166 int amdgpu_vm_fault_stop; 167 int amdgpu_vm_update_mode = -1; 168 int amdgpu_exp_hw_support; 169 int amdgpu_dc = -1; 170 int amdgpu_sched_jobs = 32; 171 int amdgpu_sched_hw_submission = 2; 172 uint amdgpu_pcie_gen_cap; 173 uint amdgpu_pcie_lane_cap; 174 u64 amdgpu_cg_mask = 0xffffffffffffffff; 175 uint amdgpu_pg_mask = 0xffffffff; 176 uint amdgpu_sdma_phase_quantum = 32; 177 char *amdgpu_disable_cu; 178 char *amdgpu_virtual_display; 179 bool enforce_isolation; 180 int amdgpu_modeset = -1; 181 182 /* Specifies the default granularity for SVM, used in buffer 183 * migration and restoration of backing memory when handling 184 * recoverable page faults. 185 * 186 * The value is given as log(numPages(buffer)); for a 2 MiB 187 * buffer it computes to be 9 188 */ 189 uint amdgpu_svm_default_granularity = 9; 190 191 /* 192 * OverDrive(bit 14) disabled by default 193 * GFX DCS(bit 19) disabled by default 194 */ 195 uint amdgpu_pp_feature_mask = 0xfff7bfff; 196 uint amdgpu_force_long_training; 197 int amdgpu_lbpw = -1; 198 int amdgpu_compute_multipipe = -1; 199 int amdgpu_gpu_recovery = -1; /* auto */ 200 int amdgpu_emu_mode; 201 uint amdgpu_smu_memory_pool_size; 202 int amdgpu_smu_pptable_id = -1; 203 /* 204 * FBC (bit 0) disabled by default 205 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 206 * - With this, for multiple monitors in sync(e.g. with the same model), 207 * mclk switching will be allowed. And the mclk will be not foced to the 208 * highest. That helps saving some idle power. 209 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 210 * PSR (bit 3) disabled by default 211 * EDP NO POWER SEQUENCING (bit 4) disabled by default 212 */ 213 uint amdgpu_dc_feature_mask = 2; 214 uint amdgpu_dc_debug_mask; 215 uint amdgpu_dc_visual_confirm; 216 int amdgpu_async_gfx_ring = 1; 217 int amdgpu_mcbp = -1; 218 int amdgpu_discovery = -1; 219 int amdgpu_mes; 220 int amdgpu_mes_log_enable = 0; 221 int amdgpu_mes_kiq; 222 int amdgpu_uni_mes = 1; 223 int amdgpu_noretry = -1; 224 int amdgpu_force_asic_type = -1; 225 int amdgpu_tmz = -1; /* auto */ 226 uint amdgpu_freesync_vid_mode; 227 int amdgpu_reset_method = -1; /* auto */ 228 int amdgpu_num_kcq = -1; 229 int amdgpu_smartshift_bias; 230 int amdgpu_use_xgmi_p2p = 1; 231 int amdgpu_vcnfw_log; 232 int amdgpu_sg_display = -1; /* auto */ 233 int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE; 234 int amdgpu_umsch_mm; 235 int amdgpu_seamless = -1; /* auto */ 236 uint amdgpu_debug_mask; 237 int amdgpu_agp = -1; /* auto */ 238 int amdgpu_wbrf = -1; 239 int amdgpu_damage_clips = -1; /* auto */ 240 int amdgpu_umsch_mm_fwlog; 241 int amdgpu_rebar = -1; /* auto */ 242 243 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 244 "DRM_UT_CORE", 245 "DRM_UT_DRIVER", 246 "DRM_UT_KMS", 247 "DRM_UT_PRIME", 248 "DRM_UT_ATOMIC", 249 "DRM_UT_VBL", 250 "DRM_UT_STATE", 251 "DRM_UT_LEASE", 252 "DRM_UT_DP", 253 "DRM_UT_DRMRES"); 254 255 struct amdgpu_mgpu_info mgpu_info = { 256 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 257 }; 258 int amdgpu_ras_enable = -1; 259 uint amdgpu_ras_mask = 0xffffffff; 260 int amdgpu_bad_page_threshold = -1; 261 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 262 .timeout_fatal_disable = false, 263 .period = 0x0, /* default to 0x0 (timeout disable) */ 264 }; 265 266 /** 267 * DOC: vramlimit (int) 268 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 269 */ 270 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 271 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 272 273 /** 274 * DOC: vis_vramlimit (int) 275 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 276 */ 277 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 278 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 279 280 /** 281 * DOC: gartsize (uint) 282 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing. 283 * The default is -1 (The size depends on asic). 284 */ 285 MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)"); 286 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 287 288 /** 289 * DOC: gttsize (int) 290 * Restrict the size of GTT domain (for userspace use) in MiB for testing. 291 * The default is -1 (Use value specified by TTM). 292 * This parameter is deprecated and will be removed in the future. 293 */ 294 MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)"); 295 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 296 297 /** 298 * DOC: moverate (int) 299 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 300 */ 301 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 302 module_param_named(moverate, amdgpu_moverate, int, 0600); 303 304 /** 305 * DOC: audio (int) 306 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 307 */ 308 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 309 module_param_named(audio, amdgpu_audio, int, 0444); 310 311 /** 312 * DOC: disp_priority (int) 313 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 314 */ 315 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 316 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 317 318 /** 319 * DOC: hw_i2c (int) 320 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 321 */ 322 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 323 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 324 325 /** 326 * DOC: pcie_gen2 (int) 327 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 328 */ 329 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 330 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 331 332 /** 333 * DOC: msi (int) 334 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 335 */ 336 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 337 module_param_named(msi, amdgpu_msi, int, 0444); 338 339 /** 340 * DOC: svm_default_granularity (uint) 341 * Used in buffer migration and handling of recoverable page faults 342 */ 343 MODULE_PARM_DESC(svm_default_granularity, "SVM's default granularity in log(2^Pages), default 9 = 2^9 = 2 MiB"); 344 module_param_named(svm_default_granularity, amdgpu_svm_default_granularity, uint, 0644); 345 346 /** 347 * DOC: lockup_timeout (string) 348 * Set GPU scheduler timeout value in ms. 349 * 350 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 351 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 352 * to the default timeout. 353 * 354 * - With one value specified, the setting will apply to all non-compute jobs. 355 * - With multiple values specified, the first one will be for GFX. 356 * The second one is for Compute. The third and fourth ones are 357 * for SDMA and Video. 358 * 359 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 360 * jobs is 10000. The timeout for compute is 60000. 361 */ 362 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 363 "for passthrough or sriov, 10000 for all jobs. 0: keep default value. negative: infinity timeout), format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 364 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 365 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 366 367 /** 368 * DOC: dpm (int) 369 * Override for dynamic power management setting 370 * (0 = disable, 1 = enable) 371 * The default is -1 (auto). 372 */ 373 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 374 module_param_named(dpm, amdgpu_dpm, int, 0444); 375 376 /** 377 * DOC: fw_load_type (int) 378 * Set different firmware loading type for debugging, if supported. 379 * Set to 0 to force direct loading if supported by the ASIC. Set 380 * to -1 to select the default loading mode for the ASIC, as defined 381 * by the driver. The default is -1 (auto). 382 */ 383 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); 384 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 385 386 /** 387 * DOC: aspm (int) 388 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 389 */ 390 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 391 module_param_named(aspm, amdgpu_aspm, int, 0444); 392 393 /** 394 * DOC: runpm (int) 395 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 396 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 397 * Setting the value to 0 disables this functionality. 398 * Setting the value to -2 is auto enabled with power down when displays are attached. 399 */ 400 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto, -2 = auto with displays)"); 401 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 402 403 /** 404 * DOC: ip_block_mask (uint) 405 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 406 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 407 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 408 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 409 */ 410 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 411 module_param_named_unsafe(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 412 413 /** 414 * DOC: bapm (int) 415 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 416 * The default -1 (auto, enabled) 417 */ 418 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 419 module_param_named(bapm, amdgpu_bapm, int, 0444); 420 421 /** 422 * DOC: deep_color (int) 423 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 424 */ 425 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 426 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 427 428 /** 429 * DOC: vm_size (int) 430 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 431 */ 432 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 433 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 434 435 /** 436 * DOC: vm_fragment_size (int) 437 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 438 */ 439 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 440 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 441 442 /** 443 * DOC: vm_block_size (int) 444 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 445 */ 446 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 447 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 448 449 /** 450 * DOC: vm_fault_stop (int) 451 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 452 */ 453 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 454 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 455 456 /** 457 * DOC: vm_update_mode (int) 458 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 459 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 460 */ 461 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 462 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 463 464 /** 465 * DOC: exp_hw_support (int) 466 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 467 */ 468 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 469 module_param_named_unsafe(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 470 471 /** 472 * DOC: dc (int) 473 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 474 */ 475 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 476 module_param_named(dc, amdgpu_dc, int, 0444); 477 478 /** 479 * DOC: sched_jobs (int) 480 * Override the max number of jobs supported in the sw queue. The default is 32. 481 */ 482 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 483 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 484 485 /** 486 * DOC: sched_hw_submission (int) 487 * Override the max number of HW submissions. The default is 2. 488 */ 489 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 490 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 491 492 /** 493 * DOC: ppfeaturemask (hexint) 494 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 495 * The default is the current set of stable power features. 496 */ 497 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 498 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 499 500 /** 501 * DOC: forcelongtraining (uint) 502 * Force long memory training in resume. 503 * The default is zero, indicates short training in resume. 504 */ 505 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 506 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 507 508 /** 509 * DOC: pcie_gen_cap (uint) 510 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 511 * The default is 0 (automatic for each asic). 512 */ 513 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 514 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 515 516 /** 517 * DOC: pcie_lane_cap (uint) 518 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 519 * The default is 0 (automatic for each asic). 520 */ 521 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 522 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 523 524 /** 525 * DOC: cg_mask (ullong) 526 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 527 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 528 */ 529 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 530 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 531 532 /** 533 * DOC: pg_mask (uint) 534 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 535 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 536 */ 537 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 538 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 539 540 /** 541 * DOC: sdma_phase_quantum (uint) 542 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 543 */ 544 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 545 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 546 547 /** 548 * DOC: disable_cu (charp) 549 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 550 */ 551 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 552 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 553 554 /** 555 * DOC: virtual_display (charp) 556 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 557 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 558 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 559 * device at 26:00.0. The default is NULL. 560 */ 561 MODULE_PARM_DESC(virtual_display, 562 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 563 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 564 565 /** 566 * DOC: lbpw (int) 567 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 568 */ 569 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 570 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 571 572 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 573 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 574 575 /** 576 * DOC: gpu_recovery (int) 577 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 578 */ 579 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 580 module_param_named_unsafe(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 581 582 /** 583 * DOC: emu_mode (int) 584 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 585 */ 586 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 587 module_param_named_unsafe(emu_mode, amdgpu_emu_mode, int, 0444); 588 589 /** 590 * DOC: ras_enable (int) 591 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 592 */ 593 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 594 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 595 596 /** 597 * DOC: ras_mask (uint) 598 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 599 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 600 */ 601 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 602 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 603 604 /** 605 * DOC: timeout_fatal_disable (bool) 606 * Disable Watchdog timeout fatal error event 607 */ 608 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 609 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 610 611 /** 612 * DOC: timeout_period (uint) 613 * Modify the watchdog timeout max_cycles as (1 << period) 614 */ 615 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 616 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 617 618 /** 619 * DOC: si_support (int) 620 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 621 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 622 * otherwise using amdgpu driver. 623 */ 624 #ifdef CONFIG_DRM_AMDGPU_SI 625 626 #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) 627 int amdgpu_si_support; 628 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 629 #else 630 int amdgpu_si_support = 1; 631 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 632 #endif 633 634 module_param_named(si_support, amdgpu_si_support, int, 0444); 635 #endif 636 637 /** 638 * DOC: cik_support (int) 639 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 640 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 641 * otherwise using amdgpu driver. 642 */ 643 #ifdef CONFIG_DRM_AMDGPU_CIK 644 645 #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) 646 int amdgpu_cik_support; 647 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 648 #else 649 int amdgpu_cik_support = 1; 650 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 651 #endif 652 653 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 654 #endif 655 656 /** 657 * DOC: smu_memory_pool_size (uint) 658 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 659 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 660 */ 661 MODULE_PARM_DESC(smu_memory_pool_size, 662 "reserve gtt for smu debug usage, 0 = disable,0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 663 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 664 665 /** 666 * DOC: async_gfx_ring (int) 667 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 668 */ 669 MODULE_PARM_DESC(async_gfx_ring, 670 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 671 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 672 673 /** 674 * DOC: mcbp (int) 675 * It is used to enable mid command buffer preemption. (0 = disabled, 1 = enabled, -1 auto (default)) 676 */ 677 MODULE_PARM_DESC(mcbp, 678 "Enable Mid-command buffer preemption (0 = disabled, 1 = enabled), -1 = auto (default)"); 679 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 680 681 /** 682 * DOC: discovery (int) 683 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 684 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 685 */ 686 MODULE_PARM_DESC(discovery, 687 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 688 module_param_named(discovery, amdgpu_discovery, int, 0444); 689 690 /** 691 * DOC: mes (int) 692 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 693 * (0 = disabled (default), 1 = enabled) 694 */ 695 MODULE_PARM_DESC(mes, 696 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 697 module_param_named(mes, amdgpu_mes, int, 0444); 698 699 /** 700 * DOC: mes_log_enable (int) 701 * Enable Micro Engine Scheduler log. This is used to enable/disable MES internal log. 702 * (0 = disabled (default), 1 = enabled) 703 */ 704 MODULE_PARM_DESC(mes_log_enable, 705 "Enable Micro Engine Scheduler log (0 = disabled (default), 1 = enabled)"); 706 module_param_named(mes_log_enable, amdgpu_mes_log_enable, int, 0444); 707 708 /** 709 * DOC: mes_kiq (int) 710 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq. 711 * (0 = disabled (default), 1 = enabled) 712 */ 713 MODULE_PARM_DESC(mes_kiq, 714 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)"); 715 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444); 716 717 /** 718 * DOC: uni_mes (int) 719 * Enable Unified Micro Engine Scheduler. This is a new engine pipe for unified scheduler. 720 * (0 = disabled (default), 1 = enabled) 721 */ 722 MODULE_PARM_DESC(uni_mes, 723 "Enable Unified Micro Engine Scheduler (0 = disabled, 1 = enabled(default)"); 724 module_param_named(uni_mes, amdgpu_uni_mes, int, 0444); 725 726 /** 727 * DOC: noretry (int) 728 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 729 * do not support per-process XNACK this also disables retry page faults. 730 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 731 */ 732 MODULE_PARM_DESC(noretry, 733 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 734 module_param_named(noretry, amdgpu_noretry, int, 0644); 735 736 /** 737 * DOC: force_asic_type (int) 738 * A non negative value used to specify the asic type for all supported GPUs. 739 */ 740 MODULE_PARM_DESC(force_asic_type, 741 "A non negative value used to specify the asic type for all supported GPUs"); 742 module_param_named_unsafe(force_asic_type, amdgpu_force_asic_type, int, 0444); 743 744 /** 745 * DOC: use_xgmi_p2p (int) 746 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 747 */ 748 MODULE_PARM_DESC(use_xgmi_p2p, 749 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 750 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 751 752 753 #ifdef CONFIG_HSA_AMD 754 /** 755 * DOC: sched_policy (int) 756 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 757 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 758 * assigns queues to HQDs. 759 */ 760 int sched_policy = KFD_SCHED_POLICY_HWS; 761 module_param_unsafe(sched_policy, int, 0444); 762 MODULE_PARM_DESC(sched_policy, 763 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 764 765 /** 766 * DOC: hws_max_conc_proc (int) 767 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 768 * number of VMIDs assigned to the HWS, which is also the default. 769 */ 770 int hws_max_conc_proc = -1; 771 module_param(hws_max_conc_proc, int, 0444); 772 MODULE_PARM_DESC(hws_max_conc_proc, 773 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 774 775 /** 776 * DOC: cwsr_enable (int) 777 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 778 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 779 * disables it. 780 */ 781 int cwsr_enable = 1; 782 module_param(cwsr_enable, int, 0444); 783 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 784 785 /** 786 * DOC: max_num_of_queues_per_device (int) 787 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 788 * is 4096. 789 */ 790 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 791 module_param(max_num_of_queues_per_device, int, 0444); 792 MODULE_PARM_DESC(max_num_of_queues_per_device, 793 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 794 795 /** 796 * DOC: send_sigterm (int) 797 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 798 * but just print errors on dmesg. Setting 1 enables sending sigterm. 799 */ 800 int send_sigterm; 801 module_param(send_sigterm, int, 0444); 802 MODULE_PARM_DESC(send_sigterm, 803 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 804 805 /** 806 * DOC: halt_if_hws_hang (int) 807 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 808 * Setting 1 enables halt on hang. 809 */ 810 int halt_if_hws_hang; 811 module_param_unsafe(halt_if_hws_hang, int, 0644); 812 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 813 814 /** 815 * DOC: hws_gws_support(bool) 816 * Assume that HWS supports GWS barriers regardless of what firmware version 817 * check says. Default value: false (rely on MEC2 firmware version check). 818 */ 819 bool hws_gws_support; 820 module_param_unsafe(hws_gws_support, bool, 0444); 821 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 822 823 /** 824 * DOC: queue_preemption_timeout_ms (int) 825 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 826 */ 827 int queue_preemption_timeout_ms = 9000; 828 module_param(queue_preemption_timeout_ms, int, 0644); 829 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 830 831 /** 832 * DOC: debug_evictions(bool) 833 * Enable extra debug messages to help determine the cause of evictions 834 */ 835 bool debug_evictions; 836 module_param(debug_evictions, bool, 0644); 837 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 838 839 /** 840 * DOC: no_system_mem_limit(bool) 841 * Disable system memory limit, to support multiple process shared memory 842 */ 843 bool no_system_mem_limit; 844 module_param(no_system_mem_limit, bool, 0644); 845 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 846 847 /** 848 * DOC: no_queue_eviction_on_vm_fault (int) 849 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 850 */ 851 int amdgpu_no_queue_eviction_on_vm_fault; 852 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 853 module_param_named_unsafe(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 854 #endif 855 856 /** 857 * DOC: mtype_local (int) 858 */ 859 int amdgpu_mtype_local; 860 MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (0 = MTYPE_RW (default), 1 = MTYPE_NC, 2 = MTYPE_CC)"); 861 module_param_named_unsafe(mtype_local, amdgpu_mtype_local, int, 0444); 862 863 /** 864 * DOC: pcie_p2p (bool) 865 * Enable PCIe P2P (requires large-BAR). Default value: true (on) 866 */ 867 #ifdef CONFIG_HSA_AMD_P2P 868 bool pcie_p2p = true; 869 module_param(pcie_p2p, bool, 0444); 870 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); 871 #endif 872 873 /** 874 * DOC: dcfeaturemask (uint) 875 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 876 * The default is the current set of stable display features. 877 */ 878 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 879 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 880 881 /** 882 * DOC: dcdebugmask (uint) 883 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 884 */ 885 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 886 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 887 888 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)"); 889 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444); 890 891 /** 892 * DOC: abmlevel (uint) 893 * Override the default ABM (Adaptive Backlight Management) level used for DC 894 * enabled hardware. Requires DMCU to be supported and loaded. 895 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 896 * default. Values 1-4 control the maximum allowable brightness reduction via 897 * the ABM algorithm, with 1 being the least reduction and 4 being the most 898 * reduction. 899 * 900 * Defaults to -1, or auto. Userspace can only override this level after 901 * boot if it's set to auto. 902 */ 903 int amdgpu_dm_abm_level = -1; 904 MODULE_PARM_DESC(abmlevel, 905 "ABM level (0 = off, 1-4 = backlight reduction level, -1 auto (default))"); 906 module_param_named(abmlevel, amdgpu_dm_abm_level, int, 0444); 907 908 int amdgpu_backlight = -1; 909 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 910 module_param_named(backlight, amdgpu_backlight, bint, 0444); 911 912 /** 913 * DOC: damageclips (int) 914 * Enable or disable damage clips support. If damage clips support is disabled, 915 * we will force full frame updates, irrespective of what user space sends to 916 * us. 917 * 918 * Defaults to -1 (where it is enabled unless a PSR-SU display is detected). 919 */ 920 MODULE_PARM_DESC(damageclips, 921 "Damage clips support (0 = disable, 1 = enable, -1 auto (default))"); 922 module_param_named(damageclips, amdgpu_damage_clips, int, 0444); 923 924 /** 925 * DOC: tmz (int) 926 * Trusted Memory Zone (TMZ) is a method to protect data being written 927 * to or read from memory. 928 * 929 * The default value: 0 (off). TODO: change to auto till it is completed. 930 */ 931 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 932 module_param_named(tmz, amdgpu_tmz, int, 0444); 933 934 /** 935 * DOC: freesync_video (uint) 936 * Enable the optimization to adjust front porch timing to achieve seamless 937 * mode change experience when setting a freesync supported mode for which full 938 * modeset is not needed. 939 * 940 * The Display Core will add a set of modes derived from the base FreeSync 941 * video mode into the corresponding connector's mode list based on commonly 942 * used refresh rates and VRR range of the connected display, when users enable 943 * this feature. From the userspace perspective, they can see a seamless mode 944 * change experience when the change between different refresh rates under the 945 * same resolution. Additionally, userspace applications such as Video playback 946 * can read this modeset list and change the refresh rate based on the video 947 * frame rate. Finally, the userspace can also derive an appropriate mode for a 948 * particular refresh rate based on the FreeSync Mode and add it to the 949 * connector's mode list. 950 * 951 * Note: This is an experimental feature. 952 * 953 * The default value: 0 (off). 954 */ 955 MODULE_PARM_DESC( 956 freesync_video, 957 "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)"); 958 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); 959 960 /** 961 * DOC: reset_method (int) 962 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 963 */ 964 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 965 module_param_named_unsafe(reset_method, amdgpu_reset_method, int, 0644); 966 967 /** 968 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 969 * threshold value of faulty pages detected by RAS ECC, which may 970 * result in the GPU entering bad status when the number of total 971 * faulty pages by ECC exceeds the threshold value. 972 */ 973 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = threshold determined by a formula, 0 < threshold < max records, user-defined threshold)"); 974 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 975 976 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 977 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 978 979 /** 980 * DOC: vcnfw_log (int) 981 * Enable vcnfw log output for debugging, the default is disabled. 982 */ 983 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 984 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 985 986 /** 987 * DOC: sg_display (int) 988 * Disable S/G (scatter/gather) display (i.e., display from system memory). 989 * This option is only relevant on APUs. Set this option to 0 to disable 990 * S/G display if you experience flickering or other issues under memory 991 * pressure and report the issue. 992 */ 993 MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)"); 994 module_param_named(sg_display, amdgpu_sg_display, int, 0444); 995 996 /** 997 * DOC: umsch_mm (int) 998 * Enable Multi Media User Mode Scheduler. This is a HW scheduling engine for VCN and VPE. 999 * (0 = disabled (default), 1 = enabled) 1000 */ 1001 MODULE_PARM_DESC(umsch_mm, 1002 "Enable Multi Media User Mode Scheduler (0 = disabled (default), 1 = enabled)"); 1003 module_param_named(umsch_mm, amdgpu_umsch_mm, int, 0444); 1004 1005 /** 1006 * DOC: umsch_mm_fwlog (int) 1007 * Enable umschfw log output for debugging, the default is disabled. 1008 */ 1009 MODULE_PARM_DESC(umsch_mm_fwlog, "Enable umschfw log(0 = disable (default value), 1 = enable)"); 1010 module_param_named(umsch_mm_fwlog, amdgpu_umsch_mm_fwlog, int, 0444); 1011 1012 /** 1013 * DOC: smu_pptable_id (int) 1014 * Used to override pptable id. id = 0 use VBIOS pptable. 1015 * id > 0 use the soft pptable with specicfied id. 1016 */ 1017 MODULE_PARM_DESC(smu_pptable_id, 1018 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 1019 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 1020 1021 /** 1022 * DOC: partition_mode (int) 1023 * Used to override the default SPX mode. 1024 */ 1025 MODULE_PARM_DESC( 1026 user_partt_mode, 1027 "specify partition mode to be used (-2 = AMDGPU_AUTO_COMPUTE_PARTITION_MODE(default value) \ 1028 0 = AMDGPU_SPX_PARTITION_MODE, \ 1029 1 = AMDGPU_DPX_PARTITION_MODE, \ 1030 2 = AMDGPU_TPX_PARTITION_MODE, \ 1031 3 = AMDGPU_QPX_PARTITION_MODE, \ 1032 4 = AMDGPU_CPX_PARTITION_MODE)"); 1033 module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint, 0444); 1034 1035 1036 /** 1037 * DOC: enforce_isolation (bool) 1038 * enforce process isolation between graphics and compute via using the same reserved vmid. 1039 */ 1040 module_param(enforce_isolation, bool, 0444); 1041 MODULE_PARM_DESC(enforce_isolation, "enforce process isolation between graphics and compute . enforce_isolation = on"); 1042 1043 /** 1044 * DOC: modeset (int) 1045 * Override nomodeset (1 = override, -1 = auto). The default is -1 (auto). 1046 */ 1047 MODULE_PARM_DESC(modeset, "Override nomodeset (1 = enable, -1 = auto)"); 1048 module_param_named(modeset, amdgpu_modeset, int, 0444); 1049 1050 /** 1051 * DOC: seamless (int) 1052 * Seamless boot will keep the image on the screen during the boot process. 1053 */ 1054 MODULE_PARM_DESC(seamless, "Seamless boot (-1 = auto (default), 0 = disable, 1 = enable)"); 1055 module_param_named(seamless, amdgpu_seamless, int, 0444); 1056 1057 /** 1058 * DOC: debug_mask (uint) 1059 * Debug options for amdgpu, work as a binary mask with the following options: 1060 * 1061 * - 0x1: Debug VM handling 1062 * - 0x2: Enable simulating large-bar capability on non-large bar system. This 1063 * limits the VRAM size reported to ROCm applications to the visible 1064 * size, usually 256MB. 1065 * - 0x4: Disable GPU soft recovery, always do a full reset 1066 * - 0x8: Use VRAM for firmware loading 1067 * - 0x10: Enable ACA based RAS logging 1068 * - 0x20: Enable experimental resets 1069 * - 0x40: Disable ring resets 1070 * - 0x80: Use VRAM for SMU pool 1071 */ 1072 MODULE_PARM_DESC(debug_mask, "debug options for amdgpu, disabled by default"); 1073 module_param_named_unsafe(debug_mask, amdgpu_debug_mask, uint, 0444); 1074 1075 /** 1076 * DOC: agp (int) 1077 * Enable the AGP aperture. This provides an aperture in the GPU's internal 1078 * address space for direct access to system memory. Note that these accesses 1079 * are non-snooped, so they are only used for access to uncached memory. 1080 */ 1081 MODULE_PARM_DESC(agp, "AGP (-1 = auto (default), 0 = disable, 1 = enable)"); 1082 module_param_named(agp, amdgpu_agp, int, 0444); 1083 1084 /** 1085 * DOC: wbrf (int) 1086 * Enable Wifi RFI interference mitigation feature. 1087 * Due to electrical and mechanical constraints there may be likely interference of 1088 * relatively high-powered harmonics of the (G-)DDR memory clocks with local radio 1089 * module frequency bands used by Wifi 6/6e/7. To mitigate the possible RFI interference, 1090 * with this feature enabled, PMFW will use either “shadowed P-State” or “P-State” based 1091 * on active list of frequencies in-use (to be avoided) as part of initial setting or 1092 * P-state transition. However, there may be potential performance impact with this 1093 * feature enabled. 1094 * (0 = disabled, 1 = enabled, -1 = auto (default setting, will be enabled if supported)) 1095 */ 1096 MODULE_PARM_DESC(wbrf, 1097 "Enable Wifi RFI interference mitigation (0 = disabled, 1 = enabled, -1 = auto(default)"); 1098 module_param_named(wbrf, amdgpu_wbrf, int, 0444); 1099 1100 /** 1101 * DOC: rebar (int) 1102 * Allow BAR resizing. Disable this to prevent the driver from attempting 1103 * to resize the BAR if the GPU supports it and there is available MMIO space. 1104 * Note that this just prevents the driver from resizing the BAR. The BIOS 1105 * may have already resized the BAR at boot time. 1106 */ 1107 MODULE_PARM_DESC(rebar, "Resizable BAR (-1 = auto (default), 0 = disable, 1 = enable)"); 1108 module_param_named(rebar, amdgpu_rebar, int, 0444); 1109 1110 /* These devices are not supported by amdgpu. 1111 * They are supported by the mach64, r128, radeon drivers 1112 */ 1113 static const u16 amdgpu_unsupported_pciidlist[] = { 1114 /* mach64 */ 1115 0x4354, 1116 0x4358, 1117 0x4554, 1118 0x4742, 1119 0x4744, 1120 0x4749, 1121 0x474C, 1122 0x474D, 1123 0x474E, 1124 0x474F, 1125 0x4750, 1126 0x4751, 1127 0x4752, 1128 0x4753, 1129 0x4754, 1130 0x4755, 1131 0x4756, 1132 0x4757, 1133 0x4758, 1134 0x4759, 1135 0x475A, 1136 0x4C42, 1137 0x4C44, 1138 0x4C47, 1139 0x4C49, 1140 0x4C4D, 1141 0x4C4E, 1142 0x4C50, 1143 0x4C51, 1144 0x4C52, 1145 0x4C53, 1146 0x5654, 1147 0x5655, 1148 0x5656, 1149 /* r128 */ 1150 0x4c45, 1151 0x4c46, 1152 0x4d46, 1153 0x4d4c, 1154 0x5041, 1155 0x5042, 1156 0x5043, 1157 0x5044, 1158 0x5045, 1159 0x5046, 1160 0x5047, 1161 0x5048, 1162 0x5049, 1163 0x504A, 1164 0x504B, 1165 0x504C, 1166 0x504D, 1167 0x504E, 1168 0x504F, 1169 0x5050, 1170 0x5051, 1171 0x5052, 1172 0x5053, 1173 0x5054, 1174 0x5055, 1175 0x5056, 1176 0x5057, 1177 0x5058, 1178 0x5245, 1179 0x5246, 1180 0x5247, 1181 0x524b, 1182 0x524c, 1183 0x534d, 1184 0x5446, 1185 0x544C, 1186 0x5452, 1187 /* radeon */ 1188 0x3150, 1189 0x3151, 1190 0x3152, 1191 0x3154, 1192 0x3155, 1193 0x3E50, 1194 0x3E54, 1195 0x4136, 1196 0x4137, 1197 0x4144, 1198 0x4145, 1199 0x4146, 1200 0x4147, 1201 0x4148, 1202 0x4149, 1203 0x414A, 1204 0x414B, 1205 0x4150, 1206 0x4151, 1207 0x4152, 1208 0x4153, 1209 0x4154, 1210 0x4155, 1211 0x4156, 1212 0x4237, 1213 0x4242, 1214 0x4336, 1215 0x4337, 1216 0x4437, 1217 0x4966, 1218 0x4967, 1219 0x4A48, 1220 0x4A49, 1221 0x4A4A, 1222 0x4A4B, 1223 0x4A4C, 1224 0x4A4D, 1225 0x4A4E, 1226 0x4A4F, 1227 0x4A50, 1228 0x4A54, 1229 0x4B48, 1230 0x4B49, 1231 0x4B4A, 1232 0x4B4B, 1233 0x4B4C, 1234 0x4C57, 1235 0x4C58, 1236 0x4C59, 1237 0x4C5A, 1238 0x4C64, 1239 0x4C66, 1240 0x4C67, 1241 0x4E44, 1242 0x4E45, 1243 0x4E46, 1244 0x4E47, 1245 0x4E48, 1246 0x4E49, 1247 0x4E4A, 1248 0x4E4B, 1249 0x4E50, 1250 0x4E51, 1251 0x4E52, 1252 0x4E53, 1253 0x4E54, 1254 0x4E56, 1255 0x5144, 1256 0x5145, 1257 0x5146, 1258 0x5147, 1259 0x5148, 1260 0x514C, 1261 0x514D, 1262 0x5157, 1263 0x5158, 1264 0x5159, 1265 0x515A, 1266 0x515E, 1267 0x5460, 1268 0x5462, 1269 0x5464, 1270 0x5548, 1271 0x5549, 1272 0x554A, 1273 0x554B, 1274 0x554C, 1275 0x554D, 1276 0x554E, 1277 0x554F, 1278 0x5550, 1279 0x5551, 1280 0x5552, 1281 0x5554, 1282 0x564A, 1283 0x564B, 1284 0x564F, 1285 0x5652, 1286 0x5653, 1287 0x5657, 1288 0x5834, 1289 0x5835, 1290 0x5954, 1291 0x5955, 1292 0x5974, 1293 0x5975, 1294 0x5960, 1295 0x5961, 1296 0x5962, 1297 0x5964, 1298 0x5965, 1299 0x5969, 1300 0x5a41, 1301 0x5a42, 1302 0x5a61, 1303 0x5a62, 1304 0x5b60, 1305 0x5b62, 1306 0x5b63, 1307 0x5b64, 1308 0x5b65, 1309 0x5c61, 1310 0x5c63, 1311 0x5d48, 1312 0x5d49, 1313 0x5d4a, 1314 0x5d4c, 1315 0x5d4d, 1316 0x5d4e, 1317 0x5d4f, 1318 0x5d50, 1319 0x5d52, 1320 0x5d57, 1321 0x5e48, 1322 0x5e4a, 1323 0x5e4b, 1324 0x5e4c, 1325 0x5e4d, 1326 0x5e4f, 1327 0x6700, 1328 0x6701, 1329 0x6702, 1330 0x6703, 1331 0x6704, 1332 0x6705, 1333 0x6706, 1334 0x6707, 1335 0x6708, 1336 0x6709, 1337 0x6718, 1338 0x6719, 1339 0x671c, 1340 0x671d, 1341 0x671f, 1342 0x6720, 1343 0x6721, 1344 0x6722, 1345 0x6723, 1346 0x6724, 1347 0x6725, 1348 0x6726, 1349 0x6727, 1350 0x6728, 1351 0x6729, 1352 0x6738, 1353 0x6739, 1354 0x673e, 1355 0x6740, 1356 0x6741, 1357 0x6742, 1358 0x6743, 1359 0x6744, 1360 0x6745, 1361 0x6746, 1362 0x6747, 1363 0x6748, 1364 0x6749, 1365 0x674A, 1366 0x6750, 1367 0x6751, 1368 0x6758, 1369 0x6759, 1370 0x675B, 1371 0x675D, 1372 0x675F, 1373 0x6760, 1374 0x6761, 1375 0x6762, 1376 0x6763, 1377 0x6764, 1378 0x6765, 1379 0x6766, 1380 0x6767, 1381 0x6768, 1382 0x6770, 1383 0x6771, 1384 0x6772, 1385 0x6778, 1386 0x6779, 1387 0x677B, 1388 0x6840, 1389 0x6841, 1390 0x6842, 1391 0x6843, 1392 0x6849, 1393 0x684C, 1394 0x6850, 1395 0x6858, 1396 0x6859, 1397 0x6880, 1398 0x6888, 1399 0x6889, 1400 0x688A, 1401 0x688C, 1402 0x688D, 1403 0x6898, 1404 0x6899, 1405 0x689b, 1406 0x689c, 1407 0x689d, 1408 0x689e, 1409 0x68a0, 1410 0x68a1, 1411 0x68a8, 1412 0x68a9, 1413 0x68b0, 1414 0x68b8, 1415 0x68b9, 1416 0x68ba, 1417 0x68be, 1418 0x68bf, 1419 0x68c0, 1420 0x68c1, 1421 0x68c7, 1422 0x68c8, 1423 0x68c9, 1424 0x68d8, 1425 0x68d9, 1426 0x68da, 1427 0x68de, 1428 0x68e0, 1429 0x68e1, 1430 0x68e4, 1431 0x68e5, 1432 0x68e8, 1433 0x68e9, 1434 0x68f1, 1435 0x68f2, 1436 0x68f8, 1437 0x68f9, 1438 0x68fa, 1439 0x68fe, 1440 0x7100, 1441 0x7101, 1442 0x7102, 1443 0x7103, 1444 0x7104, 1445 0x7105, 1446 0x7106, 1447 0x7108, 1448 0x7109, 1449 0x710A, 1450 0x710B, 1451 0x710C, 1452 0x710E, 1453 0x710F, 1454 0x7140, 1455 0x7141, 1456 0x7142, 1457 0x7143, 1458 0x7144, 1459 0x7145, 1460 0x7146, 1461 0x7147, 1462 0x7149, 1463 0x714A, 1464 0x714B, 1465 0x714C, 1466 0x714D, 1467 0x714E, 1468 0x714F, 1469 0x7151, 1470 0x7152, 1471 0x7153, 1472 0x715E, 1473 0x715F, 1474 0x7180, 1475 0x7181, 1476 0x7183, 1477 0x7186, 1478 0x7187, 1479 0x7188, 1480 0x718A, 1481 0x718B, 1482 0x718C, 1483 0x718D, 1484 0x718F, 1485 0x7193, 1486 0x7196, 1487 0x719B, 1488 0x719F, 1489 0x71C0, 1490 0x71C1, 1491 0x71C2, 1492 0x71C3, 1493 0x71C4, 1494 0x71C5, 1495 0x71C6, 1496 0x71C7, 1497 0x71CD, 1498 0x71CE, 1499 0x71D2, 1500 0x71D4, 1501 0x71D5, 1502 0x71D6, 1503 0x71DA, 1504 0x71DE, 1505 0x7200, 1506 0x7210, 1507 0x7211, 1508 0x7240, 1509 0x7243, 1510 0x7244, 1511 0x7245, 1512 0x7246, 1513 0x7247, 1514 0x7248, 1515 0x7249, 1516 0x724A, 1517 0x724B, 1518 0x724C, 1519 0x724D, 1520 0x724E, 1521 0x724F, 1522 0x7280, 1523 0x7281, 1524 0x7283, 1525 0x7284, 1526 0x7287, 1527 0x7288, 1528 0x7289, 1529 0x728B, 1530 0x728C, 1531 0x7290, 1532 0x7291, 1533 0x7293, 1534 0x7297, 1535 0x7834, 1536 0x7835, 1537 0x791e, 1538 0x791f, 1539 0x793f, 1540 0x7941, 1541 0x7942, 1542 0x796c, 1543 0x796d, 1544 0x796e, 1545 0x796f, 1546 0x9400, 1547 0x9401, 1548 0x9402, 1549 0x9403, 1550 0x9405, 1551 0x940A, 1552 0x940B, 1553 0x940F, 1554 0x94A0, 1555 0x94A1, 1556 0x94A3, 1557 0x94B1, 1558 0x94B3, 1559 0x94B4, 1560 0x94B5, 1561 0x94B9, 1562 0x9440, 1563 0x9441, 1564 0x9442, 1565 0x9443, 1566 0x9444, 1567 0x9446, 1568 0x944A, 1569 0x944B, 1570 0x944C, 1571 0x944E, 1572 0x9450, 1573 0x9452, 1574 0x9456, 1575 0x945A, 1576 0x945B, 1577 0x945E, 1578 0x9460, 1579 0x9462, 1580 0x946A, 1581 0x946B, 1582 0x947A, 1583 0x947B, 1584 0x9480, 1585 0x9487, 1586 0x9488, 1587 0x9489, 1588 0x948A, 1589 0x948F, 1590 0x9490, 1591 0x9491, 1592 0x9495, 1593 0x9498, 1594 0x949C, 1595 0x949E, 1596 0x949F, 1597 0x94C0, 1598 0x94C1, 1599 0x94C3, 1600 0x94C4, 1601 0x94C5, 1602 0x94C6, 1603 0x94C7, 1604 0x94C8, 1605 0x94C9, 1606 0x94CB, 1607 0x94CC, 1608 0x94CD, 1609 0x9500, 1610 0x9501, 1611 0x9504, 1612 0x9505, 1613 0x9506, 1614 0x9507, 1615 0x9508, 1616 0x9509, 1617 0x950F, 1618 0x9511, 1619 0x9515, 1620 0x9517, 1621 0x9519, 1622 0x9540, 1623 0x9541, 1624 0x9542, 1625 0x954E, 1626 0x954F, 1627 0x9552, 1628 0x9553, 1629 0x9555, 1630 0x9557, 1631 0x955f, 1632 0x9580, 1633 0x9581, 1634 0x9583, 1635 0x9586, 1636 0x9587, 1637 0x9588, 1638 0x9589, 1639 0x958A, 1640 0x958B, 1641 0x958C, 1642 0x958D, 1643 0x958E, 1644 0x958F, 1645 0x9590, 1646 0x9591, 1647 0x9593, 1648 0x9595, 1649 0x9596, 1650 0x9597, 1651 0x9598, 1652 0x9599, 1653 0x959B, 1654 0x95C0, 1655 0x95C2, 1656 0x95C4, 1657 0x95C5, 1658 0x95C6, 1659 0x95C7, 1660 0x95C9, 1661 0x95CC, 1662 0x95CD, 1663 0x95CE, 1664 0x95CF, 1665 0x9610, 1666 0x9611, 1667 0x9612, 1668 0x9613, 1669 0x9614, 1670 0x9615, 1671 0x9616, 1672 0x9640, 1673 0x9641, 1674 0x9642, 1675 0x9643, 1676 0x9644, 1677 0x9645, 1678 0x9647, 1679 0x9648, 1680 0x9649, 1681 0x964a, 1682 0x964b, 1683 0x964c, 1684 0x964e, 1685 0x964f, 1686 0x9710, 1687 0x9711, 1688 0x9712, 1689 0x9713, 1690 0x9714, 1691 0x9715, 1692 0x9802, 1693 0x9803, 1694 0x9804, 1695 0x9805, 1696 0x9806, 1697 0x9807, 1698 0x9808, 1699 0x9809, 1700 0x980A, 1701 0x9900, 1702 0x9901, 1703 0x9903, 1704 0x9904, 1705 0x9905, 1706 0x9906, 1707 0x9907, 1708 0x9908, 1709 0x9909, 1710 0x990A, 1711 0x990B, 1712 0x990C, 1713 0x990D, 1714 0x990E, 1715 0x990F, 1716 0x9910, 1717 0x9913, 1718 0x9917, 1719 0x9918, 1720 0x9919, 1721 0x9990, 1722 0x9991, 1723 0x9992, 1724 0x9993, 1725 0x9994, 1726 0x9995, 1727 0x9996, 1728 0x9997, 1729 0x9998, 1730 0x9999, 1731 0x999A, 1732 0x999B, 1733 0x999C, 1734 0x999D, 1735 0x99A0, 1736 0x99A2, 1737 0x99A4, 1738 /* radeon secondary ids */ 1739 0x3171, 1740 0x3e70, 1741 0x4164, 1742 0x4165, 1743 0x4166, 1744 0x4168, 1745 0x4170, 1746 0x4171, 1747 0x4172, 1748 0x4173, 1749 0x496e, 1750 0x4a69, 1751 0x4a6a, 1752 0x4a6b, 1753 0x4a70, 1754 0x4a74, 1755 0x4b69, 1756 0x4b6b, 1757 0x4b6c, 1758 0x4c6e, 1759 0x4e64, 1760 0x4e65, 1761 0x4e66, 1762 0x4e67, 1763 0x4e68, 1764 0x4e69, 1765 0x4e6a, 1766 0x4e71, 1767 0x4f73, 1768 0x5569, 1769 0x556b, 1770 0x556d, 1771 0x556f, 1772 0x5571, 1773 0x5854, 1774 0x5874, 1775 0x5940, 1776 0x5941, 1777 0x5b70, 1778 0x5b72, 1779 0x5b73, 1780 0x5b74, 1781 0x5b75, 1782 0x5d44, 1783 0x5d45, 1784 0x5d6d, 1785 0x5d6f, 1786 0x5d72, 1787 0x5d77, 1788 0x5e6b, 1789 0x5e6d, 1790 0x7120, 1791 0x7124, 1792 0x7129, 1793 0x712e, 1794 0x712f, 1795 0x7162, 1796 0x7163, 1797 0x7166, 1798 0x7167, 1799 0x7172, 1800 0x7173, 1801 0x71a0, 1802 0x71a1, 1803 0x71a3, 1804 0x71a7, 1805 0x71bb, 1806 0x71e0, 1807 0x71e1, 1808 0x71e2, 1809 0x71e6, 1810 0x71e7, 1811 0x71f2, 1812 0x7269, 1813 0x726b, 1814 0x726e, 1815 0x72a0, 1816 0x72a8, 1817 0x72b1, 1818 0x72b3, 1819 0x793f, 1820 }; 1821 1822 static const struct pci_device_id pciidlist[] = { 1823 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1824 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1825 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1826 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1827 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1828 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1829 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1830 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1831 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1832 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1833 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1834 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1835 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1836 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1837 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1838 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1839 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1840 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1841 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1842 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1843 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1844 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1845 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1846 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1847 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1848 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1849 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1850 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1851 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1852 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1853 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1854 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1855 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1856 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1857 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1858 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1859 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1860 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1861 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1862 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1863 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1864 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1865 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1866 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1867 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1868 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1869 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1870 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1871 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1872 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1873 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1874 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1875 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1876 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1877 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1878 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1879 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1880 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1881 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1882 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1883 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1884 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1885 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1886 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1887 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1888 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1889 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1890 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1891 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1892 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1893 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1894 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1895 /* Kaveri */ 1896 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1897 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1898 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1899 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1900 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1901 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1902 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1903 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1904 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1905 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1906 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1907 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1908 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1909 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1910 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1911 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1912 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1913 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1914 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1915 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1916 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1917 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1918 /* Bonaire */ 1919 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1920 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1921 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1922 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1923 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1924 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1925 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1926 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1927 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1928 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1929 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1930 /* Hawaii */ 1931 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1932 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1933 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1934 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1935 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1936 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1937 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1938 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1939 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1940 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1941 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1942 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1943 /* Kabini */ 1944 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1945 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1946 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1947 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1948 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1949 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1950 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1951 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1952 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1953 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1954 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1955 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1956 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1957 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1958 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1959 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1960 /* mullins */ 1961 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1962 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1963 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1964 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1965 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1966 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1967 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1968 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1969 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1970 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1971 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1972 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1973 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1974 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1975 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1976 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1977 /* topaz */ 1978 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1979 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1980 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1981 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1982 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1983 /* tonga */ 1984 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1985 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1986 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1987 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1988 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1989 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1990 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1991 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1992 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1993 /* fiji */ 1994 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1995 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1996 /* carrizo */ 1997 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1998 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1999 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 2000 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 2001 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 2002 /* stoney */ 2003 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 2004 /* Polaris11 */ 2005 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2006 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2007 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2008 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2009 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2010 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2011 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2012 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2013 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2014 /* Polaris10 */ 2015 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2016 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2017 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2018 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2019 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2020 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2021 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2022 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2023 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2024 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2025 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2026 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2027 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2028 /* Polaris12 */ 2029 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2030 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2031 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2032 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2033 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2034 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2035 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2036 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2037 /* VEGAM */ 2038 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 2039 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 2040 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 2041 /* Vega 10 */ 2042 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2043 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2044 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2045 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2046 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2047 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2048 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2049 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2050 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2051 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2052 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2053 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2054 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2055 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2056 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2057 /* Vega 12 */ 2058 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2059 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2060 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2061 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2062 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2063 /* Vega 20 */ 2064 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2065 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2066 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2067 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2068 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2069 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2070 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2071 /* Raven */ 2072 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 2073 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 2074 /* Arcturus */ 2075 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2076 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2077 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2078 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2079 /* Navi10 */ 2080 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2081 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2082 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2083 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2084 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2085 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2086 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2087 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2088 /* Navi14 */ 2089 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2090 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2091 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2092 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2093 2094 /* Renoir */ 2095 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2096 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2097 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2098 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2099 2100 /* Navi12 */ 2101 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 2102 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 2103 2104 /* Sienna_Cichlid */ 2105 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2106 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2107 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2108 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2109 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2110 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2111 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2112 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2113 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2114 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2115 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2116 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2117 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2118 2119 /* Yellow Carp */ 2120 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 2121 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 2122 2123 /* Navy_Flounder */ 2124 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2125 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2126 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2127 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2128 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2129 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2130 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2131 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2132 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2133 2134 /* DIMGREY_CAVEFISH */ 2135 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2136 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2137 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2138 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2139 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2140 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2141 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2142 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2143 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2144 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2145 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2146 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2147 2148 /* Aldebaran */ 2149 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2150 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2151 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2152 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2153 2154 /* CYAN_SKILLFISH */ 2155 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2156 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2157 2158 /* BEIGE_GOBY */ 2159 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2160 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2161 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2162 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2163 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2164 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2165 2166 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2167 .class = PCI_CLASS_DISPLAY_VGA << 8, 2168 .class_mask = 0xffffff, 2169 .driver_data = CHIP_IP_DISCOVERY }, 2170 2171 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2172 .class = PCI_CLASS_DISPLAY_OTHER << 8, 2173 .class_mask = 0xffffff, 2174 .driver_data = CHIP_IP_DISCOVERY }, 2175 2176 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2177 .class = PCI_CLASS_ACCELERATOR_PROCESSING << 8, 2178 .class_mask = 0xffffff, 2179 .driver_data = CHIP_IP_DISCOVERY }, 2180 2181 {0, 0, 0} 2182 }; 2183 2184 MODULE_DEVICE_TABLE(pci, pciidlist); 2185 2186 static const struct amdgpu_asic_type_quirk asic_type_quirks[] = { 2187 /* differentiate between P10 and P11 asics with the same DID */ 2188 {0x67FF, 0xE3, CHIP_POLARIS10}, 2189 {0x67FF, 0xE7, CHIP_POLARIS10}, 2190 {0x67FF, 0xF3, CHIP_POLARIS10}, 2191 {0x67FF, 0xF7, CHIP_POLARIS10}, 2192 }; 2193 2194 static const struct drm_driver amdgpu_kms_driver; 2195 2196 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 2197 { 2198 struct pci_dev *p = NULL; 2199 int i; 2200 2201 /* 0 - GPU 2202 * 1 - audio 2203 * 2 - USB 2204 * 3 - UCSI 2205 */ 2206 for (i = 1; i < 4; i++) { 2207 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 2208 adev->pdev->bus->number, i); 2209 if (p) { 2210 pm_runtime_get_sync(&p->dev); 2211 pm_runtime_mark_last_busy(&p->dev); 2212 pm_runtime_put_autosuspend(&p->dev); 2213 pci_dev_put(p); 2214 } 2215 } 2216 } 2217 2218 static void amdgpu_init_debug_options(struct amdgpu_device *adev) 2219 { 2220 if (amdgpu_debug_mask & AMDGPU_DEBUG_VM) { 2221 pr_info("debug: VM handling debug enabled\n"); 2222 adev->debug_vm = true; 2223 } 2224 2225 if (amdgpu_debug_mask & AMDGPU_DEBUG_LARGEBAR) { 2226 pr_info("debug: enabled simulating large-bar capability on non-large bar system\n"); 2227 adev->debug_largebar = true; 2228 } 2229 2230 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY) { 2231 pr_info("debug: soft reset for GPU recovery disabled\n"); 2232 adev->debug_disable_soft_recovery = true; 2233 } 2234 2235 if (amdgpu_debug_mask & AMDGPU_DEBUG_USE_VRAM_FW_BUF) { 2236 pr_info("debug: place fw in vram for frontdoor loading\n"); 2237 adev->debug_use_vram_fw_buf = true; 2238 } 2239 2240 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_RAS_ACA) { 2241 pr_info("debug: enable RAS ACA\n"); 2242 adev->debug_enable_ras_aca = true; 2243 } 2244 2245 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_EXP_RESETS) { 2246 pr_info("debug: enable experimental reset features\n"); 2247 adev->debug_exp_resets = true; 2248 } 2249 2250 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_RING_RESET) { 2251 pr_info("debug: ring reset disabled\n"); 2252 adev->debug_disable_gpu_ring_reset = true; 2253 } 2254 if (amdgpu_debug_mask & AMDGPU_DEBUG_SMU_POOL) { 2255 pr_info("debug: use vram for smu pool\n"); 2256 adev->pm.smu_debug_mask |= SMU_DEBUG_POOL_USE_VRAM; 2257 } 2258 } 2259 2260 static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long flags) 2261 { 2262 int i; 2263 2264 for (i = 0; i < ARRAY_SIZE(asic_type_quirks); i++) { 2265 if (pdev->device == asic_type_quirks[i].device && 2266 pdev->revision == asic_type_quirks[i].revision) { 2267 flags &= ~AMD_ASIC_MASK; 2268 flags |= asic_type_quirks[i].type; 2269 break; 2270 } 2271 } 2272 2273 return flags; 2274 } 2275 2276 static int amdgpu_pci_probe(struct pci_dev *pdev, 2277 const struct pci_device_id *ent) 2278 { 2279 struct drm_device *ddev; 2280 struct amdgpu_device *adev; 2281 unsigned long flags = ent->driver_data; 2282 int ret, retry = 0, i; 2283 bool supports_atomic = false; 2284 2285 if ((pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA || 2286 (pdev->class >> 8) == PCI_CLASS_DISPLAY_OTHER) { 2287 if (drm_firmware_drivers_only() && amdgpu_modeset == -1) 2288 return -EINVAL; 2289 } 2290 2291 /* skip devices which are owned by radeon */ 2292 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2293 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2294 return -ENODEV; 2295 } 2296 2297 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) 2298 amdgpu_aspm = 0; 2299 2300 if (amdgpu_virtual_display || 2301 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 2302 supports_atomic = true; 2303 2304 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2305 DRM_INFO("This hardware requires experimental hardware support.\n" 2306 "See modparam exp_hw_support\n"); 2307 return -ENODEV; 2308 } 2309 2310 flags = amdgpu_fix_asic_type(pdev, flags); 2311 2312 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2313 * however, SME requires an indirect IOMMU mapping because the encryption 2314 * bit is beyond the DMA mask of the chip. 2315 */ 2316 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2317 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2318 dev_info(&pdev->dev, 2319 "SME is not compatible with RAVEN\n"); 2320 return -ENOTSUPP; 2321 } 2322 2323 switch (flags & AMD_ASIC_MASK) { 2324 case CHIP_TAHITI: 2325 case CHIP_PITCAIRN: 2326 case CHIP_VERDE: 2327 case CHIP_OLAND: 2328 case CHIP_HAINAN: 2329 #ifdef CONFIG_DRM_AMDGPU_SI 2330 if (!amdgpu_si_support) { 2331 dev_info(&pdev->dev, 2332 "SI support provided by radeon.\n"); 2333 dev_info(&pdev->dev, 2334 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 2335 ); 2336 return -ENODEV; 2337 } 2338 break; 2339 #else 2340 dev_info(&pdev->dev, "amdgpu is built without SI support.\n"); 2341 return -ENODEV; 2342 #endif 2343 case CHIP_KAVERI: 2344 case CHIP_BONAIRE: 2345 case CHIP_HAWAII: 2346 case CHIP_KABINI: 2347 case CHIP_MULLINS: 2348 #ifdef CONFIG_DRM_AMDGPU_CIK 2349 if (!amdgpu_cik_support) { 2350 dev_info(&pdev->dev, 2351 "CIK support provided by radeon.\n"); 2352 dev_info(&pdev->dev, 2353 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 2354 ); 2355 return -ENODEV; 2356 } 2357 break; 2358 #else 2359 dev_info(&pdev->dev, "amdgpu is built without CIK support.\n"); 2360 return -ENODEV; 2361 #endif 2362 default: 2363 break; 2364 } 2365 2366 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2367 if (IS_ERR(adev)) 2368 return PTR_ERR(adev); 2369 2370 adev->dev = &pdev->dev; 2371 adev->pdev = pdev; 2372 ddev = adev_to_drm(adev); 2373 2374 if (!supports_atomic) 2375 ddev->driver_features &= ~DRIVER_ATOMIC; 2376 2377 ret = pci_enable_device(pdev); 2378 if (ret) 2379 return ret; 2380 2381 pci_set_drvdata(pdev, ddev); 2382 2383 amdgpu_init_debug_options(adev); 2384 2385 ret = amdgpu_driver_load_kms(adev, flags); 2386 if (ret) 2387 goto err_pci; 2388 2389 retry_init: 2390 ret = drm_dev_register(ddev, flags); 2391 if (ret == -EAGAIN && ++retry <= 3) { 2392 DRM_INFO("retry init %d\n", retry); 2393 /* Don't request EX mode too frequently which is attacking */ 2394 msleep(5000); 2395 goto retry_init; 2396 } else if (ret) { 2397 goto err_pci; 2398 } 2399 2400 ret = amdgpu_xcp_dev_register(adev, ent); 2401 if (ret) 2402 goto err_pci; 2403 2404 ret = amdgpu_amdkfd_drm_client_create(adev); 2405 if (ret) 2406 goto err_pci; 2407 2408 /* 2409 * 1. don't init fbdev on hw without DCE 2410 * 2. don't init fbdev if there are no connectors 2411 */ 2412 if (adev->mode_info.mode_config_initialized && 2413 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2414 const struct drm_format_info *format; 2415 2416 /* select 8 bpp console on low vram cards */ 2417 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2418 format = drm_format_info(DRM_FORMAT_C8); 2419 else 2420 format = NULL; 2421 2422 drm_client_setup(adev_to_drm(adev), format); 2423 } 2424 2425 ret = amdgpu_debugfs_init(adev); 2426 if (ret) 2427 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2428 2429 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2430 /* only need to skip on ATPX */ 2431 if (amdgpu_device_supports_px(ddev)) 2432 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2433 /* we want direct complete for BOCO */ 2434 if (amdgpu_device_supports_boco(ddev)) 2435 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2436 DPM_FLAG_SMART_SUSPEND | 2437 DPM_FLAG_MAY_SKIP_RESUME); 2438 pm_runtime_use_autosuspend(ddev->dev); 2439 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2440 2441 pm_runtime_allow(ddev->dev); 2442 2443 pm_runtime_mark_last_busy(ddev->dev); 2444 pm_runtime_put_autosuspend(ddev->dev); 2445 2446 pci_wake_from_d3(pdev, TRUE); 2447 2448 /* 2449 * For runpm implemented via BACO, PMFW will handle the 2450 * timing for BACO in and out: 2451 * - put ASIC into BACO state only when both video and 2452 * audio functions are in D3 state. 2453 * - pull ASIC out of BACO state when either video or 2454 * audio function is in D0 state. 2455 * Also, at startup, PMFW assumes both functions are in 2456 * D0 state. 2457 * 2458 * So if snd driver was loaded prior to amdgpu driver 2459 * and audio function was put into D3 state, there will 2460 * be no PMFW-aware D-state transition(D0->D3) on runpm 2461 * suspend. Thus the BACO will be not correctly kicked in. 2462 * 2463 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2464 * into D0 state. Then there will be a PMFW-aware D-state 2465 * transition(D0->D3) on runpm suspend. 2466 */ 2467 if (amdgpu_device_supports_baco(ddev) && 2468 !(adev->flags & AMD_IS_APU) && 2469 (adev->asic_type >= CHIP_NAVI10)) 2470 amdgpu_get_secondary_funcs(adev); 2471 } 2472 2473 return 0; 2474 2475 err_pci: 2476 pci_disable_device(pdev); 2477 return ret; 2478 } 2479 2480 static void 2481 amdgpu_pci_remove(struct pci_dev *pdev) 2482 { 2483 struct drm_device *dev = pci_get_drvdata(pdev); 2484 struct amdgpu_device *adev = drm_to_adev(dev); 2485 2486 amdgpu_xcp_dev_unplug(adev); 2487 amdgpu_gmc_prepare_nps_mode_change(adev); 2488 drm_dev_unplug(dev); 2489 2490 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2491 pm_runtime_get_sync(dev->dev); 2492 pm_runtime_forbid(dev->dev); 2493 } 2494 2495 amdgpu_driver_unload_kms(dev); 2496 2497 /* 2498 * Flush any in flight DMA operations from device. 2499 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2500 * StatusTransactions Pending bit. 2501 */ 2502 pci_disable_device(pdev); 2503 pci_wait_for_pending_transaction(pdev); 2504 } 2505 2506 static void 2507 amdgpu_pci_shutdown(struct pci_dev *pdev) 2508 { 2509 struct drm_device *dev = pci_get_drvdata(pdev); 2510 struct amdgpu_device *adev = drm_to_adev(dev); 2511 2512 if (amdgpu_ras_intr_triggered()) 2513 return; 2514 2515 /* if we are running in a VM, make sure the device 2516 * torn down properly on reboot/shutdown. 2517 * unfortunately we can't detect certain 2518 * hypervisors so just do this all the time. 2519 */ 2520 if (!amdgpu_passthrough(adev)) 2521 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2522 amdgpu_device_ip_suspend(adev); 2523 adev->mp1_state = PP_MP1_STATE_NONE; 2524 } 2525 2526 static int amdgpu_pmops_prepare(struct device *dev) 2527 { 2528 struct drm_device *drm_dev = dev_get_drvdata(dev); 2529 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2530 2531 /* Return a positive number here so 2532 * DPM_FLAG_SMART_SUSPEND works properly 2533 */ 2534 if (amdgpu_device_supports_boco(drm_dev) && 2535 pm_runtime_suspended(dev)) 2536 return 1; 2537 2538 /* if we will not support s3 or s2i for the device 2539 * then skip suspend 2540 */ 2541 if (!amdgpu_acpi_is_s0ix_active(adev) && 2542 !amdgpu_acpi_is_s3_active(adev)) 2543 return 1; 2544 2545 return amdgpu_device_prepare(drm_dev); 2546 } 2547 2548 static void amdgpu_pmops_complete(struct device *dev) 2549 { 2550 /* nothing to do */ 2551 } 2552 2553 static int amdgpu_pmops_suspend(struct device *dev) 2554 { 2555 struct drm_device *drm_dev = dev_get_drvdata(dev); 2556 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2557 2558 if (amdgpu_acpi_is_s0ix_active(adev)) 2559 adev->in_s0ix = true; 2560 else if (amdgpu_acpi_is_s3_active(adev)) 2561 adev->in_s3 = true; 2562 if (!adev->in_s0ix && !adev->in_s3) 2563 return 0; 2564 return amdgpu_device_suspend(drm_dev, true); 2565 } 2566 2567 static int amdgpu_pmops_suspend_noirq(struct device *dev) 2568 { 2569 struct drm_device *drm_dev = dev_get_drvdata(dev); 2570 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2571 2572 if (amdgpu_acpi_should_gpu_reset(adev)) 2573 return amdgpu_asic_reset(adev); 2574 2575 return 0; 2576 } 2577 2578 static int amdgpu_pmops_resume(struct device *dev) 2579 { 2580 struct drm_device *drm_dev = dev_get_drvdata(dev); 2581 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2582 int r; 2583 2584 if (!adev->in_s0ix && !adev->in_s3) 2585 return 0; 2586 2587 /* Avoids registers access if device is physically gone */ 2588 if (!pci_device_is_present(adev->pdev)) 2589 adev->no_hw_access = true; 2590 2591 r = amdgpu_device_resume(drm_dev, true); 2592 if (amdgpu_acpi_is_s0ix_active(adev)) 2593 adev->in_s0ix = false; 2594 else 2595 adev->in_s3 = false; 2596 return r; 2597 } 2598 2599 static int amdgpu_pmops_freeze(struct device *dev) 2600 { 2601 struct drm_device *drm_dev = dev_get_drvdata(dev); 2602 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2603 int r; 2604 2605 r = amdgpu_device_suspend(drm_dev, true); 2606 if (r) 2607 return r; 2608 2609 if (amdgpu_acpi_should_gpu_reset(adev)) 2610 return amdgpu_asic_reset(adev); 2611 return 0; 2612 } 2613 2614 static int amdgpu_pmops_thaw(struct device *dev) 2615 { 2616 struct drm_device *drm_dev = dev_get_drvdata(dev); 2617 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2618 int r; 2619 2620 r = amdgpu_device_resume(drm_dev, true); 2621 adev->in_s4 = false; 2622 2623 return r; 2624 } 2625 2626 static int amdgpu_pmops_poweroff(struct device *dev) 2627 { 2628 struct drm_device *drm_dev = dev_get_drvdata(dev); 2629 2630 return amdgpu_device_suspend(drm_dev, true); 2631 } 2632 2633 static int amdgpu_pmops_restore(struct device *dev) 2634 { 2635 struct drm_device *drm_dev = dev_get_drvdata(dev); 2636 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2637 2638 adev->in_s4 = false; 2639 2640 return amdgpu_device_resume(drm_dev, true); 2641 } 2642 2643 static int amdgpu_runtime_idle_check_display(struct device *dev) 2644 { 2645 struct pci_dev *pdev = to_pci_dev(dev); 2646 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2647 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2648 2649 if (adev->mode_info.num_crtc) { 2650 struct drm_connector *list_connector; 2651 struct drm_connector_list_iter iter; 2652 int ret = 0; 2653 2654 if (amdgpu_runtime_pm != -2) { 2655 /* XXX: Return busy if any displays are connected to avoid 2656 * possible display wakeups after runtime resume due to 2657 * hotplug events in case any displays were connected while 2658 * the GPU was in suspend. Remove this once that is fixed. 2659 */ 2660 mutex_lock(&drm_dev->mode_config.mutex); 2661 drm_connector_list_iter_begin(drm_dev, &iter); 2662 drm_for_each_connector_iter(list_connector, &iter) { 2663 if (list_connector->status == connector_status_connected) { 2664 ret = -EBUSY; 2665 break; 2666 } 2667 } 2668 drm_connector_list_iter_end(&iter); 2669 mutex_unlock(&drm_dev->mode_config.mutex); 2670 2671 if (ret) 2672 return ret; 2673 } 2674 2675 if (adev->dc_enabled) { 2676 struct drm_crtc *crtc; 2677 2678 drm_for_each_crtc(crtc, drm_dev) { 2679 drm_modeset_lock(&crtc->mutex, NULL); 2680 if (crtc->state->active) 2681 ret = -EBUSY; 2682 drm_modeset_unlock(&crtc->mutex); 2683 if (ret < 0) 2684 break; 2685 } 2686 } else { 2687 mutex_lock(&drm_dev->mode_config.mutex); 2688 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2689 2690 drm_connector_list_iter_begin(drm_dev, &iter); 2691 drm_for_each_connector_iter(list_connector, &iter) { 2692 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2693 ret = -EBUSY; 2694 break; 2695 } 2696 } 2697 2698 drm_connector_list_iter_end(&iter); 2699 2700 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2701 mutex_unlock(&drm_dev->mode_config.mutex); 2702 } 2703 if (ret) 2704 return ret; 2705 } 2706 2707 return 0; 2708 } 2709 2710 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2711 { 2712 struct pci_dev *pdev = to_pci_dev(dev); 2713 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2714 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2715 int ret, i; 2716 2717 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2718 pm_runtime_forbid(dev); 2719 return -EBUSY; 2720 } 2721 2722 ret = amdgpu_runtime_idle_check_display(dev); 2723 if (ret) 2724 return ret; 2725 2726 /* wait for all rings to drain before suspending */ 2727 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2728 struct amdgpu_ring *ring = adev->rings[i]; 2729 2730 if (ring && ring->sched.ready) { 2731 ret = amdgpu_fence_wait_empty(ring); 2732 if (ret) 2733 return -EBUSY; 2734 } 2735 } 2736 2737 adev->in_runpm = true; 2738 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2739 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2740 2741 /* 2742 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2743 * proper cleanups and put itself into a state ready for PNP. That 2744 * can address some random resuming failure observed on BOCO capable 2745 * platforms. 2746 * TODO: this may be also needed for PX capable platform. 2747 */ 2748 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2749 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2750 2751 ret = amdgpu_device_prepare(drm_dev); 2752 if (ret) 2753 return ret; 2754 ret = amdgpu_device_suspend(drm_dev, false); 2755 if (ret) { 2756 adev->in_runpm = false; 2757 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2758 adev->mp1_state = PP_MP1_STATE_NONE; 2759 return ret; 2760 } 2761 2762 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2763 adev->mp1_state = PP_MP1_STATE_NONE; 2764 2765 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) { 2766 /* Only need to handle PCI state in the driver for ATPX 2767 * PCI core handles it for _PR3. 2768 */ 2769 amdgpu_device_cache_pci_state(pdev); 2770 pci_disable_device(pdev); 2771 pci_ignore_hotplug(pdev); 2772 pci_set_power_state(pdev, PCI_D3cold); 2773 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2774 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) { 2775 /* nothing to do */ 2776 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2777 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) { 2778 amdgpu_device_baco_enter(drm_dev); 2779 } 2780 2781 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n"); 2782 2783 return 0; 2784 } 2785 2786 static int amdgpu_pmops_runtime_resume(struct device *dev) 2787 { 2788 struct pci_dev *pdev = to_pci_dev(dev); 2789 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2790 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2791 int ret; 2792 2793 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) 2794 return -EINVAL; 2795 2796 /* Avoids registers access if device is physically gone */ 2797 if (!pci_device_is_present(adev->pdev)) 2798 adev->no_hw_access = true; 2799 2800 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) { 2801 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2802 2803 /* Only need to handle PCI state in the driver for ATPX 2804 * PCI core handles it for _PR3. 2805 */ 2806 pci_set_power_state(pdev, PCI_D0); 2807 amdgpu_device_load_pci_state(pdev); 2808 ret = pci_enable_device(pdev); 2809 if (ret) 2810 return ret; 2811 pci_set_master(pdev); 2812 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) { 2813 /* Only need to handle PCI state in the driver for ATPX 2814 * PCI core handles it for _PR3. 2815 */ 2816 pci_set_master(pdev); 2817 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2818 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) { 2819 amdgpu_device_baco_exit(drm_dev); 2820 } 2821 ret = amdgpu_device_resume(drm_dev, false); 2822 if (ret) { 2823 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2824 pci_disable_device(pdev); 2825 return ret; 2826 } 2827 2828 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2829 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2830 adev->in_runpm = false; 2831 return 0; 2832 } 2833 2834 static int amdgpu_pmops_runtime_idle(struct device *dev) 2835 { 2836 struct drm_device *drm_dev = dev_get_drvdata(dev); 2837 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2838 int ret; 2839 2840 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2841 pm_runtime_forbid(dev); 2842 return -EBUSY; 2843 } 2844 2845 ret = amdgpu_runtime_idle_check_display(dev); 2846 2847 pm_runtime_mark_last_busy(dev); 2848 pm_runtime_autosuspend(dev); 2849 return ret; 2850 } 2851 2852 long amdgpu_drm_ioctl(struct file *filp, 2853 unsigned int cmd, unsigned long arg) 2854 { 2855 struct drm_file *file_priv = filp->private_data; 2856 struct drm_device *dev; 2857 long ret; 2858 2859 dev = file_priv->minor->dev; 2860 ret = pm_runtime_get_sync(dev->dev); 2861 if (ret < 0) 2862 goto out; 2863 2864 ret = drm_ioctl(filp, cmd, arg); 2865 2866 pm_runtime_mark_last_busy(dev->dev); 2867 out: 2868 pm_runtime_put_autosuspend(dev->dev); 2869 return ret; 2870 } 2871 2872 static const struct dev_pm_ops amdgpu_pm_ops = { 2873 .prepare = amdgpu_pmops_prepare, 2874 .complete = amdgpu_pmops_complete, 2875 .suspend = amdgpu_pmops_suspend, 2876 .suspend_noirq = amdgpu_pmops_suspend_noirq, 2877 .resume = amdgpu_pmops_resume, 2878 .freeze = amdgpu_pmops_freeze, 2879 .thaw = amdgpu_pmops_thaw, 2880 .poweroff = amdgpu_pmops_poweroff, 2881 .restore = amdgpu_pmops_restore, 2882 .runtime_suspend = amdgpu_pmops_runtime_suspend, 2883 .runtime_resume = amdgpu_pmops_runtime_resume, 2884 .runtime_idle = amdgpu_pmops_runtime_idle, 2885 }; 2886 2887 static int amdgpu_flush(struct file *f, fl_owner_t id) 2888 { 2889 struct drm_file *file_priv = f->private_data; 2890 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2891 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2892 2893 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 2894 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 2895 2896 return timeout >= 0 ? 0 : timeout; 2897 } 2898 2899 static const struct file_operations amdgpu_driver_kms_fops = { 2900 .owner = THIS_MODULE, 2901 .open = drm_open, 2902 .flush = amdgpu_flush, 2903 .release = drm_release, 2904 .unlocked_ioctl = amdgpu_drm_ioctl, 2905 .mmap = drm_gem_mmap, 2906 .poll = drm_poll, 2907 .read = drm_read, 2908 #ifdef CONFIG_COMPAT 2909 .compat_ioctl = amdgpu_kms_compat_ioctl, 2910 #endif 2911 #ifdef CONFIG_PROC_FS 2912 .show_fdinfo = drm_show_fdinfo, 2913 #endif 2914 .fop_flags = FOP_UNSIGNED_OFFSET, 2915 }; 2916 2917 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 2918 { 2919 struct drm_file *file; 2920 2921 if (!filp) 2922 return -EINVAL; 2923 2924 if (filp->f_op != &amdgpu_driver_kms_fops) 2925 return -EINVAL; 2926 2927 file = filp->private_data; 2928 *fpriv = file->driver_priv; 2929 return 0; 2930 } 2931 2932 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 2933 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2934 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2935 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2936 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 2937 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2938 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2939 /* KMS */ 2940 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2941 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2942 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2943 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2944 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2945 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2946 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2947 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2948 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2949 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2950 }; 2951 2952 static const struct drm_driver amdgpu_kms_driver = { 2953 .driver_features = 2954 DRIVER_ATOMIC | 2955 DRIVER_GEM | 2956 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 2957 DRIVER_SYNCOBJ_TIMELINE, 2958 .open = amdgpu_driver_open_kms, 2959 .postclose = amdgpu_driver_postclose_kms, 2960 .ioctls = amdgpu_ioctls_kms, 2961 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2962 .dumb_create = amdgpu_mode_dumb_create, 2963 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2964 DRM_FBDEV_TTM_DRIVER_OPS, 2965 .fops = &amdgpu_driver_kms_fops, 2966 .release = &amdgpu_driver_release_kms, 2967 #ifdef CONFIG_PROC_FS 2968 .show_fdinfo = amdgpu_show_fdinfo, 2969 #endif 2970 2971 .gem_prime_import = amdgpu_gem_prime_import, 2972 2973 .name = DRIVER_NAME, 2974 .desc = DRIVER_DESC, 2975 .major = KMS_DRIVER_MAJOR, 2976 .minor = KMS_DRIVER_MINOR, 2977 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2978 }; 2979 2980 const struct drm_driver amdgpu_partition_driver = { 2981 .driver_features = 2982 DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ | 2983 DRIVER_SYNCOBJ_TIMELINE, 2984 .open = amdgpu_driver_open_kms, 2985 .postclose = amdgpu_driver_postclose_kms, 2986 .ioctls = amdgpu_ioctls_kms, 2987 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2988 .dumb_create = amdgpu_mode_dumb_create, 2989 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2990 DRM_FBDEV_TTM_DRIVER_OPS, 2991 .fops = &amdgpu_driver_kms_fops, 2992 .release = &amdgpu_driver_release_kms, 2993 2994 .gem_prime_import = amdgpu_gem_prime_import, 2995 2996 .name = DRIVER_NAME, 2997 .desc = DRIVER_DESC, 2998 .major = KMS_DRIVER_MAJOR, 2999 .minor = KMS_DRIVER_MINOR, 3000 .patchlevel = KMS_DRIVER_PATCHLEVEL, 3001 }; 3002 3003 static struct pci_error_handlers amdgpu_pci_err_handler = { 3004 .error_detected = amdgpu_pci_error_detected, 3005 .mmio_enabled = amdgpu_pci_mmio_enabled, 3006 .slot_reset = amdgpu_pci_slot_reset, 3007 .resume = amdgpu_pci_resume, 3008 }; 3009 3010 static const struct attribute_group *amdgpu_sysfs_groups[] = { 3011 &amdgpu_vram_mgr_attr_group, 3012 &amdgpu_gtt_mgr_attr_group, 3013 &amdgpu_flash_attr_group, 3014 NULL, 3015 }; 3016 3017 static struct pci_driver amdgpu_kms_pci_driver = { 3018 .name = DRIVER_NAME, 3019 .id_table = pciidlist, 3020 .probe = amdgpu_pci_probe, 3021 .remove = amdgpu_pci_remove, 3022 .shutdown = amdgpu_pci_shutdown, 3023 .driver.pm = &amdgpu_pm_ops, 3024 .err_handler = &amdgpu_pci_err_handler, 3025 .dev_groups = amdgpu_sysfs_groups, 3026 }; 3027 3028 static int __init amdgpu_init(void) 3029 { 3030 int r; 3031 3032 r = amdgpu_sync_init(); 3033 if (r) 3034 goto error_sync; 3035 3036 r = amdgpu_fence_slab_init(); 3037 if (r) 3038 goto error_fence; 3039 3040 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 3041 amdgpu_register_atpx_handler(); 3042 amdgpu_acpi_detect(); 3043 3044 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 3045 amdgpu_amdkfd_init(); 3046 3047 if (amdgpu_pp_feature_mask & PP_OVERDRIVE_MASK) { 3048 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 3049 pr_crit("Overdrive is enabled, please disable it before " 3050 "reporting any bugs unrelated to overdrive.\n"); 3051 } 3052 3053 /* let modprobe override vga console setting */ 3054 return pci_register_driver(&amdgpu_kms_pci_driver); 3055 3056 error_fence: 3057 amdgpu_sync_fini(); 3058 3059 error_sync: 3060 return r; 3061 } 3062 3063 static void __exit amdgpu_exit(void) 3064 { 3065 amdgpu_amdkfd_fini(); 3066 pci_unregister_driver(&amdgpu_kms_pci_driver); 3067 amdgpu_unregister_atpx_handler(); 3068 amdgpu_acpi_release(); 3069 amdgpu_sync_fini(); 3070 amdgpu_fence_slab_fini(); 3071 mmu_notifier_synchronize(); 3072 amdgpu_xcp_drv_release(); 3073 } 3074 3075 module_init(amdgpu_init); 3076 module_exit(amdgpu_exit); 3077 3078 MODULE_AUTHOR(DRIVER_AUTHOR); 3079 MODULE_DESCRIPTION(DRIVER_DESC); 3080 MODULE_LICENSE("GPL and additional rights"); 3081