1 /** 2 * \file amdgpu_drv.c 3 * AMD Amdgpu driver 4 * 5 * \author Gareth Hughes <gareth@valinux.com> 6 */ 7 8 /* 9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 10 * All Rights Reserved. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a 13 * copy of this software and associated documentation files (the "Software"), 14 * to deal in the Software without restriction, including without limitation 15 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 16 * and/or sell copies of the Software, and to permit persons to whom the 17 * Software is furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice (including the next 20 * paragraph) shall be included in all copies or substantial portions of the 21 * Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 29 * OTHER DEALINGS IN THE SOFTWARE. 30 */ 31 32 #include <drm/drmP.h> 33 #include <drm/amdgpu_drm.h> 34 #include <drm/drm_gem.h> 35 #include "amdgpu_drv.h" 36 37 #include <drm/drm_pciids.h> 38 #include <linux/console.h> 39 #include <linux/module.h> 40 #include <linux/pm_runtime.h> 41 #include <linux/vga_switcheroo.h> 42 #include "drm_crtc_helper.h" 43 44 #include "amdgpu.h" 45 #include "amdgpu_irq.h" 46 47 #include "amdgpu_amdkfd.h" 48 49 /* 50 * KMS wrapper. 51 * - 3.0.0 - initial driver 52 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 53 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 54 * at the end of IBs. 55 * - 3.3.0 - Add VM support for UVD on supported hardware. 56 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 57 * - 3.5.0 - Add support for new UVD_NO_OP register. 58 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 59 * - 3.7.0 - Add support for VCE clock list packet 60 * - 3.8.0 - Add support raster config init in the kernel 61 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 62 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 63 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 64 * - 3.12.0 - Add query for double offchip LDS buffers 65 * - 3.13.0 - Add PRT support 66 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 67 * - 3.15.0 - Export more gpu info for gfx9 68 */ 69 #define KMS_DRIVER_MAJOR 3 70 #define KMS_DRIVER_MINOR 15 71 #define KMS_DRIVER_PATCHLEVEL 0 72 73 int amdgpu_vram_limit = 0; 74 int amdgpu_gart_size = -1; /* auto */ 75 int amdgpu_moverate = -1; /* auto */ 76 int amdgpu_benchmarking = 0; 77 int amdgpu_testing = 0; 78 int amdgpu_audio = -1; 79 int amdgpu_disp_priority = 0; 80 int amdgpu_hw_i2c = 0; 81 int amdgpu_pcie_gen2 = -1; 82 int amdgpu_msi = -1; 83 int amdgpu_lockup_timeout = 0; 84 int amdgpu_dpm = -1; 85 int amdgpu_fw_load_type = -1; 86 int amdgpu_aspm = -1; 87 int amdgpu_runtime_pm = -1; 88 unsigned amdgpu_ip_block_mask = 0xffffffff; 89 int amdgpu_bapm = -1; 90 int amdgpu_deep_color = 0; 91 int amdgpu_vm_size = -1; 92 int amdgpu_vm_block_size = -1; 93 int amdgpu_vm_fault_stop = 0; 94 int amdgpu_vm_debug = 0; 95 int amdgpu_vram_page_split = 1024; 96 int amdgpu_exp_hw_support = 0; 97 int amdgpu_sched_jobs = 32; 98 int amdgpu_sched_hw_submission = 2; 99 int amdgpu_no_evict = 0; 100 int amdgpu_direct_gma_size = 0; 101 unsigned amdgpu_pcie_gen_cap = 0; 102 unsigned amdgpu_pcie_lane_cap = 0; 103 unsigned amdgpu_cg_mask = 0xffffffff; 104 unsigned amdgpu_pg_mask = 0xffffffff; 105 char *amdgpu_disable_cu = NULL; 106 char *amdgpu_virtual_display = NULL; 107 unsigned amdgpu_pp_feature_mask = 0xffffffff; 108 int amdgpu_ngg = 0; 109 int amdgpu_prim_buf_per_se = 0; 110 int amdgpu_pos_buf_per_se = 0; 111 int amdgpu_cntl_sb_buf_per_se = 0; 112 int amdgpu_param_buf_per_se = 0; 113 114 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 115 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 116 117 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)"); 118 module_param_named(gartsize, amdgpu_gart_size, int, 0600); 119 120 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 121 module_param_named(moverate, amdgpu_moverate, int, 0600); 122 123 MODULE_PARM_DESC(benchmark, "Run benchmark"); 124 module_param_named(benchmark, amdgpu_benchmarking, int, 0444); 125 126 MODULE_PARM_DESC(test, "Run tests"); 127 module_param_named(test, amdgpu_testing, int, 0444); 128 129 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 130 module_param_named(audio, amdgpu_audio, int, 0444); 131 132 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 133 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 134 135 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 136 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 137 138 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 139 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 140 141 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 142 module_param_named(msi, amdgpu_msi, int, 0444); 143 144 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 0 = disable)"); 145 module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444); 146 147 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 148 module_param_named(dpm, amdgpu_dpm, int, 0444); 149 150 MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)"); 151 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 152 153 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 154 module_param_named(aspm, amdgpu_aspm, int, 0444); 155 156 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 157 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 158 159 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 160 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 161 162 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 163 module_param_named(bapm, amdgpu_bapm, int, 0444); 164 165 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 166 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 167 168 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 169 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 170 171 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 172 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 173 174 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 175 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 176 177 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 178 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 179 180 MODULE_PARM_DESC(vram_page_split, "Number of pages after we split VRAM allocations (default 1024, -1 = disable)"); 181 module_param_named(vram_page_split, amdgpu_vram_page_split, int, 0444); 182 183 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 184 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 185 186 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 187 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 188 189 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 190 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 191 192 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 193 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, int, 0444); 194 195 MODULE_PARM_DESC(no_evict, "Support pinning request from user space (1 = enable, 0 = disable (default))"); 196 module_param_named(no_evict, amdgpu_no_evict, int, 0444); 197 198 MODULE_PARM_DESC(direct_gma_size, "Direct GMA size in megabytes (max 96MB)"); 199 module_param_named(direct_gma_size, amdgpu_direct_gma_size, int, 0444); 200 201 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 202 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 203 204 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 205 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 206 207 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 208 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); 209 210 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 211 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 212 213 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 214 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 215 216 MODULE_PARM_DESC(virtual_display, 217 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 218 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 219 220 MODULE_PARM_DESC(ngg, "Next Generation Graphics (1 = enable, 0 = disable(default depending on gfx))"); 221 module_param_named(ngg, amdgpu_ngg, int, 0444); 222 223 MODULE_PARM_DESC(prim_buf_per_se, "the size of Primitive Buffer per Shader Engine (default depending on gfx)"); 224 module_param_named(prim_buf_per_se, amdgpu_prim_buf_per_se, int, 0444); 225 226 MODULE_PARM_DESC(pos_buf_per_se, "the size of Position Buffer per Shader Engine (default depending on gfx)"); 227 module_param_named(pos_buf_per_se, amdgpu_pos_buf_per_se, int, 0444); 228 229 MODULE_PARM_DESC(cntl_sb_buf_per_se, "the size of Control Sideband per Shader Engine (default depending on gfx)"); 230 module_param_named(cntl_sb_buf_per_se, amdgpu_cntl_sb_buf_per_se, int, 0444); 231 232 MODULE_PARM_DESC(param_buf_per_se, "the size of Off-Chip Pramater Cache per Shader Engine (default depending on gfx)"); 233 module_param_named(param_buf_per_se, amdgpu_param_buf_per_se, int, 0444); 234 235 236 static const struct pci_device_id pciidlist[] = { 237 #ifdef CONFIG_DRM_AMDGPU_SI 238 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 239 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 240 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 241 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 242 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 243 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 244 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 245 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 246 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 247 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 248 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 249 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 250 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 251 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 252 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 253 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 254 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 255 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 256 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 257 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 258 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 259 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 260 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 261 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 262 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 263 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 264 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 265 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 266 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 267 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 268 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 269 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 270 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 271 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 272 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 273 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 274 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 275 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 276 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 277 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 278 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 279 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 280 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 281 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 282 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 283 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 284 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 285 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 286 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 287 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 288 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 289 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 290 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 291 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 292 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 293 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 294 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 295 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 296 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 297 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 298 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 299 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 300 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 301 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 302 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 303 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 304 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 305 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 306 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 307 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 308 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 309 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 310 #endif 311 #ifdef CONFIG_DRM_AMDGPU_CIK 312 /* Kaveri */ 313 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 314 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 315 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 316 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 317 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 318 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 319 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 320 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 321 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 322 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 323 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 324 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 325 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 326 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 327 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 328 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 329 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 330 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 331 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 332 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 333 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 334 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 335 /* Bonaire */ 336 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 337 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 338 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 339 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 340 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 341 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 342 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 343 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 344 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 345 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 346 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 347 /* Hawaii */ 348 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 349 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 350 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 351 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 352 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 353 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 354 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 355 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 356 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 357 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 358 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 359 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 360 /* Kabini */ 361 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 362 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 363 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 364 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 365 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 366 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 367 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 368 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 369 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 370 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 371 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 372 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 373 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 374 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 375 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 376 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 377 /* mullins */ 378 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 379 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 380 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 381 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 382 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 383 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 384 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 385 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 386 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 387 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 388 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 389 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 390 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 391 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 392 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 393 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 394 #endif 395 /* topaz */ 396 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 397 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 398 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 399 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 400 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 401 /* tonga */ 402 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 403 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 404 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 405 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 406 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 407 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 408 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 409 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 410 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 411 /* fiji */ 412 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 413 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 414 /* carrizo */ 415 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 416 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 417 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 418 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 419 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 420 /* stoney */ 421 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 422 /* Polaris11 */ 423 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 424 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 425 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 426 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 427 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 428 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 429 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 430 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 431 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 432 /* Polaris10 */ 433 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 434 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 435 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 436 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 437 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 438 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 439 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 440 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 441 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 442 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 443 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 444 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 445 /* Polaris12 */ 446 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 447 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 448 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 449 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 450 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 451 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 452 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 453 /* Vega 10 */ 454 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT}, 455 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT}, 456 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT}, 457 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT}, 458 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT}, 459 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT}, 460 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT}, 461 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT}, 462 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT}, 463 {0, 0, 0} 464 }; 465 466 MODULE_DEVICE_TABLE(pci, pciidlist); 467 468 static struct drm_driver kms_driver; 469 470 static int amdgpu_kick_out_firmware_fb(struct pci_dev *pdev) 471 { 472 struct apertures_struct *ap; 473 bool primary = false; 474 475 ap = alloc_apertures(1); 476 if (!ap) 477 return -ENOMEM; 478 479 ap->ranges[0].base = pci_resource_start(pdev, 0); 480 ap->ranges[0].size = pci_resource_len(pdev, 0); 481 482 #ifdef CONFIG_X86 483 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; 484 #endif 485 drm_fb_helper_remove_conflicting_framebuffers(ap, "amdgpudrmfb", primary); 486 kfree(ap); 487 488 return 0; 489 } 490 491 static int amdgpu_pci_probe(struct pci_dev *pdev, 492 const struct pci_device_id *ent) 493 { 494 unsigned long flags = ent->driver_data; 495 int ret; 496 497 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 498 DRM_INFO("This hardware requires experimental hardware support.\n" 499 "See modparam exp_hw_support\n"); 500 return -ENODEV; 501 } 502 503 /* 504 * Initialize amdkfd before starting radeon. If it was not loaded yet, 505 * defer radeon probing 506 */ 507 ret = amdgpu_amdkfd_init(); 508 if (ret == -EPROBE_DEFER) 509 return ret; 510 511 /* Get rid of things like offb */ 512 ret = amdgpu_kick_out_firmware_fb(pdev); 513 if (ret) 514 return ret; 515 516 return drm_get_pci_dev(pdev, ent, &kms_driver); 517 } 518 519 static void 520 amdgpu_pci_remove(struct pci_dev *pdev) 521 { 522 struct drm_device *dev = pci_get_drvdata(pdev); 523 524 drm_put_dev(dev); 525 } 526 527 static void 528 amdgpu_pci_shutdown(struct pci_dev *pdev) 529 { 530 struct drm_device *dev = pci_get_drvdata(pdev); 531 struct amdgpu_device *adev = dev->dev_private; 532 533 /* if we are running in a VM, make sure the device 534 * torn down properly on reboot/shutdown. 535 * unfortunately we can't detect certain 536 * hypervisors so just do this all the time. 537 */ 538 amdgpu_suspend(adev); 539 } 540 541 static int amdgpu_pmops_suspend(struct device *dev) 542 { 543 struct pci_dev *pdev = to_pci_dev(dev); 544 545 struct drm_device *drm_dev = pci_get_drvdata(pdev); 546 return amdgpu_device_suspend(drm_dev, true, true); 547 } 548 549 static int amdgpu_pmops_resume(struct device *dev) 550 { 551 struct pci_dev *pdev = to_pci_dev(dev); 552 struct drm_device *drm_dev = pci_get_drvdata(pdev); 553 554 /* GPU comes up enabled by the bios on resume */ 555 if (amdgpu_device_is_px(drm_dev)) { 556 pm_runtime_disable(dev); 557 pm_runtime_set_active(dev); 558 pm_runtime_enable(dev); 559 } 560 561 return amdgpu_device_resume(drm_dev, true, true); 562 } 563 564 static int amdgpu_pmops_freeze(struct device *dev) 565 { 566 struct pci_dev *pdev = to_pci_dev(dev); 567 568 struct drm_device *drm_dev = pci_get_drvdata(pdev); 569 return amdgpu_device_suspend(drm_dev, false, true); 570 } 571 572 static int amdgpu_pmops_thaw(struct device *dev) 573 { 574 struct pci_dev *pdev = to_pci_dev(dev); 575 576 struct drm_device *drm_dev = pci_get_drvdata(pdev); 577 return amdgpu_device_resume(drm_dev, false, true); 578 } 579 580 static int amdgpu_pmops_poweroff(struct device *dev) 581 { 582 struct pci_dev *pdev = to_pci_dev(dev); 583 584 struct drm_device *drm_dev = pci_get_drvdata(pdev); 585 return amdgpu_device_suspend(drm_dev, true, true); 586 } 587 588 static int amdgpu_pmops_restore(struct device *dev) 589 { 590 struct pci_dev *pdev = to_pci_dev(dev); 591 592 struct drm_device *drm_dev = pci_get_drvdata(pdev); 593 return amdgpu_device_resume(drm_dev, false, true); 594 } 595 596 static int amdgpu_pmops_runtime_suspend(struct device *dev) 597 { 598 struct pci_dev *pdev = to_pci_dev(dev); 599 struct drm_device *drm_dev = pci_get_drvdata(pdev); 600 int ret; 601 602 if (!amdgpu_device_is_px(drm_dev)) { 603 pm_runtime_forbid(dev); 604 return -EBUSY; 605 } 606 607 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 608 drm_kms_helper_poll_disable(drm_dev); 609 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF); 610 611 ret = amdgpu_device_suspend(drm_dev, false, false); 612 pci_save_state(pdev); 613 pci_disable_device(pdev); 614 pci_ignore_hotplug(pdev); 615 if (amdgpu_is_atpx_hybrid()) 616 pci_set_power_state(pdev, PCI_D3cold); 617 else if (!amdgpu_has_atpx_dgpu_power_cntl()) 618 pci_set_power_state(pdev, PCI_D3hot); 619 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 620 621 return 0; 622 } 623 624 static int amdgpu_pmops_runtime_resume(struct device *dev) 625 { 626 struct pci_dev *pdev = to_pci_dev(dev); 627 struct drm_device *drm_dev = pci_get_drvdata(pdev); 628 int ret; 629 630 if (!amdgpu_device_is_px(drm_dev)) 631 return -EINVAL; 632 633 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 634 635 if (amdgpu_is_atpx_hybrid() || 636 !amdgpu_has_atpx_dgpu_power_cntl()) 637 pci_set_power_state(pdev, PCI_D0); 638 pci_restore_state(pdev); 639 ret = pci_enable_device(pdev); 640 if (ret) 641 return ret; 642 pci_set_master(pdev); 643 644 ret = amdgpu_device_resume(drm_dev, false, false); 645 drm_kms_helper_poll_enable(drm_dev); 646 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON); 647 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 648 return 0; 649 } 650 651 static int amdgpu_pmops_runtime_idle(struct device *dev) 652 { 653 struct pci_dev *pdev = to_pci_dev(dev); 654 struct drm_device *drm_dev = pci_get_drvdata(pdev); 655 struct drm_crtc *crtc; 656 657 if (!amdgpu_device_is_px(drm_dev)) { 658 pm_runtime_forbid(dev); 659 return -EBUSY; 660 } 661 662 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 663 if (crtc->enabled) { 664 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 665 return -EBUSY; 666 } 667 } 668 669 pm_runtime_mark_last_busy(dev); 670 pm_runtime_autosuspend(dev); 671 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 672 return 1; 673 } 674 675 long amdgpu_drm_ioctl(struct file *filp, 676 unsigned int cmd, unsigned long arg) 677 { 678 struct drm_file *file_priv = filp->private_data; 679 struct drm_device *dev; 680 long ret; 681 dev = file_priv->minor->dev; 682 ret = pm_runtime_get_sync(dev->dev); 683 if (ret < 0) 684 return ret; 685 686 ret = drm_ioctl(filp, cmd, arg); 687 688 pm_runtime_mark_last_busy(dev->dev); 689 pm_runtime_put_autosuspend(dev->dev); 690 return ret; 691 } 692 693 static const struct dev_pm_ops amdgpu_pm_ops = { 694 .suspend = amdgpu_pmops_suspend, 695 .resume = amdgpu_pmops_resume, 696 .freeze = amdgpu_pmops_freeze, 697 .thaw = amdgpu_pmops_thaw, 698 .poweroff = amdgpu_pmops_poweroff, 699 .restore = amdgpu_pmops_restore, 700 .runtime_suspend = amdgpu_pmops_runtime_suspend, 701 .runtime_resume = amdgpu_pmops_runtime_resume, 702 .runtime_idle = amdgpu_pmops_runtime_idle, 703 }; 704 705 static const struct file_operations amdgpu_driver_kms_fops = { 706 .owner = THIS_MODULE, 707 .open = drm_open, 708 .release = drm_release, 709 .unlocked_ioctl = amdgpu_drm_ioctl, 710 .mmap = amdgpu_mmap, 711 .poll = drm_poll, 712 .read = drm_read, 713 #ifdef CONFIG_COMPAT 714 .compat_ioctl = amdgpu_kms_compat_ioctl, 715 #endif 716 }; 717 718 static struct drm_driver kms_driver = { 719 .driver_features = 720 DRIVER_USE_AGP | 721 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | 722 DRIVER_PRIME | DRIVER_RENDER | DRIVER_MODESET, 723 .load = amdgpu_driver_load_kms, 724 .open = amdgpu_driver_open_kms, 725 .postclose = amdgpu_driver_postclose_kms, 726 .lastclose = amdgpu_driver_lastclose_kms, 727 .set_busid = drm_pci_set_busid, 728 .unload = amdgpu_driver_unload_kms, 729 .get_vblank_counter = amdgpu_get_vblank_counter_kms, 730 .enable_vblank = amdgpu_enable_vblank_kms, 731 .disable_vblank = amdgpu_disable_vblank_kms, 732 .get_vblank_timestamp = amdgpu_get_vblank_timestamp_kms, 733 .get_scanout_position = amdgpu_get_crtc_scanoutpos, 734 #if defined(CONFIG_DEBUG_FS) 735 .debugfs_init = amdgpu_debugfs_init, 736 #endif 737 .irq_preinstall = amdgpu_irq_preinstall, 738 .irq_postinstall = amdgpu_irq_postinstall, 739 .irq_uninstall = amdgpu_irq_uninstall, 740 .irq_handler = amdgpu_irq_handler, 741 .ioctls = amdgpu_ioctls_kms, 742 .gem_free_object_unlocked = amdgpu_gem_object_free, 743 .gem_open_object = amdgpu_gem_object_open, 744 .gem_close_object = amdgpu_gem_object_close, 745 .dumb_create = amdgpu_mode_dumb_create, 746 .dumb_map_offset = amdgpu_mode_dumb_mmap, 747 .dumb_destroy = drm_gem_dumb_destroy, 748 .fops = &amdgpu_driver_kms_fops, 749 750 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 751 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 752 .gem_prime_export = amdgpu_gem_prime_export, 753 .gem_prime_import = drm_gem_prime_import, 754 .gem_prime_pin = amdgpu_gem_prime_pin, 755 .gem_prime_unpin = amdgpu_gem_prime_unpin, 756 .gem_prime_res_obj = amdgpu_gem_prime_res_obj, 757 .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table, 758 .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table, 759 .gem_prime_vmap = amdgpu_gem_prime_vmap, 760 .gem_prime_vunmap = amdgpu_gem_prime_vunmap, 761 762 .name = DRIVER_NAME, 763 .desc = DRIVER_DESC, 764 .date = DRIVER_DATE, 765 .major = KMS_DRIVER_MAJOR, 766 .minor = KMS_DRIVER_MINOR, 767 .patchlevel = KMS_DRIVER_PATCHLEVEL, 768 }; 769 770 static struct drm_driver *driver; 771 static struct pci_driver *pdriver; 772 773 static struct pci_driver amdgpu_kms_pci_driver = { 774 .name = DRIVER_NAME, 775 .id_table = pciidlist, 776 .probe = amdgpu_pci_probe, 777 .remove = amdgpu_pci_remove, 778 .shutdown = amdgpu_pci_shutdown, 779 .driver.pm = &amdgpu_pm_ops, 780 }; 781 782 783 784 static int __init amdgpu_init(void) 785 { 786 int r; 787 788 r = amdgpu_sync_init(); 789 if (r) 790 goto error_sync; 791 792 r = amdgpu_fence_slab_init(); 793 if (r) 794 goto error_fence; 795 796 r = amd_sched_fence_slab_init(); 797 if (r) 798 goto error_sched; 799 800 if (vgacon_text_force()) { 801 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); 802 return -EINVAL; 803 } 804 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 805 driver = &kms_driver; 806 pdriver = &amdgpu_kms_pci_driver; 807 driver->num_ioctls = amdgpu_max_kms_ioctl; 808 amdgpu_register_atpx_handler(); 809 /* let modprobe override vga console setting */ 810 return drm_pci_init(driver, pdriver); 811 812 error_sched: 813 amdgpu_fence_slab_fini(); 814 815 error_fence: 816 amdgpu_sync_fini(); 817 818 error_sync: 819 return r; 820 } 821 822 static void __exit amdgpu_exit(void) 823 { 824 amdgpu_amdkfd_fini(); 825 drm_pci_exit(driver, pdriver); 826 amdgpu_unregister_atpx_handler(); 827 amdgpu_sync_fini(); 828 amd_sched_fence_slab_fini(); 829 amdgpu_fence_slab_fini(); 830 } 831 832 module_init(amdgpu_init); 833 module_exit(amdgpu_exit); 834 835 MODULE_AUTHOR(DRIVER_AUTHOR); 836 MODULE_DESCRIPTION(DRIVER_DESC); 837 MODULE_LICENSE("GPL and additional rights"); 838