1 /** 2 * \file amdgpu_drv.c 3 * AMD Amdgpu driver 4 * 5 * \author Gareth Hughes <gareth@valinux.com> 6 */ 7 8 /* 9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 10 * All Rights Reserved. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a 13 * copy of this software and associated documentation files (the "Software"), 14 * to deal in the Software without restriction, including without limitation 15 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 16 * and/or sell copies of the Software, and to permit persons to whom the 17 * Software is furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice (including the next 20 * paragraph) shall be included in all copies or substantial portions of the 21 * Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 29 * OTHER DEALINGS IN THE SOFTWARE. 30 */ 31 32 #include <drm/drmP.h> 33 #include <drm/amdgpu_drm.h> 34 #include <drm/drm_gem.h> 35 #include "amdgpu_drv.h" 36 37 #include <drm/drm_pciids.h> 38 #include <linux/console.h> 39 #include <linux/module.h> 40 #include <linux/pm_runtime.h> 41 #include <linux/vga_switcheroo.h> 42 #include <drm/drm_crtc_helper.h> 43 44 #include "amdgpu.h" 45 #include "amdgpu_irq.h" 46 47 #include "amdgpu_amdkfd.h" 48 49 /* 50 * KMS wrapper. 51 * - 3.0.0 - initial driver 52 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 53 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 54 * at the end of IBs. 55 * - 3.3.0 - Add VM support for UVD on supported hardware. 56 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 57 * - 3.5.0 - Add support for new UVD_NO_OP register. 58 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 59 * - 3.7.0 - Add support for VCE clock list packet 60 * - 3.8.0 - Add support raster config init in the kernel 61 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 62 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 63 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 64 * - 3.12.0 - Add query for double offchip LDS buffers 65 * - 3.13.0 - Add PRT support 66 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 67 * - 3.15.0 - Export more gpu info for gfx9 68 * - 3.16.0 - Add reserved vmid support 69 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 70 * - 3.18.0 - Export gpu always on cu bitmap 71 * - 3.19.0 - Add support for UVD MJPEG decode 72 * - 3.20.0 - Add support for local BOs 73 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 74 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 75 * - 3.23.0 - Add query for VRAM lost counter 76 * - 3.24.0 - Add high priority compute support for gfx9 77 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 78 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 79 */ 80 #define KMS_DRIVER_MAJOR 3 81 #define KMS_DRIVER_MINOR 26 82 #define KMS_DRIVER_PATCHLEVEL 0 83 84 int amdgpu_vram_limit = 0; 85 int amdgpu_vis_vram_limit = 0; 86 int amdgpu_gart_size = -1; /* auto */ 87 int amdgpu_gtt_size = -1; /* auto */ 88 int amdgpu_moverate = -1; /* auto */ 89 int amdgpu_benchmarking = 0; 90 int amdgpu_testing = 0; 91 int amdgpu_audio = -1; 92 int amdgpu_disp_priority = 0; 93 int amdgpu_hw_i2c = 0; 94 int amdgpu_pcie_gen2 = -1; 95 int amdgpu_msi = -1; 96 int amdgpu_lockup_timeout = 10000; 97 int amdgpu_dpm = -1; 98 int amdgpu_fw_load_type = -1; 99 int amdgpu_aspm = -1; 100 int amdgpu_runtime_pm = -1; 101 uint amdgpu_ip_block_mask = 0xffffffff; 102 int amdgpu_bapm = -1; 103 int amdgpu_deep_color = 0; 104 int amdgpu_vm_size = -1; 105 int amdgpu_vm_fragment_size = -1; 106 int amdgpu_vm_block_size = -1; 107 int amdgpu_vm_fault_stop = 0; 108 int amdgpu_vm_debug = 0; 109 int amdgpu_vram_page_split = 512; 110 int amdgpu_vm_update_mode = -1; 111 int amdgpu_exp_hw_support = 0; 112 int amdgpu_dc = -1; 113 int amdgpu_dc_log = 0; 114 int amdgpu_sched_jobs = 32; 115 int amdgpu_sched_hw_submission = 2; 116 int amdgpu_no_evict = 0; 117 int amdgpu_direct_gma_size = 0; 118 uint amdgpu_pcie_gen_cap = 0; 119 uint amdgpu_pcie_lane_cap = 0; 120 uint amdgpu_cg_mask = 0xffffffff; 121 uint amdgpu_pg_mask = 0xffffffff; 122 uint amdgpu_sdma_phase_quantum = 32; 123 char *amdgpu_disable_cu = NULL; 124 char *amdgpu_virtual_display = NULL; 125 uint amdgpu_pp_feature_mask = 0xffff3fff; /* gfxoff (bit 15) disabled by default */ 126 int amdgpu_ngg = 0; 127 int amdgpu_prim_buf_per_se = 0; 128 int amdgpu_pos_buf_per_se = 0; 129 int amdgpu_cntl_sb_buf_per_se = 0; 130 int amdgpu_param_buf_per_se = 0; 131 int amdgpu_job_hang_limit = 0; 132 int amdgpu_lbpw = -1; 133 int amdgpu_compute_multipipe = -1; 134 int amdgpu_gpu_recovery = -1; /* auto */ 135 int amdgpu_emu_mode = 0; 136 uint amdgpu_smu_memory_pool_size = 0; 137 138 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 139 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 140 141 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 142 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 143 144 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); 145 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 146 147 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); 148 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 149 150 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 151 module_param_named(moverate, amdgpu_moverate, int, 0600); 152 153 MODULE_PARM_DESC(benchmark, "Run benchmark"); 154 module_param_named(benchmark, amdgpu_benchmarking, int, 0444); 155 156 MODULE_PARM_DESC(test, "Run tests"); 157 module_param_named(test, amdgpu_testing, int, 0444); 158 159 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 160 module_param_named(audio, amdgpu_audio, int, 0444); 161 162 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 163 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 164 165 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 166 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 167 168 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 169 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 170 171 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 172 module_param_named(msi, amdgpu_msi, int, 0444); 173 174 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms > 0 (default 10000)"); 175 module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444); 176 177 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 178 module_param_named(dpm, amdgpu_dpm, int, 0444); 179 180 MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)"); 181 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 182 183 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 184 module_param_named(aspm, amdgpu_aspm, int, 0444); 185 186 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 187 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 188 189 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 190 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 191 192 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 193 module_param_named(bapm, amdgpu_bapm, int, 0444); 194 195 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 196 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 197 198 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 199 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 200 201 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 202 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 203 204 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 205 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 206 207 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 208 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 209 210 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 211 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 212 213 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 214 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 215 216 MODULE_PARM_DESC(vram_page_split, "Number of pages after we split VRAM allocations (default 512, -1 = disable)"); 217 module_param_named(vram_page_split, amdgpu_vram_page_split, int, 0444); 218 219 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 220 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 221 222 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 223 module_param_named(dc, amdgpu_dc, int, 0444); 224 225 MODULE_PARM_DESC(dc_log, "Display Core Log Level (0 = minimal (default), 1 = chatty"); 226 module_param_named(dc_log, amdgpu_dc_log, int, 0444); 227 228 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 229 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 230 231 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 232 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 233 234 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 235 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, uint, 0444); 236 237 MODULE_PARM_DESC(no_evict, "Support pinning request from user space (1 = enable, 0 = disable (default))"); 238 module_param_named(no_evict, amdgpu_no_evict, int, 0444); 239 240 MODULE_PARM_DESC(direct_gma_size, "Direct GMA size in megabytes (max 96MB)"); 241 module_param_named(direct_gma_size, amdgpu_direct_gma_size, int, 0444); 242 243 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 244 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 245 246 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 247 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 248 249 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 250 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); 251 252 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 253 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 254 255 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 256 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 257 258 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 259 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 260 261 MODULE_PARM_DESC(virtual_display, 262 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 263 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 264 265 MODULE_PARM_DESC(ngg, "Next Generation Graphics (1 = enable, 0 = disable(default depending on gfx))"); 266 module_param_named(ngg, amdgpu_ngg, int, 0444); 267 268 MODULE_PARM_DESC(prim_buf_per_se, "the size of Primitive Buffer per Shader Engine (default depending on gfx)"); 269 module_param_named(prim_buf_per_se, amdgpu_prim_buf_per_se, int, 0444); 270 271 MODULE_PARM_DESC(pos_buf_per_se, "the size of Position Buffer per Shader Engine (default depending on gfx)"); 272 module_param_named(pos_buf_per_se, amdgpu_pos_buf_per_se, int, 0444); 273 274 MODULE_PARM_DESC(cntl_sb_buf_per_se, "the size of Control Sideband per Shader Engine (default depending on gfx)"); 275 module_param_named(cntl_sb_buf_per_se, amdgpu_cntl_sb_buf_per_se, int, 0444); 276 277 MODULE_PARM_DESC(param_buf_per_se, "the size of Off-Chip Pramater Cache per Shader Engine (default depending on gfx)"); 278 module_param_named(param_buf_per_se, amdgpu_param_buf_per_se, int, 0444); 279 280 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 281 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 282 283 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 284 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 285 286 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 287 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 288 289 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 290 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 291 292 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 293 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 294 295 #ifdef CONFIG_DRM_AMDGPU_SI 296 297 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 298 int amdgpu_si_support = 0; 299 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 300 #else 301 int amdgpu_si_support = 1; 302 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 303 #endif 304 305 module_param_named(si_support, amdgpu_si_support, int, 0444); 306 #endif 307 308 #ifdef CONFIG_DRM_AMDGPU_CIK 309 310 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 311 int amdgpu_cik_support = 0; 312 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 313 #else 314 int amdgpu_cik_support = 1; 315 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 316 #endif 317 318 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 319 #endif 320 321 MODULE_PARM_DESC(smu_memory_pool_size, 322 "reserve gtt for smu debug usage, 0 = disable," 323 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 324 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 325 326 static const struct pci_device_id pciidlist[] = { 327 #ifdef CONFIG_DRM_AMDGPU_SI 328 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 329 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 330 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 331 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 332 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 333 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 334 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 335 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 336 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 337 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 338 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 339 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 340 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 341 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 342 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 343 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 344 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 345 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 346 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 347 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 348 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 349 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 350 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 351 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 352 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 353 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 354 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 355 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 356 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 357 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 358 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 359 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 360 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 361 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 362 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 363 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 364 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 365 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 366 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 367 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 368 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 369 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 370 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 371 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 372 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 373 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 374 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 375 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 376 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 377 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 378 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 379 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 380 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 381 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 382 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 383 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 384 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 385 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 386 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 387 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 388 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 389 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 390 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 391 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 392 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 393 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 394 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 395 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 396 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 397 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 398 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 399 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 400 #endif 401 #ifdef CONFIG_DRM_AMDGPU_CIK 402 /* Kaveri */ 403 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 404 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 405 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 406 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 407 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 408 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 409 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 410 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 411 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 412 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 413 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 414 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 415 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 416 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 417 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 418 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 419 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 420 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 421 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 422 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 423 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 424 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 425 /* Bonaire */ 426 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 427 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 428 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 429 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 430 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 431 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 432 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 433 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 434 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 435 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 436 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 437 /* Hawaii */ 438 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 439 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 440 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 441 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 442 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 443 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 444 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 445 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 446 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 447 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 448 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 449 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 450 /* Kabini */ 451 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 452 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 453 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 454 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 455 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 456 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 457 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 458 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 459 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 460 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 461 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 462 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 463 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 464 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 465 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 466 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 467 /* mullins */ 468 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 469 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 470 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 471 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 472 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 473 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 474 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 475 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 476 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 477 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 478 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 479 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 480 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 481 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 482 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 483 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 484 #endif 485 /* topaz */ 486 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 487 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 488 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 489 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 490 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 491 /* tonga */ 492 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 493 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 494 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 495 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 496 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 497 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 498 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 499 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 500 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 501 /* fiji */ 502 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 503 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 504 /* carrizo */ 505 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 506 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 507 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 508 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 509 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 510 /* stoney */ 511 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 512 /* Polaris11 */ 513 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 514 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 515 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 516 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 517 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 518 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 519 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 520 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 521 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 522 /* Polaris10 */ 523 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 524 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 525 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 526 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 527 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 528 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 529 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 530 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 531 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 532 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 533 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 534 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 535 /* Polaris12 */ 536 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 537 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 538 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 539 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 540 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 541 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 542 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 543 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 544 /* VEGAM */ 545 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 546 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 547 /* Vega 10 */ 548 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 549 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 550 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 551 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 552 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 553 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 554 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 555 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 556 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 557 /* Vega 12 */ 558 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 559 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 560 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 561 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 562 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 563 /* Raven */ 564 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 565 566 {0, 0, 0} 567 }; 568 569 MODULE_DEVICE_TABLE(pci, pciidlist); 570 571 static struct drm_driver kms_driver; 572 573 static int amdgpu_kick_out_firmware_fb(struct pci_dev *pdev) 574 { 575 struct apertures_struct *ap; 576 bool primary = false; 577 578 ap = alloc_apertures(1); 579 if (!ap) 580 return -ENOMEM; 581 582 ap->ranges[0].base = pci_resource_start(pdev, 0); 583 ap->ranges[0].size = pci_resource_len(pdev, 0); 584 585 #ifdef CONFIG_X86 586 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; 587 #endif 588 drm_fb_helper_remove_conflicting_framebuffers(ap, "amdgpudrmfb", primary); 589 kfree(ap); 590 591 return 0; 592 } 593 594 595 static int amdgpu_pci_probe(struct pci_dev *pdev, 596 const struct pci_device_id *ent) 597 { 598 struct drm_device *dev; 599 unsigned long flags = ent->driver_data; 600 int ret, retry = 0; 601 bool supports_atomic = false; 602 603 if (!amdgpu_virtual_display && 604 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 605 supports_atomic = true; 606 607 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 608 DRM_INFO("This hardware requires experimental hardware support.\n" 609 "See modparam exp_hw_support\n"); 610 return -ENODEV; 611 } 612 613 /* 614 * Initialize amdkfd before starting radeon. If it was not loaded yet, 615 * defer radeon probing 616 */ 617 ret = amdgpu_amdkfd_init(); 618 if (ret == -EPROBE_DEFER) 619 return ret; 620 621 /* Get rid of things like offb */ 622 ret = amdgpu_kick_out_firmware_fb(pdev); 623 if (ret) 624 return ret; 625 626 /* warn the user if they mix atomic and non-atomic capable GPUs */ 627 if ((kms_driver.driver_features & DRIVER_ATOMIC) && !supports_atomic) 628 DRM_ERROR("Mixing atomic and non-atomic capable GPUs!\n"); 629 /* support atomic early so the atomic debugfs stuff gets created */ 630 if (supports_atomic) 631 kms_driver.driver_features |= DRIVER_ATOMIC; 632 633 dev = drm_dev_alloc(&kms_driver, &pdev->dev); 634 if (IS_ERR(dev)) 635 return PTR_ERR(dev); 636 637 ret = pci_enable_device(pdev); 638 if (ret) 639 goto err_free; 640 641 dev->pdev = pdev; 642 643 pci_set_drvdata(pdev, dev); 644 645 retry_init: 646 ret = drm_dev_register(dev, ent->driver_data); 647 if (ret == -EAGAIN && ++retry <= 3) { 648 DRM_INFO("retry init %d\n", retry); 649 /* Don't request EX mode too frequently which is attacking */ 650 msleep(5000); 651 goto retry_init; 652 } else if (ret) 653 goto err_pci; 654 655 return 0; 656 657 err_pci: 658 pci_disable_device(pdev); 659 err_free: 660 drm_dev_unref(dev); 661 return ret; 662 } 663 664 static void 665 amdgpu_pci_remove(struct pci_dev *pdev) 666 { 667 struct drm_device *dev = pci_get_drvdata(pdev); 668 669 drm_dev_unregister(dev); 670 drm_dev_unref(dev); 671 pci_disable_device(pdev); 672 pci_set_drvdata(pdev, NULL); 673 } 674 675 static void 676 amdgpu_pci_shutdown(struct pci_dev *pdev) 677 { 678 struct drm_device *dev = pci_get_drvdata(pdev); 679 struct amdgpu_device *adev = dev->dev_private; 680 681 /* if we are running in a VM, make sure the device 682 * torn down properly on reboot/shutdown. 683 * unfortunately we can't detect certain 684 * hypervisors so just do this all the time. 685 */ 686 amdgpu_device_ip_suspend(adev); 687 } 688 689 static int amdgpu_pmops_suspend(struct device *dev) 690 { 691 struct pci_dev *pdev = to_pci_dev(dev); 692 693 struct drm_device *drm_dev = pci_get_drvdata(pdev); 694 return amdgpu_device_suspend(drm_dev, true, true); 695 } 696 697 static int amdgpu_pmops_resume(struct device *dev) 698 { 699 struct pci_dev *pdev = to_pci_dev(dev); 700 struct drm_device *drm_dev = pci_get_drvdata(pdev); 701 702 /* GPU comes up enabled by the bios on resume */ 703 if (amdgpu_device_is_px(drm_dev)) { 704 pm_runtime_disable(dev); 705 pm_runtime_set_active(dev); 706 pm_runtime_enable(dev); 707 } 708 709 return amdgpu_device_resume(drm_dev, true, true); 710 } 711 712 static int amdgpu_pmops_freeze(struct device *dev) 713 { 714 struct pci_dev *pdev = to_pci_dev(dev); 715 716 struct drm_device *drm_dev = pci_get_drvdata(pdev); 717 return amdgpu_device_suspend(drm_dev, false, true); 718 } 719 720 static int amdgpu_pmops_thaw(struct device *dev) 721 { 722 struct pci_dev *pdev = to_pci_dev(dev); 723 724 struct drm_device *drm_dev = pci_get_drvdata(pdev); 725 return amdgpu_device_resume(drm_dev, false, true); 726 } 727 728 static int amdgpu_pmops_poweroff(struct device *dev) 729 { 730 struct pci_dev *pdev = to_pci_dev(dev); 731 732 struct drm_device *drm_dev = pci_get_drvdata(pdev); 733 return amdgpu_device_suspend(drm_dev, true, true); 734 } 735 736 static int amdgpu_pmops_restore(struct device *dev) 737 { 738 struct pci_dev *pdev = to_pci_dev(dev); 739 740 struct drm_device *drm_dev = pci_get_drvdata(pdev); 741 return amdgpu_device_resume(drm_dev, false, true); 742 } 743 744 static int amdgpu_pmops_runtime_suspend(struct device *dev) 745 { 746 struct pci_dev *pdev = to_pci_dev(dev); 747 struct drm_device *drm_dev = pci_get_drvdata(pdev); 748 int ret; 749 750 if (!amdgpu_device_is_px(drm_dev)) { 751 pm_runtime_forbid(dev); 752 return -EBUSY; 753 } 754 755 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 756 drm_kms_helper_poll_disable(drm_dev); 757 758 ret = amdgpu_device_suspend(drm_dev, false, false); 759 pci_save_state(pdev); 760 pci_disable_device(pdev); 761 pci_ignore_hotplug(pdev); 762 if (amdgpu_is_atpx_hybrid()) 763 pci_set_power_state(pdev, PCI_D3cold); 764 else if (!amdgpu_has_atpx_dgpu_power_cntl()) 765 pci_set_power_state(pdev, PCI_D3hot); 766 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 767 768 return 0; 769 } 770 771 static int amdgpu_pmops_runtime_resume(struct device *dev) 772 { 773 struct pci_dev *pdev = to_pci_dev(dev); 774 struct drm_device *drm_dev = pci_get_drvdata(pdev); 775 int ret; 776 777 if (!amdgpu_device_is_px(drm_dev)) 778 return -EINVAL; 779 780 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 781 782 if (amdgpu_is_atpx_hybrid() || 783 !amdgpu_has_atpx_dgpu_power_cntl()) 784 pci_set_power_state(pdev, PCI_D0); 785 pci_restore_state(pdev); 786 ret = pci_enable_device(pdev); 787 if (ret) 788 return ret; 789 pci_set_master(pdev); 790 791 ret = amdgpu_device_resume(drm_dev, false, false); 792 drm_kms_helper_poll_enable(drm_dev); 793 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 794 return 0; 795 } 796 797 static int amdgpu_pmops_runtime_idle(struct device *dev) 798 { 799 struct pci_dev *pdev = to_pci_dev(dev); 800 struct drm_device *drm_dev = pci_get_drvdata(pdev); 801 struct drm_crtc *crtc; 802 803 if (!amdgpu_device_is_px(drm_dev)) { 804 pm_runtime_forbid(dev); 805 return -EBUSY; 806 } 807 808 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 809 if (crtc->enabled) { 810 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 811 return -EBUSY; 812 } 813 } 814 815 pm_runtime_mark_last_busy(dev); 816 pm_runtime_autosuspend(dev); 817 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 818 return 1; 819 } 820 821 long amdgpu_drm_ioctl(struct file *filp, 822 unsigned int cmd, unsigned long arg) 823 { 824 struct drm_file *file_priv = filp->private_data; 825 struct drm_device *dev; 826 long ret; 827 dev = file_priv->minor->dev; 828 ret = pm_runtime_get_sync(dev->dev); 829 if (ret < 0) 830 return ret; 831 832 ret = drm_ioctl(filp, cmd, arg); 833 834 pm_runtime_mark_last_busy(dev->dev); 835 pm_runtime_put_autosuspend(dev->dev); 836 return ret; 837 } 838 839 static const struct dev_pm_ops amdgpu_pm_ops = { 840 .suspend = amdgpu_pmops_suspend, 841 .resume = amdgpu_pmops_resume, 842 .freeze = amdgpu_pmops_freeze, 843 .thaw = amdgpu_pmops_thaw, 844 .poweroff = amdgpu_pmops_poweroff, 845 .restore = amdgpu_pmops_restore, 846 .runtime_suspend = amdgpu_pmops_runtime_suspend, 847 .runtime_resume = amdgpu_pmops_runtime_resume, 848 .runtime_idle = amdgpu_pmops_runtime_idle, 849 }; 850 851 static const struct file_operations amdgpu_driver_kms_fops = { 852 .owner = THIS_MODULE, 853 .open = drm_open, 854 .release = drm_release, 855 .unlocked_ioctl = amdgpu_drm_ioctl, 856 .mmap = amdgpu_mmap, 857 .poll = drm_poll, 858 .read = drm_read, 859 #ifdef CONFIG_COMPAT 860 .compat_ioctl = amdgpu_kms_compat_ioctl, 861 #endif 862 }; 863 864 static bool 865 amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe, 866 bool in_vblank_irq, int *vpos, int *hpos, 867 ktime_t *stime, ktime_t *etime, 868 const struct drm_display_mode *mode) 869 { 870 return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos, 871 stime, etime, mode); 872 } 873 874 static struct drm_driver kms_driver = { 875 .driver_features = 876 DRIVER_USE_AGP | 877 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | 878 DRIVER_PRIME | DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ, 879 .load = amdgpu_driver_load_kms, 880 .open = amdgpu_driver_open_kms, 881 .postclose = amdgpu_driver_postclose_kms, 882 .lastclose = amdgpu_driver_lastclose_kms, 883 .unload = amdgpu_driver_unload_kms, 884 .get_vblank_counter = amdgpu_get_vblank_counter_kms, 885 .enable_vblank = amdgpu_enable_vblank_kms, 886 .disable_vblank = amdgpu_disable_vblank_kms, 887 .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos, 888 .get_scanout_position = amdgpu_get_crtc_scanout_position, 889 .irq_handler = amdgpu_irq_handler, 890 .ioctls = amdgpu_ioctls_kms, 891 .gem_free_object_unlocked = amdgpu_gem_object_free, 892 .gem_open_object = amdgpu_gem_object_open, 893 .gem_close_object = amdgpu_gem_object_close, 894 .dumb_create = amdgpu_mode_dumb_create, 895 .dumb_map_offset = amdgpu_mode_dumb_mmap, 896 .fops = &amdgpu_driver_kms_fops, 897 898 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 899 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 900 .gem_prime_export = amdgpu_gem_prime_export, 901 .gem_prime_import = amdgpu_gem_prime_import, 902 .gem_prime_res_obj = amdgpu_gem_prime_res_obj, 903 .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table, 904 .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table, 905 .gem_prime_vmap = amdgpu_gem_prime_vmap, 906 .gem_prime_vunmap = amdgpu_gem_prime_vunmap, 907 .gem_prime_mmap = amdgpu_gem_prime_mmap, 908 909 .name = DRIVER_NAME, 910 .desc = DRIVER_DESC, 911 .date = DRIVER_DATE, 912 .major = KMS_DRIVER_MAJOR, 913 .minor = KMS_DRIVER_MINOR, 914 .patchlevel = KMS_DRIVER_PATCHLEVEL, 915 }; 916 917 static struct drm_driver *driver; 918 static struct pci_driver *pdriver; 919 920 static struct pci_driver amdgpu_kms_pci_driver = { 921 .name = DRIVER_NAME, 922 .id_table = pciidlist, 923 .probe = amdgpu_pci_probe, 924 .remove = amdgpu_pci_remove, 925 .shutdown = amdgpu_pci_shutdown, 926 .driver.pm = &amdgpu_pm_ops, 927 }; 928 929 930 931 static int __init amdgpu_init(void) 932 { 933 int r; 934 935 if (vgacon_text_force()) { 936 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); 937 return -EINVAL; 938 } 939 940 r = amdgpu_sync_init(); 941 if (r) 942 goto error_sync; 943 944 r = amdgpu_fence_slab_init(); 945 if (r) 946 goto error_fence; 947 948 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 949 driver = &kms_driver; 950 pdriver = &amdgpu_kms_pci_driver; 951 driver->num_ioctls = amdgpu_max_kms_ioctl; 952 amdgpu_register_atpx_handler(); 953 /* let modprobe override vga console setting */ 954 return pci_register_driver(pdriver); 955 956 error_fence: 957 amdgpu_sync_fini(); 958 959 error_sync: 960 return r; 961 } 962 963 static void __exit amdgpu_exit(void) 964 { 965 amdgpu_amdkfd_fini(); 966 pci_unregister_driver(pdriver); 967 amdgpu_unregister_atpx_handler(); 968 amdgpu_sync_fini(); 969 amdgpu_fence_slab_fini(); 970 } 971 972 module_init(amdgpu_init); 973 module_exit(amdgpu_exit); 974 975 MODULE_AUTHOR(DRIVER_AUTHOR); 976 MODULE_DESCRIPTION(DRIVER_DESC); 977 MODULE_LICENSE("GPL and additional rights"); 978