1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_drv.h> 27 #include <drm/drm_fbdev_ttm.h> 28 #include <drm/drm_gem.h> 29 #include <drm/drm_managed.h> 30 #include <drm/drm_pciids.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/drm_vblank.h> 33 34 #include <linux/cc_platform.h> 35 #include <linux/dynamic_debug.h> 36 #include <linux/module.h> 37 #include <linux/mmu_notifier.h> 38 #include <linux/pm_runtime.h> 39 #include <linux/suspend.h> 40 #include <linux/vga_switcheroo.h> 41 42 #include "amdgpu.h" 43 #include "amdgpu_amdkfd.h" 44 #include "amdgpu_dma_buf.h" 45 #include "amdgpu_drv.h" 46 #include "amdgpu_fdinfo.h" 47 #include "amdgpu_irq.h" 48 #include "amdgpu_psp.h" 49 #include "amdgpu_ras.h" 50 #include "amdgpu_reset.h" 51 #include "amdgpu_sched.h" 52 #include "amdgpu_xgmi.h" 53 #include "../amdxcp/amdgpu_xcp_drv.h" 54 55 /* 56 * KMS wrapper. 57 * - 3.0.0 - initial driver 58 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 59 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 60 * at the end of IBs. 61 * - 3.3.0 - Add VM support for UVD on supported hardware. 62 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 63 * - 3.5.0 - Add support for new UVD_NO_OP register. 64 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 65 * - 3.7.0 - Add support for VCE clock list packet 66 * - 3.8.0 - Add support raster config init in the kernel 67 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 68 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 69 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 70 * - 3.12.0 - Add query for double offchip LDS buffers 71 * - 3.13.0 - Add PRT support 72 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 73 * - 3.15.0 - Export more gpu info for gfx9 74 * - 3.16.0 - Add reserved vmid support 75 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 76 * - 3.18.0 - Export gpu always on cu bitmap 77 * - 3.19.0 - Add support for UVD MJPEG decode 78 * - 3.20.0 - Add support for local BOs 79 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 80 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 81 * - 3.23.0 - Add query for VRAM lost counter 82 * - 3.24.0 - Add high priority compute support for gfx9 83 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 84 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 85 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation. 86 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 87 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 88 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 89 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 90 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 91 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 92 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 93 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 94 * - 3.36.0 - Allow reading more status registers on si/cik 95 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 96 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 97 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 98 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 99 * - 3.41.0 - Add video codec query 100 * - 3.42.0 - Add 16bpc fixed point display support 101 * - 3.43.0 - Add device hot plug/unplug support 102 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 103 * - 3.45.0 - Add context ioctl stable pstate interface 104 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm 105 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags 106 * - 3.48.0 - Add IP discovery version info to HW INFO 107 * - 3.49.0 - Add gang submit into CS IOCTL 108 * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock 109 * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock 110 * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl 111 * 3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields: 112 * tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size, 113 * gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi 114 * 3.53.0 - Support for GFX11 CP GFX shadowing 115 * 3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support 116 * - 3.55.0 - Add AMDGPU_INFO_GPUVM_FAULT query 117 * - 3.56.0 - Update IB start address and size alignment for decode and encode 118 * - 3.57.0 - Compute tunneling on GFX10+ 119 */ 120 #define KMS_DRIVER_MAJOR 3 121 #define KMS_DRIVER_MINOR 57 122 #define KMS_DRIVER_PATCHLEVEL 0 123 124 /* 125 * amdgpu.debug module options. Are all disabled by default 126 */ 127 enum AMDGPU_DEBUG_MASK { 128 AMDGPU_DEBUG_VM = BIT(0), 129 AMDGPU_DEBUG_LARGEBAR = BIT(1), 130 AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY = BIT(2), 131 AMDGPU_DEBUG_USE_VRAM_FW_BUF = BIT(3), 132 AMDGPU_DEBUG_ENABLE_RAS_ACA = BIT(4), 133 }; 134 135 unsigned int amdgpu_vram_limit = UINT_MAX; 136 int amdgpu_vis_vram_limit; 137 int amdgpu_gart_size = -1; /* auto */ 138 int amdgpu_gtt_size = -1; /* auto */ 139 int amdgpu_moverate = -1; /* auto */ 140 int amdgpu_audio = -1; 141 int amdgpu_disp_priority; 142 int amdgpu_hw_i2c; 143 int amdgpu_pcie_gen2 = -1; 144 int amdgpu_msi = -1; 145 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 146 int amdgpu_dpm = -1; 147 int amdgpu_fw_load_type = -1; 148 int amdgpu_aspm = -1; 149 int amdgpu_runtime_pm = -1; 150 uint amdgpu_ip_block_mask = 0xffffffff; 151 int amdgpu_bapm = -1; 152 int amdgpu_deep_color; 153 int amdgpu_vm_size = -1; 154 int amdgpu_vm_fragment_size = -1; 155 int amdgpu_vm_block_size = -1; 156 int amdgpu_vm_fault_stop; 157 int amdgpu_vm_update_mode = -1; 158 int amdgpu_exp_hw_support; 159 int amdgpu_dc = -1; 160 int amdgpu_sched_jobs = 32; 161 int amdgpu_sched_hw_submission = 2; 162 uint amdgpu_pcie_gen_cap; 163 uint amdgpu_pcie_lane_cap; 164 u64 amdgpu_cg_mask = 0xffffffffffffffff; 165 uint amdgpu_pg_mask = 0xffffffff; 166 uint amdgpu_sdma_phase_quantum = 32; 167 char *amdgpu_disable_cu; 168 char *amdgpu_virtual_display; 169 bool enforce_isolation; 170 /* 171 * OverDrive(bit 14) disabled by default 172 * GFX DCS(bit 19) disabled by default 173 */ 174 uint amdgpu_pp_feature_mask = 0xfff7bfff; 175 uint amdgpu_force_long_training; 176 int amdgpu_lbpw = -1; 177 int amdgpu_compute_multipipe = -1; 178 int amdgpu_gpu_recovery = -1; /* auto */ 179 int amdgpu_emu_mode; 180 uint amdgpu_smu_memory_pool_size; 181 int amdgpu_smu_pptable_id = -1; 182 /* 183 * FBC (bit 0) disabled by default 184 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 185 * - With this, for multiple monitors in sync(e.g. with the same model), 186 * mclk switching will be allowed. And the mclk will be not foced to the 187 * highest. That helps saving some idle power. 188 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 189 * PSR (bit 3) disabled by default 190 * EDP NO POWER SEQUENCING (bit 4) disabled by default 191 */ 192 uint amdgpu_dc_feature_mask = 2; 193 uint amdgpu_dc_debug_mask; 194 uint amdgpu_dc_visual_confirm; 195 int amdgpu_async_gfx_ring = 1; 196 int amdgpu_mcbp = -1; 197 int amdgpu_discovery = -1; 198 int amdgpu_mes; 199 int amdgpu_mes_log_enable = 0; 200 int amdgpu_mes_kiq; 201 int amdgpu_uni_mes = 1; 202 int amdgpu_noretry = -1; 203 int amdgpu_force_asic_type = -1; 204 int amdgpu_tmz = -1; /* auto */ 205 uint amdgpu_freesync_vid_mode; 206 int amdgpu_reset_method = -1; /* auto */ 207 int amdgpu_num_kcq = -1; 208 int amdgpu_smartshift_bias; 209 int amdgpu_use_xgmi_p2p = 1; 210 int amdgpu_vcnfw_log; 211 int amdgpu_sg_display = -1; /* auto */ 212 int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE; 213 int amdgpu_umsch_mm; 214 int amdgpu_seamless = -1; /* auto */ 215 uint amdgpu_debug_mask; 216 int amdgpu_agp = -1; /* auto */ 217 int amdgpu_wbrf = -1; 218 int amdgpu_damage_clips = -1; /* auto */ 219 int amdgpu_umsch_mm_fwlog; 220 221 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 222 223 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 224 "DRM_UT_CORE", 225 "DRM_UT_DRIVER", 226 "DRM_UT_KMS", 227 "DRM_UT_PRIME", 228 "DRM_UT_ATOMIC", 229 "DRM_UT_VBL", 230 "DRM_UT_STATE", 231 "DRM_UT_LEASE", 232 "DRM_UT_DP", 233 "DRM_UT_DRMRES"); 234 235 struct amdgpu_mgpu_info mgpu_info = { 236 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 237 .delayed_reset_work = __DELAYED_WORK_INITIALIZER( 238 mgpu_info.delayed_reset_work, 239 amdgpu_drv_delayed_reset_work_handler, 0), 240 }; 241 int amdgpu_ras_enable = -1; 242 uint amdgpu_ras_mask = 0xffffffff; 243 int amdgpu_bad_page_threshold = -1; 244 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 245 .timeout_fatal_disable = false, 246 .period = 0x0, /* default to 0x0 (timeout disable) */ 247 }; 248 249 /** 250 * DOC: vramlimit (int) 251 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 252 */ 253 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 254 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 255 256 /** 257 * DOC: vis_vramlimit (int) 258 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 259 */ 260 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 261 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 262 263 /** 264 * DOC: gartsize (uint) 265 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing. 266 * The default is -1 (The size depends on asic). 267 */ 268 MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)"); 269 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 270 271 /** 272 * DOC: gttsize (int) 273 * Restrict the size of GTT domain (for userspace use) in MiB for testing. 274 * The default is -1 (Use 1/2 RAM, minimum value is 3GB). 275 */ 276 MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)"); 277 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 278 279 /** 280 * DOC: moverate (int) 281 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 282 */ 283 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 284 module_param_named(moverate, amdgpu_moverate, int, 0600); 285 286 /** 287 * DOC: audio (int) 288 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 289 */ 290 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 291 module_param_named(audio, amdgpu_audio, int, 0444); 292 293 /** 294 * DOC: disp_priority (int) 295 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 296 */ 297 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 298 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 299 300 /** 301 * DOC: hw_i2c (int) 302 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 303 */ 304 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 305 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 306 307 /** 308 * DOC: pcie_gen2 (int) 309 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 310 */ 311 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 312 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 313 314 /** 315 * DOC: msi (int) 316 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 317 */ 318 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 319 module_param_named(msi, amdgpu_msi, int, 0444); 320 321 /** 322 * DOC: lockup_timeout (string) 323 * Set GPU scheduler timeout value in ms. 324 * 325 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 326 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 327 * to the default timeout. 328 * 329 * - With one value specified, the setting will apply to all non-compute jobs. 330 * - With multiple values specified, the first one will be for GFX. 331 * The second one is for Compute. The third and fourth ones are 332 * for SDMA and Video. 333 * 334 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 335 * jobs is 10000. The timeout for compute is 60000. 336 */ 337 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 338 "for passthrough or sriov, 10000 for all jobs. 0: keep default value. negative: infinity timeout), format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 339 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 340 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 341 342 /** 343 * DOC: dpm (int) 344 * Override for dynamic power management setting 345 * (0 = disable, 1 = enable) 346 * The default is -1 (auto). 347 */ 348 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 349 module_param_named(dpm, amdgpu_dpm, int, 0444); 350 351 /** 352 * DOC: fw_load_type (int) 353 * Set different firmware loading type for debugging, if supported. 354 * Set to 0 to force direct loading if supported by the ASIC. Set 355 * to -1 to select the default loading mode for the ASIC, as defined 356 * by the driver. The default is -1 (auto). 357 */ 358 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); 359 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 360 361 /** 362 * DOC: aspm (int) 363 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 364 */ 365 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 366 module_param_named(aspm, amdgpu_aspm, int, 0444); 367 368 /** 369 * DOC: runpm (int) 370 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 371 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 372 * Setting the value to 0 disables this functionality. 373 * Setting the value to -2 is auto enabled with power down when displays are attached. 374 */ 375 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto, -2 = auto with displays)"); 376 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 377 378 /** 379 * DOC: ip_block_mask (uint) 380 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 381 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 382 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 383 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 384 */ 385 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 386 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 387 388 /** 389 * DOC: bapm (int) 390 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 391 * The default -1 (auto, enabled) 392 */ 393 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 394 module_param_named(bapm, amdgpu_bapm, int, 0444); 395 396 /** 397 * DOC: deep_color (int) 398 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 399 */ 400 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 401 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 402 403 /** 404 * DOC: vm_size (int) 405 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 406 */ 407 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 408 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 409 410 /** 411 * DOC: vm_fragment_size (int) 412 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 413 */ 414 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 415 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 416 417 /** 418 * DOC: vm_block_size (int) 419 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 420 */ 421 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 422 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 423 424 /** 425 * DOC: vm_fault_stop (int) 426 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 427 */ 428 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 429 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 430 431 /** 432 * DOC: vm_update_mode (int) 433 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 434 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 435 */ 436 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 437 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 438 439 /** 440 * DOC: exp_hw_support (int) 441 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 442 */ 443 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 444 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 445 446 /** 447 * DOC: dc (int) 448 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 449 */ 450 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 451 module_param_named(dc, amdgpu_dc, int, 0444); 452 453 /** 454 * DOC: sched_jobs (int) 455 * Override the max number of jobs supported in the sw queue. The default is 32. 456 */ 457 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 458 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 459 460 /** 461 * DOC: sched_hw_submission (int) 462 * Override the max number of HW submissions. The default is 2. 463 */ 464 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 465 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 466 467 /** 468 * DOC: ppfeaturemask (hexint) 469 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 470 * The default is the current set of stable power features. 471 */ 472 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 473 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 474 475 /** 476 * DOC: forcelongtraining (uint) 477 * Force long memory training in resume. 478 * The default is zero, indicates short training in resume. 479 */ 480 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 481 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 482 483 /** 484 * DOC: pcie_gen_cap (uint) 485 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 486 * The default is 0 (automatic for each asic). 487 */ 488 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 489 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 490 491 /** 492 * DOC: pcie_lane_cap (uint) 493 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 494 * The default is 0 (automatic for each asic). 495 */ 496 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 497 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 498 499 /** 500 * DOC: cg_mask (ullong) 501 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 502 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 503 */ 504 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 505 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 506 507 /** 508 * DOC: pg_mask (uint) 509 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 510 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 511 */ 512 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 513 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 514 515 /** 516 * DOC: sdma_phase_quantum (uint) 517 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 518 */ 519 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 520 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 521 522 /** 523 * DOC: disable_cu (charp) 524 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 525 */ 526 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 527 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 528 529 /** 530 * DOC: virtual_display (charp) 531 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 532 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 533 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 534 * device at 26:00.0. The default is NULL. 535 */ 536 MODULE_PARM_DESC(virtual_display, 537 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 538 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 539 540 /** 541 * DOC: lbpw (int) 542 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 543 */ 544 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 545 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 546 547 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 548 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 549 550 /** 551 * DOC: gpu_recovery (int) 552 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 553 */ 554 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 555 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 556 557 /** 558 * DOC: emu_mode (int) 559 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 560 */ 561 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 562 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 563 564 /** 565 * DOC: ras_enable (int) 566 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 567 */ 568 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 569 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 570 571 /** 572 * DOC: ras_mask (uint) 573 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 574 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 575 */ 576 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 577 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 578 579 /** 580 * DOC: timeout_fatal_disable (bool) 581 * Disable Watchdog timeout fatal error event 582 */ 583 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 584 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 585 586 /** 587 * DOC: timeout_period (uint) 588 * Modify the watchdog timeout max_cycles as (1 << period) 589 */ 590 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 591 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 592 593 /** 594 * DOC: si_support (int) 595 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 596 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 597 * otherwise using amdgpu driver. 598 */ 599 #ifdef CONFIG_DRM_AMDGPU_SI 600 601 #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) 602 int amdgpu_si_support; 603 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 604 #else 605 int amdgpu_si_support = 1; 606 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 607 #endif 608 609 module_param_named(si_support, amdgpu_si_support, int, 0444); 610 #endif 611 612 /** 613 * DOC: cik_support (int) 614 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 615 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 616 * otherwise using amdgpu driver. 617 */ 618 #ifdef CONFIG_DRM_AMDGPU_CIK 619 620 #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) 621 int amdgpu_cik_support; 622 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 623 #else 624 int amdgpu_cik_support = 1; 625 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 626 #endif 627 628 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 629 #endif 630 631 /** 632 * DOC: smu_memory_pool_size (uint) 633 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 634 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 635 */ 636 MODULE_PARM_DESC(smu_memory_pool_size, 637 "reserve gtt for smu debug usage, 0 = disable,0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 638 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 639 640 /** 641 * DOC: async_gfx_ring (int) 642 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 643 */ 644 MODULE_PARM_DESC(async_gfx_ring, 645 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 646 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 647 648 /** 649 * DOC: mcbp (int) 650 * It is used to enable mid command buffer preemption. (0 = disabled, 1 = enabled, -1 auto (default)) 651 */ 652 MODULE_PARM_DESC(mcbp, 653 "Enable Mid-command buffer preemption (0 = disabled, 1 = enabled), -1 = auto (default)"); 654 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 655 656 /** 657 * DOC: discovery (int) 658 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 659 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 660 */ 661 MODULE_PARM_DESC(discovery, 662 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 663 module_param_named(discovery, amdgpu_discovery, int, 0444); 664 665 /** 666 * DOC: mes (int) 667 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 668 * (0 = disabled (default), 1 = enabled) 669 */ 670 MODULE_PARM_DESC(mes, 671 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 672 module_param_named(mes, amdgpu_mes, int, 0444); 673 674 /** 675 * DOC: mes_log_enable (int) 676 * Enable Micro Engine Scheduler log. This is used to enable/disable MES internal log. 677 * (0 = disabled (default), 1 = enabled) 678 */ 679 MODULE_PARM_DESC(mes_log_enable, 680 "Enable Micro Engine Scheduler log (0 = disabled (default), 1 = enabled)"); 681 module_param_named(mes_log_enable, amdgpu_mes_log_enable, int, 0444); 682 683 /** 684 * DOC: mes_kiq (int) 685 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq. 686 * (0 = disabled (default), 1 = enabled) 687 */ 688 MODULE_PARM_DESC(mes_kiq, 689 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)"); 690 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444); 691 692 /** 693 * DOC: uni_mes (int) 694 * Enable Unified Micro Engine Scheduler. This is a new engine pipe for unified scheduler. 695 * (0 = disabled (default), 1 = enabled) 696 */ 697 MODULE_PARM_DESC(uni_mes, 698 "Enable Unified Micro Engine Scheduler (0 = disabled, 1 = enabled(default)"); 699 module_param_named(uni_mes, amdgpu_uni_mes, int, 0444); 700 701 /** 702 * DOC: noretry (int) 703 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 704 * do not support per-process XNACK this also disables retry page faults. 705 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 706 */ 707 MODULE_PARM_DESC(noretry, 708 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 709 module_param_named(noretry, amdgpu_noretry, int, 0644); 710 711 /** 712 * DOC: force_asic_type (int) 713 * A non negative value used to specify the asic type for all supported GPUs. 714 */ 715 MODULE_PARM_DESC(force_asic_type, 716 "A non negative value used to specify the asic type for all supported GPUs"); 717 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 718 719 /** 720 * DOC: use_xgmi_p2p (int) 721 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 722 */ 723 MODULE_PARM_DESC(use_xgmi_p2p, 724 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 725 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 726 727 728 #ifdef CONFIG_HSA_AMD 729 /** 730 * DOC: sched_policy (int) 731 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 732 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 733 * assigns queues to HQDs. 734 */ 735 int sched_policy = KFD_SCHED_POLICY_HWS; 736 module_param(sched_policy, int, 0444); 737 MODULE_PARM_DESC(sched_policy, 738 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 739 740 /** 741 * DOC: hws_max_conc_proc (int) 742 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 743 * number of VMIDs assigned to the HWS, which is also the default. 744 */ 745 int hws_max_conc_proc = -1; 746 module_param(hws_max_conc_proc, int, 0444); 747 MODULE_PARM_DESC(hws_max_conc_proc, 748 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 749 750 /** 751 * DOC: cwsr_enable (int) 752 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 753 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 754 * disables it. 755 */ 756 int cwsr_enable = 1; 757 module_param(cwsr_enable, int, 0444); 758 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 759 760 /** 761 * DOC: max_num_of_queues_per_device (int) 762 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 763 * is 4096. 764 */ 765 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 766 module_param(max_num_of_queues_per_device, int, 0444); 767 MODULE_PARM_DESC(max_num_of_queues_per_device, 768 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 769 770 /** 771 * DOC: send_sigterm (int) 772 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 773 * but just print errors on dmesg. Setting 1 enables sending sigterm. 774 */ 775 int send_sigterm; 776 module_param(send_sigterm, int, 0444); 777 MODULE_PARM_DESC(send_sigterm, 778 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 779 780 /** 781 * DOC: halt_if_hws_hang (int) 782 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 783 * Setting 1 enables halt on hang. 784 */ 785 int halt_if_hws_hang; 786 module_param(halt_if_hws_hang, int, 0644); 787 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 788 789 /** 790 * DOC: hws_gws_support(bool) 791 * Assume that HWS supports GWS barriers regardless of what firmware version 792 * check says. Default value: false (rely on MEC2 firmware version check). 793 */ 794 bool hws_gws_support; 795 module_param(hws_gws_support, bool, 0444); 796 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 797 798 /** 799 * DOC: queue_preemption_timeout_ms (int) 800 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 801 */ 802 int queue_preemption_timeout_ms = 9000; 803 module_param(queue_preemption_timeout_ms, int, 0644); 804 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 805 806 /** 807 * DOC: debug_evictions(bool) 808 * Enable extra debug messages to help determine the cause of evictions 809 */ 810 bool debug_evictions; 811 module_param(debug_evictions, bool, 0644); 812 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 813 814 /** 815 * DOC: no_system_mem_limit(bool) 816 * Disable system memory limit, to support multiple process shared memory 817 */ 818 bool no_system_mem_limit; 819 module_param(no_system_mem_limit, bool, 0644); 820 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 821 822 /** 823 * DOC: no_queue_eviction_on_vm_fault (int) 824 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 825 */ 826 int amdgpu_no_queue_eviction_on_vm_fault; 827 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 828 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 829 #endif 830 831 /** 832 * DOC: mtype_local (int) 833 */ 834 int amdgpu_mtype_local; 835 MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (0 = MTYPE_RW (default), 1 = MTYPE_NC, 2 = MTYPE_CC)"); 836 module_param_named(mtype_local, amdgpu_mtype_local, int, 0444); 837 838 /** 839 * DOC: pcie_p2p (bool) 840 * Enable PCIe P2P (requires large-BAR). Default value: true (on) 841 */ 842 #ifdef CONFIG_HSA_AMD_P2P 843 bool pcie_p2p = true; 844 module_param(pcie_p2p, bool, 0444); 845 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); 846 #endif 847 848 /** 849 * DOC: dcfeaturemask (uint) 850 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 851 * The default is the current set of stable display features. 852 */ 853 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 854 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 855 856 /** 857 * DOC: dcdebugmask (uint) 858 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 859 */ 860 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 861 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 862 863 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)"); 864 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444); 865 866 /** 867 * DOC: abmlevel (uint) 868 * Override the default ABM (Adaptive Backlight Management) level used for DC 869 * enabled hardware. Requires DMCU to be supported and loaded. 870 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 871 * default. Values 1-4 control the maximum allowable brightness reduction via 872 * the ABM algorithm, with 1 being the least reduction and 4 being the most 873 * reduction. 874 * 875 * Defaults to -1, or disabled. Userspace can only override this level after 876 * boot if it's set to auto. 877 */ 878 int amdgpu_dm_abm_level = -1; 879 MODULE_PARM_DESC(abmlevel, 880 "ABM level (0 = off, 1-4 = backlight reduction level, -1 auto (default))"); 881 module_param_named(abmlevel, amdgpu_dm_abm_level, int, 0444); 882 883 int amdgpu_backlight = -1; 884 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 885 module_param_named(backlight, amdgpu_backlight, bint, 0444); 886 887 /** 888 * DOC: damageclips (int) 889 * Enable or disable damage clips support. If damage clips support is disabled, 890 * we will force full frame updates, irrespective of what user space sends to 891 * us. 892 * 893 * Defaults to -1 (where it is enabled unless a PSR-SU display is detected). 894 */ 895 MODULE_PARM_DESC(damageclips, 896 "Damage clips support (0 = disable, 1 = enable, -1 auto (default))"); 897 module_param_named(damageclips, amdgpu_damage_clips, int, 0444); 898 899 /** 900 * DOC: tmz (int) 901 * Trusted Memory Zone (TMZ) is a method to protect data being written 902 * to or read from memory. 903 * 904 * The default value: 0 (off). TODO: change to auto till it is completed. 905 */ 906 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 907 module_param_named(tmz, amdgpu_tmz, int, 0444); 908 909 /** 910 * DOC: freesync_video (uint) 911 * Enable the optimization to adjust front porch timing to achieve seamless 912 * mode change experience when setting a freesync supported mode for which full 913 * modeset is not needed. 914 * 915 * The Display Core will add a set of modes derived from the base FreeSync 916 * video mode into the corresponding connector's mode list based on commonly 917 * used refresh rates and VRR range of the connected display, when users enable 918 * this feature. From the userspace perspective, they can see a seamless mode 919 * change experience when the change between different refresh rates under the 920 * same resolution. Additionally, userspace applications such as Video playback 921 * can read this modeset list and change the refresh rate based on the video 922 * frame rate. Finally, the userspace can also derive an appropriate mode for a 923 * particular refresh rate based on the FreeSync Mode and add it to the 924 * connector's mode list. 925 * 926 * Note: This is an experimental feature. 927 * 928 * The default value: 0 (off). 929 */ 930 MODULE_PARM_DESC( 931 freesync_video, 932 "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)"); 933 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); 934 935 /** 936 * DOC: reset_method (int) 937 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 938 */ 939 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 940 module_param_named(reset_method, amdgpu_reset_method, int, 0644); 941 942 /** 943 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 944 * threshold value of faulty pages detected by RAS ECC, which may 945 * result in the GPU entering bad status when the number of total 946 * faulty pages by ECC exceeds the threshold value. 947 */ 948 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = driver sets threshold)"); 949 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 950 951 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 952 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 953 954 /** 955 * DOC: vcnfw_log (int) 956 * Enable vcnfw log output for debugging, the default is disabled. 957 */ 958 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 959 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 960 961 /** 962 * DOC: sg_display (int) 963 * Disable S/G (scatter/gather) display (i.e., display from system memory). 964 * This option is only relevant on APUs. Set this option to 0 to disable 965 * S/G display if you experience flickering or other issues under memory 966 * pressure and report the issue. 967 */ 968 MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)"); 969 module_param_named(sg_display, amdgpu_sg_display, int, 0444); 970 971 /** 972 * DOC: umsch_mm (int) 973 * Enable Multi Media User Mode Scheduler. This is a HW scheduling engine for VCN and VPE. 974 * (0 = disabled (default), 1 = enabled) 975 */ 976 MODULE_PARM_DESC(umsch_mm, 977 "Enable Multi Media User Mode Scheduler (0 = disabled (default), 1 = enabled)"); 978 module_param_named(umsch_mm, amdgpu_umsch_mm, int, 0444); 979 980 /** 981 * DOC: umsch_mm_fwlog (int) 982 * Enable umschfw log output for debugging, the default is disabled. 983 */ 984 MODULE_PARM_DESC(umsch_mm_fwlog, "Enable umschfw log(0 = disable (default value), 1 = enable)"); 985 module_param_named(umsch_mm_fwlog, amdgpu_umsch_mm_fwlog, int, 0444); 986 987 /** 988 * DOC: smu_pptable_id (int) 989 * Used to override pptable id. id = 0 use VBIOS pptable. 990 * id > 0 use the soft pptable with specicfied id. 991 */ 992 MODULE_PARM_DESC(smu_pptable_id, 993 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 994 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 995 996 /** 997 * DOC: partition_mode (int) 998 * Used to override the default SPX mode. 999 */ 1000 MODULE_PARM_DESC( 1001 user_partt_mode, 1002 "specify partition mode to be used (-2 = AMDGPU_AUTO_COMPUTE_PARTITION_MODE(default value) \ 1003 0 = AMDGPU_SPX_PARTITION_MODE, \ 1004 1 = AMDGPU_DPX_PARTITION_MODE, \ 1005 2 = AMDGPU_TPX_PARTITION_MODE, \ 1006 3 = AMDGPU_QPX_PARTITION_MODE, \ 1007 4 = AMDGPU_CPX_PARTITION_MODE)"); 1008 module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint, 0444); 1009 1010 1011 /** 1012 * DOC: enforce_isolation (bool) 1013 * enforce process isolation between graphics and compute via using the same reserved vmid. 1014 */ 1015 module_param(enforce_isolation, bool, 0444); 1016 MODULE_PARM_DESC(enforce_isolation, "enforce process isolation between graphics and compute . enforce_isolation = on"); 1017 1018 /** 1019 * DOC: seamless (int) 1020 * Seamless boot will keep the image on the screen during the boot process. 1021 */ 1022 MODULE_PARM_DESC(seamless, "Seamless boot (-1 = auto (default), 0 = disable, 1 = enable)"); 1023 module_param_named(seamless, amdgpu_seamless, int, 0444); 1024 1025 /** 1026 * DOC: debug_mask (uint) 1027 * Debug options for amdgpu, work as a binary mask with the following options: 1028 * 1029 * - 0x1: Debug VM handling 1030 * - 0x2: Enable simulating large-bar capability on non-large bar system. This 1031 * limits the VRAM size reported to ROCm applications to the visible 1032 * size, usually 256MB. 1033 * - 0x4: Disable GPU soft recovery, always do a full reset 1034 */ 1035 MODULE_PARM_DESC(debug_mask, "debug options for amdgpu, disabled by default"); 1036 module_param_named(debug_mask, amdgpu_debug_mask, uint, 0444); 1037 1038 /** 1039 * DOC: agp (int) 1040 * Enable the AGP aperture. This provides an aperture in the GPU's internal 1041 * address space for direct access to system memory. Note that these accesses 1042 * are non-snooped, so they are only used for access to uncached memory. 1043 */ 1044 MODULE_PARM_DESC(agp, "AGP (-1 = auto (default), 0 = disable, 1 = enable)"); 1045 module_param_named(agp, amdgpu_agp, int, 0444); 1046 1047 /** 1048 * DOC: wbrf (int) 1049 * Enable Wifi RFI interference mitigation feature. 1050 * Due to electrical and mechanical constraints there may be likely interference of 1051 * relatively high-powered harmonics of the (G-)DDR memory clocks with local radio 1052 * module frequency bands used by Wifi 6/6e/7. To mitigate the possible RFI interference, 1053 * with this feature enabled, PMFW will use either “shadowed P-State” or “P-State” based 1054 * on active list of frequencies in-use (to be avoided) as part of initial setting or 1055 * P-state transition. However, there may be potential performance impact with this 1056 * feature enabled. 1057 * (0 = disabled, 1 = enabled, -1 = auto (default setting, will be enabled if supported)) 1058 */ 1059 MODULE_PARM_DESC(wbrf, 1060 "Enable Wifi RFI interference mitigation (0 = disabled, 1 = enabled, -1 = auto(default)"); 1061 module_param_named(wbrf, amdgpu_wbrf, int, 0444); 1062 1063 /* These devices are not supported by amdgpu. 1064 * They are supported by the mach64, r128, radeon drivers 1065 */ 1066 static const u16 amdgpu_unsupported_pciidlist[] = { 1067 /* mach64 */ 1068 0x4354, 1069 0x4358, 1070 0x4554, 1071 0x4742, 1072 0x4744, 1073 0x4749, 1074 0x474C, 1075 0x474D, 1076 0x474E, 1077 0x474F, 1078 0x4750, 1079 0x4751, 1080 0x4752, 1081 0x4753, 1082 0x4754, 1083 0x4755, 1084 0x4756, 1085 0x4757, 1086 0x4758, 1087 0x4759, 1088 0x475A, 1089 0x4C42, 1090 0x4C44, 1091 0x4C47, 1092 0x4C49, 1093 0x4C4D, 1094 0x4C4E, 1095 0x4C50, 1096 0x4C51, 1097 0x4C52, 1098 0x4C53, 1099 0x5654, 1100 0x5655, 1101 0x5656, 1102 /* r128 */ 1103 0x4c45, 1104 0x4c46, 1105 0x4d46, 1106 0x4d4c, 1107 0x5041, 1108 0x5042, 1109 0x5043, 1110 0x5044, 1111 0x5045, 1112 0x5046, 1113 0x5047, 1114 0x5048, 1115 0x5049, 1116 0x504A, 1117 0x504B, 1118 0x504C, 1119 0x504D, 1120 0x504E, 1121 0x504F, 1122 0x5050, 1123 0x5051, 1124 0x5052, 1125 0x5053, 1126 0x5054, 1127 0x5055, 1128 0x5056, 1129 0x5057, 1130 0x5058, 1131 0x5245, 1132 0x5246, 1133 0x5247, 1134 0x524b, 1135 0x524c, 1136 0x534d, 1137 0x5446, 1138 0x544C, 1139 0x5452, 1140 /* radeon */ 1141 0x3150, 1142 0x3151, 1143 0x3152, 1144 0x3154, 1145 0x3155, 1146 0x3E50, 1147 0x3E54, 1148 0x4136, 1149 0x4137, 1150 0x4144, 1151 0x4145, 1152 0x4146, 1153 0x4147, 1154 0x4148, 1155 0x4149, 1156 0x414A, 1157 0x414B, 1158 0x4150, 1159 0x4151, 1160 0x4152, 1161 0x4153, 1162 0x4154, 1163 0x4155, 1164 0x4156, 1165 0x4237, 1166 0x4242, 1167 0x4336, 1168 0x4337, 1169 0x4437, 1170 0x4966, 1171 0x4967, 1172 0x4A48, 1173 0x4A49, 1174 0x4A4A, 1175 0x4A4B, 1176 0x4A4C, 1177 0x4A4D, 1178 0x4A4E, 1179 0x4A4F, 1180 0x4A50, 1181 0x4A54, 1182 0x4B48, 1183 0x4B49, 1184 0x4B4A, 1185 0x4B4B, 1186 0x4B4C, 1187 0x4C57, 1188 0x4C58, 1189 0x4C59, 1190 0x4C5A, 1191 0x4C64, 1192 0x4C66, 1193 0x4C67, 1194 0x4E44, 1195 0x4E45, 1196 0x4E46, 1197 0x4E47, 1198 0x4E48, 1199 0x4E49, 1200 0x4E4A, 1201 0x4E4B, 1202 0x4E50, 1203 0x4E51, 1204 0x4E52, 1205 0x4E53, 1206 0x4E54, 1207 0x4E56, 1208 0x5144, 1209 0x5145, 1210 0x5146, 1211 0x5147, 1212 0x5148, 1213 0x514C, 1214 0x514D, 1215 0x5157, 1216 0x5158, 1217 0x5159, 1218 0x515A, 1219 0x515E, 1220 0x5460, 1221 0x5462, 1222 0x5464, 1223 0x5548, 1224 0x5549, 1225 0x554A, 1226 0x554B, 1227 0x554C, 1228 0x554D, 1229 0x554E, 1230 0x554F, 1231 0x5550, 1232 0x5551, 1233 0x5552, 1234 0x5554, 1235 0x564A, 1236 0x564B, 1237 0x564F, 1238 0x5652, 1239 0x5653, 1240 0x5657, 1241 0x5834, 1242 0x5835, 1243 0x5954, 1244 0x5955, 1245 0x5974, 1246 0x5975, 1247 0x5960, 1248 0x5961, 1249 0x5962, 1250 0x5964, 1251 0x5965, 1252 0x5969, 1253 0x5a41, 1254 0x5a42, 1255 0x5a61, 1256 0x5a62, 1257 0x5b60, 1258 0x5b62, 1259 0x5b63, 1260 0x5b64, 1261 0x5b65, 1262 0x5c61, 1263 0x5c63, 1264 0x5d48, 1265 0x5d49, 1266 0x5d4a, 1267 0x5d4c, 1268 0x5d4d, 1269 0x5d4e, 1270 0x5d4f, 1271 0x5d50, 1272 0x5d52, 1273 0x5d57, 1274 0x5e48, 1275 0x5e4a, 1276 0x5e4b, 1277 0x5e4c, 1278 0x5e4d, 1279 0x5e4f, 1280 0x6700, 1281 0x6701, 1282 0x6702, 1283 0x6703, 1284 0x6704, 1285 0x6705, 1286 0x6706, 1287 0x6707, 1288 0x6708, 1289 0x6709, 1290 0x6718, 1291 0x6719, 1292 0x671c, 1293 0x671d, 1294 0x671f, 1295 0x6720, 1296 0x6721, 1297 0x6722, 1298 0x6723, 1299 0x6724, 1300 0x6725, 1301 0x6726, 1302 0x6727, 1303 0x6728, 1304 0x6729, 1305 0x6738, 1306 0x6739, 1307 0x673e, 1308 0x6740, 1309 0x6741, 1310 0x6742, 1311 0x6743, 1312 0x6744, 1313 0x6745, 1314 0x6746, 1315 0x6747, 1316 0x6748, 1317 0x6749, 1318 0x674A, 1319 0x6750, 1320 0x6751, 1321 0x6758, 1322 0x6759, 1323 0x675B, 1324 0x675D, 1325 0x675F, 1326 0x6760, 1327 0x6761, 1328 0x6762, 1329 0x6763, 1330 0x6764, 1331 0x6765, 1332 0x6766, 1333 0x6767, 1334 0x6768, 1335 0x6770, 1336 0x6771, 1337 0x6772, 1338 0x6778, 1339 0x6779, 1340 0x677B, 1341 0x6840, 1342 0x6841, 1343 0x6842, 1344 0x6843, 1345 0x6849, 1346 0x684C, 1347 0x6850, 1348 0x6858, 1349 0x6859, 1350 0x6880, 1351 0x6888, 1352 0x6889, 1353 0x688A, 1354 0x688C, 1355 0x688D, 1356 0x6898, 1357 0x6899, 1358 0x689b, 1359 0x689c, 1360 0x689d, 1361 0x689e, 1362 0x68a0, 1363 0x68a1, 1364 0x68a8, 1365 0x68a9, 1366 0x68b0, 1367 0x68b8, 1368 0x68b9, 1369 0x68ba, 1370 0x68be, 1371 0x68bf, 1372 0x68c0, 1373 0x68c1, 1374 0x68c7, 1375 0x68c8, 1376 0x68c9, 1377 0x68d8, 1378 0x68d9, 1379 0x68da, 1380 0x68de, 1381 0x68e0, 1382 0x68e1, 1383 0x68e4, 1384 0x68e5, 1385 0x68e8, 1386 0x68e9, 1387 0x68f1, 1388 0x68f2, 1389 0x68f8, 1390 0x68f9, 1391 0x68fa, 1392 0x68fe, 1393 0x7100, 1394 0x7101, 1395 0x7102, 1396 0x7103, 1397 0x7104, 1398 0x7105, 1399 0x7106, 1400 0x7108, 1401 0x7109, 1402 0x710A, 1403 0x710B, 1404 0x710C, 1405 0x710E, 1406 0x710F, 1407 0x7140, 1408 0x7141, 1409 0x7142, 1410 0x7143, 1411 0x7144, 1412 0x7145, 1413 0x7146, 1414 0x7147, 1415 0x7149, 1416 0x714A, 1417 0x714B, 1418 0x714C, 1419 0x714D, 1420 0x714E, 1421 0x714F, 1422 0x7151, 1423 0x7152, 1424 0x7153, 1425 0x715E, 1426 0x715F, 1427 0x7180, 1428 0x7181, 1429 0x7183, 1430 0x7186, 1431 0x7187, 1432 0x7188, 1433 0x718A, 1434 0x718B, 1435 0x718C, 1436 0x718D, 1437 0x718F, 1438 0x7193, 1439 0x7196, 1440 0x719B, 1441 0x719F, 1442 0x71C0, 1443 0x71C1, 1444 0x71C2, 1445 0x71C3, 1446 0x71C4, 1447 0x71C5, 1448 0x71C6, 1449 0x71C7, 1450 0x71CD, 1451 0x71CE, 1452 0x71D2, 1453 0x71D4, 1454 0x71D5, 1455 0x71D6, 1456 0x71DA, 1457 0x71DE, 1458 0x7200, 1459 0x7210, 1460 0x7211, 1461 0x7240, 1462 0x7243, 1463 0x7244, 1464 0x7245, 1465 0x7246, 1466 0x7247, 1467 0x7248, 1468 0x7249, 1469 0x724A, 1470 0x724B, 1471 0x724C, 1472 0x724D, 1473 0x724E, 1474 0x724F, 1475 0x7280, 1476 0x7281, 1477 0x7283, 1478 0x7284, 1479 0x7287, 1480 0x7288, 1481 0x7289, 1482 0x728B, 1483 0x728C, 1484 0x7290, 1485 0x7291, 1486 0x7293, 1487 0x7297, 1488 0x7834, 1489 0x7835, 1490 0x791e, 1491 0x791f, 1492 0x793f, 1493 0x7941, 1494 0x7942, 1495 0x796c, 1496 0x796d, 1497 0x796e, 1498 0x796f, 1499 0x9400, 1500 0x9401, 1501 0x9402, 1502 0x9403, 1503 0x9405, 1504 0x940A, 1505 0x940B, 1506 0x940F, 1507 0x94A0, 1508 0x94A1, 1509 0x94A3, 1510 0x94B1, 1511 0x94B3, 1512 0x94B4, 1513 0x94B5, 1514 0x94B9, 1515 0x9440, 1516 0x9441, 1517 0x9442, 1518 0x9443, 1519 0x9444, 1520 0x9446, 1521 0x944A, 1522 0x944B, 1523 0x944C, 1524 0x944E, 1525 0x9450, 1526 0x9452, 1527 0x9456, 1528 0x945A, 1529 0x945B, 1530 0x945E, 1531 0x9460, 1532 0x9462, 1533 0x946A, 1534 0x946B, 1535 0x947A, 1536 0x947B, 1537 0x9480, 1538 0x9487, 1539 0x9488, 1540 0x9489, 1541 0x948A, 1542 0x948F, 1543 0x9490, 1544 0x9491, 1545 0x9495, 1546 0x9498, 1547 0x949C, 1548 0x949E, 1549 0x949F, 1550 0x94C0, 1551 0x94C1, 1552 0x94C3, 1553 0x94C4, 1554 0x94C5, 1555 0x94C6, 1556 0x94C7, 1557 0x94C8, 1558 0x94C9, 1559 0x94CB, 1560 0x94CC, 1561 0x94CD, 1562 0x9500, 1563 0x9501, 1564 0x9504, 1565 0x9505, 1566 0x9506, 1567 0x9507, 1568 0x9508, 1569 0x9509, 1570 0x950F, 1571 0x9511, 1572 0x9515, 1573 0x9517, 1574 0x9519, 1575 0x9540, 1576 0x9541, 1577 0x9542, 1578 0x954E, 1579 0x954F, 1580 0x9552, 1581 0x9553, 1582 0x9555, 1583 0x9557, 1584 0x955f, 1585 0x9580, 1586 0x9581, 1587 0x9583, 1588 0x9586, 1589 0x9587, 1590 0x9588, 1591 0x9589, 1592 0x958A, 1593 0x958B, 1594 0x958C, 1595 0x958D, 1596 0x958E, 1597 0x958F, 1598 0x9590, 1599 0x9591, 1600 0x9593, 1601 0x9595, 1602 0x9596, 1603 0x9597, 1604 0x9598, 1605 0x9599, 1606 0x959B, 1607 0x95C0, 1608 0x95C2, 1609 0x95C4, 1610 0x95C5, 1611 0x95C6, 1612 0x95C7, 1613 0x95C9, 1614 0x95CC, 1615 0x95CD, 1616 0x95CE, 1617 0x95CF, 1618 0x9610, 1619 0x9611, 1620 0x9612, 1621 0x9613, 1622 0x9614, 1623 0x9615, 1624 0x9616, 1625 0x9640, 1626 0x9641, 1627 0x9642, 1628 0x9643, 1629 0x9644, 1630 0x9645, 1631 0x9647, 1632 0x9648, 1633 0x9649, 1634 0x964a, 1635 0x964b, 1636 0x964c, 1637 0x964e, 1638 0x964f, 1639 0x9710, 1640 0x9711, 1641 0x9712, 1642 0x9713, 1643 0x9714, 1644 0x9715, 1645 0x9802, 1646 0x9803, 1647 0x9804, 1648 0x9805, 1649 0x9806, 1650 0x9807, 1651 0x9808, 1652 0x9809, 1653 0x980A, 1654 0x9900, 1655 0x9901, 1656 0x9903, 1657 0x9904, 1658 0x9905, 1659 0x9906, 1660 0x9907, 1661 0x9908, 1662 0x9909, 1663 0x990A, 1664 0x990B, 1665 0x990C, 1666 0x990D, 1667 0x990E, 1668 0x990F, 1669 0x9910, 1670 0x9913, 1671 0x9917, 1672 0x9918, 1673 0x9919, 1674 0x9990, 1675 0x9991, 1676 0x9992, 1677 0x9993, 1678 0x9994, 1679 0x9995, 1680 0x9996, 1681 0x9997, 1682 0x9998, 1683 0x9999, 1684 0x999A, 1685 0x999B, 1686 0x999C, 1687 0x999D, 1688 0x99A0, 1689 0x99A2, 1690 0x99A4, 1691 /* radeon secondary ids */ 1692 0x3171, 1693 0x3e70, 1694 0x4164, 1695 0x4165, 1696 0x4166, 1697 0x4168, 1698 0x4170, 1699 0x4171, 1700 0x4172, 1701 0x4173, 1702 0x496e, 1703 0x4a69, 1704 0x4a6a, 1705 0x4a6b, 1706 0x4a70, 1707 0x4a74, 1708 0x4b69, 1709 0x4b6b, 1710 0x4b6c, 1711 0x4c6e, 1712 0x4e64, 1713 0x4e65, 1714 0x4e66, 1715 0x4e67, 1716 0x4e68, 1717 0x4e69, 1718 0x4e6a, 1719 0x4e71, 1720 0x4f73, 1721 0x5569, 1722 0x556b, 1723 0x556d, 1724 0x556f, 1725 0x5571, 1726 0x5854, 1727 0x5874, 1728 0x5940, 1729 0x5941, 1730 0x5b70, 1731 0x5b72, 1732 0x5b73, 1733 0x5b74, 1734 0x5b75, 1735 0x5d44, 1736 0x5d45, 1737 0x5d6d, 1738 0x5d6f, 1739 0x5d72, 1740 0x5d77, 1741 0x5e6b, 1742 0x5e6d, 1743 0x7120, 1744 0x7124, 1745 0x7129, 1746 0x712e, 1747 0x712f, 1748 0x7162, 1749 0x7163, 1750 0x7166, 1751 0x7167, 1752 0x7172, 1753 0x7173, 1754 0x71a0, 1755 0x71a1, 1756 0x71a3, 1757 0x71a7, 1758 0x71bb, 1759 0x71e0, 1760 0x71e1, 1761 0x71e2, 1762 0x71e6, 1763 0x71e7, 1764 0x71f2, 1765 0x7269, 1766 0x726b, 1767 0x726e, 1768 0x72a0, 1769 0x72a8, 1770 0x72b1, 1771 0x72b3, 1772 0x793f, 1773 }; 1774 1775 static const struct pci_device_id pciidlist[] = { 1776 #ifdef CONFIG_DRM_AMDGPU_SI 1777 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1778 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1779 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1780 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1781 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1782 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1783 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1784 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1785 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1786 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1787 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1788 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1789 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1790 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1791 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1792 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1793 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1794 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1795 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1796 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1797 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1798 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1799 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1800 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1801 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1802 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1803 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1804 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1805 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1806 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1807 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1808 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1809 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1810 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1811 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1812 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1813 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1814 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1815 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1816 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1817 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1818 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1819 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1820 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1821 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1822 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1823 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1824 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1825 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1826 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1827 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1828 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1829 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1830 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1831 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1832 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1833 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1834 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1835 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1836 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1837 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1838 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1839 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1840 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1841 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1842 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1843 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1844 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1845 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1846 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1847 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1848 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1849 #endif 1850 #ifdef CONFIG_DRM_AMDGPU_CIK 1851 /* Kaveri */ 1852 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1853 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1854 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1855 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1856 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1857 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1858 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1859 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1860 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1861 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1862 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1863 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1864 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1865 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1866 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1867 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1868 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1869 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1870 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1871 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1872 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1873 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1874 /* Bonaire */ 1875 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1876 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1877 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1878 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1879 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1880 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1881 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1882 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1883 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1884 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1885 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1886 /* Hawaii */ 1887 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1888 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1889 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1890 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1891 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1892 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1893 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1894 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1895 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1896 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1897 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1898 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1899 /* Kabini */ 1900 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1901 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1902 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1903 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1904 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1905 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1906 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1907 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1908 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1909 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1910 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1911 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1912 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1913 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1914 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1915 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1916 /* mullins */ 1917 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1918 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1919 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1920 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1921 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1922 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1923 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1924 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1925 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1926 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1927 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1928 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1929 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1930 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1931 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1932 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1933 #endif 1934 /* topaz */ 1935 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1936 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1937 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1938 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1939 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1940 /* tonga */ 1941 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1942 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1943 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1944 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1945 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1946 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1947 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1948 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1949 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1950 /* fiji */ 1951 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1952 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1953 /* carrizo */ 1954 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1955 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1956 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1957 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1958 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1959 /* stoney */ 1960 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1961 /* Polaris11 */ 1962 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1963 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1964 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1965 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1966 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1967 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1968 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1969 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1970 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1971 /* Polaris10 */ 1972 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1973 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1974 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1975 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1976 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1977 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1978 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1979 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1980 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1981 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1982 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1983 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1984 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1985 /* Polaris12 */ 1986 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1987 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1988 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1989 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1990 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1991 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1992 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1993 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1994 /* VEGAM */ 1995 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1996 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1997 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1998 /* Vega 10 */ 1999 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2000 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2001 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2002 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2003 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2004 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2005 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2006 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2007 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2008 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2009 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2010 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2011 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2012 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2013 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2014 /* Vega 12 */ 2015 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2016 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2017 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2018 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2019 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2020 /* Vega 20 */ 2021 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2022 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2023 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2024 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2025 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2026 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2027 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2028 /* Raven */ 2029 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 2030 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 2031 /* Arcturus */ 2032 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2033 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2034 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2035 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2036 /* Navi10 */ 2037 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2038 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2039 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2040 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2041 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2042 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2043 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2044 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2045 /* Navi14 */ 2046 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2047 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2048 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2049 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2050 2051 /* Renoir */ 2052 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2053 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2054 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2055 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2056 2057 /* Navi12 */ 2058 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 2059 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 2060 2061 /* Sienna_Cichlid */ 2062 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2063 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2064 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2065 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2066 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2067 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2068 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2069 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2070 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2071 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2072 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2073 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2074 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2075 2076 /* Yellow Carp */ 2077 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 2078 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 2079 2080 /* Navy_Flounder */ 2081 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2082 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2083 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2084 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2085 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2086 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2087 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2088 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2089 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2090 2091 /* DIMGREY_CAVEFISH */ 2092 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2093 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2094 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2095 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2096 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2097 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2098 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2099 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2100 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2101 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2102 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2103 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2104 2105 /* Aldebaran */ 2106 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2107 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2108 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2109 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2110 2111 /* CYAN_SKILLFISH */ 2112 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2113 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2114 2115 /* BEIGE_GOBY */ 2116 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2117 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2118 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2119 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2120 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2121 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2122 2123 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2124 .class = PCI_CLASS_DISPLAY_VGA << 8, 2125 .class_mask = 0xffffff, 2126 .driver_data = CHIP_IP_DISCOVERY }, 2127 2128 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2129 .class = PCI_CLASS_DISPLAY_OTHER << 8, 2130 .class_mask = 0xffffff, 2131 .driver_data = CHIP_IP_DISCOVERY }, 2132 2133 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2134 .class = PCI_CLASS_ACCELERATOR_PROCESSING << 8, 2135 .class_mask = 0xffffff, 2136 .driver_data = CHIP_IP_DISCOVERY }, 2137 2138 {0, 0, 0} 2139 }; 2140 2141 MODULE_DEVICE_TABLE(pci, pciidlist); 2142 2143 static const struct amdgpu_asic_type_quirk asic_type_quirks[] = { 2144 /* differentiate between P10 and P11 asics with the same DID */ 2145 {0x67FF, 0xE3, CHIP_POLARIS10}, 2146 {0x67FF, 0xE7, CHIP_POLARIS10}, 2147 {0x67FF, 0xF3, CHIP_POLARIS10}, 2148 {0x67FF, 0xF7, CHIP_POLARIS10}, 2149 }; 2150 2151 static const struct drm_driver amdgpu_kms_driver; 2152 2153 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 2154 { 2155 struct pci_dev *p = NULL; 2156 int i; 2157 2158 /* 0 - GPU 2159 * 1 - audio 2160 * 2 - USB 2161 * 3 - UCSI 2162 */ 2163 for (i = 1; i < 4; i++) { 2164 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 2165 adev->pdev->bus->number, i); 2166 if (p) { 2167 pm_runtime_get_sync(&p->dev); 2168 pm_runtime_mark_last_busy(&p->dev); 2169 pm_runtime_put_autosuspend(&p->dev); 2170 pci_dev_put(p); 2171 } 2172 } 2173 } 2174 2175 static void amdgpu_init_debug_options(struct amdgpu_device *adev) 2176 { 2177 if (amdgpu_debug_mask & AMDGPU_DEBUG_VM) { 2178 pr_info("debug: VM handling debug enabled\n"); 2179 adev->debug_vm = true; 2180 } 2181 2182 if (amdgpu_debug_mask & AMDGPU_DEBUG_LARGEBAR) { 2183 pr_info("debug: enabled simulating large-bar capability on non-large bar system\n"); 2184 adev->debug_largebar = true; 2185 } 2186 2187 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY) { 2188 pr_info("debug: soft reset for GPU recovery disabled\n"); 2189 adev->debug_disable_soft_recovery = true; 2190 } 2191 2192 if (amdgpu_debug_mask & AMDGPU_DEBUG_USE_VRAM_FW_BUF) { 2193 pr_info("debug: place fw in vram for frontdoor loading\n"); 2194 adev->debug_use_vram_fw_buf = true; 2195 } 2196 2197 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_RAS_ACA) { 2198 pr_info("debug: enable RAS ACA\n"); 2199 adev->debug_enable_ras_aca = true; 2200 } 2201 } 2202 2203 static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long flags) 2204 { 2205 int i; 2206 2207 for (i = 0; i < ARRAY_SIZE(asic_type_quirks); i++) { 2208 if (pdev->device == asic_type_quirks[i].device && 2209 pdev->revision == asic_type_quirks[i].revision) { 2210 flags &= ~AMD_ASIC_MASK; 2211 flags |= asic_type_quirks[i].type; 2212 break; 2213 } 2214 } 2215 2216 return flags; 2217 } 2218 2219 static int amdgpu_pci_probe(struct pci_dev *pdev, 2220 const struct pci_device_id *ent) 2221 { 2222 struct drm_device *ddev; 2223 struct amdgpu_device *adev; 2224 unsigned long flags = ent->driver_data; 2225 int ret, retry = 0, i; 2226 bool supports_atomic = false; 2227 2228 /* skip devices which are owned by radeon */ 2229 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2230 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2231 return -ENODEV; 2232 } 2233 2234 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) 2235 amdgpu_aspm = 0; 2236 2237 if (amdgpu_virtual_display || 2238 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 2239 supports_atomic = true; 2240 2241 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2242 DRM_INFO("This hardware requires experimental hardware support.\n" 2243 "See modparam exp_hw_support\n"); 2244 return -ENODEV; 2245 } 2246 2247 flags = amdgpu_fix_asic_type(pdev, flags); 2248 2249 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2250 * however, SME requires an indirect IOMMU mapping because the encryption 2251 * bit is beyond the DMA mask of the chip. 2252 */ 2253 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2254 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2255 dev_info(&pdev->dev, 2256 "SME is not compatible with RAVEN\n"); 2257 return -ENOTSUPP; 2258 } 2259 2260 #ifdef CONFIG_DRM_AMDGPU_SI 2261 if (!amdgpu_si_support) { 2262 switch (flags & AMD_ASIC_MASK) { 2263 case CHIP_TAHITI: 2264 case CHIP_PITCAIRN: 2265 case CHIP_VERDE: 2266 case CHIP_OLAND: 2267 case CHIP_HAINAN: 2268 dev_info(&pdev->dev, 2269 "SI support provided by radeon.\n"); 2270 dev_info(&pdev->dev, 2271 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 2272 ); 2273 return -ENODEV; 2274 } 2275 } 2276 #endif 2277 #ifdef CONFIG_DRM_AMDGPU_CIK 2278 if (!amdgpu_cik_support) { 2279 switch (flags & AMD_ASIC_MASK) { 2280 case CHIP_KAVERI: 2281 case CHIP_BONAIRE: 2282 case CHIP_HAWAII: 2283 case CHIP_KABINI: 2284 case CHIP_MULLINS: 2285 dev_info(&pdev->dev, 2286 "CIK support provided by radeon.\n"); 2287 dev_info(&pdev->dev, 2288 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 2289 ); 2290 return -ENODEV; 2291 } 2292 } 2293 #endif 2294 2295 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2296 if (IS_ERR(adev)) 2297 return PTR_ERR(adev); 2298 2299 adev->dev = &pdev->dev; 2300 adev->pdev = pdev; 2301 ddev = adev_to_drm(adev); 2302 2303 if (!supports_atomic) 2304 ddev->driver_features &= ~DRIVER_ATOMIC; 2305 2306 ret = pci_enable_device(pdev); 2307 if (ret) 2308 return ret; 2309 2310 pci_set_drvdata(pdev, ddev); 2311 2312 amdgpu_init_debug_options(adev); 2313 2314 ret = amdgpu_driver_load_kms(adev, flags); 2315 if (ret) 2316 goto err_pci; 2317 2318 retry_init: 2319 ret = drm_dev_register(ddev, flags); 2320 if (ret == -EAGAIN && ++retry <= 3) { 2321 DRM_INFO("retry init %d\n", retry); 2322 /* Don't request EX mode too frequently which is attacking */ 2323 msleep(5000); 2324 goto retry_init; 2325 } else if (ret) { 2326 goto err_pci; 2327 } 2328 2329 ret = amdgpu_xcp_dev_register(adev, ent); 2330 if (ret) 2331 goto err_pci; 2332 2333 ret = amdgpu_amdkfd_drm_client_create(adev); 2334 if (ret) 2335 goto err_pci; 2336 2337 /* 2338 * 1. don't init fbdev on hw without DCE 2339 * 2. don't init fbdev if there are no connectors 2340 */ 2341 if (adev->mode_info.mode_config_initialized && 2342 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2343 /* select 8 bpp console on low vram cards */ 2344 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2345 drm_fbdev_ttm_setup(adev_to_drm(adev), 8); 2346 else 2347 drm_fbdev_ttm_setup(adev_to_drm(adev), 32); 2348 } 2349 2350 ret = amdgpu_debugfs_init(adev); 2351 if (ret) 2352 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2353 2354 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2355 /* only need to skip on ATPX */ 2356 if (amdgpu_device_supports_px(ddev)) 2357 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2358 /* we want direct complete for BOCO */ 2359 if (amdgpu_device_supports_boco(ddev)) 2360 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2361 DPM_FLAG_SMART_SUSPEND | 2362 DPM_FLAG_MAY_SKIP_RESUME); 2363 pm_runtime_use_autosuspend(ddev->dev); 2364 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2365 2366 pm_runtime_allow(ddev->dev); 2367 2368 pm_runtime_mark_last_busy(ddev->dev); 2369 pm_runtime_put_autosuspend(ddev->dev); 2370 2371 pci_wake_from_d3(pdev, TRUE); 2372 2373 /* 2374 * For runpm implemented via BACO, PMFW will handle the 2375 * timing for BACO in and out: 2376 * - put ASIC into BACO state only when both video and 2377 * audio functions are in D3 state. 2378 * - pull ASIC out of BACO state when either video or 2379 * audio function is in D0 state. 2380 * Also, at startup, PMFW assumes both functions are in 2381 * D0 state. 2382 * 2383 * So if snd driver was loaded prior to amdgpu driver 2384 * and audio function was put into D3 state, there will 2385 * be no PMFW-aware D-state transition(D0->D3) on runpm 2386 * suspend. Thus the BACO will be not correctly kicked in. 2387 * 2388 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2389 * into D0 state. Then there will be a PMFW-aware D-state 2390 * transition(D0->D3) on runpm suspend. 2391 */ 2392 if (amdgpu_device_supports_baco(ddev) && 2393 !(adev->flags & AMD_IS_APU) && 2394 (adev->asic_type >= CHIP_NAVI10)) 2395 amdgpu_get_secondary_funcs(adev); 2396 } 2397 2398 return 0; 2399 2400 err_pci: 2401 pci_disable_device(pdev); 2402 return ret; 2403 } 2404 2405 static void 2406 amdgpu_pci_remove(struct pci_dev *pdev) 2407 { 2408 struct drm_device *dev = pci_get_drvdata(pdev); 2409 struct amdgpu_device *adev = drm_to_adev(dev); 2410 2411 amdgpu_xcp_dev_unplug(adev); 2412 drm_dev_unplug(dev); 2413 2414 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2415 pm_runtime_get_sync(dev->dev); 2416 pm_runtime_forbid(dev->dev); 2417 } 2418 2419 amdgpu_driver_unload_kms(dev); 2420 2421 /* 2422 * Flush any in flight DMA operations from device. 2423 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2424 * StatusTransactions Pending bit. 2425 */ 2426 pci_disable_device(pdev); 2427 pci_wait_for_pending_transaction(pdev); 2428 } 2429 2430 static void 2431 amdgpu_pci_shutdown(struct pci_dev *pdev) 2432 { 2433 struct drm_device *dev = pci_get_drvdata(pdev); 2434 struct amdgpu_device *adev = drm_to_adev(dev); 2435 2436 if (amdgpu_ras_intr_triggered()) 2437 return; 2438 2439 /* if we are running in a VM, make sure the device 2440 * torn down properly on reboot/shutdown. 2441 * unfortunately we can't detect certain 2442 * hypervisors so just do this all the time. 2443 */ 2444 if (!amdgpu_passthrough(adev)) 2445 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2446 amdgpu_device_ip_suspend(adev); 2447 adev->mp1_state = PP_MP1_STATE_NONE; 2448 } 2449 2450 /** 2451 * amdgpu_drv_delayed_reset_work_handler - work handler for reset 2452 * 2453 * @work: work_struct. 2454 */ 2455 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) 2456 { 2457 struct list_head device_list; 2458 struct amdgpu_device *adev; 2459 int i, r; 2460 struct amdgpu_reset_context reset_context; 2461 2462 memset(&reset_context, 0, sizeof(reset_context)); 2463 2464 mutex_lock(&mgpu_info.mutex); 2465 if (mgpu_info.pending_reset == true) { 2466 mutex_unlock(&mgpu_info.mutex); 2467 return; 2468 } 2469 mgpu_info.pending_reset = true; 2470 mutex_unlock(&mgpu_info.mutex); 2471 2472 /* Use a common context, just need to make sure full reset is done */ 2473 reset_context.method = AMD_RESET_METHOD_NONE; 2474 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2475 2476 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2477 adev = mgpu_info.gpu_ins[i].adev; 2478 reset_context.reset_req_dev = adev; 2479 r = amdgpu_device_pre_asic_reset(adev, &reset_context); 2480 if (r) { 2481 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", 2482 r, adev_to_drm(adev)->unique); 2483 } 2484 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) 2485 r = -EALREADY; 2486 } 2487 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2488 adev = mgpu_info.gpu_ins[i].adev; 2489 flush_work(&adev->xgmi_reset_work); 2490 adev->gmc.xgmi.pending_reset = false; 2491 } 2492 2493 /* reset function will rebuild the xgmi hive info , clear it now */ 2494 for (i = 0; i < mgpu_info.num_dgpu; i++) 2495 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); 2496 2497 INIT_LIST_HEAD(&device_list); 2498 2499 for (i = 0; i < mgpu_info.num_dgpu; i++) 2500 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); 2501 2502 /* unregister the GPU first, reset function will add them back */ 2503 list_for_each_entry(adev, &device_list, reset_list) 2504 amdgpu_unregister_gpu_instance(adev); 2505 2506 /* Use a common context, just need to make sure full reset is done */ 2507 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); 2508 set_bit(AMDGPU_SKIP_COREDUMP, &reset_context.flags); 2509 r = amdgpu_do_asic_reset(&device_list, &reset_context); 2510 2511 if (r) { 2512 DRM_ERROR("reinit gpus failure"); 2513 return; 2514 } 2515 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2516 adev = mgpu_info.gpu_ins[i].adev; 2517 if (!adev->kfd.init_complete) { 2518 kgd2kfd_init_zone_device(adev); 2519 amdgpu_amdkfd_device_init(adev); 2520 amdgpu_amdkfd_drm_client_create(adev); 2521 } 2522 amdgpu_ttm_set_buffer_funcs_status(adev, true); 2523 } 2524 } 2525 2526 static int amdgpu_pmops_prepare(struct device *dev) 2527 { 2528 struct drm_device *drm_dev = dev_get_drvdata(dev); 2529 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2530 2531 /* Return a positive number here so 2532 * DPM_FLAG_SMART_SUSPEND works properly 2533 */ 2534 if (amdgpu_device_supports_boco(drm_dev) && 2535 pm_runtime_suspended(dev)) 2536 return 1; 2537 2538 /* if we will not support s3 or s2i for the device 2539 * then skip suspend 2540 */ 2541 if (!amdgpu_acpi_is_s0ix_active(adev) && 2542 !amdgpu_acpi_is_s3_active(adev)) 2543 return 1; 2544 2545 return amdgpu_device_prepare(drm_dev); 2546 } 2547 2548 static void amdgpu_pmops_complete(struct device *dev) 2549 { 2550 /* nothing to do */ 2551 } 2552 2553 static int amdgpu_pmops_suspend(struct device *dev) 2554 { 2555 struct drm_device *drm_dev = dev_get_drvdata(dev); 2556 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2557 2558 adev->suspend_complete = false; 2559 if (amdgpu_acpi_is_s0ix_active(adev)) 2560 adev->in_s0ix = true; 2561 else if (amdgpu_acpi_is_s3_active(adev)) 2562 adev->in_s3 = true; 2563 if (!adev->in_s0ix && !adev->in_s3) 2564 return 0; 2565 return amdgpu_device_suspend(drm_dev, true); 2566 } 2567 2568 static int amdgpu_pmops_suspend_noirq(struct device *dev) 2569 { 2570 struct drm_device *drm_dev = dev_get_drvdata(dev); 2571 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2572 2573 adev->suspend_complete = true; 2574 if (amdgpu_acpi_should_gpu_reset(adev)) 2575 return amdgpu_asic_reset(adev); 2576 2577 return 0; 2578 } 2579 2580 static int amdgpu_pmops_resume(struct device *dev) 2581 { 2582 struct drm_device *drm_dev = dev_get_drvdata(dev); 2583 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2584 int r; 2585 2586 if (!adev->in_s0ix && !adev->in_s3) 2587 return 0; 2588 2589 /* Avoids registers access if device is physically gone */ 2590 if (!pci_device_is_present(adev->pdev)) 2591 adev->no_hw_access = true; 2592 2593 r = amdgpu_device_resume(drm_dev, true); 2594 if (amdgpu_acpi_is_s0ix_active(adev)) 2595 adev->in_s0ix = false; 2596 else 2597 adev->in_s3 = false; 2598 return r; 2599 } 2600 2601 static int amdgpu_pmops_freeze(struct device *dev) 2602 { 2603 struct drm_device *drm_dev = dev_get_drvdata(dev); 2604 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2605 int r; 2606 2607 adev->in_s4 = true; 2608 r = amdgpu_device_suspend(drm_dev, true); 2609 adev->in_s4 = false; 2610 if (r) 2611 return r; 2612 2613 if (amdgpu_acpi_should_gpu_reset(adev)) 2614 return amdgpu_asic_reset(adev); 2615 return 0; 2616 } 2617 2618 static int amdgpu_pmops_thaw(struct device *dev) 2619 { 2620 struct drm_device *drm_dev = dev_get_drvdata(dev); 2621 2622 return amdgpu_device_resume(drm_dev, true); 2623 } 2624 2625 static int amdgpu_pmops_poweroff(struct device *dev) 2626 { 2627 struct drm_device *drm_dev = dev_get_drvdata(dev); 2628 2629 return amdgpu_device_suspend(drm_dev, true); 2630 } 2631 2632 static int amdgpu_pmops_restore(struct device *dev) 2633 { 2634 struct drm_device *drm_dev = dev_get_drvdata(dev); 2635 2636 return amdgpu_device_resume(drm_dev, true); 2637 } 2638 2639 static int amdgpu_runtime_idle_check_display(struct device *dev) 2640 { 2641 struct pci_dev *pdev = to_pci_dev(dev); 2642 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2643 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2644 2645 if (adev->mode_info.num_crtc) { 2646 struct drm_connector *list_connector; 2647 struct drm_connector_list_iter iter; 2648 int ret = 0; 2649 2650 if (amdgpu_runtime_pm != -2) { 2651 /* XXX: Return busy if any displays are connected to avoid 2652 * possible display wakeups after runtime resume due to 2653 * hotplug events in case any displays were connected while 2654 * the GPU was in suspend. Remove this once that is fixed. 2655 */ 2656 mutex_lock(&drm_dev->mode_config.mutex); 2657 drm_connector_list_iter_begin(drm_dev, &iter); 2658 drm_for_each_connector_iter(list_connector, &iter) { 2659 if (list_connector->status == connector_status_connected) { 2660 ret = -EBUSY; 2661 break; 2662 } 2663 } 2664 drm_connector_list_iter_end(&iter); 2665 mutex_unlock(&drm_dev->mode_config.mutex); 2666 2667 if (ret) 2668 return ret; 2669 } 2670 2671 if (adev->dc_enabled) { 2672 struct drm_crtc *crtc; 2673 2674 drm_for_each_crtc(crtc, drm_dev) { 2675 drm_modeset_lock(&crtc->mutex, NULL); 2676 if (crtc->state->active) 2677 ret = -EBUSY; 2678 drm_modeset_unlock(&crtc->mutex); 2679 if (ret < 0) 2680 break; 2681 } 2682 } else { 2683 mutex_lock(&drm_dev->mode_config.mutex); 2684 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2685 2686 drm_connector_list_iter_begin(drm_dev, &iter); 2687 drm_for_each_connector_iter(list_connector, &iter) { 2688 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2689 ret = -EBUSY; 2690 break; 2691 } 2692 } 2693 2694 drm_connector_list_iter_end(&iter); 2695 2696 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2697 mutex_unlock(&drm_dev->mode_config.mutex); 2698 } 2699 if (ret) 2700 return ret; 2701 } 2702 2703 return 0; 2704 } 2705 2706 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2707 { 2708 struct pci_dev *pdev = to_pci_dev(dev); 2709 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2710 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2711 int ret, i; 2712 2713 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2714 pm_runtime_forbid(dev); 2715 return -EBUSY; 2716 } 2717 2718 ret = amdgpu_runtime_idle_check_display(dev); 2719 if (ret) 2720 return ret; 2721 2722 /* wait for all rings to drain before suspending */ 2723 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2724 struct amdgpu_ring *ring = adev->rings[i]; 2725 2726 if (ring && ring->sched.ready) { 2727 ret = amdgpu_fence_wait_empty(ring); 2728 if (ret) 2729 return -EBUSY; 2730 } 2731 } 2732 2733 adev->in_runpm = true; 2734 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2735 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2736 2737 /* 2738 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2739 * proper cleanups and put itself into a state ready for PNP. That 2740 * can address some random resuming failure observed on BOCO capable 2741 * platforms. 2742 * TODO: this may be also needed for PX capable platform. 2743 */ 2744 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2745 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2746 2747 ret = amdgpu_device_prepare(drm_dev); 2748 if (ret) 2749 return ret; 2750 ret = amdgpu_device_suspend(drm_dev, false); 2751 if (ret) { 2752 adev->in_runpm = false; 2753 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2754 adev->mp1_state = PP_MP1_STATE_NONE; 2755 return ret; 2756 } 2757 2758 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2759 adev->mp1_state = PP_MP1_STATE_NONE; 2760 2761 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) { 2762 /* Only need to handle PCI state in the driver for ATPX 2763 * PCI core handles it for _PR3. 2764 */ 2765 amdgpu_device_cache_pci_state(pdev); 2766 pci_disable_device(pdev); 2767 pci_ignore_hotplug(pdev); 2768 pci_set_power_state(pdev, PCI_D3cold); 2769 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2770 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) { 2771 /* nothing to do */ 2772 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2773 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) { 2774 amdgpu_device_baco_enter(drm_dev); 2775 } 2776 2777 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n"); 2778 2779 return 0; 2780 } 2781 2782 static int amdgpu_pmops_runtime_resume(struct device *dev) 2783 { 2784 struct pci_dev *pdev = to_pci_dev(dev); 2785 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2786 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2787 int ret; 2788 2789 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) 2790 return -EINVAL; 2791 2792 /* Avoids registers access if device is physically gone */ 2793 if (!pci_device_is_present(adev->pdev)) 2794 adev->no_hw_access = true; 2795 2796 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) { 2797 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2798 2799 /* Only need to handle PCI state in the driver for ATPX 2800 * PCI core handles it for _PR3. 2801 */ 2802 pci_set_power_state(pdev, PCI_D0); 2803 amdgpu_device_load_pci_state(pdev); 2804 ret = pci_enable_device(pdev); 2805 if (ret) 2806 return ret; 2807 pci_set_master(pdev); 2808 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) { 2809 /* Only need to handle PCI state in the driver for ATPX 2810 * PCI core handles it for _PR3. 2811 */ 2812 pci_set_master(pdev); 2813 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2814 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) { 2815 amdgpu_device_baco_exit(drm_dev); 2816 } 2817 ret = amdgpu_device_resume(drm_dev, false); 2818 if (ret) { 2819 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2820 pci_disable_device(pdev); 2821 return ret; 2822 } 2823 2824 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2825 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2826 adev->in_runpm = false; 2827 return 0; 2828 } 2829 2830 static int amdgpu_pmops_runtime_idle(struct device *dev) 2831 { 2832 struct drm_device *drm_dev = dev_get_drvdata(dev); 2833 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2834 int ret; 2835 2836 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2837 pm_runtime_forbid(dev); 2838 return -EBUSY; 2839 } 2840 2841 ret = amdgpu_runtime_idle_check_display(dev); 2842 2843 pm_runtime_mark_last_busy(dev); 2844 pm_runtime_autosuspend(dev); 2845 return ret; 2846 } 2847 2848 long amdgpu_drm_ioctl(struct file *filp, 2849 unsigned int cmd, unsigned long arg) 2850 { 2851 struct drm_file *file_priv = filp->private_data; 2852 struct drm_device *dev; 2853 long ret; 2854 2855 dev = file_priv->minor->dev; 2856 ret = pm_runtime_get_sync(dev->dev); 2857 if (ret < 0) 2858 goto out; 2859 2860 ret = drm_ioctl(filp, cmd, arg); 2861 2862 pm_runtime_mark_last_busy(dev->dev); 2863 out: 2864 pm_runtime_put_autosuspend(dev->dev); 2865 return ret; 2866 } 2867 2868 static const struct dev_pm_ops amdgpu_pm_ops = { 2869 .prepare = amdgpu_pmops_prepare, 2870 .complete = amdgpu_pmops_complete, 2871 .suspend = amdgpu_pmops_suspend, 2872 .suspend_noirq = amdgpu_pmops_suspend_noirq, 2873 .resume = amdgpu_pmops_resume, 2874 .freeze = amdgpu_pmops_freeze, 2875 .thaw = amdgpu_pmops_thaw, 2876 .poweroff = amdgpu_pmops_poweroff, 2877 .restore = amdgpu_pmops_restore, 2878 .runtime_suspend = amdgpu_pmops_runtime_suspend, 2879 .runtime_resume = amdgpu_pmops_runtime_resume, 2880 .runtime_idle = amdgpu_pmops_runtime_idle, 2881 }; 2882 2883 static int amdgpu_flush(struct file *f, fl_owner_t id) 2884 { 2885 struct drm_file *file_priv = f->private_data; 2886 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2887 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2888 2889 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 2890 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 2891 2892 return timeout >= 0 ? 0 : timeout; 2893 } 2894 2895 static const struct file_operations amdgpu_driver_kms_fops = { 2896 .owner = THIS_MODULE, 2897 .open = drm_open, 2898 .flush = amdgpu_flush, 2899 .release = drm_release, 2900 .unlocked_ioctl = amdgpu_drm_ioctl, 2901 .mmap = drm_gem_mmap, 2902 .poll = drm_poll, 2903 .read = drm_read, 2904 #ifdef CONFIG_COMPAT 2905 .compat_ioctl = amdgpu_kms_compat_ioctl, 2906 #endif 2907 #ifdef CONFIG_PROC_FS 2908 .show_fdinfo = drm_show_fdinfo, 2909 #endif 2910 }; 2911 2912 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 2913 { 2914 struct drm_file *file; 2915 2916 if (!filp) 2917 return -EINVAL; 2918 2919 if (filp->f_op != &amdgpu_driver_kms_fops) 2920 return -EINVAL; 2921 2922 file = filp->private_data; 2923 *fpriv = file->driver_priv; 2924 return 0; 2925 } 2926 2927 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 2928 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2929 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2930 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2931 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 2932 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2933 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2934 /* KMS */ 2935 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2936 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2937 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2938 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2939 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2940 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2941 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2942 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2943 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2944 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2945 }; 2946 2947 static const struct drm_driver amdgpu_kms_driver = { 2948 .driver_features = 2949 DRIVER_ATOMIC | 2950 DRIVER_GEM | 2951 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 2952 DRIVER_SYNCOBJ_TIMELINE, 2953 .open = amdgpu_driver_open_kms, 2954 .postclose = amdgpu_driver_postclose_kms, 2955 .lastclose = amdgpu_driver_lastclose_kms, 2956 .ioctls = amdgpu_ioctls_kms, 2957 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2958 .dumb_create = amdgpu_mode_dumb_create, 2959 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2960 .fops = &amdgpu_driver_kms_fops, 2961 .release = &amdgpu_driver_release_kms, 2962 #ifdef CONFIG_PROC_FS 2963 .show_fdinfo = amdgpu_show_fdinfo, 2964 #endif 2965 2966 .gem_prime_import = amdgpu_gem_prime_import, 2967 2968 .name = DRIVER_NAME, 2969 .desc = DRIVER_DESC, 2970 .date = DRIVER_DATE, 2971 .major = KMS_DRIVER_MAJOR, 2972 .minor = KMS_DRIVER_MINOR, 2973 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2974 }; 2975 2976 const struct drm_driver amdgpu_partition_driver = { 2977 .driver_features = 2978 DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ | 2979 DRIVER_SYNCOBJ_TIMELINE, 2980 .open = amdgpu_driver_open_kms, 2981 .postclose = amdgpu_driver_postclose_kms, 2982 .lastclose = amdgpu_driver_lastclose_kms, 2983 .ioctls = amdgpu_ioctls_kms, 2984 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2985 .dumb_create = amdgpu_mode_dumb_create, 2986 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2987 .fops = &amdgpu_driver_kms_fops, 2988 .release = &amdgpu_driver_release_kms, 2989 2990 .gem_prime_import = amdgpu_gem_prime_import, 2991 2992 .name = DRIVER_NAME, 2993 .desc = DRIVER_DESC, 2994 .date = DRIVER_DATE, 2995 .major = KMS_DRIVER_MAJOR, 2996 .minor = KMS_DRIVER_MINOR, 2997 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2998 }; 2999 3000 static struct pci_error_handlers amdgpu_pci_err_handler = { 3001 .error_detected = amdgpu_pci_error_detected, 3002 .mmio_enabled = amdgpu_pci_mmio_enabled, 3003 .slot_reset = amdgpu_pci_slot_reset, 3004 .resume = amdgpu_pci_resume, 3005 }; 3006 3007 static const struct attribute_group *amdgpu_sysfs_groups[] = { 3008 &amdgpu_vram_mgr_attr_group, 3009 &amdgpu_gtt_mgr_attr_group, 3010 &amdgpu_flash_attr_group, 3011 NULL, 3012 }; 3013 3014 static struct pci_driver amdgpu_kms_pci_driver = { 3015 .name = DRIVER_NAME, 3016 .id_table = pciidlist, 3017 .probe = amdgpu_pci_probe, 3018 .remove = amdgpu_pci_remove, 3019 .shutdown = amdgpu_pci_shutdown, 3020 .driver.pm = &amdgpu_pm_ops, 3021 .err_handler = &amdgpu_pci_err_handler, 3022 .dev_groups = amdgpu_sysfs_groups, 3023 }; 3024 3025 static int __init amdgpu_init(void) 3026 { 3027 int r; 3028 3029 if (drm_firmware_drivers_only()) 3030 return -EINVAL; 3031 3032 r = amdgpu_sync_init(); 3033 if (r) 3034 goto error_sync; 3035 3036 r = amdgpu_fence_slab_init(); 3037 if (r) 3038 goto error_fence; 3039 3040 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 3041 amdgpu_register_atpx_handler(); 3042 amdgpu_acpi_detect(); 3043 3044 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 3045 amdgpu_amdkfd_init(); 3046 3047 /* let modprobe override vga console setting */ 3048 return pci_register_driver(&amdgpu_kms_pci_driver); 3049 3050 error_fence: 3051 amdgpu_sync_fini(); 3052 3053 error_sync: 3054 return r; 3055 } 3056 3057 static void __exit amdgpu_exit(void) 3058 { 3059 amdgpu_amdkfd_fini(); 3060 pci_unregister_driver(&amdgpu_kms_pci_driver); 3061 amdgpu_unregister_atpx_handler(); 3062 amdgpu_acpi_release(); 3063 amdgpu_sync_fini(); 3064 amdgpu_fence_slab_fini(); 3065 mmu_notifier_synchronize(); 3066 amdgpu_xcp_drv_release(); 3067 } 3068 3069 module_init(amdgpu_init); 3070 module_exit(amdgpu_exit); 3071 3072 MODULE_AUTHOR(DRIVER_AUTHOR); 3073 MODULE_DESCRIPTION(DRIVER_DESC); 3074 MODULE_LICENSE("GPL and additional rights"); 3075