1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_drv.h> 27 #include <drm/drm_fbdev_generic.h> 28 #include <drm/drm_gem.h> 29 #include <drm/drm_vblank.h> 30 #include <drm/drm_managed.h> 31 #include "amdgpu_drv.h" 32 33 #include <drm/drm_pciids.h> 34 #include <linux/module.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/vga_switcheroo.h> 37 #include <drm/drm_probe_helper.h> 38 #include <linux/mmu_notifier.h> 39 #include <linux/suspend.h> 40 #include <linux/cc_platform.h> 41 #include <linux/dynamic_debug.h> 42 43 #include "amdgpu.h" 44 #include "amdgpu_irq.h" 45 #include "amdgpu_dma_buf.h" 46 #include "amdgpu_sched.h" 47 #include "amdgpu_fdinfo.h" 48 #include "amdgpu_amdkfd.h" 49 50 #include "amdgpu_ras.h" 51 #include "amdgpu_xgmi.h" 52 #include "amdgpu_reset.h" 53 #include "../amdxcp/amdgpu_xcp_drv.h" 54 55 /* 56 * KMS wrapper. 57 * - 3.0.0 - initial driver 58 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 59 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 60 * at the end of IBs. 61 * - 3.3.0 - Add VM support for UVD on supported hardware. 62 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 63 * - 3.5.0 - Add support for new UVD_NO_OP register. 64 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 65 * - 3.7.0 - Add support for VCE clock list packet 66 * - 3.8.0 - Add support raster config init in the kernel 67 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 68 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 69 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 70 * - 3.12.0 - Add query for double offchip LDS buffers 71 * - 3.13.0 - Add PRT support 72 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 73 * - 3.15.0 - Export more gpu info for gfx9 74 * - 3.16.0 - Add reserved vmid support 75 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 76 * - 3.18.0 - Export gpu always on cu bitmap 77 * - 3.19.0 - Add support for UVD MJPEG decode 78 * - 3.20.0 - Add support for local BOs 79 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 80 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 81 * - 3.23.0 - Add query for VRAM lost counter 82 * - 3.24.0 - Add high priority compute support for gfx9 83 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 84 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 85 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation. 86 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 87 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 88 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 89 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 90 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 91 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 92 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 93 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 94 * - 3.36.0 - Allow reading more status registers on si/cik 95 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 96 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 97 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 98 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 99 * - 3.41.0 - Add video codec query 100 * - 3.42.0 - Add 16bpc fixed point display support 101 * - 3.43.0 - Add device hot plug/unplug support 102 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 103 * - 3.45.0 - Add context ioctl stable pstate interface 104 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm 105 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags 106 * - 3.48.0 - Add IP discovery version info to HW INFO 107 * - 3.49.0 - Add gang submit into CS IOCTL 108 * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock 109 * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock 110 * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl 111 * 3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields: 112 * tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size, 113 * gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi 114 * 3.53.0 - Support for GFX11 CP GFX shadowing 115 * 3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support 116 */ 117 #define KMS_DRIVER_MAJOR 3 118 #define KMS_DRIVER_MINOR 54 119 #define KMS_DRIVER_PATCHLEVEL 0 120 121 unsigned int amdgpu_vram_limit = UINT_MAX; 122 int amdgpu_vis_vram_limit; 123 int amdgpu_gart_size = -1; /* auto */ 124 int amdgpu_gtt_size = -1; /* auto */ 125 int amdgpu_moverate = -1; /* auto */ 126 int amdgpu_audio = -1; 127 int amdgpu_disp_priority; 128 int amdgpu_hw_i2c; 129 int amdgpu_pcie_gen2 = -1; 130 int amdgpu_msi = -1; 131 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 132 int amdgpu_dpm = -1; 133 int amdgpu_fw_load_type = -1; 134 int amdgpu_aspm = -1; 135 int amdgpu_runtime_pm = -1; 136 uint amdgpu_ip_block_mask = 0xffffffff; 137 int amdgpu_bapm = -1; 138 int amdgpu_deep_color; 139 int amdgpu_vm_size = -1; 140 int amdgpu_vm_fragment_size = -1; 141 int amdgpu_vm_block_size = -1; 142 int amdgpu_vm_fault_stop; 143 int amdgpu_vm_debug; 144 int amdgpu_vm_update_mode = -1; 145 int amdgpu_exp_hw_support; 146 int amdgpu_dc = -1; 147 int amdgpu_sched_jobs = 32; 148 int amdgpu_sched_hw_submission = 2; 149 uint amdgpu_pcie_gen_cap; 150 uint amdgpu_pcie_lane_cap; 151 u64 amdgpu_cg_mask = 0xffffffffffffffff; 152 uint amdgpu_pg_mask = 0xffffffff; 153 uint amdgpu_sdma_phase_quantum = 32; 154 char *amdgpu_disable_cu; 155 char *amdgpu_virtual_display; 156 157 /* 158 * OverDrive(bit 14) disabled by default 159 * GFX DCS(bit 19) disabled by default 160 */ 161 uint amdgpu_pp_feature_mask = 0xfff7bfff; 162 uint amdgpu_force_long_training; 163 int amdgpu_lbpw = -1; 164 int amdgpu_compute_multipipe = -1; 165 int amdgpu_gpu_recovery = -1; /* auto */ 166 int amdgpu_emu_mode; 167 uint amdgpu_smu_memory_pool_size; 168 int amdgpu_smu_pptable_id = -1; 169 /* 170 * FBC (bit 0) disabled by default 171 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 172 * - With this, for multiple monitors in sync(e.g. with the same model), 173 * mclk switching will be allowed. And the mclk will be not foced to the 174 * highest. That helps saving some idle power. 175 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 176 * PSR (bit 3) disabled by default 177 * EDP NO POWER SEQUENCING (bit 4) disabled by default 178 */ 179 uint amdgpu_dc_feature_mask = 2; 180 uint amdgpu_dc_debug_mask; 181 uint amdgpu_dc_visual_confirm; 182 int amdgpu_async_gfx_ring = 1; 183 int amdgpu_mcbp; 184 int amdgpu_discovery = -1; 185 int amdgpu_mes; 186 int amdgpu_mes_kiq; 187 int amdgpu_noretry = -1; 188 int amdgpu_force_asic_type = -1; 189 int amdgpu_tmz = -1; /* auto */ 190 uint amdgpu_freesync_vid_mode; 191 int amdgpu_reset_method = -1; /* auto */ 192 int amdgpu_num_kcq = -1; 193 int amdgpu_smartshift_bias; 194 int amdgpu_use_xgmi_p2p = 1; 195 int amdgpu_vcnfw_log; 196 int amdgpu_sg_display = -1; /* auto */ 197 int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE; 198 199 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 200 201 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 202 "DRM_UT_CORE", 203 "DRM_UT_DRIVER", 204 "DRM_UT_KMS", 205 "DRM_UT_PRIME", 206 "DRM_UT_ATOMIC", 207 "DRM_UT_VBL", 208 "DRM_UT_STATE", 209 "DRM_UT_LEASE", 210 "DRM_UT_DP", 211 "DRM_UT_DRMRES"); 212 213 struct amdgpu_mgpu_info mgpu_info = { 214 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 215 .delayed_reset_work = __DELAYED_WORK_INITIALIZER( 216 mgpu_info.delayed_reset_work, 217 amdgpu_drv_delayed_reset_work_handler, 0), 218 }; 219 int amdgpu_ras_enable = -1; 220 uint amdgpu_ras_mask = 0xffffffff; 221 int amdgpu_bad_page_threshold = -1; 222 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 223 .timeout_fatal_disable = false, 224 .period = 0x0, /* default to 0x0 (timeout disable) */ 225 }; 226 227 /** 228 * DOC: vramlimit (int) 229 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 230 */ 231 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 232 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 233 234 /** 235 * DOC: vis_vramlimit (int) 236 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 237 */ 238 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 239 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 240 241 /** 242 * DOC: gartsize (uint) 243 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing. 244 * The default is -1 (The size depends on asic). 245 */ 246 MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)"); 247 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 248 249 /** 250 * DOC: gttsize (int) 251 * Restrict the size of GTT domain (for userspace use) in MiB for testing. 252 * The default is -1 (Use 1/2 RAM, minimum value is 3GB). 253 */ 254 MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)"); 255 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 256 257 /** 258 * DOC: moverate (int) 259 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 260 */ 261 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 262 module_param_named(moverate, amdgpu_moverate, int, 0600); 263 264 /** 265 * DOC: audio (int) 266 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 267 */ 268 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 269 module_param_named(audio, amdgpu_audio, int, 0444); 270 271 /** 272 * DOC: disp_priority (int) 273 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 274 */ 275 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 276 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 277 278 /** 279 * DOC: hw_i2c (int) 280 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 281 */ 282 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 283 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 284 285 /** 286 * DOC: pcie_gen2 (int) 287 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 288 */ 289 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 290 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 291 292 /** 293 * DOC: msi (int) 294 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 295 */ 296 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 297 module_param_named(msi, amdgpu_msi, int, 0444); 298 299 /** 300 * DOC: lockup_timeout (string) 301 * Set GPU scheduler timeout value in ms. 302 * 303 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 304 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 305 * to the default timeout. 306 * 307 * - With one value specified, the setting will apply to all non-compute jobs. 308 * - With multiple values specified, the first one will be for GFX. 309 * The second one is for Compute. The third and fourth ones are 310 * for SDMA and Video. 311 * 312 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 313 * jobs is 10000. The timeout for compute is 60000. 314 */ 315 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 316 "for passthrough or sriov, 10000 for all jobs." 317 " 0: keep default value. negative: infinity timeout), " 318 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 319 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 320 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 321 322 /** 323 * DOC: dpm (int) 324 * Override for dynamic power management setting 325 * (0 = disable, 1 = enable) 326 * The default is -1 (auto). 327 */ 328 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 329 module_param_named(dpm, amdgpu_dpm, int, 0444); 330 331 /** 332 * DOC: fw_load_type (int) 333 * Set different firmware loading type for debugging, if supported. 334 * Set to 0 to force direct loading if supported by the ASIC. Set 335 * to -1 to select the default loading mode for the ASIC, as defined 336 * by the driver. The default is -1 (auto). 337 */ 338 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); 339 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 340 341 /** 342 * DOC: aspm (int) 343 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 344 */ 345 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 346 module_param_named(aspm, amdgpu_aspm, int, 0444); 347 348 /** 349 * DOC: runpm (int) 350 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 351 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 352 * Setting the value to 0 disables this functionality. 353 */ 354 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto)"); 355 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 356 357 /** 358 * DOC: ip_block_mask (uint) 359 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 360 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 361 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 362 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 363 */ 364 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 365 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 366 367 /** 368 * DOC: bapm (int) 369 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 370 * The default -1 (auto, enabled) 371 */ 372 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 373 module_param_named(bapm, amdgpu_bapm, int, 0444); 374 375 /** 376 * DOC: deep_color (int) 377 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 378 */ 379 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 380 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 381 382 /** 383 * DOC: vm_size (int) 384 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 385 */ 386 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 387 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 388 389 /** 390 * DOC: vm_fragment_size (int) 391 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 392 */ 393 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 394 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 395 396 /** 397 * DOC: vm_block_size (int) 398 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 399 */ 400 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 401 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 402 403 /** 404 * DOC: vm_fault_stop (int) 405 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 406 */ 407 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 408 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 409 410 /** 411 * DOC: vm_debug (int) 412 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 413 */ 414 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 415 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 416 417 /** 418 * DOC: vm_update_mode (int) 419 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 420 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 421 */ 422 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 423 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 424 425 /** 426 * DOC: exp_hw_support (int) 427 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 428 */ 429 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 430 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 431 432 /** 433 * DOC: dc (int) 434 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 435 */ 436 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 437 module_param_named(dc, amdgpu_dc, int, 0444); 438 439 /** 440 * DOC: sched_jobs (int) 441 * Override the max number of jobs supported in the sw queue. The default is 32. 442 */ 443 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 444 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 445 446 /** 447 * DOC: sched_hw_submission (int) 448 * Override the max number of HW submissions. The default is 2. 449 */ 450 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 451 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 452 453 /** 454 * DOC: ppfeaturemask (hexint) 455 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 456 * The default is the current set of stable power features. 457 */ 458 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 459 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 460 461 /** 462 * DOC: forcelongtraining (uint) 463 * Force long memory training in resume. 464 * The default is zero, indicates short training in resume. 465 */ 466 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 467 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 468 469 /** 470 * DOC: pcie_gen_cap (uint) 471 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 472 * The default is 0 (automatic for each asic). 473 */ 474 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 475 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 476 477 /** 478 * DOC: pcie_lane_cap (uint) 479 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 480 * The default is 0 (automatic for each asic). 481 */ 482 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 483 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 484 485 /** 486 * DOC: cg_mask (ullong) 487 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 488 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 489 */ 490 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 491 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 492 493 /** 494 * DOC: pg_mask (uint) 495 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 496 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 497 */ 498 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 499 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 500 501 /** 502 * DOC: sdma_phase_quantum (uint) 503 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 504 */ 505 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 506 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 507 508 /** 509 * DOC: disable_cu (charp) 510 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 511 */ 512 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 513 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 514 515 /** 516 * DOC: virtual_display (charp) 517 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 518 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 519 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 520 * device at 26:00.0. The default is NULL. 521 */ 522 MODULE_PARM_DESC(virtual_display, 523 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 524 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 525 526 /** 527 * DOC: lbpw (int) 528 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 529 */ 530 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 531 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 532 533 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 534 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 535 536 /** 537 * DOC: gpu_recovery (int) 538 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 539 */ 540 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 541 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 542 543 /** 544 * DOC: emu_mode (int) 545 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 546 */ 547 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 548 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 549 550 /** 551 * DOC: ras_enable (int) 552 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 553 */ 554 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 555 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 556 557 /** 558 * DOC: ras_mask (uint) 559 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 560 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 561 */ 562 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 563 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 564 565 /** 566 * DOC: timeout_fatal_disable (bool) 567 * Disable Watchdog timeout fatal error event 568 */ 569 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 570 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 571 572 /** 573 * DOC: timeout_period (uint) 574 * Modify the watchdog timeout max_cycles as (1 << period) 575 */ 576 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 577 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 578 579 /** 580 * DOC: si_support (int) 581 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 582 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 583 * otherwise using amdgpu driver. 584 */ 585 #ifdef CONFIG_DRM_AMDGPU_SI 586 587 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 588 int amdgpu_si_support = 0; 589 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 590 #else 591 int amdgpu_si_support = 1; 592 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 593 #endif 594 595 module_param_named(si_support, amdgpu_si_support, int, 0444); 596 #endif 597 598 /** 599 * DOC: cik_support (int) 600 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 601 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 602 * otherwise using amdgpu driver. 603 */ 604 #ifdef CONFIG_DRM_AMDGPU_CIK 605 606 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 607 int amdgpu_cik_support = 0; 608 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 609 #else 610 int amdgpu_cik_support = 1; 611 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 612 #endif 613 614 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 615 #endif 616 617 /** 618 * DOC: smu_memory_pool_size (uint) 619 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 620 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 621 */ 622 MODULE_PARM_DESC(smu_memory_pool_size, 623 "reserve gtt for smu debug usage, 0 = disable," 624 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 625 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 626 627 /** 628 * DOC: async_gfx_ring (int) 629 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 630 */ 631 MODULE_PARM_DESC(async_gfx_ring, 632 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 633 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 634 635 /** 636 * DOC: mcbp (int) 637 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled) 638 */ 639 MODULE_PARM_DESC(mcbp, 640 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); 641 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 642 643 /** 644 * DOC: discovery (int) 645 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 646 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 647 */ 648 MODULE_PARM_DESC(discovery, 649 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 650 module_param_named(discovery, amdgpu_discovery, int, 0444); 651 652 /** 653 * DOC: mes (int) 654 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 655 * (0 = disabled (default), 1 = enabled) 656 */ 657 MODULE_PARM_DESC(mes, 658 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 659 module_param_named(mes, amdgpu_mes, int, 0444); 660 661 /** 662 * DOC: mes_kiq (int) 663 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq. 664 * (0 = disabled (default), 1 = enabled) 665 */ 666 MODULE_PARM_DESC(mes_kiq, 667 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)"); 668 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444); 669 670 /** 671 * DOC: noretry (int) 672 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 673 * do not support per-process XNACK this also disables retry page faults. 674 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 675 */ 676 MODULE_PARM_DESC(noretry, 677 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 678 module_param_named(noretry, amdgpu_noretry, int, 0644); 679 680 /** 681 * DOC: force_asic_type (int) 682 * A non negative value used to specify the asic type for all supported GPUs. 683 */ 684 MODULE_PARM_DESC(force_asic_type, 685 "A non negative value used to specify the asic type for all supported GPUs"); 686 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 687 688 /** 689 * DOC: use_xgmi_p2p (int) 690 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 691 */ 692 MODULE_PARM_DESC(use_xgmi_p2p, 693 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 694 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 695 696 697 #ifdef CONFIG_HSA_AMD 698 /** 699 * DOC: sched_policy (int) 700 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 701 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 702 * assigns queues to HQDs. 703 */ 704 int sched_policy = KFD_SCHED_POLICY_HWS; 705 module_param(sched_policy, int, 0444); 706 MODULE_PARM_DESC(sched_policy, 707 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 708 709 /** 710 * DOC: hws_max_conc_proc (int) 711 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 712 * number of VMIDs assigned to the HWS, which is also the default. 713 */ 714 int hws_max_conc_proc = -1; 715 module_param(hws_max_conc_proc, int, 0444); 716 MODULE_PARM_DESC(hws_max_conc_proc, 717 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 718 719 /** 720 * DOC: cwsr_enable (int) 721 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 722 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 723 * disables it. 724 */ 725 int cwsr_enable = 1; 726 module_param(cwsr_enable, int, 0444); 727 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 728 729 /** 730 * DOC: max_num_of_queues_per_device (int) 731 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 732 * is 4096. 733 */ 734 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 735 module_param(max_num_of_queues_per_device, int, 0444); 736 MODULE_PARM_DESC(max_num_of_queues_per_device, 737 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 738 739 /** 740 * DOC: send_sigterm (int) 741 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 742 * but just print errors on dmesg. Setting 1 enables sending sigterm. 743 */ 744 int send_sigterm; 745 module_param(send_sigterm, int, 0444); 746 MODULE_PARM_DESC(send_sigterm, 747 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 748 749 /** 750 * DOC: debug_largebar (int) 751 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 752 * system. This limits the VRAM size reported to ROCm applications to the visible 753 * size, usually 256MB. 754 * Default value is 0, diabled. 755 */ 756 int debug_largebar; 757 module_param(debug_largebar, int, 0444); 758 MODULE_PARM_DESC(debug_largebar, 759 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 760 761 /** 762 * DOC: ignore_crat (int) 763 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 764 * table to get information about AMD APUs. This option can serve as a workaround on 765 * systems with a broken CRAT table. 766 * 767 * Default is auto (according to asic type, iommu_v2, and crat table, to decide 768 * whether use CRAT) 769 */ 770 int ignore_crat; 771 module_param(ignore_crat, int, 0444); 772 MODULE_PARM_DESC(ignore_crat, 773 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)"); 774 775 /** 776 * DOC: halt_if_hws_hang (int) 777 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 778 * Setting 1 enables halt on hang. 779 */ 780 int halt_if_hws_hang; 781 module_param(halt_if_hws_hang, int, 0644); 782 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 783 784 /** 785 * DOC: hws_gws_support(bool) 786 * Assume that HWS supports GWS barriers regardless of what firmware version 787 * check says. Default value: false (rely on MEC2 firmware version check). 788 */ 789 bool hws_gws_support; 790 module_param(hws_gws_support, bool, 0444); 791 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 792 793 /** 794 * DOC: queue_preemption_timeout_ms (int) 795 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 796 */ 797 int queue_preemption_timeout_ms = 9000; 798 module_param(queue_preemption_timeout_ms, int, 0644); 799 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 800 801 /** 802 * DOC: debug_evictions(bool) 803 * Enable extra debug messages to help determine the cause of evictions 804 */ 805 bool debug_evictions; 806 module_param(debug_evictions, bool, 0644); 807 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 808 809 /** 810 * DOC: no_system_mem_limit(bool) 811 * Disable system memory limit, to support multiple process shared memory 812 */ 813 bool no_system_mem_limit; 814 module_param(no_system_mem_limit, bool, 0644); 815 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 816 817 /** 818 * DOC: no_queue_eviction_on_vm_fault (int) 819 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 820 */ 821 int amdgpu_no_queue_eviction_on_vm_fault; 822 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 823 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 824 #endif 825 826 /** 827 * DOC: mtype_local (int) 828 */ 829 int amdgpu_mtype_local; 830 MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (0 = MTYPE_RW (default), 1 = MTYPE_NC, 2 = MTYPE_CC)"); 831 module_param_named(mtype_local, amdgpu_mtype_local, int, 0444); 832 833 /** 834 * DOC: pcie_p2p (bool) 835 * Enable PCIe P2P (requires large-BAR). Default value: true (on) 836 */ 837 #ifdef CONFIG_HSA_AMD_P2P 838 bool pcie_p2p = true; 839 module_param(pcie_p2p, bool, 0444); 840 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); 841 #endif 842 843 /** 844 * DOC: dcfeaturemask (uint) 845 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 846 * The default is the current set of stable display features. 847 */ 848 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 849 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 850 851 /** 852 * DOC: dcdebugmask (uint) 853 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 854 */ 855 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 856 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 857 858 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)"); 859 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444); 860 861 /** 862 * DOC: abmlevel (uint) 863 * Override the default ABM (Adaptive Backlight Management) level used for DC 864 * enabled hardware. Requires DMCU to be supported and loaded. 865 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 866 * default. Values 1-4 control the maximum allowable brightness reduction via 867 * the ABM algorithm, with 1 being the least reduction and 4 being the most 868 * reduction. 869 * 870 * Defaults to 0, or disabled. Userspace can still override this level later 871 * after boot. 872 */ 873 uint amdgpu_dm_abm_level; 874 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 875 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 876 877 int amdgpu_backlight = -1; 878 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 879 module_param_named(backlight, amdgpu_backlight, bint, 0444); 880 881 /** 882 * DOC: tmz (int) 883 * Trusted Memory Zone (TMZ) is a method to protect data being written 884 * to or read from memory. 885 * 886 * The default value: 0 (off). TODO: change to auto till it is completed. 887 */ 888 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 889 module_param_named(tmz, amdgpu_tmz, int, 0444); 890 891 /** 892 * DOC: freesync_video (uint) 893 * Enable the optimization to adjust front porch timing to achieve seamless 894 * mode change experience when setting a freesync supported mode for which full 895 * modeset is not needed. 896 * 897 * The Display Core will add a set of modes derived from the base FreeSync 898 * video mode into the corresponding connector's mode list based on commonly 899 * used refresh rates and VRR range of the connected display, when users enable 900 * this feature. From the userspace perspective, they can see a seamless mode 901 * change experience when the change between different refresh rates under the 902 * same resolution. Additionally, userspace applications such as Video playback 903 * can read this modeset list and change the refresh rate based on the video 904 * frame rate. Finally, the userspace can also derive an appropriate mode for a 905 * particular refresh rate based on the FreeSync Mode and add it to the 906 * connector's mode list. 907 * 908 * Note: This is an experimental feature. 909 * 910 * The default value: 0 (off). 911 */ 912 MODULE_PARM_DESC( 913 freesync_video, 914 "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)"); 915 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); 916 917 /** 918 * DOC: reset_method (int) 919 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 920 */ 921 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 922 module_param_named(reset_method, amdgpu_reset_method, int, 0444); 923 924 /** 925 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 926 * threshold value of faulty pages detected by RAS ECC, which may 927 * result in the GPU entering bad status when the number of total 928 * faulty pages by ECC exceeds the threshold value. 929 */ 930 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = driver sets threshold)"); 931 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 932 933 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 934 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 935 936 /** 937 * DOC: vcnfw_log (int) 938 * Enable vcnfw log output for debugging, the default is disabled. 939 */ 940 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 941 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 942 943 /** 944 * DOC: sg_display (int) 945 * Disable S/G (scatter/gather) display (i.e., display from system memory). 946 * This option is only relevant on APUs. Set this option to 0 to disable 947 * S/G display if you experience flickering or other issues under memory 948 * pressure and report the issue. 949 */ 950 MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)"); 951 module_param_named(sg_display, amdgpu_sg_display, int, 0444); 952 953 /** 954 * DOC: smu_pptable_id (int) 955 * Used to override pptable id. id = 0 use VBIOS pptable. 956 * id > 0 use the soft pptable with specicfied id. 957 */ 958 MODULE_PARM_DESC(smu_pptable_id, 959 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 960 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 961 962 /** 963 * DOC: partition_mode (int) 964 * Used to override the default SPX mode. 965 */ 966 MODULE_PARM_DESC( 967 user_partt_mode, 968 "specify partition mode to be used (-2 = AMDGPU_AUTO_COMPUTE_PARTITION_MODE(default value) \ 969 0 = AMDGPU_SPX_PARTITION_MODE, \ 970 1 = AMDGPU_DPX_PARTITION_MODE, \ 971 2 = AMDGPU_TPX_PARTITION_MODE, \ 972 3 = AMDGPU_QPX_PARTITION_MODE, \ 973 4 = AMDGPU_CPX_PARTITION_MODE)"); 974 module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint, 0444); 975 976 /* These devices are not supported by amdgpu. 977 * They are supported by the mach64, r128, radeon drivers 978 */ 979 static const u16 amdgpu_unsupported_pciidlist[] = { 980 /* mach64 */ 981 0x4354, 982 0x4358, 983 0x4554, 984 0x4742, 985 0x4744, 986 0x4749, 987 0x474C, 988 0x474D, 989 0x474E, 990 0x474F, 991 0x4750, 992 0x4751, 993 0x4752, 994 0x4753, 995 0x4754, 996 0x4755, 997 0x4756, 998 0x4757, 999 0x4758, 1000 0x4759, 1001 0x475A, 1002 0x4C42, 1003 0x4C44, 1004 0x4C47, 1005 0x4C49, 1006 0x4C4D, 1007 0x4C4E, 1008 0x4C50, 1009 0x4C51, 1010 0x4C52, 1011 0x4C53, 1012 0x5654, 1013 0x5655, 1014 0x5656, 1015 /* r128 */ 1016 0x4c45, 1017 0x4c46, 1018 0x4d46, 1019 0x4d4c, 1020 0x5041, 1021 0x5042, 1022 0x5043, 1023 0x5044, 1024 0x5045, 1025 0x5046, 1026 0x5047, 1027 0x5048, 1028 0x5049, 1029 0x504A, 1030 0x504B, 1031 0x504C, 1032 0x504D, 1033 0x504E, 1034 0x504F, 1035 0x5050, 1036 0x5051, 1037 0x5052, 1038 0x5053, 1039 0x5054, 1040 0x5055, 1041 0x5056, 1042 0x5057, 1043 0x5058, 1044 0x5245, 1045 0x5246, 1046 0x5247, 1047 0x524b, 1048 0x524c, 1049 0x534d, 1050 0x5446, 1051 0x544C, 1052 0x5452, 1053 /* radeon */ 1054 0x3150, 1055 0x3151, 1056 0x3152, 1057 0x3154, 1058 0x3155, 1059 0x3E50, 1060 0x3E54, 1061 0x4136, 1062 0x4137, 1063 0x4144, 1064 0x4145, 1065 0x4146, 1066 0x4147, 1067 0x4148, 1068 0x4149, 1069 0x414A, 1070 0x414B, 1071 0x4150, 1072 0x4151, 1073 0x4152, 1074 0x4153, 1075 0x4154, 1076 0x4155, 1077 0x4156, 1078 0x4237, 1079 0x4242, 1080 0x4336, 1081 0x4337, 1082 0x4437, 1083 0x4966, 1084 0x4967, 1085 0x4A48, 1086 0x4A49, 1087 0x4A4A, 1088 0x4A4B, 1089 0x4A4C, 1090 0x4A4D, 1091 0x4A4E, 1092 0x4A4F, 1093 0x4A50, 1094 0x4A54, 1095 0x4B48, 1096 0x4B49, 1097 0x4B4A, 1098 0x4B4B, 1099 0x4B4C, 1100 0x4C57, 1101 0x4C58, 1102 0x4C59, 1103 0x4C5A, 1104 0x4C64, 1105 0x4C66, 1106 0x4C67, 1107 0x4E44, 1108 0x4E45, 1109 0x4E46, 1110 0x4E47, 1111 0x4E48, 1112 0x4E49, 1113 0x4E4A, 1114 0x4E4B, 1115 0x4E50, 1116 0x4E51, 1117 0x4E52, 1118 0x4E53, 1119 0x4E54, 1120 0x4E56, 1121 0x5144, 1122 0x5145, 1123 0x5146, 1124 0x5147, 1125 0x5148, 1126 0x514C, 1127 0x514D, 1128 0x5157, 1129 0x5158, 1130 0x5159, 1131 0x515A, 1132 0x515E, 1133 0x5460, 1134 0x5462, 1135 0x5464, 1136 0x5548, 1137 0x5549, 1138 0x554A, 1139 0x554B, 1140 0x554C, 1141 0x554D, 1142 0x554E, 1143 0x554F, 1144 0x5550, 1145 0x5551, 1146 0x5552, 1147 0x5554, 1148 0x564A, 1149 0x564B, 1150 0x564F, 1151 0x5652, 1152 0x5653, 1153 0x5657, 1154 0x5834, 1155 0x5835, 1156 0x5954, 1157 0x5955, 1158 0x5974, 1159 0x5975, 1160 0x5960, 1161 0x5961, 1162 0x5962, 1163 0x5964, 1164 0x5965, 1165 0x5969, 1166 0x5a41, 1167 0x5a42, 1168 0x5a61, 1169 0x5a62, 1170 0x5b60, 1171 0x5b62, 1172 0x5b63, 1173 0x5b64, 1174 0x5b65, 1175 0x5c61, 1176 0x5c63, 1177 0x5d48, 1178 0x5d49, 1179 0x5d4a, 1180 0x5d4c, 1181 0x5d4d, 1182 0x5d4e, 1183 0x5d4f, 1184 0x5d50, 1185 0x5d52, 1186 0x5d57, 1187 0x5e48, 1188 0x5e4a, 1189 0x5e4b, 1190 0x5e4c, 1191 0x5e4d, 1192 0x5e4f, 1193 0x6700, 1194 0x6701, 1195 0x6702, 1196 0x6703, 1197 0x6704, 1198 0x6705, 1199 0x6706, 1200 0x6707, 1201 0x6708, 1202 0x6709, 1203 0x6718, 1204 0x6719, 1205 0x671c, 1206 0x671d, 1207 0x671f, 1208 0x6720, 1209 0x6721, 1210 0x6722, 1211 0x6723, 1212 0x6724, 1213 0x6725, 1214 0x6726, 1215 0x6727, 1216 0x6728, 1217 0x6729, 1218 0x6738, 1219 0x6739, 1220 0x673e, 1221 0x6740, 1222 0x6741, 1223 0x6742, 1224 0x6743, 1225 0x6744, 1226 0x6745, 1227 0x6746, 1228 0x6747, 1229 0x6748, 1230 0x6749, 1231 0x674A, 1232 0x6750, 1233 0x6751, 1234 0x6758, 1235 0x6759, 1236 0x675B, 1237 0x675D, 1238 0x675F, 1239 0x6760, 1240 0x6761, 1241 0x6762, 1242 0x6763, 1243 0x6764, 1244 0x6765, 1245 0x6766, 1246 0x6767, 1247 0x6768, 1248 0x6770, 1249 0x6771, 1250 0x6772, 1251 0x6778, 1252 0x6779, 1253 0x677B, 1254 0x6840, 1255 0x6841, 1256 0x6842, 1257 0x6843, 1258 0x6849, 1259 0x684C, 1260 0x6850, 1261 0x6858, 1262 0x6859, 1263 0x6880, 1264 0x6888, 1265 0x6889, 1266 0x688A, 1267 0x688C, 1268 0x688D, 1269 0x6898, 1270 0x6899, 1271 0x689b, 1272 0x689c, 1273 0x689d, 1274 0x689e, 1275 0x68a0, 1276 0x68a1, 1277 0x68a8, 1278 0x68a9, 1279 0x68b0, 1280 0x68b8, 1281 0x68b9, 1282 0x68ba, 1283 0x68be, 1284 0x68bf, 1285 0x68c0, 1286 0x68c1, 1287 0x68c7, 1288 0x68c8, 1289 0x68c9, 1290 0x68d8, 1291 0x68d9, 1292 0x68da, 1293 0x68de, 1294 0x68e0, 1295 0x68e1, 1296 0x68e4, 1297 0x68e5, 1298 0x68e8, 1299 0x68e9, 1300 0x68f1, 1301 0x68f2, 1302 0x68f8, 1303 0x68f9, 1304 0x68fa, 1305 0x68fe, 1306 0x7100, 1307 0x7101, 1308 0x7102, 1309 0x7103, 1310 0x7104, 1311 0x7105, 1312 0x7106, 1313 0x7108, 1314 0x7109, 1315 0x710A, 1316 0x710B, 1317 0x710C, 1318 0x710E, 1319 0x710F, 1320 0x7140, 1321 0x7141, 1322 0x7142, 1323 0x7143, 1324 0x7144, 1325 0x7145, 1326 0x7146, 1327 0x7147, 1328 0x7149, 1329 0x714A, 1330 0x714B, 1331 0x714C, 1332 0x714D, 1333 0x714E, 1334 0x714F, 1335 0x7151, 1336 0x7152, 1337 0x7153, 1338 0x715E, 1339 0x715F, 1340 0x7180, 1341 0x7181, 1342 0x7183, 1343 0x7186, 1344 0x7187, 1345 0x7188, 1346 0x718A, 1347 0x718B, 1348 0x718C, 1349 0x718D, 1350 0x718F, 1351 0x7193, 1352 0x7196, 1353 0x719B, 1354 0x719F, 1355 0x71C0, 1356 0x71C1, 1357 0x71C2, 1358 0x71C3, 1359 0x71C4, 1360 0x71C5, 1361 0x71C6, 1362 0x71C7, 1363 0x71CD, 1364 0x71CE, 1365 0x71D2, 1366 0x71D4, 1367 0x71D5, 1368 0x71D6, 1369 0x71DA, 1370 0x71DE, 1371 0x7200, 1372 0x7210, 1373 0x7211, 1374 0x7240, 1375 0x7243, 1376 0x7244, 1377 0x7245, 1378 0x7246, 1379 0x7247, 1380 0x7248, 1381 0x7249, 1382 0x724A, 1383 0x724B, 1384 0x724C, 1385 0x724D, 1386 0x724E, 1387 0x724F, 1388 0x7280, 1389 0x7281, 1390 0x7283, 1391 0x7284, 1392 0x7287, 1393 0x7288, 1394 0x7289, 1395 0x728B, 1396 0x728C, 1397 0x7290, 1398 0x7291, 1399 0x7293, 1400 0x7297, 1401 0x7834, 1402 0x7835, 1403 0x791e, 1404 0x791f, 1405 0x793f, 1406 0x7941, 1407 0x7942, 1408 0x796c, 1409 0x796d, 1410 0x796e, 1411 0x796f, 1412 0x9400, 1413 0x9401, 1414 0x9402, 1415 0x9403, 1416 0x9405, 1417 0x940A, 1418 0x940B, 1419 0x940F, 1420 0x94A0, 1421 0x94A1, 1422 0x94A3, 1423 0x94B1, 1424 0x94B3, 1425 0x94B4, 1426 0x94B5, 1427 0x94B9, 1428 0x9440, 1429 0x9441, 1430 0x9442, 1431 0x9443, 1432 0x9444, 1433 0x9446, 1434 0x944A, 1435 0x944B, 1436 0x944C, 1437 0x944E, 1438 0x9450, 1439 0x9452, 1440 0x9456, 1441 0x945A, 1442 0x945B, 1443 0x945E, 1444 0x9460, 1445 0x9462, 1446 0x946A, 1447 0x946B, 1448 0x947A, 1449 0x947B, 1450 0x9480, 1451 0x9487, 1452 0x9488, 1453 0x9489, 1454 0x948A, 1455 0x948F, 1456 0x9490, 1457 0x9491, 1458 0x9495, 1459 0x9498, 1460 0x949C, 1461 0x949E, 1462 0x949F, 1463 0x94C0, 1464 0x94C1, 1465 0x94C3, 1466 0x94C4, 1467 0x94C5, 1468 0x94C6, 1469 0x94C7, 1470 0x94C8, 1471 0x94C9, 1472 0x94CB, 1473 0x94CC, 1474 0x94CD, 1475 0x9500, 1476 0x9501, 1477 0x9504, 1478 0x9505, 1479 0x9506, 1480 0x9507, 1481 0x9508, 1482 0x9509, 1483 0x950F, 1484 0x9511, 1485 0x9515, 1486 0x9517, 1487 0x9519, 1488 0x9540, 1489 0x9541, 1490 0x9542, 1491 0x954E, 1492 0x954F, 1493 0x9552, 1494 0x9553, 1495 0x9555, 1496 0x9557, 1497 0x955f, 1498 0x9580, 1499 0x9581, 1500 0x9583, 1501 0x9586, 1502 0x9587, 1503 0x9588, 1504 0x9589, 1505 0x958A, 1506 0x958B, 1507 0x958C, 1508 0x958D, 1509 0x958E, 1510 0x958F, 1511 0x9590, 1512 0x9591, 1513 0x9593, 1514 0x9595, 1515 0x9596, 1516 0x9597, 1517 0x9598, 1518 0x9599, 1519 0x959B, 1520 0x95C0, 1521 0x95C2, 1522 0x95C4, 1523 0x95C5, 1524 0x95C6, 1525 0x95C7, 1526 0x95C9, 1527 0x95CC, 1528 0x95CD, 1529 0x95CE, 1530 0x95CF, 1531 0x9610, 1532 0x9611, 1533 0x9612, 1534 0x9613, 1535 0x9614, 1536 0x9615, 1537 0x9616, 1538 0x9640, 1539 0x9641, 1540 0x9642, 1541 0x9643, 1542 0x9644, 1543 0x9645, 1544 0x9647, 1545 0x9648, 1546 0x9649, 1547 0x964a, 1548 0x964b, 1549 0x964c, 1550 0x964e, 1551 0x964f, 1552 0x9710, 1553 0x9711, 1554 0x9712, 1555 0x9713, 1556 0x9714, 1557 0x9715, 1558 0x9802, 1559 0x9803, 1560 0x9804, 1561 0x9805, 1562 0x9806, 1563 0x9807, 1564 0x9808, 1565 0x9809, 1566 0x980A, 1567 0x9900, 1568 0x9901, 1569 0x9903, 1570 0x9904, 1571 0x9905, 1572 0x9906, 1573 0x9907, 1574 0x9908, 1575 0x9909, 1576 0x990A, 1577 0x990B, 1578 0x990C, 1579 0x990D, 1580 0x990E, 1581 0x990F, 1582 0x9910, 1583 0x9913, 1584 0x9917, 1585 0x9918, 1586 0x9919, 1587 0x9990, 1588 0x9991, 1589 0x9992, 1590 0x9993, 1591 0x9994, 1592 0x9995, 1593 0x9996, 1594 0x9997, 1595 0x9998, 1596 0x9999, 1597 0x999A, 1598 0x999B, 1599 0x999C, 1600 0x999D, 1601 0x99A0, 1602 0x99A2, 1603 0x99A4, 1604 /* radeon secondary ids */ 1605 0x3171, 1606 0x3e70, 1607 0x4164, 1608 0x4165, 1609 0x4166, 1610 0x4168, 1611 0x4170, 1612 0x4171, 1613 0x4172, 1614 0x4173, 1615 0x496e, 1616 0x4a69, 1617 0x4a6a, 1618 0x4a6b, 1619 0x4a70, 1620 0x4a74, 1621 0x4b69, 1622 0x4b6b, 1623 0x4b6c, 1624 0x4c6e, 1625 0x4e64, 1626 0x4e65, 1627 0x4e66, 1628 0x4e67, 1629 0x4e68, 1630 0x4e69, 1631 0x4e6a, 1632 0x4e71, 1633 0x4f73, 1634 0x5569, 1635 0x556b, 1636 0x556d, 1637 0x556f, 1638 0x5571, 1639 0x5854, 1640 0x5874, 1641 0x5940, 1642 0x5941, 1643 0x5b72, 1644 0x5b73, 1645 0x5b74, 1646 0x5b75, 1647 0x5d44, 1648 0x5d45, 1649 0x5d6d, 1650 0x5d6f, 1651 0x5d72, 1652 0x5d77, 1653 0x5e6b, 1654 0x5e6d, 1655 0x7120, 1656 0x7124, 1657 0x7129, 1658 0x712e, 1659 0x712f, 1660 0x7162, 1661 0x7163, 1662 0x7166, 1663 0x7167, 1664 0x7172, 1665 0x7173, 1666 0x71a0, 1667 0x71a1, 1668 0x71a3, 1669 0x71a7, 1670 0x71bb, 1671 0x71e0, 1672 0x71e1, 1673 0x71e2, 1674 0x71e6, 1675 0x71e7, 1676 0x71f2, 1677 0x7269, 1678 0x726b, 1679 0x726e, 1680 0x72a0, 1681 0x72a8, 1682 0x72b1, 1683 0x72b3, 1684 0x793f, 1685 }; 1686 1687 static const struct pci_device_id pciidlist[] = { 1688 #ifdef CONFIG_DRM_AMDGPU_SI 1689 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1690 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1691 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1692 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1693 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1694 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1695 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1696 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1697 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1698 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1699 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1700 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1701 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1702 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1703 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1704 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1705 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1706 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1707 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1708 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1709 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1710 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1711 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1712 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1713 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1714 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1715 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1716 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1717 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1718 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1719 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1720 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1721 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1722 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1723 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1724 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1725 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1726 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1727 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1728 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1729 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1730 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1731 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1732 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1733 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1734 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1735 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1736 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1737 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1738 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1739 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1740 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1741 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1742 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1743 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1744 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1745 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1746 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1747 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1748 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1749 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1750 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1751 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1752 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1753 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1754 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1755 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1756 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1757 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1758 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1759 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1760 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1761 #endif 1762 #ifdef CONFIG_DRM_AMDGPU_CIK 1763 /* Kaveri */ 1764 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1765 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1766 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1767 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1768 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1769 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1770 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1771 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1772 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1773 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1774 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1775 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1776 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1777 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1778 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1779 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1780 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1781 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1782 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1783 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1784 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1785 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1786 /* Bonaire */ 1787 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1788 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1789 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1790 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1791 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1792 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1793 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1794 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1795 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1796 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1797 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1798 /* Hawaii */ 1799 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1800 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1801 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1802 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1803 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1804 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1805 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1806 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1807 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1808 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1809 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1810 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1811 /* Kabini */ 1812 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1813 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1814 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1815 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1816 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1817 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1818 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1819 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1820 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1821 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1822 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1823 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1824 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1825 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1826 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1827 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1828 /* mullins */ 1829 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1830 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1831 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1832 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1833 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1834 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1835 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1836 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1837 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1838 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1839 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1840 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1841 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1842 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1843 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1844 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1845 #endif 1846 /* topaz */ 1847 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1848 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1849 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1850 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1851 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1852 /* tonga */ 1853 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1854 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1855 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1856 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1857 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1858 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1859 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1860 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1861 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1862 /* fiji */ 1863 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1864 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1865 /* carrizo */ 1866 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1867 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1868 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1869 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1870 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1871 /* stoney */ 1872 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1873 /* Polaris11 */ 1874 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1875 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1876 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1877 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1878 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1879 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1880 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1881 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1882 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1883 /* Polaris10 */ 1884 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1885 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1886 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1887 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1888 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1889 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1890 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1891 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1892 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1893 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1894 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1895 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1896 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1897 /* Polaris12 */ 1898 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1899 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1900 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1901 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1902 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1903 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1904 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1905 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1906 /* VEGAM */ 1907 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1908 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1909 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1910 /* Vega 10 */ 1911 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1912 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1913 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1914 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1915 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1916 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1917 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1918 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1919 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1920 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1921 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1922 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1923 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1924 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1925 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1926 /* Vega 12 */ 1927 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1928 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1929 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1930 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1931 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1932 /* Vega 20 */ 1933 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1934 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1935 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1936 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1937 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1938 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1939 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1940 /* Raven */ 1941 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1942 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1943 /* Arcturus */ 1944 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1945 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1946 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1947 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1948 /* Navi10 */ 1949 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1950 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1951 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1952 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1953 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1954 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1955 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1956 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1957 /* Navi14 */ 1958 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1959 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1960 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1961 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1962 1963 /* Renoir */ 1964 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1965 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1966 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1967 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1968 1969 /* Navi12 */ 1970 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1971 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1972 1973 /* Sienna_Cichlid */ 1974 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1975 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1976 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1977 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1978 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1979 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1980 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1981 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1982 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1983 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1984 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1985 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1986 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1987 1988 /* Yellow Carp */ 1989 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1990 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1991 1992 /* Navy_Flounder */ 1993 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1994 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1995 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1996 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1997 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1998 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1999 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2000 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2001 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2002 2003 /* DIMGREY_CAVEFISH */ 2004 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2005 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2006 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2007 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2008 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2009 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2010 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2011 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2012 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2013 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2014 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2015 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2016 2017 /* Aldebaran */ 2018 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2019 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2020 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2021 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2022 2023 /* CYAN_SKILLFISH */ 2024 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2025 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2026 2027 /* BEIGE_GOBY */ 2028 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2029 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2030 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2031 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2032 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2033 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2034 2035 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2036 .class = PCI_CLASS_DISPLAY_VGA << 8, 2037 .class_mask = 0xffffff, 2038 .driver_data = CHIP_IP_DISCOVERY }, 2039 2040 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2041 .class = PCI_CLASS_DISPLAY_OTHER << 8, 2042 .class_mask = 0xffffff, 2043 .driver_data = CHIP_IP_DISCOVERY }, 2044 2045 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2046 .class = AMD_ACCELERATOR_PROCESSING << 8, 2047 .class_mask = 0xffffff, 2048 .driver_data = CHIP_IP_DISCOVERY }, 2049 2050 {0, 0, 0} 2051 }; 2052 2053 MODULE_DEVICE_TABLE(pci, pciidlist); 2054 2055 static const struct drm_driver amdgpu_kms_driver; 2056 2057 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 2058 { 2059 struct pci_dev *p = NULL; 2060 int i; 2061 2062 /* 0 - GPU 2063 * 1 - audio 2064 * 2 - USB 2065 * 3 - UCSI 2066 */ 2067 for (i = 1; i < 4; i++) { 2068 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 2069 adev->pdev->bus->number, i); 2070 if (p) { 2071 pm_runtime_get_sync(&p->dev); 2072 pm_runtime_mark_last_busy(&p->dev); 2073 pm_runtime_put_autosuspend(&p->dev); 2074 pci_dev_put(p); 2075 } 2076 } 2077 } 2078 2079 static int amdgpu_pci_probe(struct pci_dev *pdev, 2080 const struct pci_device_id *ent) 2081 { 2082 struct drm_device *ddev; 2083 struct amdgpu_device *adev; 2084 unsigned long flags = ent->driver_data; 2085 int ret, retry = 0, i; 2086 bool supports_atomic = false; 2087 2088 /* skip devices which are owned by radeon */ 2089 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2090 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2091 return -ENODEV; 2092 } 2093 2094 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) 2095 amdgpu_aspm = 0; 2096 2097 if (amdgpu_virtual_display || 2098 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 2099 supports_atomic = true; 2100 2101 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2102 DRM_INFO("This hardware requires experimental hardware support.\n" 2103 "See modparam exp_hw_support\n"); 2104 return -ENODEV; 2105 } 2106 /* differentiate between P10 and P11 asics with the same DID */ 2107 if (pdev->device == 0x67FF && 2108 (pdev->revision == 0xE3 || 2109 pdev->revision == 0xE7 || 2110 pdev->revision == 0xF3 || 2111 pdev->revision == 0xF7)) { 2112 flags &= ~AMD_ASIC_MASK; 2113 flags |= CHIP_POLARIS10; 2114 } 2115 2116 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2117 * however, SME requires an indirect IOMMU mapping because the encryption 2118 * bit is beyond the DMA mask of the chip. 2119 */ 2120 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2121 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2122 dev_info(&pdev->dev, 2123 "SME is not compatible with RAVEN\n"); 2124 return -ENOTSUPP; 2125 } 2126 2127 #ifdef CONFIG_DRM_AMDGPU_SI 2128 if (!amdgpu_si_support) { 2129 switch (flags & AMD_ASIC_MASK) { 2130 case CHIP_TAHITI: 2131 case CHIP_PITCAIRN: 2132 case CHIP_VERDE: 2133 case CHIP_OLAND: 2134 case CHIP_HAINAN: 2135 dev_info(&pdev->dev, 2136 "SI support provided by radeon.\n"); 2137 dev_info(&pdev->dev, 2138 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 2139 ); 2140 return -ENODEV; 2141 } 2142 } 2143 #endif 2144 #ifdef CONFIG_DRM_AMDGPU_CIK 2145 if (!amdgpu_cik_support) { 2146 switch (flags & AMD_ASIC_MASK) { 2147 case CHIP_KAVERI: 2148 case CHIP_BONAIRE: 2149 case CHIP_HAWAII: 2150 case CHIP_KABINI: 2151 case CHIP_MULLINS: 2152 dev_info(&pdev->dev, 2153 "CIK support provided by radeon.\n"); 2154 dev_info(&pdev->dev, 2155 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 2156 ); 2157 return -ENODEV; 2158 } 2159 } 2160 #endif 2161 2162 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2163 if (IS_ERR(adev)) 2164 return PTR_ERR(adev); 2165 2166 adev->dev = &pdev->dev; 2167 adev->pdev = pdev; 2168 ddev = adev_to_drm(adev); 2169 2170 if (!supports_atomic) 2171 ddev->driver_features &= ~DRIVER_ATOMIC; 2172 2173 ret = pci_enable_device(pdev); 2174 if (ret) 2175 return ret; 2176 2177 pci_set_drvdata(pdev, ddev); 2178 2179 ret = amdgpu_driver_load_kms(adev, flags); 2180 if (ret) 2181 goto err_pci; 2182 2183 retry_init: 2184 ret = drm_dev_register(ddev, flags); 2185 if (ret == -EAGAIN && ++retry <= 3) { 2186 DRM_INFO("retry init %d\n", retry); 2187 /* Don't request EX mode too frequently which is attacking */ 2188 msleep(5000); 2189 goto retry_init; 2190 } else if (ret) { 2191 goto err_pci; 2192 } 2193 2194 ret = amdgpu_xcp_dev_register(adev, ent); 2195 if (ret) 2196 goto err_pci; 2197 2198 /* 2199 * 1. don't init fbdev on hw without DCE 2200 * 2. don't init fbdev if there are no connectors 2201 */ 2202 if (adev->mode_info.mode_config_initialized && 2203 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2204 /* select 8 bpp console on low vram cards */ 2205 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2206 drm_fbdev_generic_setup(adev_to_drm(adev), 8); 2207 else 2208 drm_fbdev_generic_setup(adev_to_drm(adev), 32); 2209 } 2210 2211 ret = amdgpu_debugfs_init(adev); 2212 if (ret) 2213 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2214 2215 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2216 /* only need to skip on ATPX */ 2217 if (amdgpu_device_supports_px(ddev)) 2218 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2219 /* we want direct complete for BOCO */ 2220 if (amdgpu_device_supports_boco(ddev)) 2221 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2222 DPM_FLAG_SMART_SUSPEND | 2223 DPM_FLAG_MAY_SKIP_RESUME); 2224 pm_runtime_use_autosuspend(ddev->dev); 2225 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2226 2227 pm_runtime_allow(ddev->dev); 2228 2229 pm_runtime_mark_last_busy(ddev->dev); 2230 pm_runtime_put_autosuspend(ddev->dev); 2231 2232 /* 2233 * For runpm implemented via BACO, PMFW will handle the 2234 * timing for BACO in and out: 2235 * - put ASIC into BACO state only when both video and 2236 * audio functions are in D3 state. 2237 * - pull ASIC out of BACO state when either video or 2238 * audio function is in D0 state. 2239 * Also, at startup, PMFW assumes both functions are in 2240 * D0 state. 2241 * 2242 * So if snd driver was loaded prior to amdgpu driver 2243 * and audio function was put into D3 state, there will 2244 * be no PMFW-aware D-state transition(D0->D3) on runpm 2245 * suspend. Thus the BACO will be not correctly kicked in. 2246 * 2247 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2248 * into D0 state. Then there will be a PMFW-aware D-state 2249 * transition(D0->D3) on runpm suspend. 2250 */ 2251 if (amdgpu_device_supports_baco(ddev) && 2252 !(adev->flags & AMD_IS_APU) && 2253 (adev->asic_type >= CHIP_NAVI10)) 2254 amdgpu_get_secondary_funcs(adev); 2255 } 2256 2257 return 0; 2258 2259 err_pci: 2260 pci_disable_device(pdev); 2261 return ret; 2262 } 2263 2264 static void 2265 amdgpu_pci_remove(struct pci_dev *pdev) 2266 { 2267 struct drm_device *dev = pci_get_drvdata(pdev); 2268 struct amdgpu_device *adev = drm_to_adev(dev); 2269 2270 amdgpu_xcp_dev_unplug(adev); 2271 drm_dev_unplug(dev); 2272 2273 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2274 pm_runtime_get_sync(dev->dev); 2275 pm_runtime_forbid(dev->dev); 2276 } 2277 2278 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2) && 2279 !amdgpu_sriov_vf(adev)) { 2280 bool need_to_reset_gpu = false; 2281 2282 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2283 struct amdgpu_hive_info *hive; 2284 2285 hive = amdgpu_get_xgmi_hive(adev); 2286 if (hive->device_remove_count == 0) 2287 need_to_reset_gpu = true; 2288 hive->device_remove_count++; 2289 amdgpu_put_xgmi_hive(hive); 2290 } else { 2291 need_to_reset_gpu = true; 2292 } 2293 2294 /* Workaround for ASICs need to reset SMU. 2295 * Called only when the first device is removed. 2296 */ 2297 if (need_to_reset_gpu) { 2298 struct amdgpu_reset_context reset_context; 2299 2300 adev->shutdown = true; 2301 memset(&reset_context, 0, sizeof(reset_context)); 2302 reset_context.method = AMD_RESET_METHOD_NONE; 2303 reset_context.reset_req_dev = adev; 2304 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2305 set_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context.flags); 2306 amdgpu_device_gpu_recover(adev, NULL, &reset_context); 2307 } 2308 } 2309 2310 amdgpu_driver_unload_kms(dev); 2311 2312 /* 2313 * Flush any in flight DMA operations from device. 2314 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2315 * StatusTransactions Pending bit. 2316 */ 2317 pci_disable_device(pdev); 2318 pci_wait_for_pending_transaction(pdev); 2319 } 2320 2321 static void 2322 amdgpu_pci_shutdown(struct pci_dev *pdev) 2323 { 2324 struct drm_device *dev = pci_get_drvdata(pdev); 2325 struct amdgpu_device *adev = drm_to_adev(dev); 2326 2327 if (amdgpu_ras_intr_triggered()) 2328 return; 2329 2330 /* if we are running in a VM, make sure the device 2331 * torn down properly on reboot/shutdown. 2332 * unfortunately we can't detect certain 2333 * hypervisors so just do this all the time. 2334 */ 2335 if (!amdgpu_passthrough(adev)) 2336 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2337 amdgpu_device_ip_suspend(adev); 2338 adev->mp1_state = PP_MP1_STATE_NONE; 2339 } 2340 2341 /** 2342 * amdgpu_drv_delayed_reset_work_handler - work handler for reset 2343 * 2344 * @work: work_struct. 2345 */ 2346 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) 2347 { 2348 struct list_head device_list; 2349 struct amdgpu_device *adev; 2350 int i, r; 2351 struct amdgpu_reset_context reset_context; 2352 2353 memset(&reset_context, 0, sizeof(reset_context)); 2354 2355 mutex_lock(&mgpu_info.mutex); 2356 if (mgpu_info.pending_reset == true) { 2357 mutex_unlock(&mgpu_info.mutex); 2358 return; 2359 } 2360 mgpu_info.pending_reset = true; 2361 mutex_unlock(&mgpu_info.mutex); 2362 2363 /* Use a common context, just need to make sure full reset is done */ 2364 reset_context.method = AMD_RESET_METHOD_NONE; 2365 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2366 2367 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2368 adev = mgpu_info.gpu_ins[i].adev; 2369 reset_context.reset_req_dev = adev; 2370 r = amdgpu_device_pre_asic_reset(adev, &reset_context); 2371 if (r) { 2372 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", 2373 r, adev_to_drm(adev)->unique); 2374 } 2375 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) 2376 r = -EALREADY; 2377 } 2378 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2379 adev = mgpu_info.gpu_ins[i].adev; 2380 flush_work(&adev->xgmi_reset_work); 2381 adev->gmc.xgmi.pending_reset = false; 2382 } 2383 2384 /* reset function will rebuild the xgmi hive info , clear it now */ 2385 for (i = 0; i < mgpu_info.num_dgpu; i++) 2386 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); 2387 2388 INIT_LIST_HEAD(&device_list); 2389 2390 for (i = 0; i < mgpu_info.num_dgpu; i++) 2391 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); 2392 2393 /* unregister the GPU first, reset function will add them back */ 2394 list_for_each_entry(adev, &device_list, reset_list) 2395 amdgpu_unregister_gpu_instance(adev); 2396 2397 /* Use a common context, just need to make sure full reset is done */ 2398 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); 2399 r = amdgpu_do_asic_reset(&device_list, &reset_context); 2400 2401 if (r) { 2402 DRM_ERROR("reinit gpus failure"); 2403 return; 2404 } 2405 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2406 adev = mgpu_info.gpu_ins[i].adev; 2407 if (!adev->kfd.init_complete) 2408 amdgpu_amdkfd_device_init(adev); 2409 amdgpu_ttm_set_buffer_funcs_status(adev, true); 2410 } 2411 return; 2412 } 2413 2414 static int amdgpu_pmops_prepare(struct device *dev) 2415 { 2416 struct drm_device *drm_dev = dev_get_drvdata(dev); 2417 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2418 2419 /* Return a positive number here so 2420 * DPM_FLAG_SMART_SUSPEND works properly 2421 */ 2422 if (amdgpu_device_supports_boco(drm_dev)) 2423 return pm_runtime_suspended(dev); 2424 2425 /* if we will not support s3 or s2i for the device 2426 * then skip suspend 2427 */ 2428 if (!amdgpu_acpi_is_s0ix_active(adev) && 2429 !amdgpu_acpi_is_s3_active(adev)) 2430 return 1; 2431 2432 return 0; 2433 } 2434 2435 static void amdgpu_pmops_complete(struct device *dev) 2436 { 2437 /* nothing to do */ 2438 } 2439 2440 static int amdgpu_pmops_suspend(struct device *dev) 2441 { 2442 struct drm_device *drm_dev = dev_get_drvdata(dev); 2443 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2444 2445 if (amdgpu_acpi_is_s0ix_active(adev)) 2446 adev->in_s0ix = true; 2447 else if (amdgpu_acpi_is_s3_active(adev)) 2448 adev->in_s3 = true; 2449 if (!adev->in_s0ix && !adev->in_s3) 2450 return 0; 2451 return amdgpu_device_suspend(drm_dev, true); 2452 } 2453 2454 static int amdgpu_pmops_suspend_noirq(struct device *dev) 2455 { 2456 struct drm_device *drm_dev = dev_get_drvdata(dev); 2457 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2458 2459 if (amdgpu_acpi_should_gpu_reset(adev)) 2460 return amdgpu_asic_reset(adev); 2461 2462 return 0; 2463 } 2464 2465 static int amdgpu_pmops_resume(struct device *dev) 2466 { 2467 struct drm_device *drm_dev = dev_get_drvdata(dev); 2468 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2469 int r; 2470 2471 if (!adev->in_s0ix && !adev->in_s3) 2472 return 0; 2473 2474 /* Avoids registers access if device is physically gone */ 2475 if (!pci_device_is_present(adev->pdev)) 2476 adev->no_hw_access = true; 2477 2478 r = amdgpu_device_resume(drm_dev, true); 2479 if (amdgpu_acpi_is_s0ix_active(adev)) 2480 adev->in_s0ix = false; 2481 else 2482 adev->in_s3 = false; 2483 return r; 2484 } 2485 2486 static int amdgpu_pmops_freeze(struct device *dev) 2487 { 2488 struct drm_device *drm_dev = dev_get_drvdata(dev); 2489 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2490 int r; 2491 2492 adev->in_s4 = true; 2493 r = amdgpu_device_suspend(drm_dev, true); 2494 adev->in_s4 = false; 2495 if (r) 2496 return r; 2497 2498 if (amdgpu_acpi_should_gpu_reset(adev)) 2499 return amdgpu_asic_reset(adev); 2500 return 0; 2501 } 2502 2503 static int amdgpu_pmops_thaw(struct device *dev) 2504 { 2505 struct drm_device *drm_dev = dev_get_drvdata(dev); 2506 2507 return amdgpu_device_resume(drm_dev, true); 2508 } 2509 2510 static int amdgpu_pmops_poweroff(struct device *dev) 2511 { 2512 struct drm_device *drm_dev = dev_get_drvdata(dev); 2513 2514 return amdgpu_device_suspend(drm_dev, true); 2515 } 2516 2517 static int amdgpu_pmops_restore(struct device *dev) 2518 { 2519 struct drm_device *drm_dev = dev_get_drvdata(dev); 2520 2521 return amdgpu_device_resume(drm_dev, true); 2522 } 2523 2524 static int amdgpu_runtime_idle_check_display(struct device *dev) 2525 { 2526 struct pci_dev *pdev = to_pci_dev(dev); 2527 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2528 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2529 2530 if (adev->mode_info.num_crtc) { 2531 struct drm_connector *list_connector; 2532 struct drm_connector_list_iter iter; 2533 int ret = 0; 2534 2535 /* XXX: Return busy if any displays are connected to avoid 2536 * possible display wakeups after runtime resume due to 2537 * hotplug events in case any displays were connected while 2538 * the GPU was in suspend. Remove this once that is fixed. 2539 */ 2540 mutex_lock(&drm_dev->mode_config.mutex); 2541 drm_connector_list_iter_begin(drm_dev, &iter); 2542 drm_for_each_connector_iter(list_connector, &iter) { 2543 if (list_connector->status == connector_status_connected) { 2544 ret = -EBUSY; 2545 break; 2546 } 2547 } 2548 drm_connector_list_iter_end(&iter); 2549 mutex_unlock(&drm_dev->mode_config.mutex); 2550 2551 if (ret) 2552 return ret; 2553 2554 if (adev->dc_enabled) { 2555 struct drm_crtc *crtc; 2556 2557 drm_for_each_crtc(crtc, drm_dev) { 2558 drm_modeset_lock(&crtc->mutex, NULL); 2559 if (crtc->state->active) 2560 ret = -EBUSY; 2561 drm_modeset_unlock(&crtc->mutex); 2562 if (ret < 0) 2563 break; 2564 } 2565 } else { 2566 mutex_lock(&drm_dev->mode_config.mutex); 2567 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2568 2569 drm_connector_list_iter_begin(drm_dev, &iter); 2570 drm_for_each_connector_iter(list_connector, &iter) { 2571 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2572 ret = -EBUSY; 2573 break; 2574 } 2575 } 2576 2577 drm_connector_list_iter_end(&iter); 2578 2579 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2580 mutex_unlock(&drm_dev->mode_config.mutex); 2581 } 2582 if (ret) 2583 return ret; 2584 } 2585 2586 return 0; 2587 } 2588 2589 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2590 { 2591 struct pci_dev *pdev = to_pci_dev(dev); 2592 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2593 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2594 int ret, i; 2595 2596 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2597 pm_runtime_forbid(dev); 2598 return -EBUSY; 2599 } 2600 2601 ret = amdgpu_runtime_idle_check_display(dev); 2602 if (ret) 2603 return ret; 2604 2605 /* wait for all rings to drain before suspending */ 2606 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2607 struct amdgpu_ring *ring = adev->rings[i]; 2608 if (ring && ring->sched.ready) { 2609 ret = amdgpu_fence_wait_empty(ring); 2610 if (ret) 2611 return -EBUSY; 2612 } 2613 } 2614 2615 adev->in_runpm = true; 2616 if (amdgpu_device_supports_px(drm_dev)) 2617 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2618 2619 /* 2620 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2621 * proper cleanups and put itself into a state ready for PNP. That 2622 * can address some random resuming failure observed on BOCO capable 2623 * platforms. 2624 * TODO: this may be also needed for PX capable platform. 2625 */ 2626 if (amdgpu_device_supports_boco(drm_dev)) 2627 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2628 2629 ret = amdgpu_device_suspend(drm_dev, false); 2630 if (ret) { 2631 adev->in_runpm = false; 2632 if (amdgpu_device_supports_boco(drm_dev)) 2633 adev->mp1_state = PP_MP1_STATE_NONE; 2634 return ret; 2635 } 2636 2637 if (amdgpu_device_supports_boco(drm_dev)) 2638 adev->mp1_state = PP_MP1_STATE_NONE; 2639 2640 if (amdgpu_device_supports_px(drm_dev)) { 2641 /* Only need to handle PCI state in the driver for ATPX 2642 * PCI core handles it for _PR3. 2643 */ 2644 amdgpu_device_cache_pci_state(pdev); 2645 pci_disable_device(pdev); 2646 pci_ignore_hotplug(pdev); 2647 pci_set_power_state(pdev, PCI_D3cold); 2648 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2649 } else if (amdgpu_device_supports_boco(drm_dev)) { 2650 /* nothing to do */ 2651 } else if (amdgpu_device_supports_baco(drm_dev)) { 2652 amdgpu_device_baco_enter(drm_dev); 2653 } 2654 2655 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n"); 2656 2657 return 0; 2658 } 2659 2660 static int amdgpu_pmops_runtime_resume(struct device *dev) 2661 { 2662 struct pci_dev *pdev = to_pci_dev(dev); 2663 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2664 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2665 int ret; 2666 2667 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) 2668 return -EINVAL; 2669 2670 /* Avoids registers access if device is physically gone */ 2671 if (!pci_device_is_present(adev->pdev)) 2672 adev->no_hw_access = true; 2673 2674 if (amdgpu_device_supports_px(drm_dev)) { 2675 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2676 2677 /* Only need to handle PCI state in the driver for ATPX 2678 * PCI core handles it for _PR3. 2679 */ 2680 pci_set_power_state(pdev, PCI_D0); 2681 amdgpu_device_load_pci_state(pdev); 2682 ret = pci_enable_device(pdev); 2683 if (ret) 2684 return ret; 2685 pci_set_master(pdev); 2686 } else if (amdgpu_device_supports_boco(drm_dev)) { 2687 /* Only need to handle PCI state in the driver for ATPX 2688 * PCI core handles it for _PR3. 2689 */ 2690 pci_set_master(pdev); 2691 } else if (amdgpu_device_supports_baco(drm_dev)) { 2692 amdgpu_device_baco_exit(drm_dev); 2693 } 2694 ret = amdgpu_device_resume(drm_dev, false); 2695 if (ret) { 2696 if (amdgpu_device_supports_px(drm_dev)) 2697 pci_disable_device(pdev); 2698 return ret; 2699 } 2700 2701 if (amdgpu_device_supports_px(drm_dev)) 2702 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2703 adev->in_runpm = false; 2704 return 0; 2705 } 2706 2707 static int amdgpu_pmops_runtime_idle(struct device *dev) 2708 { 2709 struct drm_device *drm_dev = dev_get_drvdata(dev); 2710 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2711 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 2712 int ret = 1; 2713 2714 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2715 pm_runtime_forbid(dev); 2716 return -EBUSY; 2717 } 2718 2719 ret = amdgpu_runtime_idle_check_display(dev); 2720 2721 pm_runtime_mark_last_busy(dev); 2722 pm_runtime_autosuspend(dev); 2723 return ret; 2724 } 2725 2726 long amdgpu_drm_ioctl(struct file *filp, 2727 unsigned int cmd, unsigned long arg) 2728 { 2729 struct drm_file *file_priv = filp->private_data; 2730 struct drm_device *dev; 2731 long ret; 2732 dev = file_priv->minor->dev; 2733 ret = pm_runtime_get_sync(dev->dev); 2734 if (ret < 0) 2735 goto out; 2736 2737 ret = drm_ioctl(filp, cmd, arg); 2738 2739 pm_runtime_mark_last_busy(dev->dev); 2740 out: 2741 pm_runtime_put_autosuspend(dev->dev); 2742 return ret; 2743 } 2744 2745 static const struct dev_pm_ops amdgpu_pm_ops = { 2746 .prepare = amdgpu_pmops_prepare, 2747 .complete = amdgpu_pmops_complete, 2748 .suspend = amdgpu_pmops_suspend, 2749 .suspend_noirq = amdgpu_pmops_suspend_noirq, 2750 .resume = amdgpu_pmops_resume, 2751 .freeze = amdgpu_pmops_freeze, 2752 .thaw = amdgpu_pmops_thaw, 2753 .poweroff = amdgpu_pmops_poweroff, 2754 .restore = amdgpu_pmops_restore, 2755 .runtime_suspend = amdgpu_pmops_runtime_suspend, 2756 .runtime_resume = amdgpu_pmops_runtime_resume, 2757 .runtime_idle = amdgpu_pmops_runtime_idle, 2758 }; 2759 2760 static int amdgpu_flush(struct file *f, fl_owner_t id) 2761 { 2762 struct drm_file *file_priv = f->private_data; 2763 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2764 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2765 2766 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 2767 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 2768 2769 return timeout >= 0 ? 0 : timeout; 2770 } 2771 2772 static const struct file_operations amdgpu_driver_kms_fops = { 2773 .owner = THIS_MODULE, 2774 .open = drm_open, 2775 .flush = amdgpu_flush, 2776 .release = drm_release, 2777 .unlocked_ioctl = amdgpu_drm_ioctl, 2778 .mmap = drm_gem_mmap, 2779 .poll = drm_poll, 2780 .read = drm_read, 2781 #ifdef CONFIG_COMPAT 2782 .compat_ioctl = amdgpu_kms_compat_ioctl, 2783 #endif 2784 #ifdef CONFIG_PROC_FS 2785 .show_fdinfo = amdgpu_show_fdinfo 2786 #endif 2787 }; 2788 2789 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 2790 { 2791 struct drm_file *file; 2792 2793 if (!filp) 2794 return -EINVAL; 2795 2796 if (filp->f_op != &amdgpu_driver_kms_fops) { 2797 return -EINVAL; 2798 } 2799 2800 file = filp->private_data; 2801 *fpriv = file->driver_priv; 2802 return 0; 2803 } 2804 2805 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 2806 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2807 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2808 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2809 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 2810 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2811 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2812 /* KMS */ 2813 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2814 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2815 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2816 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2817 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2818 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2819 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2820 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2821 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2822 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2823 }; 2824 2825 static const struct drm_driver amdgpu_kms_driver = { 2826 .driver_features = 2827 DRIVER_ATOMIC | 2828 DRIVER_GEM | 2829 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 2830 DRIVER_SYNCOBJ_TIMELINE, 2831 .open = amdgpu_driver_open_kms, 2832 .postclose = amdgpu_driver_postclose_kms, 2833 .lastclose = amdgpu_driver_lastclose_kms, 2834 .ioctls = amdgpu_ioctls_kms, 2835 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2836 .dumb_create = amdgpu_mode_dumb_create, 2837 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2838 .fops = &amdgpu_driver_kms_fops, 2839 .release = &amdgpu_driver_release_kms, 2840 2841 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 2842 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 2843 .gem_prime_import = amdgpu_gem_prime_import, 2844 .gem_prime_mmap = drm_gem_prime_mmap, 2845 2846 .name = DRIVER_NAME, 2847 .desc = DRIVER_DESC, 2848 .date = DRIVER_DATE, 2849 .major = KMS_DRIVER_MAJOR, 2850 .minor = KMS_DRIVER_MINOR, 2851 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2852 }; 2853 2854 const struct drm_driver amdgpu_partition_driver = { 2855 .driver_features = 2856 DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ | 2857 DRIVER_SYNCOBJ_TIMELINE, 2858 .open = amdgpu_driver_open_kms, 2859 .postclose = amdgpu_driver_postclose_kms, 2860 .lastclose = amdgpu_driver_lastclose_kms, 2861 .ioctls = amdgpu_ioctls_kms, 2862 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2863 .dumb_create = amdgpu_mode_dumb_create, 2864 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2865 .fops = &amdgpu_driver_kms_fops, 2866 .release = &amdgpu_driver_release_kms, 2867 2868 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 2869 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 2870 .gem_prime_import = amdgpu_gem_prime_import, 2871 .gem_prime_mmap = drm_gem_prime_mmap, 2872 2873 .name = DRIVER_NAME, 2874 .desc = DRIVER_DESC, 2875 .date = DRIVER_DATE, 2876 .major = KMS_DRIVER_MAJOR, 2877 .minor = KMS_DRIVER_MINOR, 2878 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2879 }; 2880 2881 static struct pci_error_handlers amdgpu_pci_err_handler = { 2882 .error_detected = amdgpu_pci_error_detected, 2883 .mmio_enabled = amdgpu_pci_mmio_enabled, 2884 .slot_reset = amdgpu_pci_slot_reset, 2885 .resume = amdgpu_pci_resume, 2886 }; 2887 2888 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 2889 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 2890 extern const struct attribute_group amdgpu_vbios_version_attr_group; 2891 2892 static const struct attribute_group *amdgpu_sysfs_groups[] = { 2893 &amdgpu_vram_mgr_attr_group, 2894 &amdgpu_gtt_mgr_attr_group, 2895 &amdgpu_vbios_version_attr_group, 2896 NULL, 2897 }; 2898 2899 2900 static struct pci_driver amdgpu_kms_pci_driver = { 2901 .name = DRIVER_NAME, 2902 .id_table = pciidlist, 2903 .probe = amdgpu_pci_probe, 2904 .remove = amdgpu_pci_remove, 2905 .shutdown = amdgpu_pci_shutdown, 2906 .driver.pm = &amdgpu_pm_ops, 2907 .err_handler = &amdgpu_pci_err_handler, 2908 .dev_groups = amdgpu_sysfs_groups, 2909 }; 2910 2911 static int __init amdgpu_init(void) 2912 { 2913 int r; 2914 2915 if (drm_firmware_drivers_only()) 2916 return -EINVAL; 2917 2918 r = amdgpu_sync_init(); 2919 if (r) 2920 goto error_sync; 2921 2922 r = amdgpu_fence_slab_init(); 2923 if (r) 2924 goto error_fence; 2925 2926 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 2927 amdgpu_register_atpx_handler(); 2928 amdgpu_acpi_detect(); 2929 2930 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 2931 amdgpu_amdkfd_init(); 2932 2933 /* let modprobe override vga console setting */ 2934 return pci_register_driver(&amdgpu_kms_pci_driver); 2935 2936 error_fence: 2937 amdgpu_sync_fini(); 2938 2939 error_sync: 2940 return r; 2941 } 2942 2943 static void __exit amdgpu_exit(void) 2944 { 2945 amdgpu_amdkfd_fini(); 2946 pci_unregister_driver(&amdgpu_kms_pci_driver); 2947 amdgpu_unregister_atpx_handler(); 2948 amdgpu_acpi_release(); 2949 amdgpu_sync_fini(); 2950 amdgpu_fence_slab_fini(); 2951 mmu_notifier_synchronize(); 2952 amdgpu_xcp_drv_release(); 2953 } 2954 2955 module_init(amdgpu_init); 2956 module_exit(amdgpu_exit); 2957 2958 MODULE_AUTHOR(DRIVER_AUTHOR); 2959 MODULE_DESCRIPTION(DRIVER_DESC); 2960 MODULE_LICENSE("GPL and additional rights"); 2961