1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/clients/drm_client_setup.h> 27 #include <drm/drm_drv.h> 28 #include <drm/drm_fbdev_ttm.h> 29 #include <drm/drm_gem.h> 30 #include <drm/drm_managed.h> 31 #include <drm/drm_pciids.h> 32 #include <drm/drm_probe_helper.h> 33 #include <drm/drm_vblank.h> 34 35 #include <linux/cc_platform.h> 36 #include <linux/console.h> 37 #include <linux/dynamic_debug.h> 38 #include <linux/module.h> 39 #include <linux/mmu_notifier.h> 40 #include <linux/pm_runtime.h> 41 #include <linux/suspend.h> 42 #include <linux/vga_switcheroo.h> 43 44 #include "amdgpu.h" 45 #include "amdgpu_amdkfd.h" 46 #include "amdgpu_dma_buf.h" 47 #include "amdgpu_drv.h" 48 #include "amdgpu_fdinfo.h" 49 #include "amdgpu_irq.h" 50 #include "amdgpu_psp.h" 51 #include "amdgpu_ras.h" 52 #include "amdgpu_reset.h" 53 #include "amdgpu_sched.h" 54 #include "amdgpu_xgmi.h" 55 #include "amdgpu_userq.h" 56 #include "amdgpu_userq_fence.h" 57 #include "../amdxcp/amdgpu_xcp_drv.h" 58 59 /* 60 * KMS wrapper. 61 * - 3.0.0 - initial driver 62 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 63 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 64 * at the end of IBs. 65 * - 3.3.0 - Add VM support for UVD on supported hardware. 66 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 67 * - 3.5.0 - Add support for new UVD_NO_OP register. 68 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 69 * - 3.7.0 - Add support for VCE clock list packet 70 * - 3.8.0 - Add support raster config init in the kernel 71 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 72 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 73 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 74 * - 3.12.0 - Add query for double offchip LDS buffers 75 * - 3.13.0 - Add PRT support 76 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 77 * - 3.15.0 - Export more gpu info for gfx9 78 * - 3.16.0 - Add reserved vmid support 79 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 80 * - 3.18.0 - Export gpu always on cu bitmap 81 * - 3.19.0 - Add support for UVD MJPEG decode 82 * - 3.20.0 - Add support for local BOs 83 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 84 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 85 * - 3.23.0 - Add query for VRAM lost counter 86 * - 3.24.0 - Add high priority compute support for gfx9 87 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 88 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 89 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation. 90 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 91 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 92 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 93 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 94 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 95 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 96 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 97 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 98 * - 3.36.0 - Allow reading more status registers on si/cik 99 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 100 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 101 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 102 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 103 * - 3.41.0 - Add video codec query 104 * - 3.42.0 - Add 16bpc fixed point display support 105 * - 3.43.0 - Add device hot plug/unplug support 106 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 107 * - 3.45.0 - Add context ioctl stable pstate interface 108 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm 109 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags 110 * - 3.48.0 - Add IP discovery version info to HW INFO 111 * - 3.49.0 - Add gang submit into CS IOCTL 112 * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock 113 * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock 114 * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl 115 * 3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields: 116 * tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size, 117 * gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi 118 * 3.53.0 - Support for GFX11 CP GFX shadowing 119 * 3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support 120 * - 3.55.0 - Add AMDGPU_INFO_GPUVM_FAULT query 121 * - 3.56.0 - Update IB start address and size alignment for decode and encode 122 * - 3.57.0 - Compute tunneling on GFX10+ 123 * - 3.58.0 - Add GFX12 DCC support 124 * - 3.59.0 - Cleared VRAM 125 * - 3.60.0 - Add AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE (Vulkan requirement) 126 * - 3.61.0 - Contains fix for RV/PCO compute queues 127 * - 3.62.0 - Add AMDGPU_IDS_FLAGS_MODE_PF, AMDGPU_IDS_FLAGS_MODE_VF & AMDGPU_IDS_FLAGS_MODE_PT 128 * - 3.63.0 - GFX12 display DCC supports 256B max compressed block size 129 * - 3.64.0 - Userq IP support query 130 */ 131 #define KMS_DRIVER_MAJOR 3 132 #define KMS_DRIVER_MINOR 64 133 #define KMS_DRIVER_PATCHLEVEL 0 134 135 /* 136 * amdgpu.debug module options. Are all disabled by default 137 */ 138 enum AMDGPU_DEBUG_MASK { 139 AMDGPU_DEBUG_VM = BIT(0), 140 AMDGPU_DEBUG_LARGEBAR = BIT(1), 141 AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY = BIT(2), 142 AMDGPU_DEBUG_USE_VRAM_FW_BUF = BIT(3), 143 AMDGPU_DEBUG_ENABLE_RAS_ACA = BIT(4), 144 AMDGPU_DEBUG_ENABLE_EXP_RESETS = BIT(5), 145 AMDGPU_DEBUG_DISABLE_GPU_RING_RESET = BIT(6), 146 AMDGPU_DEBUG_SMU_POOL = BIT(7), 147 AMDGPU_DEBUG_VM_USERPTR = BIT(8), 148 AMDGPU_DEBUG_DISABLE_RAS_CE_LOG = BIT(9), 149 AMDGPU_DEBUG_ENABLE_CE_CS = BIT(10) 150 }; 151 152 unsigned int amdgpu_vram_limit = UINT_MAX; 153 int amdgpu_vis_vram_limit; 154 int amdgpu_gart_size = -1; /* auto */ 155 int amdgpu_gtt_size = -1; /* auto */ 156 int amdgpu_moverate = -1; /* auto */ 157 int amdgpu_audio = -1; 158 int amdgpu_disp_priority; 159 int amdgpu_hw_i2c; 160 int amdgpu_pcie_gen2 = -1; 161 int amdgpu_msi = -1; 162 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 163 int amdgpu_dpm = -1; 164 int amdgpu_fw_load_type = -1; 165 int amdgpu_aspm = -1; 166 int amdgpu_runtime_pm = -1; 167 uint amdgpu_ip_block_mask = 0xffffffff; 168 int amdgpu_bapm = -1; 169 int amdgpu_deep_color; 170 int amdgpu_vm_size = -1; 171 int amdgpu_vm_fragment_size = -1; 172 int amdgpu_vm_block_size = -1; 173 int amdgpu_vm_fault_stop; 174 int amdgpu_vm_update_mode = -1; 175 int amdgpu_exp_hw_support; 176 int amdgpu_dc = -1; 177 int amdgpu_sched_jobs = 32; 178 int amdgpu_sched_hw_submission = 2; 179 uint amdgpu_pcie_gen_cap; 180 uint amdgpu_pcie_lane_cap; 181 u64 amdgpu_cg_mask = 0xffffffffffffffff; 182 uint amdgpu_pg_mask = 0xffffffff; 183 uint amdgpu_sdma_phase_quantum = 32; 184 char *amdgpu_disable_cu; 185 char *amdgpu_virtual_display; 186 int amdgpu_enforce_isolation = -1; 187 int amdgpu_modeset = -1; 188 189 /* Specifies the default granularity for SVM, used in buffer 190 * migration and restoration of backing memory when handling 191 * recoverable page faults. 192 * 193 * The value is given as log(numPages(buffer)); for a 2 MiB 194 * buffer it computes to be 9 195 */ 196 uint amdgpu_svm_default_granularity = 9; 197 198 /* 199 * OverDrive(bit 14) disabled by default 200 * GFX DCS(bit 19) disabled by default 201 */ 202 uint amdgpu_pp_feature_mask = 0xfff7bfff; 203 uint amdgpu_force_long_training; 204 int amdgpu_lbpw = -1; 205 int amdgpu_compute_multipipe = -1; 206 int amdgpu_gpu_recovery = -1; /* auto */ 207 int amdgpu_emu_mode; 208 uint amdgpu_smu_memory_pool_size; 209 int amdgpu_smu_pptable_id = -1; 210 /* 211 * FBC (bit 0) disabled by default 212 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 213 * - With this, for multiple monitors in sync(e.g. with the same model), 214 * mclk switching will be allowed. And the mclk will be not foced to the 215 * highest. That helps saving some idle power. 216 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 217 * PSR (bit 3) disabled by default 218 * EDP NO POWER SEQUENCING (bit 4) disabled by default 219 */ 220 uint amdgpu_dc_feature_mask = 2; 221 uint amdgpu_dc_debug_mask; 222 uint amdgpu_dc_visual_confirm; 223 int amdgpu_async_gfx_ring = 1; 224 int amdgpu_mcbp = -1; 225 int amdgpu_discovery = -1; 226 int amdgpu_mes; 227 int amdgpu_mes_log_enable = 0; 228 int amdgpu_mes_kiq; 229 int amdgpu_uni_mes = 1; 230 int amdgpu_noretry = -1; 231 int amdgpu_force_asic_type = -1; 232 int amdgpu_tmz = -1; /* auto */ 233 uint amdgpu_freesync_vid_mode; 234 int amdgpu_reset_method = -1; /* auto */ 235 int amdgpu_num_kcq = -1; 236 int amdgpu_smartshift_bias; 237 int amdgpu_use_xgmi_p2p = 1; 238 int amdgpu_vcnfw_log; 239 int amdgpu_sg_display = -1; /* auto */ 240 int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE; 241 int amdgpu_umsch_mm; 242 int amdgpu_seamless = -1; /* auto */ 243 uint amdgpu_debug_mask; 244 int amdgpu_agp = -1; /* auto */ 245 int amdgpu_wbrf = -1; 246 int amdgpu_damage_clips = -1; /* auto */ 247 int amdgpu_umsch_mm_fwlog; 248 int amdgpu_rebar = -1; /* auto */ 249 int amdgpu_user_queue = -1; 250 251 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 252 "DRM_UT_CORE", 253 "DRM_UT_DRIVER", 254 "DRM_UT_KMS", 255 "DRM_UT_PRIME", 256 "DRM_UT_ATOMIC", 257 "DRM_UT_VBL", 258 "DRM_UT_STATE", 259 "DRM_UT_LEASE", 260 "DRM_UT_DP", 261 "DRM_UT_DRMRES"); 262 263 struct amdgpu_mgpu_info mgpu_info = { 264 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 265 }; 266 int amdgpu_ras_enable = -1; 267 uint amdgpu_ras_mask = 0xffffffff; 268 int amdgpu_bad_page_threshold = -1; 269 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 270 .timeout_fatal_disable = false, 271 .period = 0x0, /* default to 0x0 (timeout disable) */ 272 }; 273 274 /** 275 * DOC: vramlimit (int) 276 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 277 */ 278 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 279 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 280 281 /** 282 * DOC: vis_vramlimit (int) 283 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 284 */ 285 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 286 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 287 288 /** 289 * DOC: gartsize (uint) 290 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing. 291 * The default is -1 (The size depends on asic). 292 */ 293 MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)"); 294 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 295 296 /** 297 * DOC: gttsize (int) 298 * Restrict the size of GTT domain (for userspace use) in MiB for testing. 299 * The default is -1 (Use value specified by TTM). 300 * This parameter is deprecated and will be removed in the future. 301 */ 302 MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)"); 303 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 304 305 /** 306 * DOC: moverate (int) 307 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 308 */ 309 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 310 module_param_named(moverate, amdgpu_moverate, int, 0600); 311 312 /** 313 * DOC: audio (int) 314 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 315 */ 316 MODULE_PARM_DESC(audio, "HDMI/DP Audio enable for non DC displays (-1 = auto, 0 = disable, 1 = enable)"); 317 module_param_named(audio, amdgpu_audio, int, 0444); 318 319 /** 320 * DOC: disp_priority (int) 321 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 322 */ 323 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 324 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 325 326 /** 327 * DOC: hw_i2c (int) 328 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 329 */ 330 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 331 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 332 333 /** 334 * DOC: pcie_gen2 (int) 335 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 336 */ 337 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 338 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 339 340 /** 341 * DOC: msi (int) 342 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 343 */ 344 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 345 module_param_named(msi, amdgpu_msi, int, 0444); 346 347 /** 348 * DOC: svm_default_granularity (uint) 349 * Used in buffer migration and handling of recoverable page faults 350 */ 351 MODULE_PARM_DESC(svm_default_granularity, "SVM's default granularity in log(2^Pages), default 9 = 2^9 = 2 MiB"); 352 module_param_named(svm_default_granularity, amdgpu_svm_default_granularity, uint, 0644); 353 354 /** 355 * DOC: lockup_timeout (string) 356 * Set GPU scheduler timeout value in ms. 357 * 358 * The format can be [single value] for setting all timeouts at once or 359 * [GFX,Compute,SDMA,Video] to set individual timeouts. 360 * Negative values mean infinity. 361 * 362 * By default(with no lockup_timeout settings), the timeout for all queues is 2000. 363 */ 364 MODULE_PARM_DESC(lockup_timeout, 365 "GPU lockup timeout in ms (default: 2000. 0: keep default value. negative: infinity timeout), format: [single value for all] or [GFX,Compute,SDMA,Video]."); 366 module_param_string(lockup_timeout, amdgpu_lockup_timeout, 367 sizeof(amdgpu_lockup_timeout), 0444); 368 369 /** 370 * DOC: dpm (int) 371 * Override for dynamic power management setting 372 * (0 = disable, 1 = enable) 373 * The default is -1 (auto). 374 */ 375 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 376 module_param_named(dpm, amdgpu_dpm, int, 0444); 377 378 /** 379 * DOC: fw_load_type (int) 380 * Set different firmware loading type for debugging, if supported. 381 * Set to 0 to force direct loading if supported by the ASIC. Set 382 * to -1 to select the default loading mode for the ASIC, as defined 383 * by the driver. The default is -1 (auto). 384 */ 385 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); 386 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 387 388 /** 389 * DOC: aspm (int) 390 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 391 */ 392 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 393 module_param_named(aspm, amdgpu_aspm, int, 0444); 394 395 /** 396 * DOC: runpm (int) 397 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 398 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 399 * Setting the value to 0 disables this functionality. 400 * Setting the value to -2 is auto enabled with power down when displays are attached. 401 */ 402 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto, -2 = auto with displays)"); 403 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 404 405 /** 406 * DOC: ip_block_mask (uint) 407 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 408 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 409 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 410 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 411 */ 412 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 413 module_param_named_unsafe(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 414 415 /** 416 * DOC: bapm (int) 417 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 418 * The default -1 (auto, enabled) 419 */ 420 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 421 module_param_named(bapm, amdgpu_bapm, int, 0444); 422 423 /** 424 * DOC: deep_color (int) 425 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 426 */ 427 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 428 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 429 430 /** 431 * DOC: vm_size (int) 432 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 433 */ 434 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 435 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 436 437 /** 438 * DOC: vm_fragment_size (int) 439 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 440 */ 441 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 442 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 443 444 /** 445 * DOC: vm_block_size (int) 446 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 447 */ 448 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 449 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 450 451 /** 452 * DOC: vm_fault_stop (int) 453 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 454 */ 455 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 456 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 457 458 /** 459 * DOC: vm_update_mode (int) 460 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 461 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 462 */ 463 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 464 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 465 466 /** 467 * DOC: exp_hw_support (int) 468 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 469 */ 470 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 471 module_param_named_unsafe(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 472 473 /** 474 * DOC: dc (int) 475 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 476 */ 477 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 478 module_param_named(dc, amdgpu_dc, int, 0444); 479 480 /** 481 * DOC: sched_jobs (int) 482 * Override the max number of jobs supported in the sw queue. The default is 32. 483 */ 484 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 485 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 486 487 /** 488 * DOC: sched_hw_submission (int) 489 * Override the max number of HW submissions. The default is 2. 490 */ 491 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 492 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 493 494 /** 495 * DOC: ppfeaturemask (hexint) 496 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 497 * The default is the current set of stable power features. 498 */ 499 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 500 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 501 502 /** 503 * DOC: forcelongtraining (uint) 504 * Force long memory training in resume. 505 * The default is zero, indicates short training in resume. 506 */ 507 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 508 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 509 510 /** 511 * DOC: pcie_gen_cap (uint) 512 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 513 * The default is 0 (automatic for each asic). 514 */ 515 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 516 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 517 518 /** 519 * DOC: pcie_lane_cap (uint) 520 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 521 * The default is 0 (automatic for each asic). 522 */ 523 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 524 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 525 526 /** 527 * DOC: cg_mask (ullong) 528 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 529 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 530 */ 531 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 532 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 533 534 /** 535 * DOC: pg_mask (uint) 536 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 537 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 538 */ 539 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 540 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 541 542 /** 543 * DOC: sdma_phase_quantum (uint) 544 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 545 */ 546 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 547 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 548 549 /** 550 * DOC: disable_cu (charp) 551 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 552 */ 553 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 554 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 555 556 /** 557 * DOC: virtual_display (charp) 558 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 559 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 560 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 561 * device at 26:00.0. The default is NULL. 562 */ 563 MODULE_PARM_DESC(virtual_display, 564 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 565 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 566 567 /** 568 * DOC: lbpw (int) 569 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 570 */ 571 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 572 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 573 574 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 575 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 576 577 /** 578 * DOC: gpu_recovery (int) 579 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 580 */ 581 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 582 module_param_named_unsafe(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 583 584 /** 585 * DOC: emu_mode (int) 586 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 587 */ 588 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 589 module_param_named_unsafe(emu_mode, amdgpu_emu_mode, int, 0444); 590 591 /** 592 * DOC: ras_enable (int) 593 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 594 */ 595 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 596 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 597 598 /** 599 * DOC: ras_mask (uint) 600 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 601 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 602 */ 603 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 604 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 605 606 /** 607 * DOC: timeout_fatal_disable (bool) 608 * Disable Watchdog timeout fatal error event 609 */ 610 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 611 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 612 613 /** 614 * DOC: timeout_period (uint) 615 * Modify the watchdog timeout max_cycles as (1 << period) 616 */ 617 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 618 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 619 620 /** 621 * DOC: si_support (int) 622 * 1 = enabled, 0 = disabled, -1 = default 623 * 624 * SI (Southern Islands) are first generation GCN GPUs, supported by both 625 * drivers: radeon (old) and amdgpu (new). This parameter controls whether 626 * amdgpu should support SI. 627 * By default, SI dedicated GPUs are supported by amdgpu. 628 * Only relevant when CONFIG_DRM_AMDGPU_SI is enabled to build SI support in amdgpu. 629 * See also radeon.si_support which should be disabled when amdgpu.si_support is 630 * enabled, and vice versa. 631 */ 632 int amdgpu_si_support = -1; 633 #ifdef CONFIG_DRM_AMDGPU_SI 634 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled, -1 = default)"); 635 module_param_named(si_support, amdgpu_si_support, int, 0444); 636 #endif 637 638 /** 639 * DOC: cik_support (int) 640 * 1 = enabled, 0 = disabled, -1 = default 641 * 642 * CIK (Sea Islands) are second generation GCN GPUs, supported by both 643 * drivers: radeon (old) and amdgpu (new). This parameter controls whether 644 * amdgpu should support CIK. 645 * By default: 646 * - CIK dedicated GPUs are supported by amdgpu. 647 * - CIK APUs are supported by radeon (except when radeon is not built). 648 * Only relevant when CONFIG_DRM_AMDGPU_CIK is enabled to build CIK support in amdgpu. 649 * See also radeon.cik_support which should be disabled when amdgpu.cik_support is 650 * enabled, and vice versa. 651 */ 652 int amdgpu_cik_support = -1; 653 #ifdef CONFIG_DRM_AMDGPU_CIK 654 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled, -1 = default)"); 655 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 656 #endif 657 658 /** 659 * DOC: smu_memory_pool_size (uint) 660 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 661 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 662 */ 663 MODULE_PARM_DESC(smu_memory_pool_size, 664 "reserve gtt for smu debug usage, 0 = disable,0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 665 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 666 667 /** 668 * DOC: async_gfx_ring (int) 669 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 670 */ 671 MODULE_PARM_DESC(async_gfx_ring, 672 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 673 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 674 675 /** 676 * DOC: mcbp (int) 677 * It is used to enable mid command buffer preemption. (0 = disabled, 1 = enabled, -1 auto (default)) 678 */ 679 MODULE_PARM_DESC(mcbp, 680 "Enable Mid-command buffer preemption (0 = disabled, 1 = enabled), -1 = auto (default)"); 681 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 682 683 /** 684 * DOC: discovery (int) 685 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 686 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 687 */ 688 MODULE_PARM_DESC(discovery, 689 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 690 module_param_named(discovery, amdgpu_discovery, int, 0444); 691 692 /** 693 * DOC: mes (int) 694 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 695 * (0 = disabled (default), 1 = enabled) 696 */ 697 MODULE_PARM_DESC(mes, 698 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 699 module_param_named(mes, amdgpu_mes, int, 0444); 700 701 /** 702 * DOC: mes_log_enable (int) 703 * Enable Micro Engine Scheduler log. This is used to enable/disable MES internal log. 704 * (0 = disabled (default), 1 = enabled) 705 */ 706 MODULE_PARM_DESC(mes_log_enable, 707 "Enable Micro Engine Scheduler log (0 = disabled (default), 1 = enabled)"); 708 module_param_named(mes_log_enable, amdgpu_mes_log_enable, int, 0444); 709 710 /** 711 * DOC: mes_kiq (int) 712 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq. 713 * (0 = disabled (default), 1 = enabled) 714 */ 715 MODULE_PARM_DESC(mes_kiq, 716 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)"); 717 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444); 718 719 /** 720 * DOC: uni_mes (int) 721 * Enable Unified Micro Engine Scheduler. This is a new engine pipe for unified scheduler. 722 * (0 = disabled (default), 1 = enabled) 723 */ 724 MODULE_PARM_DESC(uni_mes, 725 "Enable Unified Micro Engine Scheduler (0 = disabled, 1 = enabled(default)"); 726 module_param_named(uni_mes, amdgpu_uni_mes, int, 0444); 727 728 /** 729 * DOC: noretry (int) 730 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 731 * do not support per-process XNACK this also disables retry page faults. 732 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 733 */ 734 MODULE_PARM_DESC(noretry, 735 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 736 module_param_named(noretry, amdgpu_noretry, int, 0644); 737 738 /** 739 * DOC: force_asic_type (int) 740 * A non negative value used to specify the asic type for all supported GPUs. 741 */ 742 MODULE_PARM_DESC(force_asic_type, 743 "A non negative value used to specify the asic type for all supported GPUs"); 744 module_param_named_unsafe(force_asic_type, amdgpu_force_asic_type, int, 0444); 745 746 /** 747 * DOC: use_xgmi_p2p (int) 748 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 749 */ 750 MODULE_PARM_DESC(use_xgmi_p2p, 751 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 752 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 753 754 755 #ifdef CONFIG_HSA_AMD 756 /** 757 * DOC: sched_policy (int) 758 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 759 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 760 * assigns queues to HQDs. 761 */ 762 int sched_policy = KFD_SCHED_POLICY_HWS; 763 module_param_unsafe(sched_policy, int, 0444); 764 MODULE_PARM_DESC(sched_policy, 765 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 766 767 /** 768 * DOC: hws_max_conc_proc (int) 769 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 770 * number of VMIDs assigned to the HWS, which is also the default. 771 */ 772 int hws_max_conc_proc = -1; 773 module_param(hws_max_conc_proc, int, 0444); 774 MODULE_PARM_DESC(hws_max_conc_proc, 775 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 776 777 /** 778 * DOC: cwsr_enable (int) 779 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 780 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 781 * disables it. 782 */ 783 int cwsr_enable = 1; 784 module_param(cwsr_enable, int, 0444); 785 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 786 787 /** 788 * DOC: max_num_of_queues_per_device (int) 789 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 790 * is 4096. 791 */ 792 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 793 module_param(max_num_of_queues_per_device, int, 0444); 794 MODULE_PARM_DESC(max_num_of_queues_per_device, 795 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 796 797 /** 798 * DOC: send_sigterm (int) 799 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 800 * but just print errors on dmesg. Setting 1 enables sending sigterm. 801 */ 802 int send_sigterm; 803 module_param(send_sigterm, int, 0444); 804 MODULE_PARM_DESC(send_sigterm, 805 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 806 807 /** 808 * DOC: halt_if_hws_hang (int) 809 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 810 * Setting 1 enables halt on hang. 811 */ 812 int halt_if_hws_hang; 813 module_param_unsafe(halt_if_hws_hang, int, 0644); 814 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 815 816 /** 817 * DOC: hws_gws_support(bool) 818 * Assume that HWS supports GWS barriers regardless of what firmware version 819 * check says. Default value: false (rely on MEC2 firmware version check). 820 */ 821 bool hws_gws_support; 822 module_param_unsafe(hws_gws_support, bool, 0444); 823 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 824 825 /** 826 * DOC: queue_preemption_timeout_ms (int) 827 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 828 */ 829 int queue_preemption_timeout_ms = 9000; 830 module_param(queue_preemption_timeout_ms, int, 0644); 831 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 832 833 /** 834 * DOC: debug_evictions(bool) 835 * Enable extra debug messages to help determine the cause of evictions 836 */ 837 bool debug_evictions; 838 module_param(debug_evictions, bool, 0644); 839 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 840 841 /** 842 * DOC: no_system_mem_limit(bool) 843 * Disable system memory limit, to support multiple process shared memory 844 */ 845 bool no_system_mem_limit; 846 module_param(no_system_mem_limit, bool, 0644); 847 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 848 849 /** 850 * DOC: no_queue_eviction_on_vm_fault (int) 851 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 852 */ 853 int amdgpu_no_queue_eviction_on_vm_fault; 854 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 855 module_param_named_unsafe(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 856 #endif 857 858 /** 859 * DOC: mtype_local (int) 860 */ 861 int amdgpu_mtype_local; 862 MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (0 = MTYPE_RW (default), 1 = MTYPE_NC, 2 = MTYPE_CC)"); 863 module_param_named_unsafe(mtype_local, amdgpu_mtype_local, int, 0444); 864 865 /** 866 * DOC: pcie_p2p (bool) 867 * Enable PCIe P2P (requires large-BAR). Default value: true (on) 868 */ 869 #ifdef CONFIG_HSA_AMD_P2P 870 bool pcie_p2p = true; 871 module_param(pcie_p2p, bool, 0444); 872 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); 873 #endif 874 875 /** 876 * DOC: dcfeaturemask (uint) 877 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 878 * The default is the current set of stable display features. 879 */ 880 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 881 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 882 883 /** 884 * DOC: dcdebugmask (uint) 885 * Display debug options. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 886 */ 887 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 888 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 889 890 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)"); 891 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444); 892 893 /** 894 * DOC: abmlevel (uint) 895 * Override the default ABM (Adaptive Backlight Management) level used for DC 896 * enabled hardware. Requires DMCU to be supported and loaded. 897 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 898 * default. Values 1-4 control the maximum allowable brightness reduction via 899 * the ABM algorithm, with 1 being the least reduction and 4 being the most 900 * reduction. 901 * 902 * Defaults to -1, or auto. Userspace can only override this level after 903 * boot if it's set to auto. 904 */ 905 int amdgpu_dm_abm_level = -1; 906 MODULE_PARM_DESC(abmlevel, 907 "ABM level (0 = off, 1-4 = backlight reduction level, -1 auto (default))"); 908 module_param_named(abmlevel, amdgpu_dm_abm_level, int, 0444); 909 910 int amdgpu_backlight = -1; 911 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 912 module_param_named(backlight, amdgpu_backlight, bint, 0444); 913 914 /** 915 * DOC: damageclips (int) 916 * Enable or disable damage clips support. If damage clips support is disabled, 917 * we will force full frame updates, irrespective of what user space sends to 918 * us. 919 * 920 * Defaults to -1 (where it is enabled unless a PSR-SU display is detected). 921 */ 922 MODULE_PARM_DESC(damageclips, 923 "Damage clips support (0 = disable, 1 = enable, -1 auto (default))"); 924 module_param_named(damageclips, amdgpu_damage_clips, int, 0444); 925 926 /** 927 * DOC: tmz (int) 928 * Trusted Memory Zone (TMZ) is a method to protect data being written 929 * to or read from memory. 930 * 931 * The default value: 0 (off). TODO: change to auto till it is completed. 932 */ 933 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 934 module_param_named(tmz, amdgpu_tmz, int, 0444); 935 936 /** 937 * DOC: freesync_video (uint) 938 * Enable the optimization to adjust front porch timing to achieve seamless 939 * mode change experience when setting a freesync supported mode for which full 940 * modeset is not needed. 941 * 942 * The Display Core will add a set of modes derived from the base FreeSync 943 * video mode into the corresponding connector's mode list based on commonly 944 * used refresh rates and VRR range of the connected display, when users enable 945 * this feature. From the userspace perspective, they can see a seamless mode 946 * change experience when the change between different refresh rates under the 947 * same resolution. Additionally, userspace applications such as Video playback 948 * can read this modeset list and change the refresh rate based on the video 949 * frame rate. Finally, the userspace can also derive an appropriate mode for a 950 * particular refresh rate based on the FreeSync Mode and add it to the 951 * connector's mode list. 952 * 953 * Note: This is an experimental feature. 954 * 955 * The default value: 0 (off). 956 */ 957 MODULE_PARM_DESC( 958 freesync_video, 959 "Adds additional modes via VRR for refresh changes without a full modeset (0 = off (default), 1 = on)"); 960 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); 961 962 /** 963 * DOC: reset_method (int) 964 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 965 */ 966 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 967 module_param_named_unsafe(reset_method, amdgpu_reset_method, int, 0644); 968 969 /** 970 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 971 * threshold value of faulty pages detected by RAS ECC, which may 972 * result in the GPU entering bad status when the number of total 973 * faulty pages by ECC exceeds the threshold value. 974 */ 975 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = threshold determined by a formula, 0 < threshold < max records, user-defined threshold)"); 976 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 977 978 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 979 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 980 981 /** 982 * DOC: vcnfw_log (int) 983 * Enable vcnfw log output for debugging, the default is disabled. 984 */ 985 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 986 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 987 988 /** 989 * DOC: sg_display (int) 990 * Disable S/G (scatter/gather) display (i.e., display from system memory). 991 * This option is only relevant on APUs. Set this option to 0 to disable 992 * S/G display if you experience flickering or other issues under memory 993 * pressure and report the issue. 994 */ 995 MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)"); 996 module_param_named(sg_display, amdgpu_sg_display, int, 0444); 997 998 /** 999 * DOC: umsch_mm (int) 1000 * Enable Multi Media User Mode Scheduler. This is a HW scheduling engine for VCN and VPE. 1001 * (0 = disabled (default), 1 = enabled) 1002 */ 1003 MODULE_PARM_DESC(umsch_mm, 1004 "Enable Multi Media User Mode Scheduler (0 = disabled (default), 1 = enabled)"); 1005 module_param_named(umsch_mm, amdgpu_umsch_mm, int, 0444); 1006 1007 /** 1008 * DOC: umsch_mm_fwlog (int) 1009 * Enable umschfw log output for debugging, the default is disabled. 1010 */ 1011 MODULE_PARM_DESC(umsch_mm_fwlog, "Enable umschfw log(0 = disable (default value), 1 = enable)"); 1012 module_param_named(umsch_mm_fwlog, amdgpu_umsch_mm_fwlog, int, 0444); 1013 1014 /** 1015 * DOC: smu_pptable_id (int) 1016 * Used to override pptable id. id = 0 use VBIOS pptable. 1017 * id > 0 use the soft pptable with specicfied id. 1018 */ 1019 MODULE_PARM_DESC(smu_pptable_id, 1020 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 1021 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 1022 1023 /** 1024 * DOC: partition_mode (int) 1025 * Used to override the default SPX mode. 1026 */ 1027 MODULE_PARM_DESC( 1028 user_partt_mode, 1029 "specify partition mode to be used (-2 = AMDGPU_AUTO_COMPUTE_PARTITION_MODE(default value) \ 1030 0 = AMDGPU_SPX_PARTITION_MODE, \ 1031 1 = AMDGPU_DPX_PARTITION_MODE, \ 1032 2 = AMDGPU_TPX_PARTITION_MODE, \ 1033 3 = AMDGPU_QPX_PARTITION_MODE, \ 1034 4 = AMDGPU_CPX_PARTITION_MODE)"); 1035 module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint, 0444); 1036 1037 1038 /** 1039 * DOC: enforce_isolation (int) 1040 * enforce process isolation between graphics and compute. 1041 * (-1 = auto, 0 = disable, 1 = enable, 2 = enable legacy mode, 3 = enable without cleaner shader) 1042 */ 1043 module_param_named(enforce_isolation, amdgpu_enforce_isolation, int, 0444); 1044 MODULE_PARM_DESC(enforce_isolation, 1045 "enforce process isolation between graphics and compute. (-1 = auto, 0 = disable, 1 = enable, 2 = enable legacy mode, 3 = enable without cleaner shader)"); 1046 1047 /** 1048 * DOC: modeset (int) 1049 * Override nomodeset (1 = override, -1 = auto). The default is -1 (auto). 1050 */ 1051 MODULE_PARM_DESC(modeset, "Override nomodeset (1 = enable, -1 = auto)"); 1052 module_param_named(modeset, amdgpu_modeset, int, 0444); 1053 1054 /** 1055 * DOC: seamless (int) 1056 * Seamless boot will keep the image on the screen during the boot process. 1057 */ 1058 MODULE_PARM_DESC(seamless, "Seamless boot (-1 = auto (default), 0 = disable, 1 = enable)"); 1059 module_param_named(seamless, amdgpu_seamless, int, 0444); 1060 1061 /** 1062 * DOC: debug_mask (uint) 1063 * Debug options for amdgpu, work as a binary mask with the following options: 1064 * 1065 * - 0x1: Debug VM handling 1066 * - 0x2: Enable simulating large-bar capability on non-large bar system. This 1067 * limits the VRAM size reported to ROCm applications to the visible 1068 * size, usually 256MB. 1069 * - 0x4: Disable GPU soft recovery, always do a full reset 1070 * - 0x8: Use VRAM for firmware loading 1071 * - 0x10: Enable ACA based RAS logging 1072 * - 0x20: Enable experimental resets 1073 * - 0x40: Disable ring resets 1074 * - 0x80: Use VRAM for SMU pool 1075 */ 1076 MODULE_PARM_DESC(debug_mask, "debug options for amdgpu, disabled by default"); 1077 module_param_named_unsafe(debug_mask, amdgpu_debug_mask, uint, 0444); 1078 1079 /** 1080 * DOC: agp (int) 1081 * Enable the AGP aperture. This provides an aperture in the GPU's internal 1082 * address space for direct access to system memory. Note that these accesses 1083 * are non-snooped, so they are only used for access to uncached memory. 1084 */ 1085 MODULE_PARM_DESC(agp, "AGP (-1 = auto (default), 0 = disable, 1 = enable)"); 1086 module_param_named(agp, amdgpu_agp, int, 0444); 1087 1088 /** 1089 * DOC: wbrf (int) 1090 * Enable Wifi RFI interference mitigation feature. 1091 * Due to electrical and mechanical constraints there may be likely interference of 1092 * relatively high-powered harmonics of the (G-)DDR memory clocks with local radio 1093 * module frequency bands used by Wifi 6/6e/7. To mitigate the possible RFI interference, 1094 * with this feature enabled, PMFW will use either “shadowed P-State” or “P-State” based 1095 * on active list of frequencies in-use (to be avoided) as part of initial setting or 1096 * P-state transition. However, there may be potential performance impact with this 1097 * feature enabled. 1098 * (0 = disabled, 1 = enabled, -1 = auto (default setting, will be enabled if supported)) 1099 */ 1100 MODULE_PARM_DESC(wbrf, 1101 "Enable Wifi RFI interference mitigation (0 = disabled, 1 = enabled, -1 = auto(default)"); 1102 module_param_named(wbrf, amdgpu_wbrf, int, 0444); 1103 1104 /** 1105 * DOC: rebar (int) 1106 * Allow BAR resizing. Disable this to prevent the driver from attempting 1107 * to resize the BAR if the GPU supports it and there is available MMIO space. 1108 * Note that this just prevents the driver from resizing the BAR. The BIOS 1109 * may have already resized the BAR at boot time. 1110 */ 1111 MODULE_PARM_DESC(rebar, "Resizable BAR (-1 = auto (default), 0 = disable, 1 = enable)"); 1112 module_param_named(rebar, amdgpu_rebar, int, 0444); 1113 1114 /** 1115 * DOC: user_queue (int) 1116 * Enable user queues on systems that support user queues. Possible values: 1117 * 1118 * - -1 = auto (ASIC specific default) 1119 * - 0 = user queues disabled 1120 * - 1 = user queues enabled and kernel queues enabled (if supported) 1121 * - 2 = user queues enabled and kernel queues disabled 1122 */ 1123 MODULE_PARM_DESC(user_queue, "Enable user queues (-1 = auto (default), 0 = disable, 1 = enable, 2 = enable UQs and disable KQs)"); 1124 module_param_named(user_queue, amdgpu_user_queue, int, 0444); 1125 1126 /* These devices are not supported by amdgpu. 1127 * They are supported by the mach64, r128, radeon drivers 1128 */ 1129 static const u16 amdgpu_unsupported_pciidlist[] = { 1130 /* mach64 */ 1131 0x4354, 1132 0x4358, 1133 0x4554, 1134 0x4742, 1135 0x4744, 1136 0x4749, 1137 0x474C, 1138 0x474D, 1139 0x474E, 1140 0x474F, 1141 0x4750, 1142 0x4751, 1143 0x4752, 1144 0x4753, 1145 0x4754, 1146 0x4755, 1147 0x4756, 1148 0x4757, 1149 0x4758, 1150 0x4759, 1151 0x475A, 1152 0x4C42, 1153 0x4C44, 1154 0x4C47, 1155 0x4C49, 1156 0x4C4D, 1157 0x4C4E, 1158 0x4C50, 1159 0x4C51, 1160 0x4C52, 1161 0x4C53, 1162 0x5654, 1163 0x5655, 1164 0x5656, 1165 /* r128 */ 1166 0x4c45, 1167 0x4c46, 1168 0x4d46, 1169 0x4d4c, 1170 0x5041, 1171 0x5042, 1172 0x5043, 1173 0x5044, 1174 0x5045, 1175 0x5046, 1176 0x5047, 1177 0x5048, 1178 0x5049, 1179 0x504A, 1180 0x504B, 1181 0x504C, 1182 0x504D, 1183 0x504E, 1184 0x504F, 1185 0x5050, 1186 0x5051, 1187 0x5052, 1188 0x5053, 1189 0x5054, 1190 0x5055, 1191 0x5056, 1192 0x5057, 1193 0x5058, 1194 0x5245, 1195 0x5246, 1196 0x5247, 1197 0x524b, 1198 0x524c, 1199 0x534d, 1200 0x5446, 1201 0x544C, 1202 0x5452, 1203 /* radeon */ 1204 0x3150, 1205 0x3151, 1206 0x3152, 1207 0x3154, 1208 0x3155, 1209 0x3E50, 1210 0x3E54, 1211 0x4136, 1212 0x4137, 1213 0x4144, 1214 0x4145, 1215 0x4146, 1216 0x4147, 1217 0x4148, 1218 0x4149, 1219 0x414A, 1220 0x414B, 1221 0x4150, 1222 0x4151, 1223 0x4152, 1224 0x4153, 1225 0x4154, 1226 0x4155, 1227 0x4156, 1228 0x4237, 1229 0x4242, 1230 0x4336, 1231 0x4337, 1232 0x4437, 1233 0x4966, 1234 0x4967, 1235 0x4A48, 1236 0x4A49, 1237 0x4A4A, 1238 0x4A4B, 1239 0x4A4C, 1240 0x4A4D, 1241 0x4A4E, 1242 0x4A4F, 1243 0x4A50, 1244 0x4A54, 1245 0x4B48, 1246 0x4B49, 1247 0x4B4A, 1248 0x4B4B, 1249 0x4B4C, 1250 0x4C57, 1251 0x4C58, 1252 0x4C59, 1253 0x4C5A, 1254 0x4C64, 1255 0x4C66, 1256 0x4C67, 1257 0x4E44, 1258 0x4E45, 1259 0x4E46, 1260 0x4E47, 1261 0x4E48, 1262 0x4E49, 1263 0x4E4A, 1264 0x4E4B, 1265 0x4E50, 1266 0x4E51, 1267 0x4E52, 1268 0x4E53, 1269 0x4E54, 1270 0x4E56, 1271 0x5144, 1272 0x5145, 1273 0x5146, 1274 0x5147, 1275 0x5148, 1276 0x514C, 1277 0x514D, 1278 0x5157, 1279 0x5158, 1280 0x5159, 1281 0x515A, 1282 0x515E, 1283 0x5460, 1284 0x5462, 1285 0x5464, 1286 0x5548, 1287 0x5549, 1288 0x554A, 1289 0x554B, 1290 0x554C, 1291 0x554D, 1292 0x554E, 1293 0x554F, 1294 0x5550, 1295 0x5551, 1296 0x5552, 1297 0x5554, 1298 0x564A, 1299 0x564B, 1300 0x564F, 1301 0x5652, 1302 0x5653, 1303 0x5657, 1304 0x5834, 1305 0x5835, 1306 0x5954, 1307 0x5955, 1308 0x5974, 1309 0x5975, 1310 0x5960, 1311 0x5961, 1312 0x5962, 1313 0x5964, 1314 0x5965, 1315 0x5969, 1316 0x5a41, 1317 0x5a42, 1318 0x5a61, 1319 0x5a62, 1320 0x5b60, 1321 0x5b62, 1322 0x5b63, 1323 0x5b64, 1324 0x5b65, 1325 0x5c61, 1326 0x5c63, 1327 0x5d48, 1328 0x5d49, 1329 0x5d4a, 1330 0x5d4c, 1331 0x5d4d, 1332 0x5d4e, 1333 0x5d4f, 1334 0x5d50, 1335 0x5d52, 1336 0x5d57, 1337 0x5e48, 1338 0x5e4a, 1339 0x5e4b, 1340 0x5e4c, 1341 0x5e4d, 1342 0x5e4f, 1343 0x6700, 1344 0x6701, 1345 0x6702, 1346 0x6703, 1347 0x6704, 1348 0x6705, 1349 0x6706, 1350 0x6707, 1351 0x6708, 1352 0x6709, 1353 0x6718, 1354 0x6719, 1355 0x671c, 1356 0x671d, 1357 0x671f, 1358 0x6720, 1359 0x6721, 1360 0x6722, 1361 0x6723, 1362 0x6724, 1363 0x6725, 1364 0x6726, 1365 0x6727, 1366 0x6728, 1367 0x6729, 1368 0x6738, 1369 0x6739, 1370 0x673e, 1371 0x6740, 1372 0x6741, 1373 0x6742, 1374 0x6743, 1375 0x6744, 1376 0x6745, 1377 0x6746, 1378 0x6747, 1379 0x6748, 1380 0x6749, 1381 0x674A, 1382 0x6750, 1383 0x6751, 1384 0x6758, 1385 0x6759, 1386 0x675B, 1387 0x675D, 1388 0x675F, 1389 0x6760, 1390 0x6761, 1391 0x6762, 1392 0x6763, 1393 0x6764, 1394 0x6765, 1395 0x6766, 1396 0x6767, 1397 0x6768, 1398 0x6770, 1399 0x6771, 1400 0x6772, 1401 0x6778, 1402 0x6779, 1403 0x677B, 1404 0x6840, 1405 0x6841, 1406 0x6842, 1407 0x6843, 1408 0x6849, 1409 0x684C, 1410 0x6850, 1411 0x6858, 1412 0x6859, 1413 0x6880, 1414 0x6888, 1415 0x6889, 1416 0x688A, 1417 0x688C, 1418 0x688D, 1419 0x6898, 1420 0x6899, 1421 0x689b, 1422 0x689c, 1423 0x689d, 1424 0x689e, 1425 0x68a0, 1426 0x68a1, 1427 0x68a8, 1428 0x68a9, 1429 0x68b0, 1430 0x68b8, 1431 0x68b9, 1432 0x68ba, 1433 0x68be, 1434 0x68bf, 1435 0x68c0, 1436 0x68c1, 1437 0x68c7, 1438 0x68c8, 1439 0x68c9, 1440 0x68d8, 1441 0x68d9, 1442 0x68da, 1443 0x68de, 1444 0x68e0, 1445 0x68e1, 1446 0x68e4, 1447 0x68e5, 1448 0x68e8, 1449 0x68e9, 1450 0x68f1, 1451 0x68f2, 1452 0x68f8, 1453 0x68f9, 1454 0x68fa, 1455 0x68fe, 1456 0x7100, 1457 0x7101, 1458 0x7102, 1459 0x7103, 1460 0x7104, 1461 0x7105, 1462 0x7106, 1463 0x7108, 1464 0x7109, 1465 0x710A, 1466 0x710B, 1467 0x710C, 1468 0x710E, 1469 0x710F, 1470 0x7140, 1471 0x7141, 1472 0x7142, 1473 0x7143, 1474 0x7144, 1475 0x7145, 1476 0x7146, 1477 0x7147, 1478 0x7149, 1479 0x714A, 1480 0x714B, 1481 0x714C, 1482 0x714D, 1483 0x714E, 1484 0x714F, 1485 0x7151, 1486 0x7152, 1487 0x7153, 1488 0x715E, 1489 0x715F, 1490 0x7180, 1491 0x7181, 1492 0x7183, 1493 0x7186, 1494 0x7187, 1495 0x7188, 1496 0x718A, 1497 0x718B, 1498 0x718C, 1499 0x718D, 1500 0x718F, 1501 0x7193, 1502 0x7196, 1503 0x719B, 1504 0x719F, 1505 0x71C0, 1506 0x71C1, 1507 0x71C2, 1508 0x71C3, 1509 0x71C4, 1510 0x71C5, 1511 0x71C6, 1512 0x71C7, 1513 0x71CD, 1514 0x71CE, 1515 0x71D2, 1516 0x71D4, 1517 0x71D5, 1518 0x71D6, 1519 0x71DA, 1520 0x71DE, 1521 0x7200, 1522 0x7210, 1523 0x7211, 1524 0x7240, 1525 0x7243, 1526 0x7244, 1527 0x7245, 1528 0x7246, 1529 0x7247, 1530 0x7248, 1531 0x7249, 1532 0x724A, 1533 0x724B, 1534 0x724C, 1535 0x724D, 1536 0x724E, 1537 0x724F, 1538 0x7280, 1539 0x7281, 1540 0x7283, 1541 0x7284, 1542 0x7287, 1543 0x7288, 1544 0x7289, 1545 0x728B, 1546 0x728C, 1547 0x7290, 1548 0x7291, 1549 0x7293, 1550 0x7297, 1551 0x7834, 1552 0x7835, 1553 0x791e, 1554 0x791f, 1555 0x793f, 1556 0x7941, 1557 0x7942, 1558 0x796c, 1559 0x796d, 1560 0x796e, 1561 0x796f, 1562 0x9400, 1563 0x9401, 1564 0x9402, 1565 0x9403, 1566 0x9405, 1567 0x940A, 1568 0x940B, 1569 0x940F, 1570 0x94A0, 1571 0x94A1, 1572 0x94A3, 1573 0x94B1, 1574 0x94B3, 1575 0x94B4, 1576 0x94B5, 1577 0x94B9, 1578 0x9440, 1579 0x9441, 1580 0x9442, 1581 0x9443, 1582 0x9444, 1583 0x9446, 1584 0x944A, 1585 0x944B, 1586 0x944C, 1587 0x944E, 1588 0x9450, 1589 0x9452, 1590 0x9456, 1591 0x945A, 1592 0x945B, 1593 0x945E, 1594 0x9460, 1595 0x9462, 1596 0x946A, 1597 0x946B, 1598 0x947A, 1599 0x947B, 1600 0x9480, 1601 0x9487, 1602 0x9488, 1603 0x9489, 1604 0x948A, 1605 0x948F, 1606 0x9490, 1607 0x9491, 1608 0x9495, 1609 0x9498, 1610 0x949C, 1611 0x949E, 1612 0x949F, 1613 0x94C0, 1614 0x94C1, 1615 0x94C3, 1616 0x94C4, 1617 0x94C5, 1618 0x94C6, 1619 0x94C7, 1620 0x94C8, 1621 0x94C9, 1622 0x94CB, 1623 0x94CC, 1624 0x94CD, 1625 0x9500, 1626 0x9501, 1627 0x9504, 1628 0x9505, 1629 0x9506, 1630 0x9507, 1631 0x9508, 1632 0x9509, 1633 0x950F, 1634 0x9511, 1635 0x9515, 1636 0x9517, 1637 0x9519, 1638 0x9540, 1639 0x9541, 1640 0x9542, 1641 0x954E, 1642 0x954F, 1643 0x9552, 1644 0x9553, 1645 0x9555, 1646 0x9557, 1647 0x955f, 1648 0x9580, 1649 0x9581, 1650 0x9583, 1651 0x9586, 1652 0x9587, 1653 0x9588, 1654 0x9589, 1655 0x958A, 1656 0x958B, 1657 0x958C, 1658 0x958D, 1659 0x958E, 1660 0x958F, 1661 0x9590, 1662 0x9591, 1663 0x9593, 1664 0x9595, 1665 0x9596, 1666 0x9597, 1667 0x9598, 1668 0x9599, 1669 0x959B, 1670 0x95C0, 1671 0x95C2, 1672 0x95C4, 1673 0x95C5, 1674 0x95C6, 1675 0x95C7, 1676 0x95C9, 1677 0x95CC, 1678 0x95CD, 1679 0x95CE, 1680 0x95CF, 1681 0x9610, 1682 0x9611, 1683 0x9612, 1684 0x9613, 1685 0x9614, 1686 0x9615, 1687 0x9616, 1688 0x9640, 1689 0x9641, 1690 0x9642, 1691 0x9643, 1692 0x9644, 1693 0x9645, 1694 0x9647, 1695 0x9648, 1696 0x9649, 1697 0x964a, 1698 0x964b, 1699 0x964c, 1700 0x964e, 1701 0x964f, 1702 0x9710, 1703 0x9711, 1704 0x9712, 1705 0x9713, 1706 0x9714, 1707 0x9715, 1708 0x9802, 1709 0x9803, 1710 0x9804, 1711 0x9805, 1712 0x9806, 1713 0x9807, 1714 0x9808, 1715 0x9809, 1716 0x980A, 1717 0x9900, 1718 0x9901, 1719 0x9903, 1720 0x9904, 1721 0x9905, 1722 0x9906, 1723 0x9907, 1724 0x9908, 1725 0x9909, 1726 0x990A, 1727 0x990B, 1728 0x990C, 1729 0x990D, 1730 0x990E, 1731 0x990F, 1732 0x9910, 1733 0x9913, 1734 0x9917, 1735 0x9918, 1736 0x9919, 1737 0x9990, 1738 0x9991, 1739 0x9992, 1740 0x9993, 1741 0x9994, 1742 0x9995, 1743 0x9996, 1744 0x9997, 1745 0x9998, 1746 0x9999, 1747 0x999A, 1748 0x999B, 1749 0x999C, 1750 0x999D, 1751 0x99A0, 1752 0x99A2, 1753 0x99A4, 1754 /* radeon secondary ids */ 1755 0x3171, 1756 0x3e70, 1757 0x4164, 1758 0x4165, 1759 0x4166, 1760 0x4168, 1761 0x4170, 1762 0x4171, 1763 0x4172, 1764 0x4173, 1765 0x496e, 1766 0x4a69, 1767 0x4a6a, 1768 0x4a6b, 1769 0x4a70, 1770 0x4a74, 1771 0x4b69, 1772 0x4b6b, 1773 0x4b6c, 1774 0x4c6e, 1775 0x4e64, 1776 0x4e65, 1777 0x4e66, 1778 0x4e67, 1779 0x4e68, 1780 0x4e69, 1781 0x4e6a, 1782 0x4e71, 1783 0x4f73, 1784 0x5569, 1785 0x556b, 1786 0x556d, 1787 0x556f, 1788 0x5571, 1789 0x5854, 1790 0x5874, 1791 0x5940, 1792 0x5941, 1793 0x5b70, 1794 0x5b72, 1795 0x5b73, 1796 0x5b74, 1797 0x5b75, 1798 0x5d44, 1799 0x5d45, 1800 0x5d6d, 1801 0x5d6f, 1802 0x5d72, 1803 0x5d77, 1804 0x5e6b, 1805 0x5e6d, 1806 0x7120, 1807 0x7124, 1808 0x7129, 1809 0x712e, 1810 0x712f, 1811 0x7162, 1812 0x7163, 1813 0x7166, 1814 0x7167, 1815 0x7172, 1816 0x7173, 1817 0x71a0, 1818 0x71a1, 1819 0x71a3, 1820 0x71a7, 1821 0x71bb, 1822 0x71e0, 1823 0x71e1, 1824 0x71e2, 1825 0x71e6, 1826 0x71e7, 1827 0x71f2, 1828 0x7269, 1829 0x726b, 1830 0x726e, 1831 0x72a0, 1832 0x72a8, 1833 0x72b1, 1834 0x72b3, 1835 0x793f, 1836 }; 1837 1838 static const struct pci_device_id pciidlist[] = { 1839 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1840 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1841 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1842 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1843 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1844 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1845 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1846 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1847 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1848 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1849 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1850 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1851 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1852 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1853 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1854 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1855 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1856 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1857 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1858 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1859 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1860 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1861 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1862 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1863 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1864 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1865 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1866 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1867 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1868 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1869 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1870 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1871 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1872 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1873 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1874 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1875 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1876 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1877 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1878 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1879 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1880 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1881 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1882 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1883 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1884 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1885 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1886 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1887 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1888 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1889 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1890 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1891 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1892 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1893 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1894 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1895 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1896 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1897 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1898 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1899 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1900 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1901 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1902 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1903 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1904 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1905 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1906 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1907 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1908 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1909 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1910 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1911 /* Kaveri */ 1912 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1913 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1914 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1915 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1916 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1917 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1918 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1919 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1920 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1921 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1922 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1923 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1924 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1925 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1926 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1927 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1928 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1929 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1930 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1931 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1932 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1933 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1934 /* Bonaire */ 1935 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1936 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1937 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1938 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1939 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1940 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1941 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1942 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1943 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1944 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1945 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1946 /* Hawaii */ 1947 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1948 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1949 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1950 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1951 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1952 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1953 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1954 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1955 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1956 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1957 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1958 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1959 /* Kabini */ 1960 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1961 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1962 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1963 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1964 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1965 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1966 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1967 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1968 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1969 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1970 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1971 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1972 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1973 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1974 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1975 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1976 /* mullins */ 1977 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1978 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1979 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1980 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1981 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1982 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1983 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1984 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1985 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1986 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1987 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1988 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1989 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1990 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1991 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1992 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1993 /* topaz */ 1994 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1995 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1996 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1997 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1998 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1999 /* tonga */ 2000 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2001 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2002 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2003 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2004 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2005 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2006 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2007 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2008 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2009 /* fiji */ 2010 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 2011 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 2012 /* carrizo */ 2013 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 2014 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 2015 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 2016 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 2017 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 2018 /* stoney */ 2019 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 2020 /* Polaris11 */ 2021 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2022 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2023 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2024 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2025 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2026 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2027 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2028 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2029 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2030 /* Polaris10 */ 2031 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2032 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2033 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2034 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2035 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2036 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2037 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2038 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2039 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2040 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2041 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2042 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2043 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2044 /* Polaris12 */ 2045 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2046 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2047 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2048 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2049 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2050 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2051 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2052 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2053 /* VEGAM */ 2054 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 2055 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 2056 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 2057 /* Vega 10 */ 2058 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2059 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2060 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2061 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2062 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2063 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2064 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2065 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2066 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2067 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2068 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2069 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2070 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2071 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2072 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2073 /* Vega 12 */ 2074 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2075 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2076 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2077 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2078 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2079 /* Vega 20 */ 2080 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2081 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2082 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2083 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2084 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2085 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2086 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2087 /* Raven */ 2088 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 2089 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 2090 /* Arcturus */ 2091 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2092 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2093 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2094 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2095 /* Navi10 */ 2096 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2097 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2098 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2099 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2100 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2101 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2102 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2103 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2104 /* Navi14 */ 2105 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2106 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2107 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2108 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2109 2110 /* Renoir */ 2111 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2112 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2113 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2114 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2115 2116 /* Navi12 */ 2117 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 2118 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 2119 2120 /* Sienna_Cichlid */ 2121 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2122 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2123 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2124 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2125 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2126 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2127 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2128 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2129 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2130 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2131 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2132 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2133 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2134 2135 /* Yellow Carp */ 2136 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 2137 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 2138 2139 /* Navy_Flounder */ 2140 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2141 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2142 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2143 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2144 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2145 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2146 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2147 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2148 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2149 2150 /* DIMGREY_CAVEFISH */ 2151 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2152 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2153 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2154 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2155 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2156 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2157 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2158 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2159 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2160 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2161 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2162 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2163 2164 /* Aldebaran */ 2165 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2166 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2167 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2168 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2169 2170 /* CYAN_SKILLFISH */ 2171 {0x1002, 0x13DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2172 {0x1002, 0x13F9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2173 {0x1002, 0x13FA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2174 {0x1002, 0x13FB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2175 {0x1002, 0x13FC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2176 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2177 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2178 2179 /* BEIGE_GOBY */ 2180 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2181 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2182 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2183 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2184 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2185 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2186 2187 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2188 .class = PCI_CLASS_DISPLAY_VGA << 8, 2189 .class_mask = 0xffffff, 2190 .driver_data = CHIP_IP_DISCOVERY }, 2191 2192 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2193 .class = PCI_CLASS_DISPLAY_OTHER << 8, 2194 .class_mask = 0xffffff, 2195 .driver_data = CHIP_IP_DISCOVERY }, 2196 2197 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2198 .class = PCI_CLASS_ACCELERATOR_PROCESSING << 8, 2199 .class_mask = 0xffffff, 2200 .driver_data = CHIP_IP_DISCOVERY }, 2201 2202 {0, 0, 0} 2203 }; 2204 2205 MODULE_DEVICE_TABLE(pci, pciidlist); 2206 2207 static const struct amdgpu_asic_type_quirk asic_type_quirks[] = { 2208 /* differentiate between P10 and P11 asics with the same DID */ 2209 {0x67FF, 0xE3, CHIP_POLARIS10}, 2210 {0x67FF, 0xE7, CHIP_POLARIS10}, 2211 {0x67FF, 0xF3, CHIP_POLARIS10}, 2212 {0x67FF, 0xF7, CHIP_POLARIS10}, 2213 }; 2214 2215 static const struct drm_driver amdgpu_kms_driver; 2216 2217 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 2218 { 2219 struct pci_dev *p = NULL; 2220 int i; 2221 2222 /* 0 - GPU 2223 * 1 - audio 2224 * 2 - USB 2225 * 3 - UCSI 2226 */ 2227 for (i = 1; i < 4; i++) { 2228 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 2229 adev->pdev->bus->number, i); 2230 if (p) { 2231 pm_runtime_get_sync(&p->dev); 2232 pm_runtime_put_autosuspend(&p->dev); 2233 pci_dev_put(p); 2234 } 2235 } 2236 } 2237 2238 static void amdgpu_init_debug_options(struct amdgpu_device *adev) 2239 { 2240 if (amdgpu_debug_mask & AMDGPU_DEBUG_VM) { 2241 pr_info("debug: VM handling debug enabled\n"); 2242 adev->debug_vm = true; 2243 } 2244 2245 if (amdgpu_debug_mask & AMDGPU_DEBUG_LARGEBAR) { 2246 pr_info("debug: enabled simulating large-bar capability on non-large bar system\n"); 2247 adev->debug_largebar = true; 2248 } 2249 2250 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY) { 2251 pr_info("debug: soft reset for GPU recovery disabled\n"); 2252 adev->debug_disable_soft_recovery = true; 2253 } 2254 2255 if (amdgpu_debug_mask & AMDGPU_DEBUG_USE_VRAM_FW_BUF) { 2256 pr_info("debug: place fw in vram for frontdoor loading\n"); 2257 adev->debug_use_vram_fw_buf = true; 2258 } 2259 2260 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_RAS_ACA) { 2261 pr_info("debug: enable RAS ACA\n"); 2262 adev->debug_enable_ras_aca = true; 2263 } 2264 2265 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_EXP_RESETS) { 2266 pr_info("debug: enable experimental reset features\n"); 2267 adev->debug_exp_resets = true; 2268 } 2269 2270 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_RING_RESET) { 2271 pr_info("debug: ring reset disabled\n"); 2272 adev->debug_disable_gpu_ring_reset = true; 2273 } 2274 if (amdgpu_debug_mask & AMDGPU_DEBUG_SMU_POOL) { 2275 pr_info("debug: use vram for smu pool\n"); 2276 adev->pm.smu_debug_mask |= SMU_DEBUG_POOL_USE_VRAM; 2277 } 2278 if (amdgpu_debug_mask & AMDGPU_DEBUG_VM_USERPTR) { 2279 pr_info("debug: VM mode debug for userptr is enabled\n"); 2280 adev->debug_vm_userptr = true; 2281 } 2282 2283 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_RAS_CE_LOG) { 2284 pr_info("debug: disable kernel logs of correctable errors\n"); 2285 adev->debug_disable_ce_logs = true; 2286 } 2287 2288 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_CE_CS) { 2289 pr_info("debug: allowing command submission to CE engine\n"); 2290 adev->debug_enable_ce_cs = true; 2291 } 2292 } 2293 2294 static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long flags) 2295 { 2296 int i; 2297 2298 for (i = 0; i < ARRAY_SIZE(asic_type_quirks); i++) { 2299 if (pdev->device == asic_type_quirks[i].device && 2300 pdev->revision == asic_type_quirks[i].revision) { 2301 flags &= ~AMD_ASIC_MASK; 2302 flags |= asic_type_quirks[i].type; 2303 break; 2304 } 2305 } 2306 2307 return flags; 2308 } 2309 2310 static bool amdgpu_support_enabled(struct device *dev, 2311 const enum amd_asic_type family) 2312 { 2313 const char *gen; 2314 const char *param; 2315 int module_param = -1; 2316 bool radeon_support_built = IS_ENABLED(CONFIG_DRM_RADEON); 2317 bool amdgpu_support_built = false; 2318 bool support_by_default = false; 2319 2320 switch (family) { 2321 case CHIP_TAHITI: 2322 case CHIP_PITCAIRN: 2323 case CHIP_VERDE: 2324 case CHIP_OLAND: 2325 case CHIP_HAINAN: 2326 gen = "SI"; 2327 param = "si_support"; 2328 module_param = amdgpu_si_support; 2329 amdgpu_support_built = IS_ENABLED(CONFIG_DRM_AMDGPU_SI); 2330 support_by_default = true; 2331 break; 2332 2333 case CHIP_BONAIRE: 2334 case CHIP_HAWAII: 2335 support_by_default = true; 2336 fallthrough; 2337 case CHIP_KAVERI: 2338 case CHIP_KABINI: 2339 case CHIP_MULLINS: 2340 gen = "CIK"; 2341 param = "cik_support"; 2342 module_param = amdgpu_cik_support; 2343 amdgpu_support_built = IS_ENABLED(CONFIG_DRM_AMDGPU_CIK); 2344 break; 2345 2346 default: 2347 /* All other chips are supported by amdgpu only */ 2348 return true; 2349 } 2350 2351 if (!amdgpu_support_built) { 2352 dev_info(dev, "amdgpu built without %s support\n", gen); 2353 return false; 2354 } 2355 2356 if ((module_param == -1 && (support_by_default || !radeon_support_built)) || 2357 module_param == 1) { 2358 if (radeon_support_built) 2359 dev_info(dev, "%s support provided by amdgpu.\n" 2360 "Use radeon.%s=1 amdgpu.%s=0 to override.\n", 2361 gen, param, param); 2362 2363 return true; 2364 } 2365 2366 if (radeon_support_built) 2367 dev_info(dev, "%s support provided by radeon.\n" 2368 "Use radeon.%s=0 amdgpu.%s=1 to override.\n", 2369 gen, param, param); 2370 else if (module_param == 0) 2371 dev_info(dev, "%s support disabled by module param\n", gen); 2372 2373 return false; 2374 } 2375 2376 static int amdgpu_pci_probe(struct pci_dev *pdev, 2377 const struct pci_device_id *ent) 2378 { 2379 struct drm_device *ddev; 2380 struct amdgpu_device *adev; 2381 unsigned long flags = ent->driver_data; 2382 int ret, retry = 0, i; 2383 bool supports_atomic = false; 2384 2385 if ((pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA || 2386 (pdev->class >> 8) == PCI_CLASS_DISPLAY_OTHER) { 2387 if (drm_firmware_drivers_only() && amdgpu_modeset == -1) 2388 return -EINVAL; 2389 } 2390 2391 /* skip devices which are owned by radeon */ 2392 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2393 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2394 return -ENODEV; 2395 } 2396 2397 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) 2398 amdgpu_aspm = 0; 2399 2400 if (amdgpu_virtual_display || 2401 amdgpu_device_asic_has_dc_support(pdev, flags & AMD_ASIC_MASK)) 2402 supports_atomic = true; 2403 2404 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2405 DRM_INFO("This hardware requires experimental hardware support.\n" 2406 "See modparam exp_hw_support\n"); 2407 return -ENODEV; 2408 } 2409 2410 flags = amdgpu_fix_asic_type(pdev, flags); 2411 2412 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2413 * however, SME requires an indirect IOMMU mapping because the encryption 2414 * bit is beyond the DMA mask of the chip. 2415 */ 2416 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2417 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2418 dev_info(&pdev->dev, 2419 "SME is not compatible with RAVEN\n"); 2420 return -ENOTSUPP; 2421 } 2422 2423 if (!amdgpu_support_enabled(&pdev->dev, flags & AMD_ASIC_MASK)) 2424 return -ENODEV; 2425 2426 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2427 if (IS_ERR(adev)) 2428 return PTR_ERR(adev); 2429 2430 adev->dev = &pdev->dev; 2431 adev->pdev = pdev; 2432 ddev = adev_to_drm(adev); 2433 2434 if (!supports_atomic) 2435 ddev->driver_features &= ~DRIVER_ATOMIC; 2436 2437 ret = pci_enable_device(pdev); 2438 if (ret) 2439 return ret; 2440 2441 pci_set_drvdata(pdev, ddev); 2442 2443 amdgpu_init_debug_options(adev); 2444 2445 ret = amdgpu_driver_load_kms(adev, flags); 2446 if (ret) 2447 goto err_pci; 2448 2449 retry_init: 2450 ret = drm_dev_register(ddev, flags); 2451 if (ret == -EAGAIN && ++retry <= 3) { 2452 DRM_INFO("retry init %d\n", retry); 2453 /* Don't request EX mode too frequently which is attacking */ 2454 msleep(5000); 2455 goto retry_init; 2456 } else if (ret) { 2457 goto err_pci; 2458 } 2459 2460 ret = amdgpu_xcp_dev_register(adev, ent); 2461 if (ret) 2462 goto err_pci; 2463 2464 ret = amdgpu_amdkfd_drm_client_create(adev); 2465 if (ret) 2466 goto err_pci; 2467 2468 /* 2469 * 1. don't init fbdev on hw without DCE 2470 * 2. don't init fbdev if there are no connectors 2471 */ 2472 if (adev->mode_info.mode_config_initialized && 2473 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2474 const struct drm_format_info *format; 2475 2476 /* select 8 bpp console on low vram cards */ 2477 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2478 format = drm_format_info(DRM_FORMAT_C8); 2479 else 2480 format = NULL; 2481 2482 drm_client_setup(adev_to_drm(adev), format); 2483 } 2484 2485 ret = amdgpu_debugfs_init(adev); 2486 if (ret) 2487 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2488 2489 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2490 /* only need to skip on ATPX */ 2491 if (amdgpu_device_supports_px(adev)) 2492 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2493 /* we want direct complete for BOCO */ 2494 if (amdgpu_device_supports_boco(adev)) 2495 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2496 DPM_FLAG_SMART_SUSPEND | 2497 DPM_FLAG_MAY_SKIP_RESUME); 2498 pm_runtime_use_autosuspend(ddev->dev); 2499 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2500 2501 pm_runtime_allow(ddev->dev); 2502 2503 pm_runtime_put_autosuspend(ddev->dev); 2504 2505 pci_wake_from_d3(pdev, TRUE); 2506 2507 /* 2508 * For runpm implemented via BACO, PMFW will handle the 2509 * timing for BACO in and out: 2510 * - put ASIC into BACO state only when both video and 2511 * audio functions are in D3 state. 2512 * - pull ASIC out of BACO state when either video or 2513 * audio function is in D0 state. 2514 * Also, at startup, PMFW assumes both functions are in 2515 * D0 state. 2516 * 2517 * So if snd driver was loaded prior to amdgpu driver 2518 * and audio function was put into D3 state, there will 2519 * be no PMFW-aware D-state transition(D0->D3) on runpm 2520 * suspend. Thus the BACO will be not correctly kicked in. 2521 * 2522 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2523 * into D0 state. Then there will be a PMFW-aware D-state 2524 * transition(D0->D3) on runpm suspend. 2525 */ 2526 if (amdgpu_device_supports_baco(adev) && 2527 !(adev->flags & AMD_IS_APU) && 2528 adev->asic_type >= CHIP_NAVI10) 2529 amdgpu_get_secondary_funcs(adev); 2530 } 2531 2532 return 0; 2533 2534 err_pci: 2535 pci_disable_device(pdev); 2536 return ret; 2537 } 2538 2539 static void 2540 amdgpu_pci_remove(struct pci_dev *pdev) 2541 { 2542 struct drm_device *dev = pci_get_drvdata(pdev); 2543 struct amdgpu_device *adev = drm_to_adev(dev); 2544 2545 amdgpu_ras_eeprom_check_and_recover(adev); 2546 amdgpu_xcp_dev_unplug(adev); 2547 amdgpu_gmc_prepare_nps_mode_change(adev); 2548 drm_dev_unplug(dev); 2549 2550 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2551 pm_runtime_get_sync(dev->dev); 2552 pm_runtime_forbid(dev->dev); 2553 } 2554 2555 amdgpu_driver_unload_kms(dev); 2556 2557 /* 2558 * Flush any in flight DMA operations from device. 2559 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2560 * StatusTransactions Pending bit. 2561 */ 2562 pci_disable_device(pdev); 2563 pci_wait_for_pending_transaction(pdev); 2564 } 2565 2566 static void 2567 amdgpu_pci_shutdown(struct pci_dev *pdev) 2568 { 2569 struct drm_device *dev = pci_get_drvdata(pdev); 2570 struct amdgpu_device *adev = drm_to_adev(dev); 2571 2572 if (amdgpu_ras_intr_triggered()) 2573 return; 2574 2575 /* device maybe not resumed here, return immediately in this case */ 2576 if (adev->in_s4 && adev->in_suspend) 2577 return; 2578 2579 /* if we are running in a VM, make sure the device 2580 * torn down properly on reboot/shutdown. 2581 * unfortunately we can't detect certain 2582 * hypervisors so just do this all the time. 2583 */ 2584 if (!amdgpu_passthrough(adev)) 2585 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2586 amdgpu_device_prepare(dev); 2587 amdgpu_device_suspend(dev, true); 2588 adev->mp1_state = PP_MP1_STATE_NONE; 2589 } 2590 2591 static int amdgpu_pmops_prepare(struct device *dev) 2592 { 2593 struct drm_device *drm_dev = dev_get_drvdata(dev); 2594 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2595 2596 /* device maybe not resumed here, return immediately in this case */ 2597 if (adev->in_s4 && adev->in_suspend) 2598 return 0; 2599 2600 /* Return a positive number here so 2601 * DPM_FLAG_SMART_SUSPEND works properly 2602 */ 2603 if (amdgpu_device_supports_boco(adev) && pm_runtime_suspended(dev)) 2604 return 1; 2605 2606 /* if we will not support s3 or s2i for the device 2607 * then skip suspend 2608 */ 2609 if (!amdgpu_acpi_is_s0ix_active(adev) && 2610 !amdgpu_acpi_is_s3_active(adev)) 2611 return 1; 2612 2613 return amdgpu_device_prepare(drm_dev); 2614 } 2615 2616 static void amdgpu_pmops_complete(struct device *dev) 2617 { 2618 amdgpu_device_complete(dev_get_drvdata(dev)); 2619 } 2620 2621 static int amdgpu_pmops_suspend(struct device *dev) 2622 { 2623 struct drm_device *drm_dev = dev_get_drvdata(dev); 2624 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2625 2626 if (amdgpu_acpi_is_s0ix_active(adev)) 2627 adev->in_s0ix = true; 2628 else if (amdgpu_acpi_is_s3_active(adev)) 2629 adev->in_s3 = true; 2630 if (!adev->in_s0ix && !adev->in_s3) { 2631 #if IS_ENABLED(CONFIG_SUSPEND) 2632 /* don't allow going deep first time followed by s2idle the next time */ 2633 if (adev->last_suspend_state != PM_SUSPEND_ON && 2634 adev->last_suspend_state != pm_suspend_target_state) { 2635 drm_err_once(drm_dev, "Unsupported suspend state %d\n", 2636 pm_suspend_target_state); 2637 return -EINVAL; 2638 } 2639 #endif 2640 return 0; 2641 } 2642 2643 #if IS_ENABLED(CONFIG_SUSPEND) 2644 /* cache the state last used for suspend */ 2645 adev->last_suspend_state = pm_suspend_target_state; 2646 #endif 2647 2648 return amdgpu_device_suspend(drm_dev, true); 2649 } 2650 2651 static int amdgpu_pmops_suspend_noirq(struct device *dev) 2652 { 2653 struct drm_device *drm_dev = dev_get_drvdata(dev); 2654 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2655 int r; 2656 2657 if (amdgpu_acpi_should_gpu_reset(adev)) { 2658 amdgpu_device_lock_reset_domain(adev->reset_domain); 2659 r = amdgpu_asic_reset(adev); 2660 amdgpu_device_unlock_reset_domain(adev->reset_domain); 2661 return r; 2662 } 2663 2664 return 0; 2665 } 2666 2667 static int amdgpu_pmops_resume(struct device *dev) 2668 { 2669 struct drm_device *drm_dev = dev_get_drvdata(dev); 2670 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2671 int r; 2672 2673 if (!adev->in_s0ix && !adev->in_s3) 2674 return 0; 2675 2676 /* Avoids registers access if device is physically gone */ 2677 if (!pci_device_is_present(adev->pdev)) 2678 adev->no_hw_access = true; 2679 2680 r = amdgpu_device_resume(drm_dev, true); 2681 if (amdgpu_acpi_is_s0ix_active(adev)) 2682 adev->in_s0ix = false; 2683 else 2684 adev->in_s3 = false; 2685 return r; 2686 } 2687 2688 static int amdgpu_pmops_freeze(struct device *dev) 2689 { 2690 struct drm_device *drm_dev = dev_get_drvdata(dev); 2691 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2692 int r; 2693 2694 r = amdgpu_device_suspend(drm_dev, true); 2695 if (r) 2696 return r; 2697 2698 if (amdgpu_acpi_should_gpu_reset(adev)) 2699 return amdgpu_asic_reset(adev); 2700 return 0; 2701 } 2702 2703 static int amdgpu_pmops_thaw(struct device *dev) 2704 { 2705 struct drm_device *drm_dev = dev_get_drvdata(dev); 2706 2707 /* do not resume device if it's normal hibernation */ 2708 if (console_suspend_enabled && 2709 !pm_hibernate_is_recovering() && 2710 !pm_hibernation_mode_is_suspend()) 2711 return 0; 2712 2713 return amdgpu_device_resume(drm_dev, true); 2714 } 2715 2716 static int amdgpu_pmops_poweroff(struct device *dev) 2717 { 2718 struct drm_device *drm_dev = dev_get_drvdata(dev); 2719 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2720 2721 /* device maybe not resumed here, return immediately in this case */ 2722 if (adev->in_s4 && adev->in_suspend) 2723 return 0; 2724 2725 return amdgpu_device_suspend(drm_dev, true); 2726 } 2727 2728 static int amdgpu_pmops_restore(struct device *dev) 2729 { 2730 struct drm_device *drm_dev = dev_get_drvdata(dev); 2731 2732 return amdgpu_device_resume(drm_dev, true); 2733 } 2734 2735 static int amdgpu_runtime_idle_check_display(struct device *dev) 2736 { 2737 struct pci_dev *pdev = to_pci_dev(dev); 2738 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2739 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2740 2741 if (adev->mode_info.num_crtc) { 2742 struct drm_connector *list_connector; 2743 struct drm_connector_list_iter iter; 2744 int ret = 0; 2745 2746 if (amdgpu_runtime_pm != -2) { 2747 /* XXX: Return busy if any displays are connected to avoid 2748 * possible display wakeups after runtime resume due to 2749 * hotplug events in case any displays were connected while 2750 * the GPU was in suspend. Remove this once that is fixed. 2751 */ 2752 mutex_lock(&drm_dev->mode_config.mutex); 2753 drm_connector_list_iter_begin(drm_dev, &iter); 2754 drm_for_each_connector_iter(list_connector, &iter) { 2755 if (list_connector->status == connector_status_connected) { 2756 ret = -EBUSY; 2757 break; 2758 } 2759 } 2760 drm_connector_list_iter_end(&iter); 2761 mutex_unlock(&drm_dev->mode_config.mutex); 2762 2763 if (ret) 2764 return ret; 2765 } 2766 2767 if (adev->dc_enabled) { 2768 struct drm_crtc *crtc; 2769 2770 drm_for_each_crtc(crtc, drm_dev) { 2771 drm_modeset_lock(&crtc->mutex, NULL); 2772 if (crtc->state->active) 2773 ret = -EBUSY; 2774 drm_modeset_unlock(&crtc->mutex); 2775 if (ret < 0) 2776 break; 2777 } 2778 } else { 2779 mutex_lock(&drm_dev->mode_config.mutex); 2780 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2781 2782 drm_connector_list_iter_begin(drm_dev, &iter); 2783 drm_for_each_connector_iter(list_connector, &iter) { 2784 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2785 ret = -EBUSY; 2786 break; 2787 } 2788 } 2789 2790 drm_connector_list_iter_end(&iter); 2791 2792 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2793 mutex_unlock(&drm_dev->mode_config.mutex); 2794 } 2795 if (ret) 2796 return ret; 2797 } 2798 2799 return 0; 2800 } 2801 2802 static int amdgpu_runtime_idle_check_userq(struct device *dev) 2803 { 2804 struct pci_dev *pdev = to_pci_dev(dev); 2805 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2806 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2807 2808 return xa_empty(&adev->userq_doorbell_xa) ? 0 : -EBUSY; 2809 } 2810 2811 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2812 { 2813 struct pci_dev *pdev = to_pci_dev(dev); 2814 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2815 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2816 int ret, i; 2817 2818 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2819 pm_runtime_forbid(dev); 2820 return -EBUSY; 2821 } 2822 2823 ret = amdgpu_runtime_idle_check_display(dev); 2824 if (ret) 2825 return ret; 2826 ret = amdgpu_runtime_idle_check_userq(dev); 2827 if (ret) 2828 return ret; 2829 2830 /* wait for all rings to drain before suspending */ 2831 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2832 struct amdgpu_ring *ring = adev->rings[i]; 2833 2834 if (ring && ring->sched.ready) { 2835 ret = amdgpu_fence_wait_empty(ring); 2836 if (ret) 2837 return -EBUSY; 2838 } 2839 } 2840 2841 adev->in_runpm = true; 2842 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2843 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2844 2845 /* 2846 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2847 * proper cleanups and put itself into a state ready for PNP. That 2848 * can address some random resuming failure observed on BOCO capable 2849 * platforms. 2850 * TODO: this may be also needed for PX capable platform. 2851 */ 2852 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2853 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2854 2855 ret = amdgpu_device_prepare(drm_dev); 2856 if (ret) 2857 return ret; 2858 ret = amdgpu_device_suspend(drm_dev, false); 2859 if (ret) { 2860 adev->in_runpm = false; 2861 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2862 adev->mp1_state = PP_MP1_STATE_NONE; 2863 return ret; 2864 } 2865 2866 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2867 adev->mp1_state = PP_MP1_STATE_NONE; 2868 2869 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) { 2870 /* Only need to handle PCI state in the driver for ATPX 2871 * PCI core handles it for _PR3. 2872 */ 2873 amdgpu_device_cache_pci_state(pdev); 2874 pci_disable_device(pdev); 2875 pci_ignore_hotplug(pdev); 2876 pci_set_power_state(pdev, PCI_D3cold); 2877 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2878 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) { 2879 /* nothing to do */ 2880 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2881 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) { 2882 amdgpu_device_baco_enter(adev); 2883 } 2884 2885 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n"); 2886 2887 return 0; 2888 } 2889 2890 static int amdgpu_pmops_runtime_resume(struct device *dev) 2891 { 2892 struct pci_dev *pdev = to_pci_dev(dev); 2893 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2894 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2895 int ret; 2896 2897 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) 2898 return -EINVAL; 2899 2900 /* Avoids registers access if device is physically gone */ 2901 if (!pci_device_is_present(adev->pdev)) 2902 adev->no_hw_access = true; 2903 2904 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) { 2905 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2906 2907 /* Only need to handle PCI state in the driver for ATPX 2908 * PCI core handles it for _PR3. 2909 */ 2910 pci_set_power_state(pdev, PCI_D0); 2911 amdgpu_device_load_pci_state(pdev); 2912 ret = pci_enable_device(pdev); 2913 if (ret) 2914 return ret; 2915 pci_set_master(pdev); 2916 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) { 2917 /* Only need to handle PCI state in the driver for ATPX 2918 * PCI core handles it for _PR3. 2919 */ 2920 pci_set_master(pdev); 2921 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2922 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) { 2923 amdgpu_device_baco_exit(adev); 2924 } 2925 ret = amdgpu_device_resume(drm_dev, false); 2926 if (ret) { 2927 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2928 pci_disable_device(pdev); 2929 return ret; 2930 } 2931 2932 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2933 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2934 adev->in_runpm = false; 2935 return 0; 2936 } 2937 2938 static int amdgpu_pmops_runtime_idle(struct device *dev) 2939 { 2940 struct drm_device *drm_dev = dev_get_drvdata(dev); 2941 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2942 int ret; 2943 2944 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2945 pm_runtime_forbid(dev); 2946 return -EBUSY; 2947 } 2948 2949 ret = amdgpu_runtime_idle_check_display(dev); 2950 if (ret) 2951 goto done; 2952 2953 ret = amdgpu_runtime_idle_check_userq(dev); 2954 done: 2955 pm_runtime_autosuspend(dev); 2956 return ret; 2957 } 2958 2959 static int amdgpu_drm_release(struct inode *inode, struct file *filp) 2960 { 2961 struct drm_file *file_priv = filp->private_data; 2962 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2963 struct drm_device *dev = file_priv->minor->dev; 2964 int idx; 2965 2966 if (fpriv && drm_dev_enter(dev, &idx)) { 2967 fpriv->evf_mgr.fd_closing = true; 2968 amdgpu_eviction_fence_destroy(&fpriv->evf_mgr); 2969 amdgpu_userq_mgr_fini(&fpriv->userq_mgr); 2970 drm_dev_exit(idx); 2971 } 2972 2973 return drm_release(inode, filp); 2974 } 2975 2976 long amdgpu_drm_ioctl(struct file *filp, 2977 unsigned int cmd, unsigned long arg) 2978 { 2979 struct drm_file *file_priv = filp->private_data; 2980 struct drm_device *dev; 2981 long ret; 2982 2983 dev = file_priv->minor->dev; 2984 ret = pm_runtime_get_sync(dev->dev); 2985 if (ret < 0) 2986 goto out; 2987 2988 ret = drm_ioctl(filp, cmd, arg); 2989 2990 out: 2991 pm_runtime_put_autosuspend(dev->dev); 2992 return ret; 2993 } 2994 2995 static const struct dev_pm_ops amdgpu_pm_ops = { 2996 .prepare = pm_sleep_ptr(amdgpu_pmops_prepare), 2997 .complete = pm_sleep_ptr(amdgpu_pmops_complete), 2998 .suspend = pm_sleep_ptr(amdgpu_pmops_suspend), 2999 .suspend_noirq = pm_sleep_ptr(amdgpu_pmops_suspend_noirq), 3000 .resume = pm_sleep_ptr(amdgpu_pmops_resume), 3001 .freeze = pm_sleep_ptr(amdgpu_pmops_freeze), 3002 .thaw = pm_sleep_ptr(amdgpu_pmops_thaw), 3003 .poweroff = pm_sleep_ptr(amdgpu_pmops_poweroff), 3004 .restore = pm_sleep_ptr(amdgpu_pmops_restore), 3005 .runtime_suspend = amdgpu_pmops_runtime_suspend, 3006 .runtime_resume = amdgpu_pmops_runtime_resume, 3007 .runtime_idle = amdgpu_pmops_runtime_idle, 3008 }; 3009 3010 static int amdgpu_flush(struct file *f, fl_owner_t id) 3011 { 3012 struct drm_file *file_priv = f->private_data; 3013 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 3014 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 3015 3016 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 3017 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 3018 3019 return timeout >= 0 ? 0 : timeout; 3020 } 3021 3022 static const struct file_operations amdgpu_driver_kms_fops = { 3023 .owner = THIS_MODULE, 3024 .open = drm_open, 3025 .flush = amdgpu_flush, 3026 .release = amdgpu_drm_release, 3027 .unlocked_ioctl = amdgpu_drm_ioctl, 3028 .mmap = drm_gem_mmap, 3029 .poll = drm_poll, 3030 .read = drm_read, 3031 #ifdef CONFIG_COMPAT 3032 .compat_ioctl = amdgpu_kms_compat_ioctl, 3033 #endif 3034 #ifdef CONFIG_PROC_FS 3035 .show_fdinfo = drm_show_fdinfo, 3036 #endif 3037 .fop_flags = FOP_UNSIGNED_OFFSET, 3038 }; 3039 3040 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 3041 { 3042 struct drm_file *file; 3043 3044 if (!filp) 3045 return -EINVAL; 3046 3047 if (filp->f_op != &amdgpu_driver_kms_fops) 3048 return -EINVAL; 3049 3050 file = filp->private_data; 3051 *fpriv = file->driver_priv; 3052 return 0; 3053 } 3054 3055 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 3056 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3057 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3058 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3059 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 3060 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3061 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3062 /* KMS */ 3063 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3064 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3065 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3066 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3067 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3068 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3069 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3070 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3071 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3072 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3073 DRM_IOCTL_DEF_DRV(AMDGPU_USERQ, amdgpu_userq_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3074 DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_SIGNAL, amdgpu_userq_signal_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3075 DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_WAIT, amdgpu_userq_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3076 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_LIST_HANDLES, amdgpu_gem_list_handles_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3077 }; 3078 3079 static const struct drm_driver amdgpu_kms_driver = { 3080 .driver_features = 3081 DRIVER_ATOMIC | 3082 DRIVER_GEM | 3083 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 3084 DRIVER_SYNCOBJ_TIMELINE, 3085 .open = amdgpu_driver_open_kms, 3086 .postclose = amdgpu_driver_postclose_kms, 3087 .ioctls = amdgpu_ioctls_kms, 3088 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 3089 .dumb_create = amdgpu_mode_dumb_create, 3090 .dumb_map_offset = amdgpu_mode_dumb_mmap, 3091 DRM_FBDEV_TTM_DRIVER_OPS, 3092 .fops = &amdgpu_driver_kms_fops, 3093 .release = &amdgpu_driver_release_kms, 3094 #ifdef CONFIG_PROC_FS 3095 .show_fdinfo = amdgpu_show_fdinfo, 3096 #endif 3097 3098 .gem_prime_import = amdgpu_gem_prime_import, 3099 3100 .name = DRIVER_NAME, 3101 .desc = DRIVER_DESC, 3102 .major = KMS_DRIVER_MAJOR, 3103 .minor = KMS_DRIVER_MINOR, 3104 .patchlevel = KMS_DRIVER_PATCHLEVEL, 3105 }; 3106 3107 const struct drm_driver amdgpu_partition_driver = { 3108 .driver_features = 3109 DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ | 3110 DRIVER_SYNCOBJ_TIMELINE, 3111 .open = amdgpu_driver_open_kms, 3112 .postclose = amdgpu_driver_postclose_kms, 3113 .ioctls = amdgpu_ioctls_kms, 3114 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 3115 .dumb_create = amdgpu_mode_dumb_create, 3116 .dumb_map_offset = amdgpu_mode_dumb_mmap, 3117 DRM_FBDEV_TTM_DRIVER_OPS, 3118 .fops = &amdgpu_driver_kms_fops, 3119 .release = &amdgpu_driver_release_kms, 3120 3121 .gem_prime_import = amdgpu_gem_prime_import, 3122 3123 .name = DRIVER_NAME, 3124 .desc = DRIVER_DESC, 3125 .major = KMS_DRIVER_MAJOR, 3126 .minor = KMS_DRIVER_MINOR, 3127 .patchlevel = KMS_DRIVER_PATCHLEVEL, 3128 }; 3129 3130 static struct pci_error_handlers amdgpu_pci_err_handler = { 3131 .error_detected = amdgpu_pci_error_detected, 3132 .mmio_enabled = amdgpu_pci_mmio_enabled, 3133 .slot_reset = amdgpu_pci_slot_reset, 3134 .resume = amdgpu_pci_resume, 3135 }; 3136 3137 static const struct attribute_group *amdgpu_sysfs_groups[] = { 3138 &amdgpu_vram_mgr_attr_group, 3139 &amdgpu_gtt_mgr_attr_group, 3140 &amdgpu_flash_attr_group, 3141 NULL, 3142 }; 3143 3144 static struct pci_driver amdgpu_kms_pci_driver = { 3145 .name = DRIVER_NAME, 3146 .id_table = pciidlist, 3147 .probe = amdgpu_pci_probe, 3148 .remove = amdgpu_pci_remove, 3149 .shutdown = amdgpu_pci_shutdown, 3150 .driver.pm = pm_ptr(&amdgpu_pm_ops), 3151 .err_handler = &amdgpu_pci_err_handler, 3152 .dev_groups = amdgpu_sysfs_groups, 3153 }; 3154 3155 static int __init amdgpu_init(void) 3156 { 3157 int r; 3158 3159 r = amdgpu_sync_init(); 3160 if (r) 3161 goto error_sync; 3162 3163 r = amdgpu_userq_fence_slab_init(); 3164 if (r) 3165 goto error_fence; 3166 3167 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 3168 amdgpu_register_atpx_handler(); 3169 amdgpu_acpi_detect(); 3170 3171 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 3172 amdgpu_amdkfd_init(); 3173 3174 if (amdgpu_pp_feature_mask & PP_OVERDRIVE_MASK) { 3175 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 3176 pr_crit("Overdrive is enabled, please disable it before " 3177 "reporting any bugs unrelated to overdrive.\n"); 3178 } 3179 3180 /* let modprobe override vga console setting */ 3181 return pci_register_driver(&amdgpu_kms_pci_driver); 3182 3183 error_fence: 3184 amdgpu_sync_fini(); 3185 3186 error_sync: 3187 return r; 3188 } 3189 3190 static void __exit amdgpu_exit(void) 3191 { 3192 amdgpu_amdkfd_fini(); 3193 pci_unregister_driver(&amdgpu_kms_pci_driver); 3194 amdgpu_unregister_atpx_handler(); 3195 amdgpu_acpi_release(); 3196 amdgpu_sync_fini(); 3197 amdgpu_userq_fence_slab_fini(); 3198 mmu_notifier_synchronize(); 3199 amdgpu_xcp_drv_release(); 3200 } 3201 3202 module_init(amdgpu_init); 3203 module_exit(amdgpu_exit); 3204 3205 MODULE_AUTHOR(DRIVER_AUTHOR); 3206 MODULE_DESCRIPTION(DRIVER_DESC); 3207 MODULE_LICENSE("GPL and additional rights"); 3208