1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/clients/drm_client_setup.h> 27 #include <drm/drm_drv.h> 28 #include <drm/drm_fbdev_ttm.h> 29 #include <drm/drm_gem.h> 30 #include <drm/drm_managed.h> 31 #include <drm/drm_pciids.h> 32 #include <drm/drm_probe_helper.h> 33 #include <drm/drm_vblank.h> 34 35 #include <linux/cc_platform.h> 36 #include <linux/dynamic_debug.h> 37 #include <linux/module.h> 38 #include <linux/mmu_notifier.h> 39 #include <linux/pm_runtime.h> 40 #include <linux/suspend.h> 41 #include <linux/vga_switcheroo.h> 42 43 #include "amdgpu.h" 44 #include "amdgpu_amdkfd.h" 45 #include "amdgpu_dma_buf.h" 46 #include "amdgpu_drv.h" 47 #include "amdgpu_fdinfo.h" 48 #include "amdgpu_irq.h" 49 #include "amdgpu_psp.h" 50 #include "amdgpu_ras.h" 51 #include "amdgpu_reset.h" 52 #include "amdgpu_sched.h" 53 #include "amdgpu_xgmi.h" 54 #include "../amdxcp/amdgpu_xcp_drv.h" 55 56 /* 57 * KMS wrapper. 58 * - 3.0.0 - initial driver 59 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 60 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 61 * at the end of IBs. 62 * - 3.3.0 - Add VM support for UVD on supported hardware. 63 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 64 * - 3.5.0 - Add support for new UVD_NO_OP register. 65 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 66 * - 3.7.0 - Add support for VCE clock list packet 67 * - 3.8.0 - Add support raster config init in the kernel 68 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 69 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 70 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 71 * - 3.12.0 - Add query for double offchip LDS buffers 72 * - 3.13.0 - Add PRT support 73 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 74 * - 3.15.0 - Export more gpu info for gfx9 75 * - 3.16.0 - Add reserved vmid support 76 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 77 * - 3.18.0 - Export gpu always on cu bitmap 78 * - 3.19.0 - Add support for UVD MJPEG decode 79 * - 3.20.0 - Add support for local BOs 80 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 81 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 82 * - 3.23.0 - Add query for VRAM lost counter 83 * - 3.24.0 - Add high priority compute support for gfx9 84 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 85 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 86 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation. 87 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 88 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 89 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 90 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 91 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 92 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 93 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 94 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 95 * - 3.36.0 - Allow reading more status registers on si/cik 96 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 97 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 98 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 99 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 100 * - 3.41.0 - Add video codec query 101 * - 3.42.0 - Add 16bpc fixed point display support 102 * - 3.43.0 - Add device hot plug/unplug support 103 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 104 * - 3.45.0 - Add context ioctl stable pstate interface 105 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm 106 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags 107 * - 3.48.0 - Add IP discovery version info to HW INFO 108 * - 3.49.0 - Add gang submit into CS IOCTL 109 * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock 110 * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock 111 * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl 112 * 3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields: 113 * tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size, 114 * gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi 115 * 3.53.0 - Support for GFX11 CP GFX shadowing 116 * 3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support 117 * - 3.55.0 - Add AMDGPU_INFO_GPUVM_FAULT query 118 * - 3.56.0 - Update IB start address and size alignment for decode and encode 119 * - 3.57.0 - Compute tunneling on GFX10+ 120 * - 3.58.0 - Add GFX12 DCC support 121 * - 3.59.0 - Cleared VRAM 122 * - 3.60.0 - Add AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE (Vulkan requirement) 123 * - 3.61.0 - Contains fix for RV/PCO compute queues 124 * - 3.62.0 - Add AMDGPU_IDS_FLAGS_MODE_PF, AMDGPU_IDS_FLAGS_MODE_VF & AMDGPU_IDS_FLAGS_MODE_PT 125 * - 3.63.0 - GFX12 display DCC supports 256B max compressed block size 126 */ 127 #define KMS_DRIVER_MAJOR 3 128 #define KMS_DRIVER_MINOR 63 129 #define KMS_DRIVER_PATCHLEVEL 0 130 131 /* 132 * amdgpu.debug module options. Are all disabled by default 133 */ 134 enum AMDGPU_DEBUG_MASK { 135 AMDGPU_DEBUG_VM = BIT(0), 136 AMDGPU_DEBUG_LARGEBAR = BIT(1), 137 AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY = BIT(2), 138 AMDGPU_DEBUG_USE_VRAM_FW_BUF = BIT(3), 139 AMDGPU_DEBUG_ENABLE_RAS_ACA = BIT(4), 140 AMDGPU_DEBUG_ENABLE_EXP_RESETS = BIT(5), 141 AMDGPU_DEBUG_DISABLE_GPU_RING_RESET = BIT(6), 142 }; 143 144 unsigned int amdgpu_vram_limit = UINT_MAX; 145 int amdgpu_vis_vram_limit; 146 int amdgpu_gart_size = -1; /* auto */ 147 int amdgpu_gtt_size = -1; /* auto */ 148 int amdgpu_moverate = -1; /* auto */ 149 int amdgpu_audio = -1; 150 int amdgpu_disp_priority; 151 int amdgpu_hw_i2c; 152 int amdgpu_pcie_gen2 = -1; 153 int amdgpu_msi = -1; 154 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 155 int amdgpu_dpm = -1; 156 int amdgpu_fw_load_type = -1; 157 int amdgpu_aspm = -1; 158 int amdgpu_runtime_pm = -1; 159 uint amdgpu_ip_block_mask = 0xffffffff; 160 int amdgpu_bapm = -1; 161 int amdgpu_deep_color; 162 int amdgpu_vm_size = -1; 163 int amdgpu_vm_fragment_size = -1; 164 int amdgpu_vm_block_size = -1; 165 int amdgpu_vm_fault_stop; 166 int amdgpu_vm_update_mode = -1; 167 int amdgpu_exp_hw_support; 168 int amdgpu_dc = -1; 169 int amdgpu_sched_jobs = 32; 170 int amdgpu_sched_hw_submission = 2; 171 uint amdgpu_pcie_gen_cap; 172 uint amdgpu_pcie_lane_cap; 173 u64 amdgpu_cg_mask = 0xffffffffffffffff; 174 uint amdgpu_pg_mask = 0xffffffff; 175 uint amdgpu_sdma_phase_quantum = 32; 176 char *amdgpu_disable_cu; 177 char *amdgpu_virtual_display; 178 bool enforce_isolation; 179 180 /* Specifies the default granularity for SVM, used in buffer 181 * migration and restoration of backing memory when handling 182 * recoverable page faults. 183 * 184 * The value is given as log(numPages(buffer)); for a 2 MiB 185 * buffer it computes to be 9 186 */ 187 uint amdgpu_svm_default_granularity = 9; 188 189 /* 190 * OverDrive(bit 14) disabled by default 191 * GFX DCS(bit 19) disabled by default 192 */ 193 uint amdgpu_pp_feature_mask = 0xfff7bfff; 194 uint amdgpu_force_long_training; 195 int amdgpu_lbpw = -1; 196 int amdgpu_compute_multipipe = -1; 197 int amdgpu_gpu_recovery = -1; /* auto */ 198 int amdgpu_emu_mode; 199 uint amdgpu_smu_memory_pool_size; 200 int amdgpu_smu_pptable_id = -1; 201 /* 202 * FBC (bit 0) disabled by default 203 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 204 * - With this, for multiple monitors in sync(e.g. with the same model), 205 * mclk switching will be allowed. And the mclk will be not foced to the 206 * highest. That helps saving some idle power. 207 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 208 * PSR (bit 3) disabled by default 209 * EDP NO POWER SEQUENCING (bit 4) disabled by default 210 */ 211 uint amdgpu_dc_feature_mask = 2; 212 uint amdgpu_dc_debug_mask; 213 uint amdgpu_dc_visual_confirm; 214 int amdgpu_async_gfx_ring = 1; 215 int amdgpu_mcbp = -1; 216 int amdgpu_discovery = -1; 217 int amdgpu_mes; 218 int amdgpu_mes_log_enable = 0; 219 int amdgpu_mes_kiq; 220 int amdgpu_uni_mes = 1; 221 int amdgpu_noretry = -1; 222 int amdgpu_force_asic_type = -1; 223 int amdgpu_tmz = -1; /* auto */ 224 uint amdgpu_freesync_vid_mode; 225 int amdgpu_reset_method = -1; /* auto */ 226 int amdgpu_num_kcq = -1; 227 int amdgpu_smartshift_bias; 228 int amdgpu_use_xgmi_p2p = 1; 229 int amdgpu_vcnfw_log; 230 int amdgpu_sg_display = -1; /* auto */ 231 int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE; 232 int amdgpu_umsch_mm; 233 int amdgpu_seamless = -1; /* auto */ 234 uint amdgpu_debug_mask; 235 int amdgpu_agp = -1; /* auto */ 236 int amdgpu_wbrf = -1; 237 int amdgpu_damage_clips = -1; /* auto */ 238 int amdgpu_umsch_mm_fwlog; 239 240 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 241 "DRM_UT_CORE", 242 "DRM_UT_DRIVER", 243 "DRM_UT_KMS", 244 "DRM_UT_PRIME", 245 "DRM_UT_ATOMIC", 246 "DRM_UT_VBL", 247 "DRM_UT_STATE", 248 "DRM_UT_LEASE", 249 "DRM_UT_DP", 250 "DRM_UT_DRMRES"); 251 252 struct amdgpu_mgpu_info mgpu_info = { 253 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 254 }; 255 int amdgpu_ras_enable = -1; 256 uint amdgpu_ras_mask = 0xffffffff; 257 int amdgpu_bad_page_threshold = -1; 258 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 259 .timeout_fatal_disable = false, 260 .period = 0x0, /* default to 0x0 (timeout disable) */ 261 }; 262 263 /** 264 * DOC: vramlimit (int) 265 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 266 */ 267 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 268 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 269 270 /** 271 * DOC: vis_vramlimit (int) 272 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 273 */ 274 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 275 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 276 277 /** 278 * DOC: gartsize (uint) 279 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing. 280 * The default is -1 (The size depends on asic). 281 */ 282 MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)"); 283 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 284 285 /** 286 * DOC: gttsize (int) 287 * Restrict the size of GTT domain (for userspace use) in MiB for testing. 288 * The default is -1 (Use value specified by TTM). 289 * This parameter is deprecated and will be removed in the future. 290 */ 291 MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)"); 292 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 293 294 /** 295 * DOC: moverate (int) 296 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 297 */ 298 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 299 module_param_named(moverate, amdgpu_moverate, int, 0600); 300 301 /** 302 * DOC: audio (int) 303 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 304 */ 305 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 306 module_param_named(audio, amdgpu_audio, int, 0444); 307 308 /** 309 * DOC: disp_priority (int) 310 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 311 */ 312 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 313 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 314 315 /** 316 * DOC: hw_i2c (int) 317 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 318 */ 319 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 320 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 321 322 /** 323 * DOC: pcie_gen2 (int) 324 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 325 */ 326 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 327 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 328 329 /** 330 * DOC: msi (int) 331 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 332 */ 333 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 334 module_param_named(msi, amdgpu_msi, int, 0444); 335 336 /** 337 * DOC: svm_default_granularity (uint) 338 * Used in buffer migration and handling of recoverable page faults 339 */ 340 MODULE_PARM_DESC(svm_default_granularity, "SVM's default granularity in log(2^Pages), default 9 = 2^9 = 2 MiB"); 341 module_param_named(svm_default_granularity, amdgpu_svm_default_granularity, uint, 0644); 342 343 /** 344 * DOC: lockup_timeout (string) 345 * Set GPU scheduler timeout value in ms. 346 * 347 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 348 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 349 * to the default timeout. 350 * 351 * - With one value specified, the setting will apply to all non-compute jobs. 352 * - With multiple values specified, the first one will be for GFX. 353 * The second one is for Compute. The third and fourth ones are 354 * for SDMA and Video. 355 * 356 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 357 * jobs is 10000. The timeout for compute is 60000. 358 */ 359 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 360 "for passthrough or sriov, 10000 for all jobs. 0: keep default value. negative: infinity timeout), format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 361 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 362 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 363 364 /** 365 * DOC: dpm (int) 366 * Override for dynamic power management setting 367 * (0 = disable, 1 = enable) 368 * The default is -1 (auto). 369 */ 370 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 371 module_param_named(dpm, amdgpu_dpm, int, 0444); 372 373 /** 374 * DOC: fw_load_type (int) 375 * Set different firmware loading type for debugging, if supported. 376 * Set to 0 to force direct loading if supported by the ASIC. Set 377 * to -1 to select the default loading mode for the ASIC, as defined 378 * by the driver. The default is -1 (auto). 379 */ 380 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); 381 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 382 383 /** 384 * DOC: aspm (int) 385 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 386 */ 387 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 388 module_param_named(aspm, amdgpu_aspm, int, 0444); 389 390 /** 391 * DOC: runpm (int) 392 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 393 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 394 * Setting the value to 0 disables this functionality. 395 * Setting the value to -2 is auto enabled with power down when displays are attached. 396 */ 397 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto, -2 = auto with displays)"); 398 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 399 400 /** 401 * DOC: ip_block_mask (uint) 402 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 403 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 404 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 405 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 406 */ 407 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 408 module_param_named_unsafe(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 409 410 /** 411 * DOC: bapm (int) 412 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 413 * The default -1 (auto, enabled) 414 */ 415 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 416 module_param_named(bapm, amdgpu_bapm, int, 0444); 417 418 /** 419 * DOC: deep_color (int) 420 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 421 */ 422 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 423 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 424 425 /** 426 * DOC: vm_size (int) 427 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 428 */ 429 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 430 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 431 432 /** 433 * DOC: vm_fragment_size (int) 434 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 435 */ 436 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 437 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 438 439 /** 440 * DOC: vm_block_size (int) 441 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 442 */ 443 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 444 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 445 446 /** 447 * DOC: vm_fault_stop (int) 448 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 449 */ 450 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 451 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 452 453 /** 454 * DOC: vm_update_mode (int) 455 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 456 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 457 */ 458 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 459 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 460 461 /** 462 * DOC: exp_hw_support (int) 463 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 464 */ 465 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 466 module_param_named_unsafe(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 467 468 /** 469 * DOC: dc (int) 470 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 471 */ 472 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 473 module_param_named(dc, amdgpu_dc, int, 0444); 474 475 /** 476 * DOC: sched_jobs (int) 477 * Override the max number of jobs supported in the sw queue. The default is 32. 478 */ 479 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 480 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 481 482 /** 483 * DOC: sched_hw_submission (int) 484 * Override the max number of HW submissions. The default is 2. 485 */ 486 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 487 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 488 489 /** 490 * DOC: ppfeaturemask (hexint) 491 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 492 * The default is the current set of stable power features. 493 */ 494 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 495 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 496 497 /** 498 * DOC: forcelongtraining (uint) 499 * Force long memory training in resume. 500 * The default is zero, indicates short training in resume. 501 */ 502 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 503 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 504 505 /** 506 * DOC: pcie_gen_cap (uint) 507 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 508 * The default is 0 (automatic for each asic). 509 */ 510 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 511 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 512 513 /** 514 * DOC: pcie_lane_cap (uint) 515 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 516 * The default is 0 (automatic for each asic). 517 */ 518 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 519 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 520 521 /** 522 * DOC: cg_mask (ullong) 523 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 524 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 525 */ 526 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 527 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 528 529 /** 530 * DOC: pg_mask (uint) 531 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 532 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 533 */ 534 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 535 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 536 537 /** 538 * DOC: sdma_phase_quantum (uint) 539 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 540 */ 541 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 542 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 543 544 /** 545 * DOC: disable_cu (charp) 546 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 547 */ 548 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 549 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 550 551 /** 552 * DOC: virtual_display (charp) 553 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 554 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 555 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 556 * device at 26:00.0. The default is NULL. 557 */ 558 MODULE_PARM_DESC(virtual_display, 559 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 560 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 561 562 /** 563 * DOC: lbpw (int) 564 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 565 */ 566 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 567 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 568 569 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 570 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 571 572 /** 573 * DOC: gpu_recovery (int) 574 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 575 */ 576 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 577 module_param_named_unsafe(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 578 579 /** 580 * DOC: emu_mode (int) 581 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 582 */ 583 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 584 module_param_named_unsafe(emu_mode, amdgpu_emu_mode, int, 0444); 585 586 /** 587 * DOC: ras_enable (int) 588 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 589 */ 590 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 591 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 592 593 /** 594 * DOC: ras_mask (uint) 595 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 596 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 597 */ 598 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 599 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 600 601 /** 602 * DOC: timeout_fatal_disable (bool) 603 * Disable Watchdog timeout fatal error event 604 */ 605 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 606 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 607 608 /** 609 * DOC: timeout_period (uint) 610 * Modify the watchdog timeout max_cycles as (1 << period) 611 */ 612 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 613 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 614 615 /** 616 * DOC: si_support (int) 617 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 618 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 619 * otherwise using amdgpu driver. 620 */ 621 #ifdef CONFIG_DRM_AMDGPU_SI 622 623 #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) 624 int amdgpu_si_support; 625 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 626 #else 627 int amdgpu_si_support = 1; 628 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 629 #endif 630 631 module_param_named(si_support, amdgpu_si_support, int, 0444); 632 #endif 633 634 /** 635 * DOC: cik_support (int) 636 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 637 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 638 * otherwise using amdgpu driver. 639 */ 640 #ifdef CONFIG_DRM_AMDGPU_CIK 641 642 #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) 643 int amdgpu_cik_support; 644 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 645 #else 646 int amdgpu_cik_support = 1; 647 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 648 #endif 649 650 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 651 #endif 652 653 /** 654 * DOC: smu_memory_pool_size (uint) 655 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 656 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 657 */ 658 MODULE_PARM_DESC(smu_memory_pool_size, 659 "reserve gtt for smu debug usage, 0 = disable,0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 660 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 661 662 /** 663 * DOC: async_gfx_ring (int) 664 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 665 */ 666 MODULE_PARM_DESC(async_gfx_ring, 667 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 668 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 669 670 /** 671 * DOC: mcbp (int) 672 * It is used to enable mid command buffer preemption. (0 = disabled, 1 = enabled, -1 auto (default)) 673 */ 674 MODULE_PARM_DESC(mcbp, 675 "Enable Mid-command buffer preemption (0 = disabled, 1 = enabled), -1 = auto (default)"); 676 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 677 678 /** 679 * DOC: discovery (int) 680 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 681 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 682 */ 683 MODULE_PARM_DESC(discovery, 684 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 685 module_param_named(discovery, amdgpu_discovery, int, 0444); 686 687 /** 688 * DOC: mes (int) 689 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 690 * (0 = disabled (default), 1 = enabled) 691 */ 692 MODULE_PARM_DESC(mes, 693 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 694 module_param_named(mes, amdgpu_mes, int, 0444); 695 696 /** 697 * DOC: mes_log_enable (int) 698 * Enable Micro Engine Scheduler log. This is used to enable/disable MES internal log. 699 * (0 = disabled (default), 1 = enabled) 700 */ 701 MODULE_PARM_DESC(mes_log_enable, 702 "Enable Micro Engine Scheduler log (0 = disabled (default), 1 = enabled)"); 703 module_param_named(mes_log_enable, amdgpu_mes_log_enable, int, 0444); 704 705 /** 706 * DOC: mes_kiq (int) 707 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq. 708 * (0 = disabled (default), 1 = enabled) 709 */ 710 MODULE_PARM_DESC(mes_kiq, 711 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)"); 712 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444); 713 714 /** 715 * DOC: uni_mes (int) 716 * Enable Unified Micro Engine Scheduler. This is a new engine pipe for unified scheduler. 717 * (0 = disabled (default), 1 = enabled) 718 */ 719 MODULE_PARM_DESC(uni_mes, 720 "Enable Unified Micro Engine Scheduler (0 = disabled, 1 = enabled(default)"); 721 module_param_named(uni_mes, amdgpu_uni_mes, int, 0444); 722 723 /** 724 * DOC: noretry (int) 725 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 726 * do not support per-process XNACK this also disables retry page faults. 727 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 728 */ 729 MODULE_PARM_DESC(noretry, 730 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 731 module_param_named(noretry, amdgpu_noretry, int, 0644); 732 733 /** 734 * DOC: force_asic_type (int) 735 * A non negative value used to specify the asic type for all supported GPUs. 736 */ 737 MODULE_PARM_DESC(force_asic_type, 738 "A non negative value used to specify the asic type for all supported GPUs"); 739 module_param_named_unsafe(force_asic_type, amdgpu_force_asic_type, int, 0444); 740 741 /** 742 * DOC: use_xgmi_p2p (int) 743 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 744 */ 745 MODULE_PARM_DESC(use_xgmi_p2p, 746 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 747 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 748 749 750 #ifdef CONFIG_HSA_AMD 751 /** 752 * DOC: sched_policy (int) 753 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 754 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 755 * assigns queues to HQDs. 756 */ 757 int sched_policy = KFD_SCHED_POLICY_HWS; 758 module_param_unsafe(sched_policy, int, 0444); 759 MODULE_PARM_DESC(sched_policy, 760 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 761 762 /** 763 * DOC: hws_max_conc_proc (int) 764 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 765 * number of VMIDs assigned to the HWS, which is also the default. 766 */ 767 int hws_max_conc_proc = -1; 768 module_param(hws_max_conc_proc, int, 0444); 769 MODULE_PARM_DESC(hws_max_conc_proc, 770 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 771 772 /** 773 * DOC: cwsr_enable (int) 774 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 775 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 776 * disables it. 777 */ 778 int cwsr_enable = 1; 779 module_param(cwsr_enable, int, 0444); 780 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 781 782 /** 783 * DOC: max_num_of_queues_per_device (int) 784 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 785 * is 4096. 786 */ 787 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 788 module_param(max_num_of_queues_per_device, int, 0444); 789 MODULE_PARM_DESC(max_num_of_queues_per_device, 790 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 791 792 /** 793 * DOC: send_sigterm (int) 794 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 795 * but just print errors on dmesg. Setting 1 enables sending sigterm. 796 */ 797 int send_sigterm; 798 module_param(send_sigterm, int, 0444); 799 MODULE_PARM_DESC(send_sigterm, 800 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 801 802 /** 803 * DOC: halt_if_hws_hang (int) 804 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 805 * Setting 1 enables halt on hang. 806 */ 807 int halt_if_hws_hang; 808 module_param_unsafe(halt_if_hws_hang, int, 0644); 809 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 810 811 /** 812 * DOC: hws_gws_support(bool) 813 * Assume that HWS supports GWS barriers regardless of what firmware version 814 * check says. Default value: false (rely on MEC2 firmware version check). 815 */ 816 bool hws_gws_support; 817 module_param_unsafe(hws_gws_support, bool, 0444); 818 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 819 820 /** 821 * DOC: queue_preemption_timeout_ms (int) 822 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 823 */ 824 int queue_preemption_timeout_ms = 9000; 825 module_param(queue_preemption_timeout_ms, int, 0644); 826 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 827 828 /** 829 * DOC: debug_evictions(bool) 830 * Enable extra debug messages to help determine the cause of evictions 831 */ 832 bool debug_evictions; 833 module_param(debug_evictions, bool, 0644); 834 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 835 836 /** 837 * DOC: no_system_mem_limit(bool) 838 * Disable system memory limit, to support multiple process shared memory 839 */ 840 bool no_system_mem_limit; 841 module_param(no_system_mem_limit, bool, 0644); 842 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 843 844 /** 845 * DOC: no_queue_eviction_on_vm_fault (int) 846 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 847 */ 848 int amdgpu_no_queue_eviction_on_vm_fault; 849 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 850 module_param_named_unsafe(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 851 #endif 852 853 /** 854 * DOC: mtype_local (int) 855 */ 856 int amdgpu_mtype_local; 857 MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (0 = MTYPE_RW (default), 1 = MTYPE_NC, 2 = MTYPE_CC)"); 858 module_param_named_unsafe(mtype_local, amdgpu_mtype_local, int, 0444); 859 860 /** 861 * DOC: pcie_p2p (bool) 862 * Enable PCIe P2P (requires large-BAR). Default value: true (on) 863 */ 864 #ifdef CONFIG_HSA_AMD_P2P 865 bool pcie_p2p = true; 866 module_param(pcie_p2p, bool, 0444); 867 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); 868 #endif 869 870 /** 871 * DOC: dcfeaturemask (uint) 872 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 873 * The default is the current set of stable display features. 874 */ 875 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 876 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 877 878 /** 879 * DOC: dcdebugmask (uint) 880 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 881 */ 882 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 883 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 884 885 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)"); 886 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444); 887 888 /** 889 * DOC: abmlevel (uint) 890 * Override the default ABM (Adaptive Backlight Management) level used for DC 891 * enabled hardware. Requires DMCU to be supported and loaded. 892 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 893 * default. Values 1-4 control the maximum allowable brightness reduction via 894 * the ABM algorithm, with 1 being the least reduction and 4 being the most 895 * reduction. 896 * 897 * Defaults to -1, or auto. Userspace can only override this level after 898 * boot if it's set to auto. 899 */ 900 int amdgpu_dm_abm_level = -1; 901 MODULE_PARM_DESC(abmlevel, 902 "ABM level (0 = off, 1-4 = backlight reduction level, -1 auto (default))"); 903 module_param_named(abmlevel, amdgpu_dm_abm_level, int, 0444); 904 905 int amdgpu_backlight = -1; 906 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 907 module_param_named(backlight, amdgpu_backlight, bint, 0444); 908 909 /** 910 * DOC: damageclips (int) 911 * Enable or disable damage clips support. If damage clips support is disabled, 912 * we will force full frame updates, irrespective of what user space sends to 913 * us. 914 * 915 * Defaults to -1 (where it is enabled unless a PSR-SU display is detected). 916 */ 917 MODULE_PARM_DESC(damageclips, 918 "Damage clips support (0 = disable, 1 = enable, -1 auto (default))"); 919 module_param_named(damageclips, amdgpu_damage_clips, int, 0444); 920 921 /** 922 * DOC: tmz (int) 923 * Trusted Memory Zone (TMZ) is a method to protect data being written 924 * to or read from memory. 925 * 926 * The default value: 0 (off). TODO: change to auto till it is completed. 927 */ 928 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 929 module_param_named(tmz, amdgpu_tmz, int, 0444); 930 931 /** 932 * DOC: freesync_video (uint) 933 * Enable the optimization to adjust front porch timing to achieve seamless 934 * mode change experience when setting a freesync supported mode for which full 935 * modeset is not needed. 936 * 937 * The Display Core will add a set of modes derived from the base FreeSync 938 * video mode into the corresponding connector's mode list based on commonly 939 * used refresh rates and VRR range of the connected display, when users enable 940 * this feature. From the userspace perspective, they can see a seamless mode 941 * change experience when the change between different refresh rates under the 942 * same resolution. Additionally, userspace applications such as Video playback 943 * can read this modeset list and change the refresh rate based on the video 944 * frame rate. Finally, the userspace can also derive an appropriate mode for a 945 * particular refresh rate based on the FreeSync Mode and add it to the 946 * connector's mode list. 947 * 948 * Note: This is an experimental feature. 949 * 950 * The default value: 0 (off). 951 */ 952 MODULE_PARM_DESC( 953 freesync_video, 954 "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)"); 955 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); 956 957 /** 958 * DOC: reset_method (int) 959 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 960 */ 961 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 962 module_param_named_unsafe(reset_method, amdgpu_reset_method, int, 0644); 963 964 /** 965 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 966 * threshold value of faulty pages detected by RAS ECC, which may 967 * result in the GPU entering bad status when the number of total 968 * faulty pages by ECC exceeds the threshold value. 969 */ 970 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = threshold determined by a formula, 0 < threshold < max records, user-defined threshold)"); 971 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 972 973 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 974 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 975 976 /** 977 * DOC: vcnfw_log (int) 978 * Enable vcnfw log output for debugging, the default is disabled. 979 */ 980 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 981 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 982 983 /** 984 * DOC: sg_display (int) 985 * Disable S/G (scatter/gather) display (i.e., display from system memory). 986 * This option is only relevant on APUs. Set this option to 0 to disable 987 * S/G display if you experience flickering or other issues under memory 988 * pressure and report the issue. 989 */ 990 MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)"); 991 module_param_named(sg_display, amdgpu_sg_display, int, 0444); 992 993 /** 994 * DOC: umsch_mm (int) 995 * Enable Multi Media User Mode Scheduler. This is a HW scheduling engine for VCN and VPE. 996 * (0 = disabled (default), 1 = enabled) 997 */ 998 MODULE_PARM_DESC(umsch_mm, 999 "Enable Multi Media User Mode Scheduler (0 = disabled (default), 1 = enabled)"); 1000 module_param_named(umsch_mm, amdgpu_umsch_mm, int, 0444); 1001 1002 /** 1003 * DOC: umsch_mm_fwlog (int) 1004 * Enable umschfw log output for debugging, the default is disabled. 1005 */ 1006 MODULE_PARM_DESC(umsch_mm_fwlog, "Enable umschfw log(0 = disable (default value), 1 = enable)"); 1007 module_param_named(umsch_mm_fwlog, amdgpu_umsch_mm_fwlog, int, 0444); 1008 1009 /** 1010 * DOC: smu_pptable_id (int) 1011 * Used to override pptable id. id = 0 use VBIOS pptable. 1012 * id > 0 use the soft pptable with specicfied id. 1013 */ 1014 MODULE_PARM_DESC(smu_pptable_id, 1015 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 1016 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 1017 1018 /** 1019 * DOC: partition_mode (int) 1020 * Used to override the default SPX mode. 1021 */ 1022 MODULE_PARM_DESC( 1023 user_partt_mode, 1024 "specify partition mode to be used (-2 = AMDGPU_AUTO_COMPUTE_PARTITION_MODE(default value) \ 1025 0 = AMDGPU_SPX_PARTITION_MODE, \ 1026 1 = AMDGPU_DPX_PARTITION_MODE, \ 1027 2 = AMDGPU_TPX_PARTITION_MODE, \ 1028 3 = AMDGPU_QPX_PARTITION_MODE, \ 1029 4 = AMDGPU_CPX_PARTITION_MODE)"); 1030 module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint, 0444); 1031 1032 1033 /** 1034 * DOC: enforce_isolation (bool) 1035 * enforce process isolation between graphics and compute via using the same reserved vmid. 1036 */ 1037 module_param(enforce_isolation, bool, 0444); 1038 MODULE_PARM_DESC(enforce_isolation, "enforce process isolation between graphics and compute . enforce_isolation = on"); 1039 1040 /** 1041 * DOC: seamless (int) 1042 * Seamless boot will keep the image on the screen during the boot process. 1043 */ 1044 MODULE_PARM_DESC(seamless, "Seamless boot (-1 = auto (default), 0 = disable, 1 = enable)"); 1045 module_param_named(seamless, amdgpu_seamless, int, 0444); 1046 1047 /** 1048 * DOC: debug_mask (uint) 1049 * Debug options for amdgpu, work as a binary mask with the following options: 1050 * 1051 * - 0x1: Debug VM handling 1052 * - 0x2: Enable simulating large-bar capability on non-large bar system. This 1053 * limits the VRAM size reported to ROCm applications to the visible 1054 * size, usually 256MB. 1055 * - 0x4: Disable GPU soft recovery, always do a full reset 1056 */ 1057 MODULE_PARM_DESC(debug_mask, "debug options for amdgpu, disabled by default"); 1058 module_param_named_unsafe(debug_mask, amdgpu_debug_mask, uint, 0444); 1059 1060 /** 1061 * DOC: agp (int) 1062 * Enable the AGP aperture. This provides an aperture in the GPU's internal 1063 * address space for direct access to system memory. Note that these accesses 1064 * are non-snooped, so they are only used for access to uncached memory. 1065 */ 1066 MODULE_PARM_DESC(agp, "AGP (-1 = auto (default), 0 = disable, 1 = enable)"); 1067 module_param_named(agp, amdgpu_agp, int, 0444); 1068 1069 /** 1070 * DOC: wbrf (int) 1071 * Enable Wifi RFI interference mitigation feature. 1072 * Due to electrical and mechanical constraints there may be likely interference of 1073 * relatively high-powered harmonics of the (G-)DDR memory clocks with local radio 1074 * module frequency bands used by Wifi 6/6e/7. To mitigate the possible RFI interference, 1075 * with this feature enabled, PMFW will use either “shadowed P-State” or “P-State” based 1076 * on active list of frequencies in-use (to be avoided) as part of initial setting or 1077 * P-state transition. However, there may be potential performance impact with this 1078 * feature enabled. 1079 * (0 = disabled, 1 = enabled, -1 = auto (default setting, will be enabled if supported)) 1080 */ 1081 MODULE_PARM_DESC(wbrf, 1082 "Enable Wifi RFI interference mitigation (0 = disabled, 1 = enabled, -1 = auto(default)"); 1083 module_param_named(wbrf, amdgpu_wbrf, int, 0444); 1084 1085 /* These devices are not supported by amdgpu. 1086 * They are supported by the mach64, r128, radeon drivers 1087 */ 1088 static const u16 amdgpu_unsupported_pciidlist[] = { 1089 /* mach64 */ 1090 0x4354, 1091 0x4358, 1092 0x4554, 1093 0x4742, 1094 0x4744, 1095 0x4749, 1096 0x474C, 1097 0x474D, 1098 0x474E, 1099 0x474F, 1100 0x4750, 1101 0x4751, 1102 0x4752, 1103 0x4753, 1104 0x4754, 1105 0x4755, 1106 0x4756, 1107 0x4757, 1108 0x4758, 1109 0x4759, 1110 0x475A, 1111 0x4C42, 1112 0x4C44, 1113 0x4C47, 1114 0x4C49, 1115 0x4C4D, 1116 0x4C4E, 1117 0x4C50, 1118 0x4C51, 1119 0x4C52, 1120 0x4C53, 1121 0x5654, 1122 0x5655, 1123 0x5656, 1124 /* r128 */ 1125 0x4c45, 1126 0x4c46, 1127 0x4d46, 1128 0x4d4c, 1129 0x5041, 1130 0x5042, 1131 0x5043, 1132 0x5044, 1133 0x5045, 1134 0x5046, 1135 0x5047, 1136 0x5048, 1137 0x5049, 1138 0x504A, 1139 0x504B, 1140 0x504C, 1141 0x504D, 1142 0x504E, 1143 0x504F, 1144 0x5050, 1145 0x5051, 1146 0x5052, 1147 0x5053, 1148 0x5054, 1149 0x5055, 1150 0x5056, 1151 0x5057, 1152 0x5058, 1153 0x5245, 1154 0x5246, 1155 0x5247, 1156 0x524b, 1157 0x524c, 1158 0x534d, 1159 0x5446, 1160 0x544C, 1161 0x5452, 1162 /* radeon */ 1163 0x3150, 1164 0x3151, 1165 0x3152, 1166 0x3154, 1167 0x3155, 1168 0x3E50, 1169 0x3E54, 1170 0x4136, 1171 0x4137, 1172 0x4144, 1173 0x4145, 1174 0x4146, 1175 0x4147, 1176 0x4148, 1177 0x4149, 1178 0x414A, 1179 0x414B, 1180 0x4150, 1181 0x4151, 1182 0x4152, 1183 0x4153, 1184 0x4154, 1185 0x4155, 1186 0x4156, 1187 0x4237, 1188 0x4242, 1189 0x4336, 1190 0x4337, 1191 0x4437, 1192 0x4966, 1193 0x4967, 1194 0x4A48, 1195 0x4A49, 1196 0x4A4A, 1197 0x4A4B, 1198 0x4A4C, 1199 0x4A4D, 1200 0x4A4E, 1201 0x4A4F, 1202 0x4A50, 1203 0x4A54, 1204 0x4B48, 1205 0x4B49, 1206 0x4B4A, 1207 0x4B4B, 1208 0x4B4C, 1209 0x4C57, 1210 0x4C58, 1211 0x4C59, 1212 0x4C5A, 1213 0x4C64, 1214 0x4C66, 1215 0x4C67, 1216 0x4E44, 1217 0x4E45, 1218 0x4E46, 1219 0x4E47, 1220 0x4E48, 1221 0x4E49, 1222 0x4E4A, 1223 0x4E4B, 1224 0x4E50, 1225 0x4E51, 1226 0x4E52, 1227 0x4E53, 1228 0x4E54, 1229 0x4E56, 1230 0x5144, 1231 0x5145, 1232 0x5146, 1233 0x5147, 1234 0x5148, 1235 0x514C, 1236 0x514D, 1237 0x5157, 1238 0x5158, 1239 0x5159, 1240 0x515A, 1241 0x515E, 1242 0x5460, 1243 0x5462, 1244 0x5464, 1245 0x5548, 1246 0x5549, 1247 0x554A, 1248 0x554B, 1249 0x554C, 1250 0x554D, 1251 0x554E, 1252 0x554F, 1253 0x5550, 1254 0x5551, 1255 0x5552, 1256 0x5554, 1257 0x564A, 1258 0x564B, 1259 0x564F, 1260 0x5652, 1261 0x5653, 1262 0x5657, 1263 0x5834, 1264 0x5835, 1265 0x5954, 1266 0x5955, 1267 0x5974, 1268 0x5975, 1269 0x5960, 1270 0x5961, 1271 0x5962, 1272 0x5964, 1273 0x5965, 1274 0x5969, 1275 0x5a41, 1276 0x5a42, 1277 0x5a61, 1278 0x5a62, 1279 0x5b60, 1280 0x5b62, 1281 0x5b63, 1282 0x5b64, 1283 0x5b65, 1284 0x5c61, 1285 0x5c63, 1286 0x5d48, 1287 0x5d49, 1288 0x5d4a, 1289 0x5d4c, 1290 0x5d4d, 1291 0x5d4e, 1292 0x5d4f, 1293 0x5d50, 1294 0x5d52, 1295 0x5d57, 1296 0x5e48, 1297 0x5e4a, 1298 0x5e4b, 1299 0x5e4c, 1300 0x5e4d, 1301 0x5e4f, 1302 0x6700, 1303 0x6701, 1304 0x6702, 1305 0x6703, 1306 0x6704, 1307 0x6705, 1308 0x6706, 1309 0x6707, 1310 0x6708, 1311 0x6709, 1312 0x6718, 1313 0x6719, 1314 0x671c, 1315 0x671d, 1316 0x671f, 1317 0x6720, 1318 0x6721, 1319 0x6722, 1320 0x6723, 1321 0x6724, 1322 0x6725, 1323 0x6726, 1324 0x6727, 1325 0x6728, 1326 0x6729, 1327 0x6738, 1328 0x6739, 1329 0x673e, 1330 0x6740, 1331 0x6741, 1332 0x6742, 1333 0x6743, 1334 0x6744, 1335 0x6745, 1336 0x6746, 1337 0x6747, 1338 0x6748, 1339 0x6749, 1340 0x674A, 1341 0x6750, 1342 0x6751, 1343 0x6758, 1344 0x6759, 1345 0x675B, 1346 0x675D, 1347 0x675F, 1348 0x6760, 1349 0x6761, 1350 0x6762, 1351 0x6763, 1352 0x6764, 1353 0x6765, 1354 0x6766, 1355 0x6767, 1356 0x6768, 1357 0x6770, 1358 0x6771, 1359 0x6772, 1360 0x6778, 1361 0x6779, 1362 0x677B, 1363 0x6840, 1364 0x6841, 1365 0x6842, 1366 0x6843, 1367 0x6849, 1368 0x684C, 1369 0x6850, 1370 0x6858, 1371 0x6859, 1372 0x6880, 1373 0x6888, 1374 0x6889, 1375 0x688A, 1376 0x688C, 1377 0x688D, 1378 0x6898, 1379 0x6899, 1380 0x689b, 1381 0x689c, 1382 0x689d, 1383 0x689e, 1384 0x68a0, 1385 0x68a1, 1386 0x68a8, 1387 0x68a9, 1388 0x68b0, 1389 0x68b8, 1390 0x68b9, 1391 0x68ba, 1392 0x68be, 1393 0x68bf, 1394 0x68c0, 1395 0x68c1, 1396 0x68c7, 1397 0x68c8, 1398 0x68c9, 1399 0x68d8, 1400 0x68d9, 1401 0x68da, 1402 0x68de, 1403 0x68e0, 1404 0x68e1, 1405 0x68e4, 1406 0x68e5, 1407 0x68e8, 1408 0x68e9, 1409 0x68f1, 1410 0x68f2, 1411 0x68f8, 1412 0x68f9, 1413 0x68fa, 1414 0x68fe, 1415 0x7100, 1416 0x7101, 1417 0x7102, 1418 0x7103, 1419 0x7104, 1420 0x7105, 1421 0x7106, 1422 0x7108, 1423 0x7109, 1424 0x710A, 1425 0x710B, 1426 0x710C, 1427 0x710E, 1428 0x710F, 1429 0x7140, 1430 0x7141, 1431 0x7142, 1432 0x7143, 1433 0x7144, 1434 0x7145, 1435 0x7146, 1436 0x7147, 1437 0x7149, 1438 0x714A, 1439 0x714B, 1440 0x714C, 1441 0x714D, 1442 0x714E, 1443 0x714F, 1444 0x7151, 1445 0x7152, 1446 0x7153, 1447 0x715E, 1448 0x715F, 1449 0x7180, 1450 0x7181, 1451 0x7183, 1452 0x7186, 1453 0x7187, 1454 0x7188, 1455 0x718A, 1456 0x718B, 1457 0x718C, 1458 0x718D, 1459 0x718F, 1460 0x7193, 1461 0x7196, 1462 0x719B, 1463 0x719F, 1464 0x71C0, 1465 0x71C1, 1466 0x71C2, 1467 0x71C3, 1468 0x71C4, 1469 0x71C5, 1470 0x71C6, 1471 0x71C7, 1472 0x71CD, 1473 0x71CE, 1474 0x71D2, 1475 0x71D4, 1476 0x71D5, 1477 0x71D6, 1478 0x71DA, 1479 0x71DE, 1480 0x7200, 1481 0x7210, 1482 0x7211, 1483 0x7240, 1484 0x7243, 1485 0x7244, 1486 0x7245, 1487 0x7246, 1488 0x7247, 1489 0x7248, 1490 0x7249, 1491 0x724A, 1492 0x724B, 1493 0x724C, 1494 0x724D, 1495 0x724E, 1496 0x724F, 1497 0x7280, 1498 0x7281, 1499 0x7283, 1500 0x7284, 1501 0x7287, 1502 0x7288, 1503 0x7289, 1504 0x728B, 1505 0x728C, 1506 0x7290, 1507 0x7291, 1508 0x7293, 1509 0x7297, 1510 0x7834, 1511 0x7835, 1512 0x791e, 1513 0x791f, 1514 0x793f, 1515 0x7941, 1516 0x7942, 1517 0x796c, 1518 0x796d, 1519 0x796e, 1520 0x796f, 1521 0x9400, 1522 0x9401, 1523 0x9402, 1524 0x9403, 1525 0x9405, 1526 0x940A, 1527 0x940B, 1528 0x940F, 1529 0x94A0, 1530 0x94A1, 1531 0x94A3, 1532 0x94B1, 1533 0x94B3, 1534 0x94B4, 1535 0x94B5, 1536 0x94B9, 1537 0x9440, 1538 0x9441, 1539 0x9442, 1540 0x9443, 1541 0x9444, 1542 0x9446, 1543 0x944A, 1544 0x944B, 1545 0x944C, 1546 0x944E, 1547 0x9450, 1548 0x9452, 1549 0x9456, 1550 0x945A, 1551 0x945B, 1552 0x945E, 1553 0x9460, 1554 0x9462, 1555 0x946A, 1556 0x946B, 1557 0x947A, 1558 0x947B, 1559 0x9480, 1560 0x9487, 1561 0x9488, 1562 0x9489, 1563 0x948A, 1564 0x948F, 1565 0x9490, 1566 0x9491, 1567 0x9495, 1568 0x9498, 1569 0x949C, 1570 0x949E, 1571 0x949F, 1572 0x94C0, 1573 0x94C1, 1574 0x94C3, 1575 0x94C4, 1576 0x94C5, 1577 0x94C6, 1578 0x94C7, 1579 0x94C8, 1580 0x94C9, 1581 0x94CB, 1582 0x94CC, 1583 0x94CD, 1584 0x9500, 1585 0x9501, 1586 0x9504, 1587 0x9505, 1588 0x9506, 1589 0x9507, 1590 0x9508, 1591 0x9509, 1592 0x950F, 1593 0x9511, 1594 0x9515, 1595 0x9517, 1596 0x9519, 1597 0x9540, 1598 0x9541, 1599 0x9542, 1600 0x954E, 1601 0x954F, 1602 0x9552, 1603 0x9553, 1604 0x9555, 1605 0x9557, 1606 0x955f, 1607 0x9580, 1608 0x9581, 1609 0x9583, 1610 0x9586, 1611 0x9587, 1612 0x9588, 1613 0x9589, 1614 0x958A, 1615 0x958B, 1616 0x958C, 1617 0x958D, 1618 0x958E, 1619 0x958F, 1620 0x9590, 1621 0x9591, 1622 0x9593, 1623 0x9595, 1624 0x9596, 1625 0x9597, 1626 0x9598, 1627 0x9599, 1628 0x959B, 1629 0x95C0, 1630 0x95C2, 1631 0x95C4, 1632 0x95C5, 1633 0x95C6, 1634 0x95C7, 1635 0x95C9, 1636 0x95CC, 1637 0x95CD, 1638 0x95CE, 1639 0x95CF, 1640 0x9610, 1641 0x9611, 1642 0x9612, 1643 0x9613, 1644 0x9614, 1645 0x9615, 1646 0x9616, 1647 0x9640, 1648 0x9641, 1649 0x9642, 1650 0x9643, 1651 0x9644, 1652 0x9645, 1653 0x9647, 1654 0x9648, 1655 0x9649, 1656 0x964a, 1657 0x964b, 1658 0x964c, 1659 0x964e, 1660 0x964f, 1661 0x9710, 1662 0x9711, 1663 0x9712, 1664 0x9713, 1665 0x9714, 1666 0x9715, 1667 0x9802, 1668 0x9803, 1669 0x9804, 1670 0x9805, 1671 0x9806, 1672 0x9807, 1673 0x9808, 1674 0x9809, 1675 0x980A, 1676 0x9900, 1677 0x9901, 1678 0x9903, 1679 0x9904, 1680 0x9905, 1681 0x9906, 1682 0x9907, 1683 0x9908, 1684 0x9909, 1685 0x990A, 1686 0x990B, 1687 0x990C, 1688 0x990D, 1689 0x990E, 1690 0x990F, 1691 0x9910, 1692 0x9913, 1693 0x9917, 1694 0x9918, 1695 0x9919, 1696 0x9990, 1697 0x9991, 1698 0x9992, 1699 0x9993, 1700 0x9994, 1701 0x9995, 1702 0x9996, 1703 0x9997, 1704 0x9998, 1705 0x9999, 1706 0x999A, 1707 0x999B, 1708 0x999C, 1709 0x999D, 1710 0x99A0, 1711 0x99A2, 1712 0x99A4, 1713 /* radeon secondary ids */ 1714 0x3171, 1715 0x3e70, 1716 0x4164, 1717 0x4165, 1718 0x4166, 1719 0x4168, 1720 0x4170, 1721 0x4171, 1722 0x4172, 1723 0x4173, 1724 0x496e, 1725 0x4a69, 1726 0x4a6a, 1727 0x4a6b, 1728 0x4a70, 1729 0x4a74, 1730 0x4b69, 1731 0x4b6b, 1732 0x4b6c, 1733 0x4c6e, 1734 0x4e64, 1735 0x4e65, 1736 0x4e66, 1737 0x4e67, 1738 0x4e68, 1739 0x4e69, 1740 0x4e6a, 1741 0x4e71, 1742 0x4f73, 1743 0x5569, 1744 0x556b, 1745 0x556d, 1746 0x556f, 1747 0x5571, 1748 0x5854, 1749 0x5874, 1750 0x5940, 1751 0x5941, 1752 0x5b70, 1753 0x5b72, 1754 0x5b73, 1755 0x5b74, 1756 0x5b75, 1757 0x5d44, 1758 0x5d45, 1759 0x5d6d, 1760 0x5d6f, 1761 0x5d72, 1762 0x5d77, 1763 0x5e6b, 1764 0x5e6d, 1765 0x7120, 1766 0x7124, 1767 0x7129, 1768 0x712e, 1769 0x712f, 1770 0x7162, 1771 0x7163, 1772 0x7166, 1773 0x7167, 1774 0x7172, 1775 0x7173, 1776 0x71a0, 1777 0x71a1, 1778 0x71a3, 1779 0x71a7, 1780 0x71bb, 1781 0x71e0, 1782 0x71e1, 1783 0x71e2, 1784 0x71e6, 1785 0x71e7, 1786 0x71f2, 1787 0x7269, 1788 0x726b, 1789 0x726e, 1790 0x72a0, 1791 0x72a8, 1792 0x72b1, 1793 0x72b3, 1794 0x793f, 1795 }; 1796 1797 static const struct pci_device_id pciidlist[] = { 1798 #ifdef CONFIG_DRM_AMDGPU_SI 1799 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1800 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1801 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1802 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1803 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1804 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1805 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1806 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1807 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1808 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1809 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1810 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1811 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1812 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1813 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1814 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1815 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1816 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1817 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1818 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1819 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1820 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1821 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1822 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1823 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1824 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1825 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1826 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1827 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1828 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1829 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1830 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1831 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1832 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1833 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1834 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1835 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1836 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1837 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1838 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1839 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1840 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1841 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1842 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1843 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1844 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1845 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1846 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1847 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1848 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1849 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1850 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1851 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1852 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1853 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1854 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1855 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1856 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1857 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1858 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1859 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1860 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1861 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1862 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1863 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1864 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1865 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1866 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1867 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1868 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1869 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1870 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1871 #endif 1872 #ifdef CONFIG_DRM_AMDGPU_CIK 1873 /* Kaveri */ 1874 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1875 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1876 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1877 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1878 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1879 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1880 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1881 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1882 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1883 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1884 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1885 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1886 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1887 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1888 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1889 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1890 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1891 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1892 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1893 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1894 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1895 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1896 /* Bonaire */ 1897 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1898 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1899 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1900 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1901 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1902 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1903 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1904 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1905 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1906 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1907 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1908 /* Hawaii */ 1909 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1910 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1911 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1912 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1913 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1914 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1915 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1916 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1917 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1918 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1919 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1920 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1921 /* Kabini */ 1922 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1923 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1924 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1925 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1926 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1927 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1928 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1929 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1930 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1931 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1932 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1933 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1934 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1935 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1936 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1937 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1938 /* mullins */ 1939 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1940 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1941 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1942 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1943 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1944 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1945 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1946 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1947 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1948 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1949 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1950 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1951 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1952 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1953 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1954 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1955 #endif 1956 /* topaz */ 1957 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1958 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1959 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1960 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1961 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1962 /* tonga */ 1963 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1964 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1965 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1966 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1967 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1968 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1969 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1970 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1971 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1972 /* fiji */ 1973 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1974 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1975 /* carrizo */ 1976 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1977 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1978 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1979 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1980 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1981 /* stoney */ 1982 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1983 /* Polaris11 */ 1984 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1985 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1986 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1987 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1988 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1989 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1990 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1991 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1992 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1993 /* Polaris10 */ 1994 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1995 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1996 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1997 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1998 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1999 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2000 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2001 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2002 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2003 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2004 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2005 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2006 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2007 /* Polaris12 */ 2008 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2009 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2010 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2011 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2012 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2013 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2014 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2015 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2016 /* VEGAM */ 2017 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 2018 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 2019 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 2020 /* Vega 10 */ 2021 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2022 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2023 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2024 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2025 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2026 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2027 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2028 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2029 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2030 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2031 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2032 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2033 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2034 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2035 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2036 /* Vega 12 */ 2037 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2038 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2039 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2040 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2041 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2042 /* Vega 20 */ 2043 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2044 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2045 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2046 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2047 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2048 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2049 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2050 /* Raven */ 2051 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 2052 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 2053 /* Arcturus */ 2054 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2055 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2056 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2057 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2058 /* Navi10 */ 2059 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2060 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2061 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2062 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2063 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2064 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2065 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2066 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2067 /* Navi14 */ 2068 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2069 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2070 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2071 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2072 2073 /* Renoir */ 2074 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2075 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2076 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2077 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2078 2079 /* Navi12 */ 2080 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 2081 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 2082 2083 /* Sienna_Cichlid */ 2084 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2085 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2086 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2087 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2088 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2089 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2090 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2091 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2092 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2093 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2094 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2095 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2096 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2097 2098 /* Yellow Carp */ 2099 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 2100 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 2101 2102 /* Navy_Flounder */ 2103 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2104 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2105 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2106 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2107 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2108 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2109 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2110 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2111 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2112 2113 /* DIMGREY_CAVEFISH */ 2114 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2115 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2116 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2117 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2118 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2119 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2120 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2121 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2122 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2123 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2124 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2125 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2126 2127 /* Aldebaran */ 2128 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2129 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2130 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2131 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2132 2133 /* CYAN_SKILLFISH */ 2134 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2135 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2136 2137 /* BEIGE_GOBY */ 2138 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2139 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2140 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2141 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2142 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2143 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2144 2145 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2146 .class = PCI_CLASS_DISPLAY_VGA << 8, 2147 .class_mask = 0xffffff, 2148 .driver_data = CHIP_IP_DISCOVERY }, 2149 2150 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2151 .class = PCI_CLASS_DISPLAY_OTHER << 8, 2152 .class_mask = 0xffffff, 2153 .driver_data = CHIP_IP_DISCOVERY }, 2154 2155 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2156 .class = PCI_CLASS_ACCELERATOR_PROCESSING << 8, 2157 .class_mask = 0xffffff, 2158 .driver_data = CHIP_IP_DISCOVERY }, 2159 2160 {0, 0, 0} 2161 }; 2162 2163 MODULE_DEVICE_TABLE(pci, pciidlist); 2164 2165 static const struct amdgpu_asic_type_quirk asic_type_quirks[] = { 2166 /* differentiate between P10 and P11 asics with the same DID */ 2167 {0x67FF, 0xE3, CHIP_POLARIS10}, 2168 {0x67FF, 0xE7, CHIP_POLARIS10}, 2169 {0x67FF, 0xF3, CHIP_POLARIS10}, 2170 {0x67FF, 0xF7, CHIP_POLARIS10}, 2171 }; 2172 2173 static const struct drm_driver amdgpu_kms_driver; 2174 2175 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 2176 { 2177 struct pci_dev *p = NULL; 2178 int i; 2179 2180 /* 0 - GPU 2181 * 1 - audio 2182 * 2 - USB 2183 * 3 - UCSI 2184 */ 2185 for (i = 1; i < 4; i++) { 2186 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 2187 adev->pdev->bus->number, i); 2188 if (p) { 2189 pm_runtime_get_sync(&p->dev); 2190 pm_runtime_mark_last_busy(&p->dev); 2191 pm_runtime_put_autosuspend(&p->dev); 2192 pci_dev_put(p); 2193 } 2194 } 2195 } 2196 2197 static void amdgpu_init_debug_options(struct amdgpu_device *adev) 2198 { 2199 if (amdgpu_debug_mask & AMDGPU_DEBUG_VM) { 2200 pr_info("debug: VM handling debug enabled\n"); 2201 adev->debug_vm = true; 2202 } 2203 2204 if (amdgpu_debug_mask & AMDGPU_DEBUG_LARGEBAR) { 2205 pr_info("debug: enabled simulating large-bar capability on non-large bar system\n"); 2206 adev->debug_largebar = true; 2207 } 2208 2209 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY) { 2210 pr_info("debug: soft reset for GPU recovery disabled\n"); 2211 adev->debug_disable_soft_recovery = true; 2212 } 2213 2214 if (amdgpu_debug_mask & AMDGPU_DEBUG_USE_VRAM_FW_BUF) { 2215 pr_info("debug: place fw in vram for frontdoor loading\n"); 2216 adev->debug_use_vram_fw_buf = true; 2217 } 2218 2219 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_RAS_ACA) { 2220 pr_info("debug: enable RAS ACA\n"); 2221 adev->debug_enable_ras_aca = true; 2222 } 2223 2224 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_EXP_RESETS) { 2225 pr_info("debug: enable experimental reset features\n"); 2226 adev->debug_exp_resets = true; 2227 } 2228 2229 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_RING_RESET) { 2230 pr_info("debug: ring reset disabled\n"); 2231 adev->debug_disable_gpu_ring_reset = true; 2232 } 2233 } 2234 2235 static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long flags) 2236 { 2237 int i; 2238 2239 for (i = 0; i < ARRAY_SIZE(asic_type_quirks); i++) { 2240 if (pdev->device == asic_type_quirks[i].device && 2241 pdev->revision == asic_type_quirks[i].revision) { 2242 flags &= ~AMD_ASIC_MASK; 2243 flags |= asic_type_quirks[i].type; 2244 break; 2245 } 2246 } 2247 2248 return flags; 2249 } 2250 2251 static int amdgpu_pci_probe(struct pci_dev *pdev, 2252 const struct pci_device_id *ent) 2253 { 2254 struct drm_device *ddev; 2255 struct amdgpu_device *adev; 2256 unsigned long flags = ent->driver_data; 2257 int ret, retry = 0, i; 2258 bool supports_atomic = false; 2259 2260 /* skip devices which are owned by radeon */ 2261 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2262 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2263 return -ENODEV; 2264 } 2265 2266 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) 2267 amdgpu_aspm = 0; 2268 2269 if (amdgpu_virtual_display || 2270 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 2271 supports_atomic = true; 2272 2273 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2274 DRM_INFO("This hardware requires experimental hardware support.\n" 2275 "See modparam exp_hw_support\n"); 2276 return -ENODEV; 2277 } 2278 2279 flags = amdgpu_fix_asic_type(pdev, flags); 2280 2281 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2282 * however, SME requires an indirect IOMMU mapping because the encryption 2283 * bit is beyond the DMA mask of the chip. 2284 */ 2285 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2286 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2287 dev_info(&pdev->dev, 2288 "SME is not compatible with RAVEN\n"); 2289 return -ENOTSUPP; 2290 } 2291 2292 #ifdef CONFIG_DRM_AMDGPU_SI 2293 if (!amdgpu_si_support) { 2294 switch (flags & AMD_ASIC_MASK) { 2295 case CHIP_TAHITI: 2296 case CHIP_PITCAIRN: 2297 case CHIP_VERDE: 2298 case CHIP_OLAND: 2299 case CHIP_HAINAN: 2300 dev_info(&pdev->dev, 2301 "SI support provided by radeon.\n"); 2302 dev_info(&pdev->dev, 2303 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 2304 ); 2305 return -ENODEV; 2306 } 2307 } 2308 #endif 2309 #ifdef CONFIG_DRM_AMDGPU_CIK 2310 if (!amdgpu_cik_support) { 2311 switch (flags & AMD_ASIC_MASK) { 2312 case CHIP_KAVERI: 2313 case CHIP_BONAIRE: 2314 case CHIP_HAWAII: 2315 case CHIP_KABINI: 2316 case CHIP_MULLINS: 2317 dev_info(&pdev->dev, 2318 "CIK support provided by radeon.\n"); 2319 dev_info(&pdev->dev, 2320 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 2321 ); 2322 return -ENODEV; 2323 } 2324 } 2325 #endif 2326 2327 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2328 if (IS_ERR(adev)) 2329 return PTR_ERR(adev); 2330 2331 adev->dev = &pdev->dev; 2332 adev->pdev = pdev; 2333 ddev = adev_to_drm(adev); 2334 2335 if (!supports_atomic) 2336 ddev->driver_features &= ~DRIVER_ATOMIC; 2337 2338 ret = pci_enable_device(pdev); 2339 if (ret) 2340 return ret; 2341 2342 pci_set_drvdata(pdev, ddev); 2343 2344 amdgpu_init_debug_options(adev); 2345 2346 ret = amdgpu_driver_load_kms(adev, flags); 2347 if (ret) 2348 goto err_pci; 2349 2350 retry_init: 2351 ret = drm_dev_register(ddev, flags); 2352 if (ret == -EAGAIN && ++retry <= 3) { 2353 DRM_INFO("retry init %d\n", retry); 2354 /* Don't request EX mode too frequently which is attacking */ 2355 msleep(5000); 2356 goto retry_init; 2357 } else if (ret) { 2358 goto err_pci; 2359 } 2360 2361 ret = amdgpu_xcp_dev_register(adev, ent); 2362 if (ret) 2363 goto err_pci; 2364 2365 ret = amdgpu_amdkfd_drm_client_create(adev); 2366 if (ret) 2367 goto err_pci; 2368 2369 /* 2370 * 1. don't init fbdev on hw without DCE 2371 * 2. don't init fbdev if there are no connectors 2372 */ 2373 if (adev->mode_info.mode_config_initialized && 2374 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2375 const struct drm_format_info *format; 2376 2377 /* select 8 bpp console on low vram cards */ 2378 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2379 format = drm_format_info(DRM_FORMAT_C8); 2380 else 2381 format = NULL; 2382 2383 drm_client_setup(adev_to_drm(adev), format); 2384 } 2385 2386 ret = amdgpu_debugfs_init(adev); 2387 if (ret) 2388 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2389 2390 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2391 /* only need to skip on ATPX */ 2392 if (amdgpu_device_supports_px(ddev)) 2393 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2394 /* we want direct complete for BOCO */ 2395 if (amdgpu_device_supports_boco(ddev)) 2396 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2397 DPM_FLAG_SMART_SUSPEND | 2398 DPM_FLAG_MAY_SKIP_RESUME); 2399 pm_runtime_use_autosuspend(ddev->dev); 2400 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2401 2402 pm_runtime_allow(ddev->dev); 2403 2404 pm_runtime_mark_last_busy(ddev->dev); 2405 pm_runtime_put_autosuspend(ddev->dev); 2406 2407 pci_wake_from_d3(pdev, TRUE); 2408 2409 /* 2410 * For runpm implemented via BACO, PMFW will handle the 2411 * timing for BACO in and out: 2412 * - put ASIC into BACO state only when both video and 2413 * audio functions are in D3 state. 2414 * - pull ASIC out of BACO state when either video or 2415 * audio function is in D0 state. 2416 * Also, at startup, PMFW assumes both functions are in 2417 * D0 state. 2418 * 2419 * So if snd driver was loaded prior to amdgpu driver 2420 * and audio function was put into D3 state, there will 2421 * be no PMFW-aware D-state transition(D0->D3) on runpm 2422 * suspend. Thus the BACO will be not correctly kicked in. 2423 * 2424 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2425 * into D0 state. Then there will be a PMFW-aware D-state 2426 * transition(D0->D3) on runpm suspend. 2427 */ 2428 if (amdgpu_device_supports_baco(ddev) && 2429 !(adev->flags & AMD_IS_APU) && 2430 (adev->asic_type >= CHIP_NAVI10)) 2431 amdgpu_get_secondary_funcs(adev); 2432 } 2433 2434 return 0; 2435 2436 err_pci: 2437 pci_disable_device(pdev); 2438 return ret; 2439 } 2440 2441 static void 2442 amdgpu_pci_remove(struct pci_dev *pdev) 2443 { 2444 struct drm_device *dev = pci_get_drvdata(pdev); 2445 struct amdgpu_device *adev = drm_to_adev(dev); 2446 2447 amdgpu_xcp_dev_unplug(adev); 2448 amdgpu_gmc_prepare_nps_mode_change(adev); 2449 drm_dev_unplug(dev); 2450 2451 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2452 pm_runtime_get_sync(dev->dev); 2453 pm_runtime_forbid(dev->dev); 2454 } 2455 2456 amdgpu_driver_unload_kms(dev); 2457 2458 /* 2459 * Flush any in flight DMA operations from device. 2460 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2461 * StatusTransactions Pending bit. 2462 */ 2463 pci_disable_device(pdev); 2464 pci_wait_for_pending_transaction(pdev); 2465 } 2466 2467 static void 2468 amdgpu_pci_shutdown(struct pci_dev *pdev) 2469 { 2470 struct drm_device *dev = pci_get_drvdata(pdev); 2471 struct amdgpu_device *adev = drm_to_adev(dev); 2472 2473 if (amdgpu_ras_intr_triggered()) 2474 return; 2475 2476 /* if we are running in a VM, make sure the device 2477 * torn down properly on reboot/shutdown. 2478 * unfortunately we can't detect certain 2479 * hypervisors so just do this all the time. 2480 */ 2481 if (!amdgpu_passthrough(adev)) 2482 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2483 amdgpu_device_ip_suspend(adev); 2484 adev->mp1_state = PP_MP1_STATE_NONE; 2485 } 2486 2487 static int amdgpu_pmops_prepare(struct device *dev) 2488 { 2489 struct drm_device *drm_dev = dev_get_drvdata(dev); 2490 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2491 2492 /* Return a positive number here so 2493 * DPM_FLAG_SMART_SUSPEND works properly 2494 */ 2495 if (amdgpu_device_supports_boco(drm_dev) && 2496 pm_runtime_suspended(dev)) 2497 return 1; 2498 2499 /* if we will not support s3 or s2i for the device 2500 * then skip suspend 2501 */ 2502 if (!amdgpu_acpi_is_s0ix_active(adev) && 2503 !amdgpu_acpi_is_s3_active(adev)) 2504 return 1; 2505 2506 return amdgpu_device_prepare(drm_dev); 2507 } 2508 2509 static void amdgpu_pmops_complete(struct device *dev) 2510 { 2511 /* nothing to do */ 2512 } 2513 2514 static int amdgpu_pmops_suspend(struct device *dev) 2515 { 2516 struct drm_device *drm_dev = dev_get_drvdata(dev); 2517 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2518 2519 if (amdgpu_acpi_is_s0ix_active(adev)) 2520 adev->in_s0ix = true; 2521 else if (amdgpu_acpi_is_s3_active(adev)) 2522 adev->in_s3 = true; 2523 if (!adev->in_s0ix && !adev->in_s3) 2524 return 0; 2525 return amdgpu_device_suspend(drm_dev, true); 2526 } 2527 2528 static int amdgpu_pmops_suspend_noirq(struct device *dev) 2529 { 2530 struct drm_device *drm_dev = dev_get_drvdata(dev); 2531 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2532 2533 if (amdgpu_acpi_should_gpu_reset(adev)) 2534 return amdgpu_asic_reset(adev); 2535 2536 return 0; 2537 } 2538 2539 static int amdgpu_pmops_resume(struct device *dev) 2540 { 2541 struct drm_device *drm_dev = dev_get_drvdata(dev); 2542 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2543 int r; 2544 2545 if (!adev->in_s0ix && !adev->in_s3) 2546 return 0; 2547 2548 /* Avoids registers access if device is physically gone */ 2549 if (!pci_device_is_present(adev->pdev)) 2550 adev->no_hw_access = true; 2551 2552 r = amdgpu_device_resume(drm_dev, true); 2553 if (amdgpu_acpi_is_s0ix_active(adev)) 2554 adev->in_s0ix = false; 2555 else 2556 adev->in_s3 = false; 2557 return r; 2558 } 2559 2560 static int amdgpu_pmops_freeze(struct device *dev) 2561 { 2562 struct drm_device *drm_dev = dev_get_drvdata(dev); 2563 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2564 int r; 2565 2566 r = amdgpu_device_suspend(drm_dev, true); 2567 if (r) 2568 return r; 2569 2570 if (amdgpu_acpi_should_gpu_reset(adev)) 2571 return amdgpu_asic_reset(adev); 2572 return 0; 2573 } 2574 2575 static int amdgpu_pmops_thaw(struct device *dev) 2576 { 2577 struct drm_device *drm_dev = dev_get_drvdata(dev); 2578 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2579 int r; 2580 2581 r = amdgpu_device_resume(drm_dev, true); 2582 adev->in_s4 = false; 2583 2584 return r; 2585 } 2586 2587 static int amdgpu_pmops_poweroff(struct device *dev) 2588 { 2589 struct drm_device *drm_dev = dev_get_drvdata(dev); 2590 2591 return amdgpu_device_suspend(drm_dev, true); 2592 } 2593 2594 static int amdgpu_pmops_restore(struct device *dev) 2595 { 2596 struct drm_device *drm_dev = dev_get_drvdata(dev); 2597 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2598 2599 adev->in_s4 = false; 2600 2601 return amdgpu_device_resume(drm_dev, true); 2602 } 2603 2604 static int amdgpu_runtime_idle_check_display(struct device *dev) 2605 { 2606 struct pci_dev *pdev = to_pci_dev(dev); 2607 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2608 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2609 2610 if (adev->mode_info.num_crtc) { 2611 struct drm_connector *list_connector; 2612 struct drm_connector_list_iter iter; 2613 int ret = 0; 2614 2615 if (amdgpu_runtime_pm != -2) { 2616 /* XXX: Return busy if any displays are connected to avoid 2617 * possible display wakeups after runtime resume due to 2618 * hotplug events in case any displays were connected while 2619 * the GPU was in suspend. Remove this once that is fixed. 2620 */ 2621 mutex_lock(&drm_dev->mode_config.mutex); 2622 drm_connector_list_iter_begin(drm_dev, &iter); 2623 drm_for_each_connector_iter(list_connector, &iter) { 2624 if (list_connector->status == connector_status_connected) { 2625 ret = -EBUSY; 2626 break; 2627 } 2628 } 2629 drm_connector_list_iter_end(&iter); 2630 mutex_unlock(&drm_dev->mode_config.mutex); 2631 2632 if (ret) 2633 return ret; 2634 } 2635 2636 if (adev->dc_enabled) { 2637 struct drm_crtc *crtc; 2638 2639 drm_for_each_crtc(crtc, drm_dev) { 2640 drm_modeset_lock(&crtc->mutex, NULL); 2641 if (crtc->state->active) 2642 ret = -EBUSY; 2643 drm_modeset_unlock(&crtc->mutex); 2644 if (ret < 0) 2645 break; 2646 } 2647 } else { 2648 mutex_lock(&drm_dev->mode_config.mutex); 2649 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2650 2651 drm_connector_list_iter_begin(drm_dev, &iter); 2652 drm_for_each_connector_iter(list_connector, &iter) { 2653 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2654 ret = -EBUSY; 2655 break; 2656 } 2657 } 2658 2659 drm_connector_list_iter_end(&iter); 2660 2661 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2662 mutex_unlock(&drm_dev->mode_config.mutex); 2663 } 2664 if (ret) 2665 return ret; 2666 } 2667 2668 return 0; 2669 } 2670 2671 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2672 { 2673 struct pci_dev *pdev = to_pci_dev(dev); 2674 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2675 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2676 int ret, i; 2677 2678 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2679 pm_runtime_forbid(dev); 2680 return -EBUSY; 2681 } 2682 2683 ret = amdgpu_runtime_idle_check_display(dev); 2684 if (ret) 2685 return ret; 2686 2687 /* wait for all rings to drain before suspending */ 2688 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2689 struct amdgpu_ring *ring = adev->rings[i]; 2690 2691 if (ring && ring->sched.ready) { 2692 ret = amdgpu_fence_wait_empty(ring); 2693 if (ret) 2694 return -EBUSY; 2695 } 2696 } 2697 2698 adev->in_runpm = true; 2699 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2700 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2701 2702 /* 2703 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2704 * proper cleanups and put itself into a state ready for PNP. That 2705 * can address some random resuming failure observed on BOCO capable 2706 * platforms. 2707 * TODO: this may be also needed for PX capable platform. 2708 */ 2709 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2710 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2711 2712 ret = amdgpu_device_prepare(drm_dev); 2713 if (ret) 2714 return ret; 2715 ret = amdgpu_device_suspend(drm_dev, false); 2716 if (ret) { 2717 adev->in_runpm = false; 2718 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2719 adev->mp1_state = PP_MP1_STATE_NONE; 2720 return ret; 2721 } 2722 2723 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2724 adev->mp1_state = PP_MP1_STATE_NONE; 2725 2726 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) { 2727 /* Only need to handle PCI state in the driver for ATPX 2728 * PCI core handles it for _PR3. 2729 */ 2730 amdgpu_device_cache_pci_state(pdev); 2731 pci_disable_device(pdev); 2732 pci_ignore_hotplug(pdev); 2733 pci_set_power_state(pdev, PCI_D3cold); 2734 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2735 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) { 2736 /* nothing to do */ 2737 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2738 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) { 2739 amdgpu_device_baco_enter(drm_dev); 2740 } 2741 2742 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n"); 2743 2744 return 0; 2745 } 2746 2747 static int amdgpu_pmops_runtime_resume(struct device *dev) 2748 { 2749 struct pci_dev *pdev = to_pci_dev(dev); 2750 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2751 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2752 int ret; 2753 2754 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) 2755 return -EINVAL; 2756 2757 /* Avoids registers access if device is physically gone */ 2758 if (!pci_device_is_present(adev->pdev)) 2759 adev->no_hw_access = true; 2760 2761 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) { 2762 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2763 2764 /* Only need to handle PCI state in the driver for ATPX 2765 * PCI core handles it for _PR3. 2766 */ 2767 pci_set_power_state(pdev, PCI_D0); 2768 amdgpu_device_load_pci_state(pdev); 2769 ret = pci_enable_device(pdev); 2770 if (ret) 2771 return ret; 2772 pci_set_master(pdev); 2773 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) { 2774 /* Only need to handle PCI state in the driver for ATPX 2775 * PCI core handles it for _PR3. 2776 */ 2777 pci_set_master(pdev); 2778 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2779 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) { 2780 amdgpu_device_baco_exit(drm_dev); 2781 } 2782 ret = amdgpu_device_resume(drm_dev, false); 2783 if (ret) { 2784 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2785 pci_disable_device(pdev); 2786 return ret; 2787 } 2788 2789 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2790 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2791 adev->in_runpm = false; 2792 return 0; 2793 } 2794 2795 static int amdgpu_pmops_runtime_idle(struct device *dev) 2796 { 2797 struct drm_device *drm_dev = dev_get_drvdata(dev); 2798 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2799 int ret; 2800 2801 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2802 pm_runtime_forbid(dev); 2803 return -EBUSY; 2804 } 2805 2806 ret = amdgpu_runtime_idle_check_display(dev); 2807 2808 pm_runtime_mark_last_busy(dev); 2809 pm_runtime_autosuspend(dev); 2810 return ret; 2811 } 2812 2813 long amdgpu_drm_ioctl(struct file *filp, 2814 unsigned int cmd, unsigned long arg) 2815 { 2816 struct drm_file *file_priv = filp->private_data; 2817 struct drm_device *dev; 2818 long ret; 2819 2820 dev = file_priv->minor->dev; 2821 ret = pm_runtime_get_sync(dev->dev); 2822 if (ret < 0) 2823 goto out; 2824 2825 ret = drm_ioctl(filp, cmd, arg); 2826 2827 pm_runtime_mark_last_busy(dev->dev); 2828 out: 2829 pm_runtime_put_autosuspend(dev->dev); 2830 return ret; 2831 } 2832 2833 static const struct dev_pm_ops amdgpu_pm_ops = { 2834 .prepare = amdgpu_pmops_prepare, 2835 .complete = amdgpu_pmops_complete, 2836 .suspend = amdgpu_pmops_suspend, 2837 .suspend_noirq = amdgpu_pmops_suspend_noirq, 2838 .resume = amdgpu_pmops_resume, 2839 .freeze = amdgpu_pmops_freeze, 2840 .thaw = amdgpu_pmops_thaw, 2841 .poweroff = amdgpu_pmops_poweroff, 2842 .restore = amdgpu_pmops_restore, 2843 .runtime_suspend = amdgpu_pmops_runtime_suspend, 2844 .runtime_resume = amdgpu_pmops_runtime_resume, 2845 .runtime_idle = amdgpu_pmops_runtime_idle, 2846 }; 2847 2848 static int amdgpu_flush(struct file *f, fl_owner_t id) 2849 { 2850 struct drm_file *file_priv = f->private_data; 2851 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2852 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2853 2854 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 2855 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 2856 2857 return timeout >= 0 ? 0 : timeout; 2858 } 2859 2860 static const struct file_operations amdgpu_driver_kms_fops = { 2861 .owner = THIS_MODULE, 2862 .open = drm_open, 2863 .flush = amdgpu_flush, 2864 .release = drm_release, 2865 .unlocked_ioctl = amdgpu_drm_ioctl, 2866 .mmap = drm_gem_mmap, 2867 .poll = drm_poll, 2868 .read = drm_read, 2869 #ifdef CONFIG_COMPAT 2870 .compat_ioctl = amdgpu_kms_compat_ioctl, 2871 #endif 2872 #ifdef CONFIG_PROC_FS 2873 .show_fdinfo = drm_show_fdinfo, 2874 #endif 2875 .fop_flags = FOP_UNSIGNED_OFFSET, 2876 }; 2877 2878 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 2879 { 2880 struct drm_file *file; 2881 2882 if (!filp) 2883 return -EINVAL; 2884 2885 if (filp->f_op != &amdgpu_driver_kms_fops) 2886 return -EINVAL; 2887 2888 file = filp->private_data; 2889 *fpriv = file->driver_priv; 2890 return 0; 2891 } 2892 2893 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 2894 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2895 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2896 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2897 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 2898 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2899 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2900 /* KMS */ 2901 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2902 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2903 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2904 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2905 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2906 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2907 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2908 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2909 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2910 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2911 }; 2912 2913 static const struct drm_driver amdgpu_kms_driver = { 2914 .driver_features = 2915 DRIVER_ATOMIC | 2916 DRIVER_GEM | 2917 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 2918 DRIVER_SYNCOBJ_TIMELINE, 2919 .open = amdgpu_driver_open_kms, 2920 .postclose = amdgpu_driver_postclose_kms, 2921 .ioctls = amdgpu_ioctls_kms, 2922 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2923 .dumb_create = amdgpu_mode_dumb_create, 2924 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2925 DRM_FBDEV_TTM_DRIVER_OPS, 2926 .fops = &amdgpu_driver_kms_fops, 2927 .release = &amdgpu_driver_release_kms, 2928 #ifdef CONFIG_PROC_FS 2929 .show_fdinfo = amdgpu_show_fdinfo, 2930 #endif 2931 2932 .gem_prime_import = amdgpu_gem_prime_import, 2933 2934 .name = DRIVER_NAME, 2935 .desc = DRIVER_DESC, 2936 .major = KMS_DRIVER_MAJOR, 2937 .minor = KMS_DRIVER_MINOR, 2938 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2939 }; 2940 2941 const struct drm_driver amdgpu_partition_driver = { 2942 .driver_features = 2943 DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ | 2944 DRIVER_SYNCOBJ_TIMELINE, 2945 .open = amdgpu_driver_open_kms, 2946 .postclose = amdgpu_driver_postclose_kms, 2947 .ioctls = amdgpu_ioctls_kms, 2948 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2949 .dumb_create = amdgpu_mode_dumb_create, 2950 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2951 DRM_FBDEV_TTM_DRIVER_OPS, 2952 .fops = &amdgpu_driver_kms_fops, 2953 .release = &amdgpu_driver_release_kms, 2954 2955 .gem_prime_import = amdgpu_gem_prime_import, 2956 2957 .name = DRIVER_NAME, 2958 .desc = DRIVER_DESC, 2959 .major = KMS_DRIVER_MAJOR, 2960 .minor = KMS_DRIVER_MINOR, 2961 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2962 }; 2963 2964 static struct pci_error_handlers amdgpu_pci_err_handler = { 2965 .error_detected = amdgpu_pci_error_detected, 2966 .mmio_enabled = amdgpu_pci_mmio_enabled, 2967 .slot_reset = amdgpu_pci_slot_reset, 2968 .resume = amdgpu_pci_resume, 2969 }; 2970 2971 static const struct attribute_group *amdgpu_sysfs_groups[] = { 2972 &amdgpu_vram_mgr_attr_group, 2973 &amdgpu_gtt_mgr_attr_group, 2974 &amdgpu_flash_attr_group, 2975 NULL, 2976 }; 2977 2978 static struct pci_driver amdgpu_kms_pci_driver = { 2979 .name = DRIVER_NAME, 2980 .id_table = pciidlist, 2981 .probe = amdgpu_pci_probe, 2982 .remove = amdgpu_pci_remove, 2983 .shutdown = amdgpu_pci_shutdown, 2984 .driver.pm = &amdgpu_pm_ops, 2985 .err_handler = &amdgpu_pci_err_handler, 2986 .dev_groups = amdgpu_sysfs_groups, 2987 }; 2988 2989 static int __init amdgpu_init(void) 2990 { 2991 int r; 2992 2993 if (drm_firmware_drivers_only()) 2994 return -EINVAL; 2995 2996 r = amdgpu_sync_init(); 2997 if (r) 2998 goto error_sync; 2999 3000 r = amdgpu_fence_slab_init(); 3001 if (r) 3002 goto error_fence; 3003 3004 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 3005 amdgpu_register_atpx_handler(); 3006 amdgpu_acpi_detect(); 3007 3008 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 3009 amdgpu_amdkfd_init(); 3010 3011 if (amdgpu_pp_feature_mask & PP_OVERDRIVE_MASK) { 3012 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 3013 pr_crit("Overdrive is enabled, please disable it before " 3014 "reporting any bugs unrelated to overdrive.\n"); 3015 } 3016 3017 /* let modprobe override vga console setting */ 3018 return pci_register_driver(&amdgpu_kms_pci_driver); 3019 3020 error_fence: 3021 amdgpu_sync_fini(); 3022 3023 error_sync: 3024 return r; 3025 } 3026 3027 static void __exit amdgpu_exit(void) 3028 { 3029 amdgpu_amdkfd_fini(); 3030 pci_unregister_driver(&amdgpu_kms_pci_driver); 3031 amdgpu_unregister_atpx_handler(); 3032 amdgpu_acpi_release(); 3033 amdgpu_sync_fini(); 3034 amdgpu_fence_slab_fini(); 3035 mmu_notifier_synchronize(); 3036 amdgpu_xcp_drv_release(); 3037 } 3038 3039 module_init(amdgpu_init); 3040 module_exit(amdgpu_exit); 3041 3042 MODULE_AUTHOR(DRIVER_AUTHOR); 3043 MODULE_DESCRIPTION(DRIVER_DESC); 3044 MODULE_LICENSE("GPL and additional rights"); 3045