1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_drv.h> 27 #include <drm/drm_gem.h> 28 #include <drm/drm_vblank.h> 29 #include "amdgpu_drv.h" 30 31 #include <drm/drm_pciids.h> 32 #include <linux/console.h> 33 #include <linux/module.h> 34 #include <linux/pci.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/vga_switcheroo.h> 37 #include <drm/drm_probe_helper.h> 38 #include <linux/mmu_notifier.h> 39 40 #include "amdgpu.h" 41 #include "amdgpu_irq.h" 42 #include "amdgpu_dma_buf.h" 43 44 #include "amdgpu_amdkfd.h" 45 46 #include "amdgpu_ras.h" 47 48 /* 49 * KMS wrapper. 50 * - 3.0.0 - initial driver 51 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 52 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 53 * at the end of IBs. 54 * - 3.3.0 - Add VM support for UVD on supported hardware. 55 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 56 * - 3.5.0 - Add support for new UVD_NO_OP register. 57 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 58 * - 3.7.0 - Add support for VCE clock list packet 59 * - 3.8.0 - Add support raster config init in the kernel 60 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 61 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 62 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 63 * - 3.12.0 - Add query for double offchip LDS buffers 64 * - 3.13.0 - Add PRT support 65 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 66 * - 3.15.0 - Export more gpu info for gfx9 67 * - 3.16.0 - Add reserved vmid support 68 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 69 * - 3.18.0 - Export gpu always on cu bitmap 70 * - 3.19.0 - Add support for UVD MJPEG decode 71 * - 3.20.0 - Add support for local BOs 72 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 73 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 74 * - 3.23.0 - Add query for VRAM lost counter 75 * - 3.24.0 - Add high priority compute support for gfx9 76 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 77 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 78 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation. 79 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 80 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 81 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 82 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 83 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 84 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 85 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 86 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 87 * - 3.36.0 - Allow reading more status registers on si/cik 88 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 89 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 90 */ 91 #define KMS_DRIVER_MAJOR 3 92 #define KMS_DRIVER_MINOR 38 93 #define KMS_DRIVER_PATCHLEVEL 0 94 95 int amdgpu_vram_limit = 0; 96 int amdgpu_vis_vram_limit = 0; 97 int amdgpu_gart_size = -1; /* auto */ 98 int amdgpu_gtt_size = -1; /* auto */ 99 int amdgpu_moverate = -1; /* auto */ 100 int amdgpu_benchmarking = 0; 101 int amdgpu_testing = 0; 102 int amdgpu_audio = -1; 103 int amdgpu_disp_priority = 0; 104 int amdgpu_hw_i2c = 0; 105 int amdgpu_pcie_gen2 = -1; 106 int amdgpu_msi = -1; 107 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 108 int amdgpu_dpm = -1; 109 int amdgpu_fw_load_type = -1; 110 int amdgpu_aspm = -1; 111 int amdgpu_runtime_pm = -1; 112 uint amdgpu_ip_block_mask = 0xffffffff; 113 int amdgpu_bapm = -1; 114 int amdgpu_deep_color = 0; 115 int amdgpu_vm_size = -1; 116 int amdgpu_vm_fragment_size = -1; 117 int amdgpu_vm_block_size = -1; 118 int amdgpu_vm_fault_stop = 0; 119 int amdgpu_vm_debug = 0; 120 int amdgpu_vm_update_mode = -1; 121 int amdgpu_exp_hw_support = 0; 122 int amdgpu_dc = -1; 123 int amdgpu_sched_jobs = 32; 124 int amdgpu_sched_hw_submission = 2; 125 uint amdgpu_pcie_gen_cap = 0; 126 uint amdgpu_pcie_lane_cap = 0; 127 uint amdgpu_cg_mask = 0xffffffff; 128 uint amdgpu_pg_mask = 0xffffffff; 129 uint amdgpu_sdma_phase_quantum = 32; 130 char *amdgpu_disable_cu = NULL; 131 char *amdgpu_virtual_display = NULL; 132 /* OverDrive(bit 14) disabled by default*/ 133 uint amdgpu_pp_feature_mask = 0xffffbfff; 134 uint amdgpu_force_long_training = 0; 135 int amdgpu_job_hang_limit = 0; 136 int amdgpu_lbpw = -1; 137 int amdgpu_compute_multipipe = -1; 138 int amdgpu_gpu_recovery = -1; /* auto */ 139 int amdgpu_emu_mode = 0; 140 uint amdgpu_smu_memory_pool_size = 0; 141 /* FBC (bit 0) disabled by default*/ 142 uint amdgpu_dc_feature_mask = 0; 143 uint amdgpu_dc_debug_mask = 0; 144 int amdgpu_async_gfx_ring = 1; 145 int amdgpu_mcbp = 0; 146 int amdgpu_discovery = -1; 147 int amdgpu_mes = 0; 148 int amdgpu_noretry; 149 int amdgpu_force_asic_type = -1; 150 int amdgpu_tmz = 0; 151 152 struct amdgpu_mgpu_info mgpu_info = { 153 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 154 }; 155 int amdgpu_ras_enable = -1; 156 uint amdgpu_ras_mask = 0xffffffff; 157 158 /** 159 * DOC: vramlimit (int) 160 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 161 */ 162 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 163 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 164 165 /** 166 * DOC: vis_vramlimit (int) 167 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 168 */ 169 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 170 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 171 172 /** 173 * DOC: gartsize (uint) 174 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic). 175 */ 176 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); 177 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 178 179 /** 180 * DOC: gttsize (int) 181 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM, 182 * otherwise 3/4 RAM size). 183 */ 184 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); 185 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 186 187 /** 188 * DOC: moverate (int) 189 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 190 */ 191 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 192 module_param_named(moverate, amdgpu_moverate, int, 0600); 193 194 /** 195 * DOC: benchmark (int) 196 * Run benchmarks. The default is 0 (Skip benchmarks). 197 */ 198 MODULE_PARM_DESC(benchmark, "Run benchmark"); 199 module_param_named(benchmark, amdgpu_benchmarking, int, 0444); 200 201 /** 202 * DOC: test (int) 203 * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test). 204 */ 205 MODULE_PARM_DESC(test, "Run tests"); 206 module_param_named(test, amdgpu_testing, int, 0444); 207 208 /** 209 * DOC: audio (int) 210 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 211 */ 212 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 213 module_param_named(audio, amdgpu_audio, int, 0444); 214 215 /** 216 * DOC: disp_priority (int) 217 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 218 */ 219 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 220 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 221 222 /** 223 * DOC: hw_i2c (int) 224 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 225 */ 226 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 227 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 228 229 /** 230 * DOC: pcie_gen2 (int) 231 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 232 */ 233 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 234 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 235 236 /** 237 * DOC: msi (int) 238 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 239 */ 240 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 241 module_param_named(msi, amdgpu_msi, int, 0444); 242 243 /** 244 * DOC: lockup_timeout (string) 245 * Set GPU scheduler timeout value in ms. 246 * 247 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 248 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 249 * to the default timeout. 250 * 251 * - With one value specified, the setting will apply to all non-compute jobs. 252 * - With multiple values specified, the first one will be for GFX. 253 * The second one is for Compute. The third and fourth ones are 254 * for SDMA and Video. 255 * 256 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 257 * jobs is 10000. And there is no timeout enforced on compute jobs. 258 */ 259 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and infinity timeout for compute jobs; " 260 "for passthrough or sriov, 10000 for all jobs." 261 " 0: keep default value. negative: infinity timeout), " 262 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 263 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 264 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 265 266 /** 267 * DOC: dpm (int) 268 * Override for dynamic power management setting 269 * (0 = disable, 1 = enable, 2 = enable sw smu driver for vega20) 270 * The default is -1 (auto). 271 */ 272 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 273 module_param_named(dpm, amdgpu_dpm, int, 0444); 274 275 /** 276 * DOC: fw_load_type (int) 277 * Set different firmware loading type for debugging (0 = direct, 1 = SMU, 2 = PSP). The default is -1 (auto). 278 */ 279 MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)"); 280 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 281 282 /** 283 * DOC: aspm (int) 284 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 285 */ 286 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 287 module_param_named(aspm, amdgpu_aspm, int, 0444); 288 289 /** 290 * DOC: runpm (int) 291 * Override for runtime power management control for dGPUs in PX/HG laptops. The amdgpu driver can dynamically power down 292 * the dGPU on PX/HG laptops when it is idle. The default is -1 (auto enable). Setting the value to 0 disables this functionality. 293 */ 294 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 295 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 296 297 /** 298 * DOC: ip_block_mask (uint) 299 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 300 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 301 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 302 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 303 */ 304 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 305 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 306 307 /** 308 * DOC: bapm (int) 309 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 310 * The default -1 (auto, enabled) 311 */ 312 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 313 module_param_named(bapm, amdgpu_bapm, int, 0444); 314 315 /** 316 * DOC: deep_color (int) 317 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 318 */ 319 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 320 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 321 322 /** 323 * DOC: vm_size (int) 324 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 325 */ 326 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 327 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 328 329 /** 330 * DOC: vm_fragment_size (int) 331 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 332 */ 333 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 334 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 335 336 /** 337 * DOC: vm_block_size (int) 338 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 339 */ 340 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 341 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 342 343 /** 344 * DOC: vm_fault_stop (int) 345 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 346 */ 347 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 348 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 349 350 /** 351 * DOC: vm_debug (int) 352 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 353 */ 354 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 355 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 356 357 /** 358 * DOC: vm_update_mode (int) 359 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 360 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 361 */ 362 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 363 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 364 365 /** 366 * DOC: exp_hw_support (int) 367 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 368 */ 369 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 370 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 371 372 /** 373 * DOC: dc (int) 374 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 375 */ 376 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 377 module_param_named(dc, amdgpu_dc, int, 0444); 378 379 /** 380 * DOC: sched_jobs (int) 381 * Override the max number of jobs supported in the sw queue. The default is 32. 382 */ 383 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 384 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 385 386 /** 387 * DOC: sched_hw_submission (int) 388 * Override the max number of HW submissions. The default is 2. 389 */ 390 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 391 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 392 393 /** 394 * DOC: ppfeaturemask (uint) 395 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 396 * The default is the current set of stable power features. 397 */ 398 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 399 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, uint, 0444); 400 401 /** 402 * DOC: forcelongtraining (uint) 403 * Force long memory training in resume. 404 * The default is zero, indicates short training in resume. 405 */ 406 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 407 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 408 409 /** 410 * DOC: pcie_gen_cap (uint) 411 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 412 * The default is 0 (automatic for each asic). 413 */ 414 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 415 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 416 417 /** 418 * DOC: pcie_lane_cap (uint) 419 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 420 * The default is 0 (automatic for each asic). 421 */ 422 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 423 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 424 425 /** 426 * DOC: cg_mask (uint) 427 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 428 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 429 */ 430 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 431 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); 432 433 /** 434 * DOC: pg_mask (uint) 435 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 436 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 437 */ 438 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 439 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 440 441 /** 442 * DOC: sdma_phase_quantum (uint) 443 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 444 */ 445 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 446 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 447 448 /** 449 * DOC: disable_cu (charp) 450 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 451 */ 452 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 453 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 454 455 /** 456 * DOC: virtual_display (charp) 457 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 458 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 459 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 460 * device at 26:00.0. The default is NULL. 461 */ 462 MODULE_PARM_DESC(virtual_display, 463 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 464 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 465 466 /** 467 * DOC: job_hang_limit (int) 468 * Set how much time allow a job hang and not drop it. The default is 0. 469 */ 470 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 471 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 472 473 /** 474 * DOC: lbpw (int) 475 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 476 */ 477 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 478 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 479 480 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 481 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 482 483 /** 484 * DOC: gpu_recovery (int) 485 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 486 */ 487 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 488 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 489 490 /** 491 * DOC: emu_mode (int) 492 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 493 */ 494 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 495 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 496 497 /** 498 * DOC: ras_enable (int) 499 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 500 */ 501 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 502 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 503 504 /** 505 * DOC: ras_mask (uint) 506 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 507 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 508 */ 509 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 510 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 511 512 /** 513 * DOC: si_support (int) 514 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 515 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 516 * otherwise using amdgpu driver. 517 */ 518 #ifdef CONFIG_DRM_AMDGPU_SI 519 520 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 521 int amdgpu_si_support = 0; 522 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 523 #else 524 int amdgpu_si_support = 1; 525 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 526 #endif 527 528 module_param_named(si_support, amdgpu_si_support, int, 0444); 529 #endif 530 531 /** 532 * DOC: cik_support (int) 533 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 534 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 535 * otherwise using amdgpu driver. 536 */ 537 #ifdef CONFIG_DRM_AMDGPU_CIK 538 539 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 540 int amdgpu_cik_support = 0; 541 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 542 #else 543 int amdgpu_cik_support = 1; 544 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 545 #endif 546 547 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 548 #endif 549 550 /** 551 * DOC: smu_memory_pool_size (uint) 552 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 553 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 554 */ 555 MODULE_PARM_DESC(smu_memory_pool_size, 556 "reserve gtt for smu debug usage, 0 = disable," 557 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 558 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 559 560 /** 561 * DOC: async_gfx_ring (int) 562 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 563 */ 564 MODULE_PARM_DESC(async_gfx_ring, 565 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 566 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 567 568 /** 569 * DOC: mcbp (int) 570 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled) 571 */ 572 MODULE_PARM_DESC(mcbp, 573 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); 574 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 575 576 /** 577 * DOC: discovery (int) 578 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 579 * (-1 = auto (default), 0 = disabled, 1 = enabled) 580 */ 581 MODULE_PARM_DESC(discovery, 582 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 583 module_param_named(discovery, amdgpu_discovery, int, 0444); 584 585 /** 586 * DOC: mes (int) 587 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 588 * (0 = disabled (default), 1 = enabled) 589 */ 590 MODULE_PARM_DESC(mes, 591 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 592 module_param_named(mes, amdgpu_mes, int, 0444); 593 594 MODULE_PARM_DESC(noretry, 595 "Disable retry faults (0 = retry enabled (default), 1 = retry disabled)"); 596 module_param_named(noretry, amdgpu_noretry, int, 0644); 597 598 /** 599 * DOC: force_asic_type (int) 600 * A non negative value used to specify the asic type for all supported GPUs. 601 */ 602 MODULE_PARM_DESC(force_asic_type, 603 "A non negative value used to specify the asic type for all supported GPUs"); 604 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 605 606 607 608 #ifdef CONFIG_HSA_AMD 609 /** 610 * DOC: sched_policy (int) 611 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 612 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 613 * assigns queues to HQDs. 614 */ 615 int sched_policy = KFD_SCHED_POLICY_HWS; 616 module_param(sched_policy, int, 0444); 617 MODULE_PARM_DESC(sched_policy, 618 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 619 620 /** 621 * DOC: hws_max_conc_proc (int) 622 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 623 * number of VMIDs assigned to the HWS, which is also the default. 624 */ 625 int hws_max_conc_proc = 8; 626 module_param(hws_max_conc_proc, int, 0444); 627 MODULE_PARM_DESC(hws_max_conc_proc, 628 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 629 630 /** 631 * DOC: cwsr_enable (int) 632 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 633 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 634 * disables it. 635 */ 636 int cwsr_enable = 1; 637 module_param(cwsr_enable, int, 0444); 638 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 639 640 /** 641 * DOC: max_num_of_queues_per_device (int) 642 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 643 * is 4096. 644 */ 645 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 646 module_param(max_num_of_queues_per_device, int, 0444); 647 MODULE_PARM_DESC(max_num_of_queues_per_device, 648 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 649 650 /** 651 * DOC: send_sigterm (int) 652 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 653 * but just print errors on dmesg. Setting 1 enables sending sigterm. 654 */ 655 int send_sigterm; 656 module_param(send_sigterm, int, 0444); 657 MODULE_PARM_DESC(send_sigterm, 658 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 659 660 /** 661 * DOC: debug_largebar (int) 662 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 663 * system. This limits the VRAM size reported to ROCm applications to the visible 664 * size, usually 256MB. 665 * Default value is 0, diabled. 666 */ 667 int debug_largebar; 668 module_param(debug_largebar, int, 0444); 669 MODULE_PARM_DESC(debug_largebar, 670 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 671 672 /** 673 * DOC: ignore_crat (int) 674 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 675 * table to get information about AMD APUs. This option can serve as a workaround on 676 * systems with a broken CRAT table. 677 */ 678 int ignore_crat; 679 module_param(ignore_crat, int, 0444); 680 MODULE_PARM_DESC(ignore_crat, 681 "Ignore CRAT table during KFD initialization (0 = use CRAT (default), 1 = ignore CRAT)"); 682 683 /** 684 * DOC: halt_if_hws_hang (int) 685 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 686 * Setting 1 enables halt on hang. 687 */ 688 int halt_if_hws_hang; 689 module_param(halt_if_hws_hang, int, 0644); 690 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 691 692 /** 693 * DOC: hws_gws_support(bool) 694 * Assume that HWS supports GWS barriers regardless of what firmware version 695 * check says. Default value: false (rely on MEC2 firmware version check). 696 */ 697 bool hws_gws_support; 698 module_param(hws_gws_support, bool, 0444); 699 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 700 701 /** 702 * DOC: queue_preemption_timeout_ms (int) 703 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 704 */ 705 int queue_preemption_timeout_ms = 9000; 706 module_param(queue_preemption_timeout_ms, int, 0644); 707 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 708 #endif 709 710 /** 711 * DOC: dcfeaturemask (uint) 712 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 713 * The default is the current set of stable display features. 714 */ 715 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 716 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 717 718 /** 719 * DOC: dcdebugmask (uint) 720 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 721 */ 722 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 723 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 724 725 /** 726 * DOC: abmlevel (uint) 727 * Override the default ABM (Adaptive Backlight Management) level used for DC 728 * enabled hardware. Requires DMCU to be supported and loaded. 729 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 730 * default. Values 1-4 control the maximum allowable brightness reduction via 731 * the ABM algorithm, with 1 being the least reduction and 4 being the most 732 * reduction. 733 * 734 * Defaults to 0, or disabled. Userspace can still override this level later 735 * after boot. 736 */ 737 uint amdgpu_dm_abm_level = 0; 738 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 739 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 740 741 /** 742 * DOC: tmz (int) 743 * Trusted Memory Zone (TMZ) is a method to protect data being written 744 * to or read from memory. 745 * 746 * The default value: 0 (off). TODO: change to auto till it is completed. 747 */ 748 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto, 0 = off (default), 1 = on)"); 749 module_param_named(tmz, amdgpu_tmz, int, 0444); 750 751 static const struct pci_device_id pciidlist[] = { 752 #ifdef CONFIG_DRM_AMDGPU_SI 753 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 754 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 755 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 756 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 757 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 758 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 759 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 760 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 761 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 762 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 763 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 764 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 765 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 766 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 767 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 768 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 769 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 770 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 771 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 772 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 773 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 774 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 775 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 776 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 777 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 778 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 779 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 780 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 781 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 782 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 783 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 784 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 785 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 786 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 787 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 788 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 789 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 790 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 791 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 792 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 793 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 794 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 795 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 796 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 797 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 798 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 799 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 800 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 801 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 802 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 803 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 804 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 805 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 806 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 807 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 808 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 809 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 810 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 811 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 812 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 813 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 814 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 815 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 816 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 817 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 818 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 819 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 820 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 821 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 822 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 823 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 824 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 825 #endif 826 #ifdef CONFIG_DRM_AMDGPU_CIK 827 /* Kaveri */ 828 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 829 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 830 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 831 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 832 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 833 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 834 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 835 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 836 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 837 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 838 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 839 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 840 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 841 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 842 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 843 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 844 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 845 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 846 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 847 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 848 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 849 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 850 /* Bonaire */ 851 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 852 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 853 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 854 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 855 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 856 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 857 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 858 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 859 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 860 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 861 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 862 /* Hawaii */ 863 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 864 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 865 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 866 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 867 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 868 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 869 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 870 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 871 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 872 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 873 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 874 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 875 /* Kabini */ 876 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 877 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 878 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 879 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 880 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 881 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 882 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 883 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 884 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 885 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 886 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 887 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 888 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 889 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 890 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 891 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 892 /* mullins */ 893 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 894 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 895 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 896 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 897 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 898 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 899 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 900 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 901 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 902 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 903 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 904 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 905 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 906 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 907 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 908 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 909 #endif 910 /* topaz */ 911 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 912 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 913 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 914 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 915 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 916 /* tonga */ 917 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 918 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 919 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 920 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 921 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 922 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 923 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 924 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 925 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 926 /* fiji */ 927 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 928 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 929 /* carrizo */ 930 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 931 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 932 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 933 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 934 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 935 /* stoney */ 936 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 937 /* Polaris11 */ 938 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 939 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 940 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 941 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 942 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 943 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 944 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 945 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 946 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 947 /* Polaris10 */ 948 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 949 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 950 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 951 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 952 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 953 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 954 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 955 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 956 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 957 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 958 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 959 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 960 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 961 /* Polaris12 */ 962 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 963 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 964 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 965 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 966 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 967 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 968 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 969 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 970 /* VEGAM */ 971 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 972 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 973 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 974 /* Vega 10 */ 975 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 976 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 977 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 978 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 979 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 980 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 981 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 982 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 983 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 984 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 985 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 986 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 987 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 988 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 989 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 990 /* Vega 12 */ 991 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 992 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 993 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 994 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 995 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 996 /* Vega 20 */ 997 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 998 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 999 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1000 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1001 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1002 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1003 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1004 /* Raven */ 1005 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1006 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1007 /* Arcturus */ 1008 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT}, 1009 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT}, 1010 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT}, 1011 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT}, 1012 /* Navi10 */ 1013 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1014 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1015 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1016 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1017 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1018 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1019 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1020 /* Navi14 */ 1021 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1022 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1023 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1024 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1025 1026 /* Renoir */ 1027 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1028 1029 /* Navi12 */ 1030 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12|AMD_EXP_HW_SUPPORT}, 1031 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12|AMD_EXP_HW_SUPPORT}, 1032 1033 {0, 0, 0} 1034 }; 1035 1036 MODULE_DEVICE_TABLE(pci, pciidlist); 1037 1038 static struct drm_driver kms_driver; 1039 1040 static int amdgpu_pci_probe(struct pci_dev *pdev, 1041 const struct pci_device_id *ent) 1042 { 1043 struct drm_device *dev; 1044 struct amdgpu_device *adev; 1045 unsigned long flags = ent->driver_data; 1046 int ret, retry = 0; 1047 bool supports_atomic = false; 1048 1049 if (!amdgpu_virtual_display && 1050 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 1051 supports_atomic = true; 1052 1053 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 1054 DRM_INFO("This hardware requires experimental hardware support.\n" 1055 "See modparam exp_hw_support\n"); 1056 return -ENODEV; 1057 } 1058 1059 #ifdef CONFIG_DRM_AMDGPU_SI 1060 if (!amdgpu_si_support) { 1061 switch (flags & AMD_ASIC_MASK) { 1062 case CHIP_TAHITI: 1063 case CHIP_PITCAIRN: 1064 case CHIP_VERDE: 1065 case CHIP_OLAND: 1066 case CHIP_HAINAN: 1067 dev_info(&pdev->dev, 1068 "SI support provided by radeon.\n"); 1069 dev_info(&pdev->dev, 1070 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 1071 ); 1072 return -ENODEV; 1073 } 1074 } 1075 #endif 1076 #ifdef CONFIG_DRM_AMDGPU_CIK 1077 if (!amdgpu_cik_support) { 1078 switch (flags & AMD_ASIC_MASK) { 1079 case CHIP_KAVERI: 1080 case CHIP_BONAIRE: 1081 case CHIP_HAWAII: 1082 case CHIP_KABINI: 1083 case CHIP_MULLINS: 1084 dev_info(&pdev->dev, 1085 "CIK support provided by radeon.\n"); 1086 dev_info(&pdev->dev, 1087 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 1088 ); 1089 return -ENODEV; 1090 } 1091 } 1092 #endif 1093 1094 /* Get rid of things like offb */ 1095 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "amdgpudrmfb"); 1096 if (ret) 1097 return ret; 1098 1099 dev = drm_dev_alloc(&kms_driver, &pdev->dev); 1100 if (IS_ERR(dev)) 1101 return PTR_ERR(dev); 1102 1103 if (!supports_atomic) 1104 dev->driver_features &= ~DRIVER_ATOMIC; 1105 1106 ret = pci_enable_device(pdev); 1107 if (ret) 1108 goto err_free; 1109 1110 dev->pdev = pdev; 1111 1112 pci_set_drvdata(pdev, dev); 1113 1114 amdgpu_driver_load_kms(dev, ent->driver_data); 1115 1116 retry_init: 1117 ret = drm_dev_register(dev, ent->driver_data); 1118 if (ret == -EAGAIN && ++retry <= 3) { 1119 DRM_INFO("retry init %d\n", retry); 1120 /* Don't request EX mode too frequently which is attacking */ 1121 msleep(5000); 1122 goto retry_init; 1123 } else if (ret) 1124 goto err_pci; 1125 1126 adev = dev->dev_private; 1127 ret = amdgpu_debugfs_init(adev); 1128 if (ret) 1129 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 1130 1131 return 0; 1132 1133 err_pci: 1134 pci_disable_device(pdev); 1135 err_free: 1136 drm_dev_put(dev); 1137 return ret; 1138 } 1139 1140 static void 1141 amdgpu_pci_remove(struct pci_dev *pdev) 1142 { 1143 struct drm_device *dev = pci_get_drvdata(pdev); 1144 1145 #ifdef MODULE 1146 if (THIS_MODULE->state != MODULE_STATE_GOING) 1147 #endif 1148 DRM_ERROR("Hotplug removal is not supported\n"); 1149 drm_dev_unplug(dev); 1150 amdgpu_driver_unload_kms(dev); 1151 pci_disable_device(pdev); 1152 pci_set_drvdata(pdev, NULL); 1153 drm_dev_put(dev); 1154 } 1155 1156 static void 1157 amdgpu_pci_shutdown(struct pci_dev *pdev) 1158 { 1159 struct drm_device *dev = pci_get_drvdata(pdev); 1160 struct amdgpu_device *adev = dev->dev_private; 1161 1162 if (amdgpu_ras_intr_triggered()) 1163 return; 1164 1165 /* if we are running in a VM, make sure the device 1166 * torn down properly on reboot/shutdown. 1167 * unfortunately we can't detect certain 1168 * hypervisors so just do this all the time. 1169 */ 1170 adev->mp1_state = PP_MP1_STATE_UNLOAD; 1171 amdgpu_device_ip_suspend(adev); 1172 adev->mp1_state = PP_MP1_STATE_NONE; 1173 } 1174 1175 static int amdgpu_pmops_suspend(struct device *dev) 1176 { 1177 struct drm_device *drm_dev = dev_get_drvdata(dev); 1178 1179 return amdgpu_device_suspend(drm_dev, true); 1180 } 1181 1182 static int amdgpu_pmops_resume(struct device *dev) 1183 { 1184 struct drm_device *drm_dev = dev_get_drvdata(dev); 1185 1186 return amdgpu_device_resume(drm_dev, true); 1187 } 1188 1189 static int amdgpu_pmops_freeze(struct device *dev) 1190 { 1191 struct drm_device *drm_dev = dev_get_drvdata(dev); 1192 struct amdgpu_device *adev = drm_dev->dev_private; 1193 int r; 1194 1195 adev->in_hibernate = true; 1196 r = amdgpu_device_suspend(drm_dev, true); 1197 adev->in_hibernate = false; 1198 if (r) 1199 return r; 1200 return amdgpu_asic_reset(adev); 1201 } 1202 1203 static int amdgpu_pmops_thaw(struct device *dev) 1204 { 1205 struct drm_device *drm_dev = dev_get_drvdata(dev); 1206 1207 return amdgpu_device_resume(drm_dev, true); 1208 } 1209 1210 static int amdgpu_pmops_poweroff(struct device *dev) 1211 { 1212 struct drm_device *drm_dev = dev_get_drvdata(dev); 1213 1214 return amdgpu_device_suspend(drm_dev, true); 1215 } 1216 1217 static int amdgpu_pmops_restore(struct device *dev) 1218 { 1219 struct drm_device *drm_dev = dev_get_drvdata(dev); 1220 1221 return amdgpu_device_resume(drm_dev, true); 1222 } 1223 1224 static int amdgpu_pmops_runtime_suspend(struct device *dev) 1225 { 1226 struct pci_dev *pdev = to_pci_dev(dev); 1227 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1228 struct amdgpu_device *adev = drm_dev->dev_private; 1229 int ret, i; 1230 1231 if (!adev->runpm) { 1232 pm_runtime_forbid(dev); 1233 return -EBUSY; 1234 } 1235 1236 /* wait for all rings to drain before suspending */ 1237 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 1238 struct amdgpu_ring *ring = adev->rings[i]; 1239 if (ring && ring->sched.ready) { 1240 ret = amdgpu_fence_wait_empty(ring); 1241 if (ret) 1242 return -EBUSY; 1243 } 1244 } 1245 1246 adev->in_runpm = true; 1247 if (amdgpu_device_supports_boco(drm_dev)) 1248 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1249 drm_kms_helper_poll_disable(drm_dev); 1250 1251 ret = amdgpu_device_suspend(drm_dev, false); 1252 if (ret) 1253 return ret; 1254 1255 if (amdgpu_device_supports_boco(drm_dev)) { 1256 /* Only need to handle PCI state in the driver for ATPX 1257 * PCI core handles it for _PR3. 1258 */ 1259 if (amdgpu_is_atpx_hybrid()) { 1260 pci_ignore_hotplug(pdev); 1261 } else { 1262 pci_save_state(pdev); 1263 pci_disable_device(pdev); 1264 pci_ignore_hotplug(pdev); 1265 pci_set_power_state(pdev, PCI_D3cold); 1266 } 1267 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 1268 } else if (amdgpu_device_supports_baco(drm_dev)) { 1269 amdgpu_device_baco_enter(drm_dev); 1270 } 1271 1272 return 0; 1273 } 1274 1275 static int amdgpu_pmops_runtime_resume(struct device *dev) 1276 { 1277 struct pci_dev *pdev = to_pci_dev(dev); 1278 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1279 struct amdgpu_device *adev = drm_dev->dev_private; 1280 int ret; 1281 1282 if (!adev->runpm) 1283 return -EINVAL; 1284 1285 if (amdgpu_device_supports_boco(drm_dev)) { 1286 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1287 1288 /* Only need to handle PCI state in the driver for ATPX 1289 * PCI core handles it for _PR3. 1290 */ 1291 if (amdgpu_is_atpx_hybrid()) { 1292 pci_set_master(pdev); 1293 } else { 1294 pci_set_power_state(pdev, PCI_D0); 1295 pci_restore_state(pdev); 1296 ret = pci_enable_device(pdev); 1297 if (ret) 1298 return ret; 1299 pci_set_master(pdev); 1300 } 1301 } else if (amdgpu_device_supports_baco(drm_dev)) { 1302 amdgpu_device_baco_exit(drm_dev); 1303 } 1304 ret = amdgpu_device_resume(drm_dev, false); 1305 drm_kms_helper_poll_enable(drm_dev); 1306 if (amdgpu_device_supports_boco(drm_dev)) 1307 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 1308 adev->in_runpm = false; 1309 return 0; 1310 } 1311 1312 static int amdgpu_pmops_runtime_idle(struct device *dev) 1313 { 1314 struct drm_device *drm_dev = dev_get_drvdata(dev); 1315 struct amdgpu_device *adev = drm_dev->dev_private; 1316 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 1317 int ret = 1; 1318 1319 if (!adev->runpm) { 1320 pm_runtime_forbid(dev); 1321 return -EBUSY; 1322 } 1323 1324 if (amdgpu_device_has_dc_support(adev)) { 1325 struct drm_crtc *crtc; 1326 1327 drm_modeset_lock_all(drm_dev); 1328 1329 drm_for_each_crtc(crtc, drm_dev) { 1330 if (crtc->state->active) { 1331 ret = -EBUSY; 1332 break; 1333 } 1334 } 1335 1336 drm_modeset_unlock_all(drm_dev); 1337 1338 } else { 1339 struct drm_connector *list_connector; 1340 struct drm_connector_list_iter iter; 1341 1342 mutex_lock(&drm_dev->mode_config.mutex); 1343 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 1344 1345 drm_connector_list_iter_begin(drm_dev, &iter); 1346 drm_for_each_connector_iter(list_connector, &iter) { 1347 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 1348 ret = -EBUSY; 1349 break; 1350 } 1351 } 1352 1353 drm_connector_list_iter_end(&iter); 1354 1355 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 1356 mutex_unlock(&drm_dev->mode_config.mutex); 1357 } 1358 1359 if (ret == -EBUSY) 1360 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 1361 1362 pm_runtime_mark_last_busy(dev); 1363 pm_runtime_autosuspend(dev); 1364 return ret; 1365 } 1366 1367 long amdgpu_drm_ioctl(struct file *filp, 1368 unsigned int cmd, unsigned long arg) 1369 { 1370 struct drm_file *file_priv = filp->private_data; 1371 struct drm_device *dev; 1372 long ret; 1373 dev = file_priv->minor->dev; 1374 ret = pm_runtime_get_sync(dev->dev); 1375 if (ret < 0) 1376 return ret; 1377 1378 ret = drm_ioctl(filp, cmd, arg); 1379 1380 pm_runtime_mark_last_busy(dev->dev); 1381 pm_runtime_put_autosuspend(dev->dev); 1382 return ret; 1383 } 1384 1385 static const struct dev_pm_ops amdgpu_pm_ops = { 1386 .suspend = amdgpu_pmops_suspend, 1387 .resume = amdgpu_pmops_resume, 1388 .freeze = amdgpu_pmops_freeze, 1389 .thaw = amdgpu_pmops_thaw, 1390 .poweroff = amdgpu_pmops_poweroff, 1391 .restore = amdgpu_pmops_restore, 1392 .runtime_suspend = amdgpu_pmops_runtime_suspend, 1393 .runtime_resume = amdgpu_pmops_runtime_resume, 1394 .runtime_idle = amdgpu_pmops_runtime_idle, 1395 }; 1396 1397 static int amdgpu_flush(struct file *f, fl_owner_t id) 1398 { 1399 struct drm_file *file_priv = f->private_data; 1400 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1401 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 1402 1403 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 1404 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 1405 1406 return timeout >= 0 ? 0 : timeout; 1407 } 1408 1409 static const struct file_operations amdgpu_driver_kms_fops = { 1410 .owner = THIS_MODULE, 1411 .open = drm_open, 1412 .flush = amdgpu_flush, 1413 .release = drm_release, 1414 .unlocked_ioctl = amdgpu_drm_ioctl, 1415 .mmap = amdgpu_mmap, 1416 .poll = drm_poll, 1417 .read = drm_read, 1418 #ifdef CONFIG_COMPAT 1419 .compat_ioctl = amdgpu_kms_compat_ioctl, 1420 #endif 1421 }; 1422 1423 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 1424 { 1425 struct drm_file *file; 1426 1427 if (!filp) 1428 return -EINVAL; 1429 1430 if (filp->f_op != &amdgpu_driver_kms_fops) { 1431 return -EINVAL; 1432 } 1433 1434 file = filp->private_data; 1435 *fpriv = file->driver_priv; 1436 return 0; 1437 } 1438 1439 static struct drm_driver kms_driver = { 1440 .driver_features = 1441 DRIVER_ATOMIC | 1442 DRIVER_GEM | 1443 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 1444 DRIVER_SYNCOBJ_TIMELINE, 1445 .open = amdgpu_driver_open_kms, 1446 .postclose = amdgpu_driver_postclose_kms, 1447 .lastclose = amdgpu_driver_lastclose_kms, 1448 .irq_handler = amdgpu_irq_handler, 1449 .ioctls = amdgpu_ioctls_kms, 1450 .gem_free_object_unlocked = amdgpu_gem_object_free, 1451 .gem_open_object = amdgpu_gem_object_open, 1452 .gem_close_object = amdgpu_gem_object_close, 1453 .dumb_create = amdgpu_mode_dumb_create, 1454 .dumb_map_offset = amdgpu_mode_dumb_mmap, 1455 .fops = &amdgpu_driver_kms_fops, 1456 1457 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 1458 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 1459 .gem_prime_export = amdgpu_gem_prime_export, 1460 .gem_prime_import = amdgpu_gem_prime_import, 1461 .gem_prime_vmap = amdgpu_gem_prime_vmap, 1462 .gem_prime_vunmap = amdgpu_gem_prime_vunmap, 1463 .gem_prime_mmap = amdgpu_gem_prime_mmap, 1464 1465 .name = DRIVER_NAME, 1466 .desc = DRIVER_DESC, 1467 .date = DRIVER_DATE, 1468 .major = KMS_DRIVER_MAJOR, 1469 .minor = KMS_DRIVER_MINOR, 1470 .patchlevel = KMS_DRIVER_PATCHLEVEL, 1471 }; 1472 1473 static struct pci_driver amdgpu_kms_pci_driver = { 1474 .name = DRIVER_NAME, 1475 .id_table = pciidlist, 1476 .probe = amdgpu_pci_probe, 1477 .remove = amdgpu_pci_remove, 1478 .shutdown = amdgpu_pci_shutdown, 1479 .driver.pm = &amdgpu_pm_ops, 1480 }; 1481 1482 1483 1484 static int __init amdgpu_init(void) 1485 { 1486 int r; 1487 1488 if (vgacon_text_force()) { 1489 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); 1490 return -EINVAL; 1491 } 1492 1493 r = amdgpu_sync_init(); 1494 if (r) 1495 goto error_sync; 1496 1497 r = amdgpu_fence_slab_init(); 1498 if (r) 1499 goto error_fence; 1500 1501 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 1502 kms_driver.num_ioctls = amdgpu_max_kms_ioctl; 1503 amdgpu_register_atpx_handler(); 1504 1505 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 1506 amdgpu_amdkfd_init(); 1507 1508 /* let modprobe override vga console setting */ 1509 return pci_register_driver(&amdgpu_kms_pci_driver); 1510 1511 error_fence: 1512 amdgpu_sync_fini(); 1513 1514 error_sync: 1515 return r; 1516 } 1517 1518 static void __exit amdgpu_exit(void) 1519 { 1520 amdgpu_amdkfd_fini(); 1521 pci_unregister_driver(&amdgpu_kms_pci_driver); 1522 amdgpu_unregister_atpx_handler(); 1523 amdgpu_sync_fini(); 1524 amdgpu_fence_slab_fini(); 1525 mmu_notifier_synchronize(); 1526 } 1527 1528 module_init(amdgpu_init); 1529 module_exit(amdgpu_exit); 1530 1531 MODULE_AUTHOR(DRIVER_AUTHOR); 1532 MODULE_DESCRIPTION(DRIVER_DESC); 1533 MODULE_LICENSE("GPL and additional rights"); 1534