1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/clients/drm_client_setup.h> 27 #include <drm/drm_drv.h> 28 #include <drm/drm_fbdev_ttm.h> 29 #include <drm/drm_gem.h> 30 #include <drm/drm_managed.h> 31 #include <drm/drm_pciids.h> 32 #include <drm/drm_probe_helper.h> 33 #include <drm/drm_vblank.h> 34 35 #include <linux/cc_platform.h> 36 #include <linux/dynamic_debug.h> 37 #include <linux/module.h> 38 #include <linux/mmu_notifier.h> 39 #include <linux/pm_runtime.h> 40 #include <linux/suspend.h> 41 #include <linux/vga_switcheroo.h> 42 43 #include "amdgpu.h" 44 #include "amdgpu_amdkfd.h" 45 #include "amdgpu_dma_buf.h" 46 #include "amdgpu_drv.h" 47 #include "amdgpu_fdinfo.h" 48 #include "amdgpu_irq.h" 49 #include "amdgpu_psp.h" 50 #include "amdgpu_ras.h" 51 #include "amdgpu_reset.h" 52 #include "amdgpu_sched.h" 53 #include "amdgpu_xgmi.h" 54 #include "amdgpu_userq.h" 55 #include "amdgpu_userq_fence.h" 56 #include "../amdxcp/amdgpu_xcp_drv.h" 57 58 /* 59 * KMS wrapper. 60 * - 3.0.0 - initial driver 61 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 62 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 63 * at the end of IBs. 64 * - 3.3.0 - Add VM support for UVD on supported hardware. 65 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 66 * - 3.5.0 - Add support for new UVD_NO_OP register. 67 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 68 * - 3.7.0 - Add support for VCE clock list packet 69 * - 3.8.0 - Add support raster config init in the kernel 70 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 71 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 72 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 73 * - 3.12.0 - Add query for double offchip LDS buffers 74 * - 3.13.0 - Add PRT support 75 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 76 * - 3.15.0 - Export more gpu info for gfx9 77 * - 3.16.0 - Add reserved vmid support 78 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 79 * - 3.18.0 - Export gpu always on cu bitmap 80 * - 3.19.0 - Add support for UVD MJPEG decode 81 * - 3.20.0 - Add support for local BOs 82 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 83 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 84 * - 3.23.0 - Add query for VRAM lost counter 85 * - 3.24.0 - Add high priority compute support for gfx9 86 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 87 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 88 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation. 89 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 90 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 91 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 92 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 93 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 94 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 95 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 96 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 97 * - 3.36.0 - Allow reading more status registers on si/cik 98 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 99 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 100 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 101 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 102 * - 3.41.0 - Add video codec query 103 * - 3.42.0 - Add 16bpc fixed point display support 104 * - 3.43.0 - Add device hot plug/unplug support 105 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 106 * - 3.45.0 - Add context ioctl stable pstate interface 107 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm 108 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags 109 * - 3.48.0 - Add IP discovery version info to HW INFO 110 * - 3.49.0 - Add gang submit into CS IOCTL 111 * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock 112 * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock 113 * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl 114 * 3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields: 115 * tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size, 116 * gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi 117 * 3.53.0 - Support for GFX11 CP GFX shadowing 118 * 3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support 119 * - 3.55.0 - Add AMDGPU_INFO_GPUVM_FAULT query 120 * - 3.56.0 - Update IB start address and size alignment for decode and encode 121 * - 3.57.0 - Compute tunneling on GFX10+ 122 * - 3.58.0 - Add GFX12 DCC support 123 * - 3.59.0 - Cleared VRAM 124 * - 3.60.0 - Add AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE (Vulkan requirement) 125 * - 3.61.0 - Contains fix for RV/PCO compute queues 126 * - 3.62.0 - Add AMDGPU_IDS_FLAGS_MODE_PF, AMDGPU_IDS_FLAGS_MODE_VF & AMDGPU_IDS_FLAGS_MODE_PT 127 * - 3.63.0 - GFX12 display DCC supports 256B max compressed block size 128 * - 3.64.0 - Userq IP support query 129 */ 130 #define KMS_DRIVER_MAJOR 3 131 #define KMS_DRIVER_MINOR 64 132 #define KMS_DRIVER_PATCHLEVEL 0 133 134 /* 135 * amdgpu.debug module options. Are all disabled by default 136 */ 137 enum AMDGPU_DEBUG_MASK { 138 AMDGPU_DEBUG_VM = BIT(0), 139 AMDGPU_DEBUG_LARGEBAR = BIT(1), 140 AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY = BIT(2), 141 AMDGPU_DEBUG_USE_VRAM_FW_BUF = BIT(3), 142 AMDGPU_DEBUG_ENABLE_RAS_ACA = BIT(4), 143 AMDGPU_DEBUG_ENABLE_EXP_RESETS = BIT(5), 144 AMDGPU_DEBUG_DISABLE_GPU_RING_RESET = BIT(6), 145 AMDGPU_DEBUG_SMU_POOL = BIT(7), 146 AMDGPU_DEBUG_VM_USERPTR = BIT(8), 147 AMDGPU_DEBUG_DISABLE_RAS_CE_LOG = BIT(9), 148 AMDGPU_DEBUG_ENABLE_CE_CS = BIT(10), 149 AMDGPU_DEBUG_HIBERNATION_THAW_RESUME_GPU = BIT(11), 150 AMDGPU_DEBUG_DISABLE_IP_BLOCK_SOFT_RESET = BIT(12), 151 }; 152 153 unsigned int amdgpu_vram_limit = UINT_MAX; 154 int amdgpu_vis_vram_limit; 155 int amdgpu_gart_size = -1; /* auto */ 156 int amdgpu_gtt_size = -1; /* auto */ 157 int amdgpu_moverate = -1; /* auto */ 158 int amdgpu_audio = -1; 159 int amdgpu_disp_priority; 160 int amdgpu_hw_i2c; 161 int amdgpu_pcie_gen2 = -1; 162 int amdgpu_msi = -1; 163 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 164 int amdgpu_dpm = -1; 165 int amdgpu_fw_load_type = -1; 166 int amdgpu_aspm = -1; 167 int amdgpu_runtime_pm = -1; 168 uint amdgpu_ip_block_mask = 0xffffffff; 169 int amdgpu_bapm = -1; 170 int amdgpu_deep_color; 171 int amdgpu_vm_size = -1; 172 int amdgpu_vm_fragment_size = -1; 173 int amdgpu_vm_block_size = -1; 174 int amdgpu_vm_fault_stop; 175 int amdgpu_vm_update_mode = -1; 176 int amdgpu_exp_hw_support; 177 int amdgpu_dc = -1; 178 int amdgpu_sched_jobs = 32; 179 int amdgpu_sched_hw_submission = 2; 180 uint amdgpu_pcie_gen_cap; 181 uint amdgpu_pcie_lane_cap; 182 u64 amdgpu_cg_mask = 0xffffffffffffffff; 183 uint amdgpu_pg_mask = 0xffffffff; 184 uint amdgpu_sdma_phase_quantum = 32; 185 char *amdgpu_disable_cu; 186 char *amdgpu_virtual_display; 187 int amdgpu_enforce_isolation = -1; 188 int amdgpu_modeset = -1; 189 190 /* Specifies the default granularity for SVM, used in buffer 191 * migration and restoration of backing memory when handling 192 * recoverable page faults. 193 * 194 * The value is given as log(numPages(buffer)); for a 2 MiB 195 * buffer it computes to be 9 196 */ 197 uint amdgpu_svm_default_granularity = 9; 198 199 /* 200 * OverDrive(bit 14) disabled by default 201 * GFX DCS(bit 19) disabled by default 202 */ 203 uint amdgpu_pp_feature_mask = 0xfff7bfff; 204 uint amdgpu_force_long_training; 205 int amdgpu_lbpw = -1; 206 int amdgpu_compute_multipipe = -1; 207 int amdgpu_gpu_recovery = -1; /* auto */ 208 int amdgpu_emu_mode; 209 uint amdgpu_smu_memory_pool_size; 210 int amdgpu_smu_pptable_id = -1; 211 /* 212 * FBC (bit 0) disabled by default 213 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 214 * - With this, for multiple monitors in sync(e.g. with the same model), 215 * mclk switching will be allowed. And the mclk will be not foced to the 216 * highest. That helps saving some idle power. 217 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 218 * PSR (bit 3) disabled by default 219 * EDP NO POWER SEQUENCING (bit 4) disabled by default 220 */ 221 uint amdgpu_dc_feature_mask = 2; 222 uint amdgpu_dc_debug_mask; 223 uint amdgpu_dc_visual_confirm; 224 int amdgpu_async_gfx_ring = 1; 225 int amdgpu_mcbp = -1; 226 int amdgpu_discovery = -1; 227 int amdgpu_mes_log_enable = 0; 228 int amdgpu_uni_mes = 1; 229 int amdgpu_noretry = -1; 230 int amdgpu_force_asic_type = -1; 231 int amdgpu_tmz = -1; /* auto */ 232 uint amdgpu_freesync_vid_mode; 233 int amdgpu_reset_method = -1; /* auto */ 234 int amdgpu_num_kcq = -1; 235 int amdgpu_smartshift_bias; 236 int amdgpu_use_xgmi_p2p = 1; 237 int amdgpu_vcnfw_log; 238 int amdgpu_sg_display = -1; /* auto */ 239 int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE; 240 int amdgpu_umsch_mm; 241 int amdgpu_seamless = -1; /* auto */ 242 uint amdgpu_debug_mask; 243 int amdgpu_agp = -1; /* auto */ 244 int amdgpu_wbrf = -1; 245 int amdgpu_damage_clips = -1; /* auto */ 246 int amdgpu_umsch_mm_fwlog; 247 int amdgpu_rebar = -1; /* auto */ 248 int amdgpu_user_queue = -1; 249 uint amdgpu_hdmi_hpd_debounce_delay_ms; 250 int amdgpu_ptl = -1; /* auto */ 251 252 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 253 "DRM_UT_CORE", 254 "DRM_UT_DRIVER", 255 "DRM_UT_KMS", 256 "DRM_UT_PRIME", 257 "DRM_UT_ATOMIC", 258 "DRM_UT_VBL", 259 "DRM_UT_STATE", 260 "DRM_UT_LEASE", 261 "DRM_UT_DP", 262 "DRM_UT_DRMRES"); 263 264 struct amdgpu_mgpu_info mgpu_info = { 265 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 266 }; 267 int amdgpu_ras_enable = -1; 268 uint amdgpu_ras_mask = 0xffffffff; 269 int amdgpu_bad_page_threshold = -1; 270 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 271 .timeout_fatal_disable = false, 272 .period = 0x0, /* default to 0x0 (timeout disable) */ 273 }; 274 275 /** 276 * DOC: vramlimit (int) 277 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 278 */ 279 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 280 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 281 282 /** 283 * DOC: vis_vramlimit (int) 284 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 285 */ 286 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 287 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 288 289 /** 290 * DOC: gartsize (uint) 291 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing. 292 * The default is -1 (The size depends on asic). 293 */ 294 MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)"); 295 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 296 297 /** 298 * DOC: gttsize (int) 299 * Restrict the size of GTT domain (for userspace use) in MiB for testing. 300 * The default is -1 (Use value specified by TTM). 301 * This parameter is deprecated and will be removed in the future. 302 */ 303 MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)"); 304 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 305 306 /** 307 * DOC: moverate (int) 308 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 309 */ 310 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 311 module_param_named(moverate, amdgpu_moverate, int, 0600); 312 313 /** 314 * DOC: audio (int) 315 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 316 */ 317 MODULE_PARM_DESC(audio, "HDMI/DP Audio enable for non DC displays (-1 = auto, 0 = disable, 1 = enable)"); 318 module_param_named(audio, amdgpu_audio, int, 0444); 319 320 /** 321 * DOC: disp_priority (int) 322 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 323 */ 324 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 325 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 326 327 /** 328 * DOC: hw_i2c (int) 329 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 330 */ 331 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 332 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 333 334 /** 335 * DOC: pcie_gen2 (int) 336 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 337 */ 338 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 339 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 340 341 /** 342 * DOC: msi (int) 343 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 344 */ 345 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 346 module_param_named(msi, amdgpu_msi, int, 0444); 347 348 /** 349 * DOC: svm_default_granularity (uint) 350 * Used in buffer migration and handling of recoverable page faults 351 */ 352 MODULE_PARM_DESC(svm_default_granularity, "SVM's default granularity in log(2^Pages), default 9 = 2^9 = 2 MiB"); 353 module_param_named(svm_default_granularity, amdgpu_svm_default_granularity, uint, 0644); 354 355 /** 356 * DOC: lockup_timeout (string) 357 * Set GPU scheduler timeout value in ms. 358 * 359 * The format can be [single value] for setting all timeouts at once or 360 * [GFX,Compute,SDMA,Video] to set individual timeouts. 361 * Negative values mean infinity. 362 * 363 * By default(with no lockup_timeout settings), the timeout for all queues is 2000. 364 */ 365 MODULE_PARM_DESC(lockup_timeout, 366 "GPU lockup timeout in ms (default: 2000. 0: keep default value. negative: infinity timeout), format: [single value for all] or [GFX,Compute,SDMA,Video]."); 367 module_param_string(lockup_timeout, amdgpu_lockup_timeout, 368 sizeof(amdgpu_lockup_timeout), 0444); 369 370 /** 371 * DOC: dpm (int) 372 * Override for dynamic power management setting 373 * (0 = disable, 1 = enable) 374 * The default is -1 (auto). 375 */ 376 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 377 module_param_named(dpm, amdgpu_dpm, int, 0444); 378 379 /** 380 * DOC: fw_load_type (int) 381 * Set different firmware loading type for debugging, if supported. 382 * Set to 0 to force direct loading if supported by the ASIC. Set 383 * to -1 to select the default loading mode for the ASIC, as defined 384 * by the driver. The default is -1 (auto). 385 */ 386 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); 387 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 388 389 /** 390 * DOC: aspm (int) 391 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 392 */ 393 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 394 module_param_named(aspm, amdgpu_aspm, int, 0444); 395 396 /** 397 * DOC: runpm (int) 398 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 399 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 400 * Setting the value to 0 disables this functionality. 401 * Setting the value to -2 is auto enabled with power down when displays are attached. 402 */ 403 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto, -2 = auto with displays)"); 404 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 405 406 /** 407 * DOC: ip_block_mask (uint) 408 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 409 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 410 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 411 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 412 */ 413 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 414 module_param_named_unsafe(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 415 416 /** 417 * DOC: bapm (int) 418 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 419 * The default -1 (auto, enabled) 420 */ 421 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 422 module_param_named(bapm, amdgpu_bapm, int, 0444); 423 424 /** 425 * DOC: deep_color (int) 426 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 427 */ 428 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 429 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 430 431 /** 432 * DOC: vm_size (int) 433 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 434 */ 435 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 436 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 437 438 /** 439 * DOC: vm_fragment_size (int) 440 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 441 */ 442 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 443 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 444 445 /** 446 * DOC: vm_block_size (int) 447 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 448 */ 449 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 450 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 451 452 /** 453 * DOC: vm_fault_stop (int) 454 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 455 */ 456 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 457 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 458 459 /** 460 * DOC: vm_update_mode (int) 461 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 462 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 463 */ 464 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 465 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 466 467 /** 468 * DOC: exp_hw_support (int) 469 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 470 */ 471 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 472 module_param_named_unsafe(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 473 474 /** 475 * DOC: dc (int) 476 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 477 */ 478 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 479 module_param_named(dc, amdgpu_dc, int, 0444); 480 481 /** 482 * DOC: sched_jobs (int) 483 * Override the max number of jobs supported in the sw queue. The default is 32. 484 */ 485 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 486 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 487 488 /** 489 * DOC: sched_hw_submission (int) 490 * Override the max number of HW submissions. The default is 2. 491 */ 492 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 493 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 494 495 /** 496 * DOC: ppfeaturemask (hexint) 497 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 498 * The default is the current set of stable power features. 499 */ 500 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 501 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 502 503 /** 504 * DOC: forcelongtraining (uint) 505 * Force long memory training in resume. 506 * The default is zero, indicates short training in resume. 507 */ 508 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 509 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 510 511 /** 512 * DOC: pcie_gen_cap (uint) 513 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 514 * The default is 0 (automatic for each asic). 515 */ 516 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 517 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 518 519 /** 520 * DOC: pcie_lane_cap (uint) 521 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 522 * The default is 0 (automatic for each asic). 523 */ 524 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 525 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 526 527 /** 528 * DOC: cg_mask (ullong) 529 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 530 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 531 */ 532 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 533 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 534 535 /** 536 * DOC: pg_mask (uint) 537 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 538 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 539 */ 540 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 541 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 542 543 /** 544 * DOC: sdma_phase_quantum (uint) 545 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 546 */ 547 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 548 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 549 550 /** 551 * DOC: disable_cu (charp) 552 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 553 */ 554 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 555 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 556 557 /** 558 * DOC: virtual_display (charp) 559 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 560 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 561 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 562 * device at 26:00.0. The default is NULL. 563 */ 564 MODULE_PARM_DESC(virtual_display, 565 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 566 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 567 568 /** 569 * DOC: lbpw (int) 570 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 571 */ 572 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 573 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 574 575 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 576 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 577 578 /** 579 * DOC: gpu_recovery (int) 580 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 581 */ 582 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 583 module_param_named_unsafe(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 584 585 /** 586 * DOC: emu_mode (int) 587 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 588 */ 589 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 590 module_param_named_unsafe(emu_mode, amdgpu_emu_mode, int, 0444); 591 592 /** 593 * DOC: ras_enable (int) 594 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 595 */ 596 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 597 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 598 599 /** 600 * DOC: ras_mask (uint) 601 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 602 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 603 */ 604 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 605 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 606 607 /** 608 * DOC: timeout_fatal_disable (bool) 609 * Disable Watchdog timeout fatal error event 610 */ 611 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 612 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 613 614 /** 615 * DOC: timeout_period (uint) 616 * Modify the watchdog timeout max_cycles as (1 << period) 617 */ 618 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 619 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 620 621 /** 622 * DOC: si_support (int) 623 * 1 = enabled, 0 = disabled, -1 = default 624 * 625 * SI (Southern Islands) are first generation GCN GPUs, supported by both 626 * drivers: radeon (old) and amdgpu (new). This parameter controls whether 627 * amdgpu should support SI. 628 * By default, SI dedicated GPUs are supported by amdgpu. 629 * Only relevant when CONFIG_DRM_AMDGPU_SI is enabled to build SI support in amdgpu. 630 * See also radeon.si_support which should be disabled when amdgpu.si_support is 631 * enabled, and vice versa. 632 */ 633 int amdgpu_si_support = -1; 634 #ifdef CONFIG_DRM_AMDGPU_SI 635 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled, -1 = default)"); 636 module_param_named(si_support, amdgpu_si_support, int, 0444); 637 #endif 638 639 /** 640 * DOC: cik_support (int) 641 * 1 = enabled, 0 = disabled, -1 = default 642 * 643 * CIK (Sea Islands) are second generation GCN GPUs, supported by both 644 * drivers: radeon (old) and amdgpu (new). This parameter controls whether 645 * amdgpu should support CIK. 646 * By default, CIK dedicated GPUs and APUs are supported by amdgpu. 647 * Only relevant when CONFIG_DRM_AMDGPU_CIK is enabled to build CIK support in amdgpu. 648 * See also radeon.cik_support which should be disabled when amdgpu.cik_support is 649 * enabled, and vice versa. 650 */ 651 int amdgpu_cik_support = -1; 652 #ifdef CONFIG_DRM_AMDGPU_CIK 653 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled, -1 = default)"); 654 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 655 #endif 656 657 /** 658 * DOC: smu_memory_pool_size (uint) 659 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 660 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 661 */ 662 MODULE_PARM_DESC(smu_memory_pool_size, 663 "reserve gtt for smu debug usage, 0 = disable,0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 664 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 665 666 /** 667 * DOC: async_gfx_ring (int) 668 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 669 */ 670 MODULE_PARM_DESC(async_gfx_ring, 671 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 672 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 673 674 /** 675 * DOC: mcbp (int) 676 * It is used to enable mid command buffer preemption. (0 = disabled, 1 = enabled, -1 auto (default)) 677 */ 678 MODULE_PARM_DESC(mcbp, 679 "Enable Mid-command buffer preemption (0 = disabled, 1 = enabled), -1 = auto (default)"); 680 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 681 682 /** 683 * DOC: discovery (int) 684 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 685 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 686 */ 687 MODULE_PARM_DESC(discovery, 688 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 689 module_param_named(discovery, amdgpu_discovery, int, 0444); 690 691 /** 692 * DOC: mes_log_enable (int) 693 * Enable Micro Engine Scheduler log. This is used to enable/disable MES internal log. 694 * (0 = disabled (default), 1 = enabled) 695 */ 696 MODULE_PARM_DESC(mes_log_enable, 697 "Enable Micro Engine Scheduler log (0 = disabled (default), 1 = enabled)"); 698 module_param_named(mes_log_enable, amdgpu_mes_log_enable, int, 0444); 699 700 /** 701 * DOC: uni_mes (int) 702 * Enable Unified Micro Engine Scheduler. This is a new engine pipe for unified scheduler. 703 * (0 = disabled (default), 1 = enabled) 704 */ 705 MODULE_PARM_DESC(uni_mes, 706 "Enable Unified Micro Engine Scheduler (0 = disabled, 1 = enabled(default)"); 707 module_param_named(uni_mes, amdgpu_uni_mes, int, 0444); 708 709 /** 710 * DOC: noretry (int) 711 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 712 * do not support per-process XNACK this also disables retry page faults. 713 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 714 */ 715 MODULE_PARM_DESC(noretry, 716 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 717 module_param_named(noretry, amdgpu_noretry, int, 0644); 718 719 /** 720 * DOC: force_asic_type (int) 721 * A non negative value used to specify the asic type for all supported GPUs. 722 */ 723 MODULE_PARM_DESC(force_asic_type, 724 "A non negative value used to specify the asic type for all supported GPUs"); 725 module_param_named_unsafe(force_asic_type, amdgpu_force_asic_type, int, 0444); 726 727 /** 728 * DOC: use_xgmi_p2p (int) 729 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 730 */ 731 MODULE_PARM_DESC(use_xgmi_p2p, 732 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 733 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 734 735 736 #ifdef CONFIG_HSA_AMD 737 /** 738 * DOC: sched_policy (int) 739 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 740 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 741 * assigns queues to HQDs. 742 */ 743 int sched_policy = KFD_SCHED_POLICY_HWS; 744 module_param_unsafe(sched_policy, int, 0444); 745 MODULE_PARM_DESC(sched_policy, 746 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 747 748 /** 749 * DOC: hws_max_conc_proc (int) 750 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 751 * number of VMIDs assigned to the HWS, which is also the default. 752 */ 753 int hws_max_conc_proc = -1; 754 module_param(hws_max_conc_proc, int, 0444); 755 MODULE_PARM_DESC(hws_max_conc_proc, 756 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 757 758 /** 759 * DOC: cwsr_enable (int) 760 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 761 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 762 * disables it. 763 */ 764 int cwsr_enable = 1; 765 module_param(cwsr_enable, int, 0444); 766 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 767 768 /** 769 * DOC: max_num_of_queues_per_device (int) 770 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 771 * is 4096. 772 */ 773 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 774 module_param(max_num_of_queues_per_device, int, 0444); 775 MODULE_PARM_DESC(max_num_of_queues_per_device, 776 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 777 778 /** 779 * DOC: send_sigterm (int) 780 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 781 * but just print errors on dmesg. Setting 1 enables sending sigterm. 782 */ 783 int send_sigterm; 784 module_param(send_sigterm, int, 0444); 785 MODULE_PARM_DESC(send_sigterm, 786 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 787 788 /** 789 * DOC: halt_if_hws_hang (int) 790 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 791 * Setting 1 enables halt on hang. 792 */ 793 int halt_if_hws_hang; 794 module_param_unsafe(halt_if_hws_hang, int, 0644); 795 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 796 797 /** 798 * DOC: hws_gws_support(bool) 799 * Assume that HWS supports GWS barriers regardless of what firmware version 800 * check says. Default value: false (rely on MEC2 firmware version check). 801 */ 802 bool hws_gws_support; 803 module_param_unsafe(hws_gws_support, bool, 0444); 804 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 805 806 /** 807 * DOC: queue_preemption_timeout_ms (int) 808 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 809 */ 810 int queue_preemption_timeout_ms = 9000; 811 module_param(queue_preemption_timeout_ms, int, 0644); 812 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 813 814 /** 815 * DOC: debug_evictions(bool) 816 * Enable extra debug messages to help determine the cause of evictions 817 */ 818 bool debug_evictions; 819 module_param(debug_evictions, bool, 0644); 820 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 821 822 /** 823 * DOC: no_system_mem_limit(bool) 824 * Disable system memory limit, to support multiple process shared memory 825 */ 826 bool no_system_mem_limit; 827 module_param(no_system_mem_limit, bool, 0644); 828 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 829 830 /** 831 * DOC: no_queue_eviction_on_vm_fault (int) 832 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 833 */ 834 int amdgpu_no_queue_eviction_on_vm_fault; 835 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 836 module_param_named_unsafe(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 837 #endif 838 839 /** 840 * DOC: mtype_local (int) 841 */ 842 int amdgpu_mtype_local = -1; 843 MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (default: ASIC dependent, 0 = MTYPE_RW, 1 = MTYPE_NC, 2 = MTYPE_CC)"); 844 module_param_named_unsafe(mtype_local, amdgpu_mtype_local, int, 0444); 845 846 /** 847 * DOC: pcie_p2p (bool) 848 * Enable PCIe P2P (requires large-BAR). Default value: true (on) 849 */ 850 #ifdef CONFIG_HSA_AMD_P2P 851 bool pcie_p2p = true; 852 module_param(pcie_p2p, bool, 0444); 853 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); 854 #endif 855 856 /** 857 * DOC: dcfeaturemask (uint) 858 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 859 * The default is the current set of stable display features. 860 */ 861 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 862 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 863 864 /** 865 * DOC: dcdebugmask (uint) 866 * Display debug options. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 867 */ 868 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 869 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 870 871 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)"); 872 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444); 873 874 /** 875 * DOC: abmlevel (uint) 876 * Override the default ABM (Adaptive Backlight Management) level used for DC 877 * enabled hardware. Requires DMCU to be supported and loaded. 878 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 879 * default. Values 1-4 control the maximum allowable brightness reduction via 880 * the ABM algorithm, with 1 being the least reduction and 4 being the most 881 * reduction. 882 * 883 * Defaults to -1, or auto. Userspace can only override this level after 884 * boot if it's set to auto. 885 */ 886 int amdgpu_dm_abm_level = -1; 887 MODULE_PARM_DESC(abmlevel, 888 "ABM level (0 = off, 1-4 = backlight reduction level, -1 auto (default))"); 889 module_param_named(abmlevel, amdgpu_dm_abm_level, int, 0444); 890 891 int amdgpu_backlight = -1; 892 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 893 module_param_named(backlight, amdgpu_backlight, bint, 0444); 894 895 /** 896 * DOC: damageclips (int) 897 * Enable or disable damage clips support. If damage clips support is disabled, 898 * we will force full frame updates, irrespective of what user space sends to 899 * us. 900 * 901 * Defaults to -1 (where it is enabled unless a PSR-SU display is detected). 902 */ 903 MODULE_PARM_DESC(damageclips, 904 "Damage clips support (0 = disable, 1 = enable, -1 auto (default))"); 905 module_param_named(damageclips, amdgpu_damage_clips, int, 0444); 906 907 /** 908 * DOC: tmz (int) 909 * Trusted Memory Zone (TMZ) is a method to protect data being written 910 * to or read from memory. 911 * 912 * The default value: 0 (off). TODO: change to auto till it is completed. 913 */ 914 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 915 module_param_named(tmz, amdgpu_tmz, int, 0444); 916 917 /** 918 * DOC: freesync_video (uint) 919 * Enable the optimization to adjust front porch timing to achieve seamless 920 * mode change experience when setting a freesync supported mode for which full 921 * modeset is not needed. 922 * 923 * The Display Core will add a set of modes derived from the base FreeSync 924 * video mode into the corresponding connector's mode list based on commonly 925 * used refresh rates and VRR range of the connected display, when users enable 926 * this feature. From the userspace perspective, they can see a seamless mode 927 * change experience when the change between different refresh rates under the 928 * same resolution. Additionally, userspace applications such as Video playback 929 * can read this modeset list and change the refresh rate based on the video 930 * frame rate. Finally, the userspace can also derive an appropriate mode for a 931 * particular refresh rate based on the FreeSync Mode and add it to the 932 * connector's mode list. 933 * 934 * Note: This is an experimental feature. 935 * 936 * The default value: 0 (off). 937 */ 938 MODULE_PARM_DESC( 939 freesync_video, 940 "Adds additional modes via VRR for refresh changes without a full modeset (0 = off (default), 1 = on)"); 941 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); 942 943 /** 944 * DOC: reset_method (int) 945 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 946 */ 947 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 948 module_param_named_unsafe(reset_method, amdgpu_reset_method, int, 0644); 949 950 /** 951 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 952 * threshold value of faulty pages detected by RAS ECC, which may 953 * result in the GPU entering bad status when the number of total 954 * faulty pages by ECC exceeds the threshold value. 955 */ 956 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = threshold determined by a formula, 0 < threshold < max records, user-defined threshold)"); 957 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 958 959 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 960 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 961 962 /** 963 * DOC: vcnfw_log (int) 964 * Enable vcnfw log output for debugging, the default is disabled. 965 */ 966 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 967 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 968 969 /** 970 * DOC: sg_display (int) 971 * Disable S/G (scatter/gather) display (i.e., display from system memory). 972 * This option is only relevant on APUs. Set this option to 0 to disable 973 * S/G display if you experience flickering or other issues under memory 974 * pressure and report the issue. 975 */ 976 MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)"); 977 module_param_named(sg_display, amdgpu_sg_display, int, 0444); 978 979 /** 980 * DOC: umsch_mm (int) 981 * Enable Multi Media User Mode Scheduler. This is a HW scheduling engine for VCN and VPE. 982 * (0 = disabled (default), 1 = enabled) 983 */ 984 MODULE_PARM_DESC(umsch_mm, 985 "Enable Multi Media User Mode Scheduler (0 = disabled (default), 1 = enabled)"); 986 module_param_named(umsch_mm, amdgpu_umsch_mm, int, 0444); 987 988 /** 989 * DOC: umsch_mm_fwlog (int) 990 * Enable umschfw log output for debugging, the default is disabled. 991 */ 992 MODULE_PARM_DESC(umsch_mm_fwlog, "Enable umschfw log(0 = disable (default value), 1 = enable)"); 993 module_param_named(umsch_mm_fwlog, amdgpu_umsch_mm_fwlog, int, 0444); 994 995 /** 996 * DOC: smu_pptable_id (int) 997 * Used to override pptable id. id = 0 use VBIOS pptable. 998 * id > 0 use the soft pptable with specicfied id. 999 */ 1000 MODULE_PARM_DESC(smu_pptable_id, 1001 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 1002 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 1003 1004 /** 1005 * DOC: partition_mode (int) 1006 * Used to override the default SPX mode. 1007 */ 1008 MODULE_PARM_DESC( 1009 user_partt_mode, 1010 "specify partition mode to be used (-2 = AMDGPU_AUTO_COMPUTE_PARTITION_MODE(default value) \ 1011 0 = AMDGPU_SPX_PARTITION_MODE, \ 1012 1 = AMDGPU_DPX_PARTITION_MODE, \ 1013 2 = AMDGPU_TPX_PARTITION_MODE, \ 1014 3 = AMDGPU_QPX_PARTITION_MODE, \ 1015 4 = AMDGPU_CPX_PARTITION_MODE)"); 1016 module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint, 0444); 1017 1018 1019 /** 1020 * DOC: enforce_isolation (int) 1021 * enforce process isolation between graphics and compute. 1022 * (-1 = auto, 0 = disable, 1 = enable, 2 = enable legacy mode, 3 = enable without cleaner shader) 1023 */ 1024 module_param_named(enforce_isolation, amdgpu_enforce_isolation, int, 0444); 1025 MODULE_PARM_DESC(enforce_isolation, 1026 "enforce process isolation between graphics and compute. (-1 = auto, 0 = disable, 1 = enable, 2 = enable legacy mode, 3 = enable without cleaner shader)"); 1027 1028 /** 1029 * DOC: modeset (int) 1030 * Override nomodeset (1 = override, -1 = auto). The default is -1 (auto). 1031 */ 1032 MODULE_PARM_DESC(modeset, "Override nomodeset (1 = enable, -1 = auto)"); 1033 module_param_named(modeset, amdgpu_modeset, int, 0444); 1034 1035 /** 1036 * DOC: seamless (int) 1037 * Seamless boot will keep the image on the screen during the boot process. 1038 */ 1039 MODULE_PARM_DESC(seamless, "Seamless boot (-1 = auto (default), 0 = disable, 1 = enable)"); 1040 module_param_named(seamless, amdgpu_seamless, int, 0444); 1041 1042 /** 1043 * DOC: debug_mask (uint) 1044 * Debug options for amdgpu, work as a binary mask with the following options: 1045 * 1046 * - 0x1: Debug VM handling 1047 * - 0x2: Enable simulating large-bar capability on non-large bar system. This 1048 * limits the VRAM size reported to ROCm applications to the visible 1049 * size, usually 256MB. 1050 * - 0x4: Disable GPU soft recovery, always do a full reset 1051 * - 0x8: Use VRAM for firmware loading 1052 * - 0x10: Enable ACA based RAS logging 1053 * - 0x20: Enable experimental resets 1054 * - 0x40: Disable ring resets 1055 * - 0x80: Use VRAM for SMU pool 1056 */ 1057 MODULE_PARM_DESC(debug_mask, "debug options for amdgpu, disabled by default"); 1058 module_param_named_unsafe(debug_mask, amdgpu_debug_mask, uint, 0444); 1059 1060 /** 1061 * DOC: agp (int) 1062 * Enable the AGP aperture. This provides an aperture in the GPU's internal 1063 * address space for direct access to system memory. Note that these accesses 1064 * are non-snooped, so they are only used for access to uncached memory. 1065 */ 1066 MODULE_PARM_DESC(agp, "AGP (-1 = auto (default), 0 = disable, 1 = enable)"); 1067 module_param_named(agp, amdgpu_agp, int, 0444); 1068 1069 /** 1070 * DOC: wbrf (int) 1071 * Enable Wifi RFI interference mitigation feature. 1072 * Due to electrical and mechanical constraints there may be likely interference of 1073 * relatively high-powered harmonics of the (G-)DDR memory clocks with local radio 1074 * module frequency bands used by Wifi 6/6e/7. To mitigate the possible RFI interference, 1075 * with this feature enabled, PMFW will use either “shadowed P-State” or “P-State” based 1076 * on active list of frequencies in-use (to be avoided) as part of initial setting or 1077 * P-state transition. However, there may be potential performance impact with this 1078 * feature enabled. 1079 * (0 = disabled, 1 = enabled, -1 = auto (default setting, will be enabled if supported)) 1080 */ 1081 MODULE_PARM_DESC(wbrf, 1082 "Enable Wifi RFI interference mitigation (0 = disabled, 1 = enabled, -1 = auto(default)"); 1083 module_param_named(wbrf, amdgpu_wbrf, int, 0444); 1084 1085 /** 1086 * DOC: rebar (int) 1087 * Allow BAR resizing. Disable this to prevent the driver from attempting 1088 * to resize the BAR if the GPU supports it and there is available MMIO space. 1089 * Note that this just prevents the driver from resizing the BAR. The BIOS 1090 * may have already resized the BAR at boot time. 1091 */ 1092 MODULE_PARM_DESC(rebar, "Resizable BAR (-1 = auto (default), 0 = disable, 1 = enable)"); 1093 module_param_named(rebar, amdgpu_rebar, int, 0444); 1094 1095 /** 1096 * DOC: user_queue (int) 1097 * Enable user queues on systems that support user queues. Possible values: 1098 * 1099 * - -1 = auto (ASIC specific default) 1100 * - 0 = user queues disabled 1101 * - 1 = user queues enabled and kernel queues enabled (if supported) 1102 * - 2 = user queues enabled and kernel queues disabled 1103 */ 1104 MODULE_PARM_DESC(user_queue, "Enable user queues (-1 = auto (default), 0 = disable, 1 = enable, 2 = enable UQs and disable KQs)"); 1105 module_param_named(user_queue, amdgpu_user_queue, int, 0444); 1106 1107 /* 1108 * DOC: hdmi_hpd_debounce_delay_ms (uint) 1109 * HDMI HPD disconnect debounce delay in milliseconds. 1110 * 1111 * Used to filter short disconnect->reconnect HPD toggles some HDMI sinks 1112 * generate while entering/leaving power save. Set to 0 to disable by default. 1113 */ 1114 MODULE_PARM_DESC(hdmi_hpd_debounce_delay_ms, "HDMI HPD disconnect debounce delay in milliseconds (0 to disable (by default), 1500 is common)"); 1115 module_param_named(hdmi_hpd_debounce_delay_ms, amdgpu_hdmi_hpd_debounce_delay_ms, uint, 0644); 1116 1117 /** 1118 * DOC: ptl (int) 1119 * Enable PTL feature at boot time. Possible values: 1120 * 1121 * - -1 = auto (ASIC specific default) 1122 * - 0 = disable PTL (default) 1123 * - 1 = enable PTL 1124 * - 2 = permanently disable PTL (cannot be re-enabled at runtime) 1125 */ 1126 MODULE_PARM_DESC(ptl, "Enable PTL (-1 = auto, 0 = disable (default), 1 = enable, 2 = permanently disable)"); 1127 module_param_named(ptl, amdgpu_ptl, int, 0444); 1128 1129 /* These devices are not supported by amdgpu. 1130 * They are supported by the mach64, r128, radeon drivers 1131 */ 1132 static const u16 amdgpu_unsupported_pciidlist[] = { 1133 /* mach64 */ 1134 0x4354, 1135 0x4358, 1136 0x4554, 1137 0x4742, 1138 0x4744, 1139 0x4749, 1140 0x474C, 1141 0x474D, 1142 0x474E, 1143 0x474F, 1144 0x4750, 1145 0x4751, 1146 0x4752, 1147 0x4753, 1148 0x4754, 1149 0x4755, 1150 0x4756, 1151 0x4757, 1152 0x4758, 1153 0x4759, 1154 0x475A, 1155 0x4C42, 1156 0x4C44, 1157 0x4C47, 1158 0x4C49, 1159 0x4C4D, 1160 0x4C4E, 1161 0x4C50, 1162 0x4C51, 1163 0x4C52, 1164 0x4C53, 1165 0x5654, 1166 0x5655, 1167 0x5656, 1168 /* r128 */ 1169 0x4c45, 1170 0x4c46, 1171 0x4d46, 1172 0x4d4c, 1173 0x5041, 1174 0x5042, 1175 0x5043, 1176 0x5044, 1177 0x5045, 1178 0x5046, 1179 0x5047, 1180 0x5048, 1181 0x5049, 1182 0x504A, 1183 0x504B, 1184 0x504C, 1185 0x504D, 1186 0x504E, 1187 0x504F, 1188 0x5050, 1189 0x5051, 1190 0x5052, 1191 0x5053, 1192 0x5054, 1193 0x5055, 1194 0x5056, 1195 0x5057, 1196 0x5058, 1197 0x5245, 1198 0x5246, 1199 0x5247, 1200 0x524b, 1201 0x524c, 1202 0x534d, 1203 0x5446, 1204 0x544C, 1205 0x5452, 1206 /* radeon */ 1207 0x3150, 1208 0x3151, 1209 0x3152, 1210 0x3154, 1211 0x3155, 1212 0x3E50, 1213 0x3E54, 1214 0x4136, 1215 0x4137, 1216 0x4144, 1217 0x4145, 1218 0x4146, 1219 0x4147, 1220 0x4148, 1221 0x4149, 1222 0x414A, 1223 0x414B, 1224 0x4150, 1225 0x4151, 1226 0x4152, 1227 0x4153, 1228 0x4154, 1229 0x4155, 1230 0x4156, 1231 0x4237, 1232 0x4242, 1233 0x4336, 1234 0x4337, 1235 0x4437, 1236 0x4966, 1237 0x4967, 1238 0x4A48, 1239 0x4A49, 1240 0x4A4A, 1241 0x4A4B, 1242 0x4A4C, 1243 0x4A4D, 1244 0x4A4E, 1245 0x4A4F, 1246 0x4A50, 1247 0x4A54, 1248 0x4B48, 1249 0x4B49, 1250 0x4B4A, 1251 0x4B4B, 1252 0x4B4C, 1253 0x4C57, 1254 0x4C58, 1255 0x4C59, 1256 0x4C5A, 1257 0x4C64, 1258 0x4C66, 1259 0x4C67, 1260 0x4E44, 1261 0x4E45, 1262 0x4E46, 1263 0x4E47, 1264 0x4E48, 1265 0x4E49, 1266 0x4E4A, 1267 0x4E4B, 1268 0x4E50, 1269 0x4E51, 1270 0x4E52, 1271 0x4E53, 1272 0x4E54, 1273 0x4E56, 1274 0x5144, 1275 0x5145, 1276 0x5146, 1277 0x5147, 1278 0x5148, 1279 0x514C, 1280 0x514D, 1281 0x5157, 1282 0x5158, 1283 0x5159, 1284 0x515A, 1285 0x515E, 1286 0x5460, 1287 0x5462, 1288 0x5464, 1289 0x5548, 1290 0x5549, 1291 0x554A, 1292 0x554B, 1293 0x554C, 1294 0x554D, 1295 0x554E, 1296 0x554F, 1297 0x5550, 1298 0x5551, 1299 0x5552, 1300 0x5554, 1301 0x564A, 1302 0x564B, 1303 0x564F, 1304 0x5652, 1305 0x5653, 1306 0x5657, 1307 0x5834, 1308 0x5835, 1309 0x5954, 1310 0x5955, 1311 0x5974, 1312 0x5975, 1313 0x5960, 1314 0x5961, 1315 0x5962, 1316 0x5964, 1317 0x5965, 1318 0x5969, 1319 0x5a41, 1320 0x5a42, 1321 0x5a61, 1322 0x5a62, 1323 0x5b60, 1324 0x5b62, 1325 0x5b63, 1326 0x5b64, 1327 0x5b65, 1328 0x5c61, 1329 0x5c63, 1330 0x5d48, 1331 0x5d49, 1332 0x5d4a, 1333 0x5d4c, 1334 0x5d4d, 1335 0x5d4e, 1336 0x5d4f, 1337 0x5d50, 1338 0x5d52, 1339 0x5d57, 1340 0x5e48, 1341 0x5e4a, 1342 0x5e4b, 1343 0x5e4c, 1344 0x5e4d, 1345 0x5e4f, 1346 0x6700, 1347 0x6701, 1348 0x6702, 1349 0x6703, 1350 0x6704, 1351 0x6705, 1352 0x6706, 1353 0x6707, 1354 0x6708, 1355 0x6709, 1356 0x6718, 1357 0x6719, 1358 0x671c, 1359 0x671d, 1360 0x671f, 1361 0x6720, 1362 0x6721, 1363 0x6722, 1364 0x6723, 1365 0x6724, 1366 0x6725, 1367 0x6726, 1368 0x6727, 1369 0x6728, 1370 0x6729, 1371 0x6738, 1372 0x6739, 1373 0x673e, 1374 0x6740, 1375 0x6741, 1376 0x6742, 1377 0x6743, 1378 0x6744, 1379 0x6745, 1380 0x6746, 1381 0x6747, 1382 0x6748, 1383 0x6749, 1384 0x674A, 1385 0x6750, 1386 0x6751, 1387 0x6758, 1388 0x6759, 1389 0x675B, 1390 0x675D, 1391 0x675F, 1392 0x6760, 1393 0x6761, 1394 0x6762, 1395 0x6763, 1396 0x6764, 1397 0x6765, 1398 0x6766, 1399 0x6767, 1400 0x6768, 1401 0x6770, 1402 0x6771, 1403 0x6772, 1404 0x6778, 1405 0x6779, 1406 0x677B, 1407 0x6840, 1408 0x6841, 1409 0x6842, 1410 0x6843, 1411 0x6849, 1412 0x684C, 1413 0x6850, 1414 0x6858, 1415 0x6859, 1416 0x6880, 1417 0x6888, 1418 0x6889, 1419 0x688A, 1420 0x688C, 1421 0x688D, 1422 0x6898, 1423 0x6899, 1424 0x689b, 1425 0x689c, 1426 0x689d, 1427 0x689e, 1428 0x68a0, 1429 0x68a1, 1430 0x68a8, 1431 0x68a9, 1432 0x68b0, 1433 0x68b8, 1434 0x68b9, 1435 0x68ba, 1436 0x68be, 1437 0x68bf, 1438 0x68c0, 1439 0x68c1, 1440 0x68c7, 1441 0x68c8, 1442 0x68c9, 1443 0x68d8, 1444 0x68d9, 1445 0x68da, 1446 0x68de, 1447 0x68e0, 1448 0x68e1, 1449 0x68e4, 1450 0x68e5, 1451 0x68e8, 1452 0x68e9, 1453 0x68f1, 1454 0x68f2, 1455 0x68f8, 1456 0x68f9, 1457 0x68fa, 1458 0x68fe, 1459 0x7100, 1460 0x7101, 1461 0x7102, 1462 0x7103, 1463 0x7104, 1464 0x7105, 1465 0x7106, 1466 0x7108, 1467 0x7109, 1468 0x710A, 1469 0x710B, 1470 0x710C, 1471 0x710E, 1472 0x710F, 1473 0x7140, 1474 0x7141, 1475 0x7142, 1476 0x7143, 1477 0x7144, 1478 0x7145, 1479 0x7146, 1480 0x7147, 1481 0x7149, 1482 0x714A, 1483 0x714B, 1484 0x714C, 1485 0x714D, 1486 0x714E, 1487 0x714F, 1488 0x7151, 1489 0x7152, 1490 0x7153, 1491 0x715E, 1492 0x715F, 1493 0x7180, 1494 0x7181, 1495 0x7183, 1496 0x7186, 1497 0x7187, 1498 0x7188, 1499 0x718A, 1500 0x718B, 1501 0x718C, 1502 0x718D, 1503 0x718F, 1504 0x7193, 1505 0x7196, 1506 0x719B, 1507 0x719F, 1508 0x71C0, 1509 0x71C1, 1510 0x71C2, 1511 0x71C3, 1512 0x71C4, 1513 0x71C5, 1514 0x71C6, 1515 0x71C7, 1516 0x71CD, 1517 0x71CE, 1518 0x71D2, 1519 0x71D4, 1520 0x71D5, 1521 0x71D6, 1522 0x71DA, 1523 0x71DE, 1524 0x7200, 1525 0x7210, 1526 0x7211, 1527 0x7240, 1528 0x7243, 1529 0x7244, 1530 0x7245, 1531 0x7246, 1532 0x7247, 1533 0x7248, 1534 0x7249, 1535 0x724A, 1536 0x724B, 1537 0x724C, 1538 0x724D, 1539 0x724E, 1540 0x724F, 1541 0x7280, 1542 0x7281, 1543 0x7283, 1544 0x7284, 1545 0x7287, 1546 0x7288, 1547 0x7289, 1548 0x728B, 1549 0x728C, 1550 0x7290, 1551 0x7291, 1552 0x7293, 1553 0x7297, 1554 0x7834, 1555 0x7835, 1556 0x791e, 1557 0x791f, 1558 0x793f, 1559 0x7941, 1560 0x7942, 1561 0x796c, 1562 0x796d, 1563 0x796e, 1564 0x796f, 1565 0x9400, 1566 0x9401, 1567 0x9402, 1568 0x9403, 1569 0x9405, 1570 0x940A, 1571 0x940B, 1572 0x940F, 1573 0x94A0, 1574 0x94A1, 1575 0x94A3, 1576 0x94B1, 1577 0x94B3, 1578 0x94B4, 1579 0x94B5, 1580 0x94B9, 1581 0x9440, 1582 0x9441, 1583 0x9442, 1584 0x9443, 1585 0x9444, 1586 0x9446, 1587 0x944A, 1588 0x944B, 1589 0x944C, 1590 0x944E, 1591 0x9450, 1592 0x9452, 1593 0x9456, 1594 0x945A, 1595 0x945B, 1596 0x945E, 1597 0x9460, 1598 0x9462, 1599 0x946A, 1600 0x946B, 1601 0x947A, 1602 0x947B, 1603 0x9480, 1604 0x9487, 1605 0x9488, 1606 0x9489, 1607 0x948A, 1608 0x948F, 1609 0x9490, 1610 0x9491, 1611 0x9495, 1612 0x9498, 1613 0x949C, 1614 0x949E, 1615 0x949F, 1616 0x94C0, 1617 0x94C1, 1618 0x94C3, 1619 0x94C4, 1620 0x94C5, 1621 0x94C6, 1622 0x94C7, 1623 0x94C8, 1624 0x94C9, 1625 0x94CB, 1626 0x94CC, 1627 0x94CD, 1628 0x9500, 1629 0x9501, 1630 0x9504, 1631 0x9505, 1632 0x9506, 1633 0x9507, 1634 0x9508, 1635 0x9509, 1636 0x950F, 1637 0x9511, 1638 0x9515, 1639 0x9517, 1640 0x9519, 1641 0x9540, 1642 0x9541, 1643 0x9542, 1644 0x954E, 1645 0x954F, 1646 0x9552, 1647 0x9553, 1648 0x9555, 1649 0x9557, 1650 0x955f, 1651 0x9580, 1652 0x9581, 1653 0x9583, 1654 0x9586, 1655 0x9587, 1656 0x9588, 1657 0x9589, 1658 0x958A, 1659 0x958B, 1660 0x958C, 1661 0x958D, 1662 0x958E, 1663 0x958F, 1664 0x9590, 1665 0x9591, 1666 0x9593, 1667 0x9595, 1668 0x9596, 1669 0x9597, 1670 0x9598, 1671 0x9599, 1672 0x959B, 1673 0x95C0, 1674 0x95C2, 1675 0x95C4, 1676 0x95C5, 1677 0x95C6, 1678 0x95C7, 1679 0x95C9, 1680 0x95CC, 1681 0x95CD, 1682 0x95CE, 1683 0x95CF, 1684 0x9610, 1685 0x9611, 1686 0x9612, 1687 0x9613, 1688 0x9614, 1689 0x9615, 1690 0x9616, 1691 0x9640, 1692 0x9641, 1693 0x9642, 1694 0x9643, 1695 0x9644, 1696 0x9645, 1697 0x9647, 1698 0x9648, 1699 0x9649, 1700 0x964a, 1701 0x964b, 1702 0x964c, 1703 0x964e, 1704 0x964f, 1705 0x9710, 1706 0x9711, 1707 0x9712, 1708 0x9713, 1709 0x9714, 1710 0x9715, 1711 0x9802, 1712 0x9803, 1713 0x9804, 1714 0x9805, 1715 0x9806, 1716 0x9807, 1717 0x9808, 1718 0x9809, 1719 0x980A, 1720 0x9900, 1721 0x9901, 1722 0x9903, 1723 0x9904, 1724 0x9905, 1725 0x9906, 1726 0x9907, 1727 0x9908, 1728 0x9909, 1729 0x990A, 1730 0x990B, 1731 0x990C, 1732 0x990D, 1733 0x990E, 1734 0x990F, 1735 0x9910, 1736 0x9913, 1737 0x9917, 1738 0x9918, 1739 0x9919, 1740 0x9990, 1741 0x9991, 1742 0x9992, 1743 0x9993, 1744 0x9994, 1745 0x9995, 1746 0x9996, 1747 0x9997, 1748 0x9998, 1749 0x9999, 1750 0x999A, 1751 0x999B, 1752 0x999C, 1753 0x999D, 1754 0x99A0, 1755 0x99A2, 1756 0x99A4, 1757 /* radeon secondary ids */ 1758 0x3171, 1759 0x3e70, 1760 0x4164, 1761 0x4165, 1762 0x4166, 1763 0x4168, 1764 0x4170, 1765 0x4171, 1766 0x4172, 1767 0x4173, 1768 0x496e, 1769 0x4a69, 1770 0x4a6a, 1771 0x4a6b, 1772 0x4a70, 1773 0x4a74, 1774 0x4b69, 1775 0x4b6b, 1776 0x4b6c, 1777 0x4c6e, 1778 0x4e64, 1779 0x4e65, 1780 0x4e66, 1781 0x4e67, 1782 0x4e68, 1783 0x4e69, 1784 0x4e6a, 1785 0x4e71, 1786 0x4f73, 1787 0x5569, 1788 0x556b, 1789 0x556d, 1790 0x556f, 1791 0x5571, 1792 0x5854, 1793 0x5874, 1794 0x5940, 1795 0x5941, 1796 0x5b70, 1797 0x5b72, 1798 0x5b73, 1799 0x5b74, 1800 0x5b75, 1801 0x5d44, 1802 0x5d45, 1803 0x5d6d, 1804 0x5d6f, 1805 0x5d72, 1806 0x5d77, 1807 0x5e6b, 1808 0x5e6d, 1809 0x7120, 1810 0x7124, 1811 0x7129, 1812 0x712e, 1813 0x712f, 1814 0x7162, 1815 0x7163, 1816 0x7166, 1817 0x7167, 1818 0x7172, 1819 0x7173, 1820 0x71a0, 1821 0x71a1, 1822 0x71a3, 1823 0x71a7, 1824 0x71bb, 1825 0x71e0, 1826 0x71e1, 1827 0x71e2, 1828 0x71e6, 1829 0x71e7, 1830 0x71f2, 1831 0x7269, 1832 0x726b, 1833 0x726e, 1834 0x72a0, 1835 0x72a8, 1836 0x72b1, 1837 0x72b3, 1838 0x793f, 1839 }; 1840 1841 static const struct pci_device_id pciidlist[] = { 1842 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1843 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1844 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1845 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1846 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1847 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1848 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1849 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1850 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1851 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1852 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1853 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1854 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1855 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1856 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1857 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1858 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1859 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1860 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1861 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1862 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1863 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1864 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1865 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1866 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1867 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1868 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1869 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1870 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1871 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1872 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1873 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1874 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1875 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1876 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1877 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1878 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1879 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1880 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1881 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1882 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1883 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1884 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1885 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1886 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1887 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1888 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1889 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1890 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1891 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1892 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1893 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1894 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1895 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1896 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1897 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1898 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1899 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1900 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1901 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1902 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1903 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1904 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1905 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1906 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1907 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1908 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1909 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1910 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1911 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1912 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1913 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1914 /* Kaveri */ 1915 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1916 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1917 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1918 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1919 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1920 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1921 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1922 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1923 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1924 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1925 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1926 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1927 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1928 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1929 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1930 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1931 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1932 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1933 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1934 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1935 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1936 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1937 /* Bonaire */ 1938 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1939 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1940 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1941 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1942 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1943 {0x1002, 0x664D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1944 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1945 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1946 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1947 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1948 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1949 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1950 /* Hawaii */ 1951 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1952 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1953 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1954 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1955 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1956 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1957 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1958 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1959 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1960 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1961 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1962 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1963 /* Kabini */ 1964 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1965 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1966 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1967 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1968 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1969 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1970 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1971 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1972 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1973 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1974 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1975 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1976 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1977 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1978 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1979 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1980 /* mullins */ 1981 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1982 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1983 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1984 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1985 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1986 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1987 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1988 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1989 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1990 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1991 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1992 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1993 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1994 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1995 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1996 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1997 /* topaz */ 1998 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1999 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 2000 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 2001 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 2002 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 2003 /* tonga */ 2004 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2005 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2006 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2007 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2008 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2009 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2010 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2011 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2012 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2013 {0x1002, 0x693B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2014 /* fiji */ 2015 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 2016 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 2017 /* carrizo */ 2018 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 2019 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 2020 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 2021 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 2022 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 2023 /* stoney */ 2024 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 2025 /* Polaris11 */ 2026 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2027 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2028 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2029 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2030 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2031 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2032 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2033 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2034 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2035 /* Polaris10 */ 2036 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2037 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2038 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2039 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2040 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2041 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2042 {0x1002, 0x67D4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2043 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2044 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2045 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2046 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2047 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2048 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2049 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2050 /* Polaris12 */ 2051 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2052 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2053 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2054 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2055 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2056 {0x1002, 0x698F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2057 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2058 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2059 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2060 /* VEGAM */ 2061 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 2062 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 2063 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 2064 /* Vega 10 */ 2065 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2066 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2067 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2068 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2069 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2070 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2071 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2072 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2073 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2074 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2075 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2076 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2077 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2078 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2079 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2080 /* Vega 12 */ 2081 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2082 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2083 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2084 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2085 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2086 /* Vega 20 */ 2087 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2088 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2089 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2090 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2091 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2092 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2093 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2094 /* Raven */ 2095 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 2096 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 2097 /* Arcturus */ 2098 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2099 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2100 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2101 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2102 /* Navi10 */ 2103 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2104 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2105 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2106 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2107 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2108 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2109 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2110 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2111 /* Navi14 */ 2112 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2113 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2114 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2115 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2116 2117 /* Renoir */ 2118 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2119 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2120 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2121 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2122 2123 /* Navi12 */ 2124 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 2125 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 2126 2127 /* Sienna_Cichlid */ 2128 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2129 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2130 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2131 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2132 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2133 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2134 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2135 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2136 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2137 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2138 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2139 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2140 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2141 2142 /* Yellow Carp */ 2143 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 2144 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 2145 2146 /* Navy_Flounder */ 2147 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2148 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2149 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2150 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2151 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2152 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2153 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2154 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2155 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2156 2157 /* DIMGREY_CAVEFISH */ 2158 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2159 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2160 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2161 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2162 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2163 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2164 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2165 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2166 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2167 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2168 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2169 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2170 2171 /* Aldebaran */ 2172 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2173 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2174 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2175 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2176 2177 /* CYAN_SKILLFISH */ 2178 {0x1002, 0x13DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2179 {0x1002, 0x13F9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2180 {0x1002, 0x13FA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2181 {0x1002, 0x13FB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2182 {0x1002, 0x13FC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2183 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2184 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2185 2186 /* BEIGE_GOBY */ 2187 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2188 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2189 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2190 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2191 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2192 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2193 2194 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2195 .class = PCI_CLASS_DISPLAY_VGA << 8, 2196 .class_mask = 0xffffff, 2197 .driver_data = CHIP_IP_DISCOVERY }, 2198 2199 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2200 .class = PCI_CLASS_DISPLAY_OTHER << 8, 2201 .class_mask = 0xffffff, 2202 .driver_data = CHIP_IP_DISCOVERY }, 2203 2204 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2205 .class = PCI_CLASS_ACCELERATOR_PROCESSING << 8, 2206 .class_mask = 0xffffff, 2207 .driver_data = CHIP_IP_DISCOVERY }, 2208 2209 {0, 0, 0} 2210 }; 2211 2212 MODULE_DEVICE_TABLE(pci, pciidlist); 2213 2214 static const struct amdgpu_asic_type_quirk asic_type_quirks[] = { 2215 /* differentiate between P10 and P11 asics with the same DID */ 2216 {0x67FF, 0xE3, CHIP_POLARIS10}, 2217 {0x67FF, 0xE7, CHIP_POLARIS10}, 2218 {0x67FF, 0xF3, CHIP_POLARIS10}, 2219 {0x67FF, 0xF7, CHIP_POLARIS10}, 2220 }; 2221 2222 static const struct drm_driver amdgpu_kms_driver; 2223 2224 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 2225 { 2226 struct pci_dev *p = NULL; 2227 int i; 2228 2229 /* 0 - GPU 2230 * 1 - audio 2231 * 2 - USB 2232 * 3 - UCSI 2233 */ 2234 for (i = 1; i < 4; i++) { 2235 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 2236 adev->pdev->bus->number, i); 2237 if (p) { 2238 pm_runtime_get_sync(&p->dev); 2239 pm_runtime_put_autosuspend(&p->dev); 2240 pci_dev_put(p); 2241 } 2242 } 2243 } 2244 2245 static void amdgpu_init_debug_options(struct amdgpu_device *adev) 2246 { 2247 if (amdgpu_debug_mask & AMDGPU_DEBUG_VM) { 2248 pr_info("debug: VM handling debug enabled\n"); 2249 adev->debug_vm = true; 2250 } 2251 2252 if (amdgpu_debug_mask & AMDGPU_DEBUG_LARGEBAR) { 2253 pr_info("debug: enabled simulating large-bar capability on non-large bar system\n"); 2254 adev->debug_largebar = true; 2255 } 2256 2257 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY) { 2258 pr_info("debug: soft recovery disabled\n"); 2259 adev->debug_disable_soft_recovery = true; 2260 } 2261 2262 if (amdgpu_debug_mask & AMDGPU_DEBUG_USE_VRAM_FW_BUF) { 2263 pr_info("debug: place fw in vram for frontdoor loading\n"); 2264 adev->debug_use_vram_fw_buf = true; 2265 } 2266 2267 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_RAS_ACA) { 2268 pr_info("debug: enable RAS ACA\n"); 2269 adev->debug_enable_ras_aca = true; 2270 } 2271 2272 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_EXP_RESETS) { 2273 pr_info("debug: enable experimental reset features\n"); 2274 adev->debug_exp_resets = true; 2275 } 2276 2277 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_RING_RESET) { 2278 pr_info("debug: ring reset disabled\n"); 2279 adev->debug_disable_gpu_ring_reset = true; 2280 } 2281 if (amdgpu_debug_mask & AMDGPU_DEBUG_SMU_POOL) { 2282 pr_info("debug: use vram for smu pool\n"); 2283 adev->pm.smu_debug_mask |= SMU_DEBUG_POOL_USE_VRAM; 2284 } 2285 if (amdgpu_debug_mask & AMDGPU_DEBUG_VM_USERPTR) { 2286 pr_info("debug: VM mode debug for userptr is enabled\n"); 2287 adev->debug_vm_userptr = true; 2288 } 2289 2290 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_RAS_CE_LOG) { 2291 pr_info("debug: disable kernel logs of correctable errors\n"); 2292 adev->debug_disable_ce_logs = true; 2293 } 2294 2295 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_CE_CS) { 2296 pr_info("debug: allowing command submission to CE engine\n"); 2297 adev->debug_enable_ce_cs = true; 2298 } 2299 2300 if (amdgpu_debug_mask & AMDGPU_DEBUG_HIBERNATION_THAW_RESUME_GPU) { 2301 pr_info("debug: resume gpu in thaw() of hibernation\n"); 2302 adev->debug_hibernation_thaw_resume_gpu = true; 2303 } 2304 2305 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_IP_BLOCK_SOFT_RESET) { 2306 pr_info("debug: IP block soft reset disabled\n"); 2307 adev->debug_disable_ip_block_soft_reset = true; 2308 } 2309 } 2310 2311 static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long flags) 2312 { 2313 int i; 2314 2315 for (i = 0; i < ARRAY_SIZE(asic_type_quirks); i++) { 2316 if (pdev->device == asic_type_quirks[i].device && 2317 pdev->revision == asic_type_quirks[i].revision) { 2318 flags &= ~AMD_ASIC_MASK; 2319 flags |= asic_type_quirks[i].type; 2320 break; 2321 } 2322 } 2323 2324 return flags; 2325 } 2326 2327 static bool amdgpu_support_enabled(struct device *dev, 2328 const enum amd_asic_type family) 2329 { 2330 const char *gen; 2331 const char *param; 2332 int module_param = -1; 2333 bool radeon_support_built = IS_ENABLED(CONFIG_DRM_RADEON); 2334 bool amdgpu_support_built = false; 2335 bool support_by_default = false; 2336 2337 switch (family) { 2338 case CHIP_TAHITI: 2339 case CHIP_PITCAIRN: 2340 case CHIP_VERDE: 2341 case CHIP_OLAND: 2342 case CHIP_HAINAN: 2343 gen = "SI"; 2344 param = "si_support"; 2345 module_param = amdgpu_si_support; 2346 amdgpu_support_built = IS_ENABLED(CONFIG_DRM_AMDGPU_SI); 2347 support_by_default = true; 2348 break; 2349 2350 case CHIP_BONAIRE: 2351 case CHIP_HAWAII: 2352 case CHIP_KAVERI: 2353 case CHIP_KABINI: 2354 case CHIP_MULLINS: 2355 gen = "CIK"; 2356 param = "cik_support"; 2357 module_param = amdgpu_cik_support; 2358 amdgpu_support_built = IS_ENABLED(CONFIG_DRM_AMDGPU_CIK); 2359 support_by_default = true; 2360 break; 2361 2362 default: 2363 /* All other chips are supported by amdgpu only */ 2364 return true; 2365 } 2366 2367 if (!amdgpu_support_built) { 2368 dev_info(dev, "amdgpu built without %s support\n", gen); 2369 return false; 2370 } 2371 2372 if ((module_param == -1 && (support_by_default || !radeon_support_built)) || 2373 module_param == 1) { 2374 if (radeon_support_built) 2375 dev_info(dev, "%s support provided by amdgpu.\n" 2376 "Use radeon.%s=1 amdgpu.%s=0 to override.\n", 2377 gen, param, param); 2378 2379 return true; 2380 } 2381 2382 if (radeon_support_built) 2383 dev_info(dev, "%s support provided by radeon.\n" 2384 "Use radeon.%s=0 amdgpu.%s=1 to override.\n", 2385 gen, param, param); 2386 else if (module_param == 0) 2387 dev_info(dev, "%s support disabled by module param\n", gen); 2388 2389 return false; 2390 } 2391 2392 static int amdgpu_pci_probe(struct pci_dev *pdev, 2393 const struct pci_device_id *ent) 2394 { 2395 struct drm_device *ddev; 2396 struct amdgpu_device *adev; 2397 unsigned long flags = ent->driver_data; 2398 int ret, retry = 0, i; 2399 bool supports_atomic = false; 2400 2401 if ((pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA || 2402 (pdev->class >> 8) == PCI_CLASS_DISPLAY_OTHER) { 2403 if (drm_firmware_drivers_only() && amdgpu_modeset == -1) 2404 return -EINVAL; 2405 } 2406 2407 /* skip devices which are owned by radeon */ 2408 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2409 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2410 return -ENODEV; 2411 } 2412 2413 if (amdgpu_virtual_display || 2414 amdgpu_device_asic_has_dc_support(pdev, flags & AMD_ASIC_MASK)) 2415 supports_atomic = true; 2416 2417 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2418 dev_info(&pdev->dev, "This hardware requires experimental hardware support.\n" 2419 "See modparam exp_hw_support\n"); 2420 return -ENODEV; 2421 } 2422 2423 flags = amdgpu_fix_asic_type(pdev, flags); 2424 2425 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2426 * however, SME requires an indirect IOMMU mapping because the encryption 2427 * bit is beyond the DMA mask of the chip. 2428 */ 2429 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2430 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2431 dev_info(&pdev->dev, 2432 "SME is not compatible with RAVEN\n"); 2433 return -ENOTSUPP; 2434 } 2435 2436 if (!amdgpu_support_enabled(&pdev->dev, flags & AMD_ASIC_MASK)) 2437 return -ENODEV; 2438 2439 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2440 if (IS_ERR(adev)) 2441 return PTR_ERR(adev); 2442 2443 adev->dev = &pdev->dev; 2444 adev->pdev = pdev; 2445 ddev = adev_to_drm(adev); 2446 2447 if (!supports_atomic) 2448 ddev->driver_features &= ~DRIVER_ATOMIC; 2449 2450 ret = pci_enable_device(pdev); 2451 if (ret) 2452 return ret; 2453 2454 pci_set_drvdata(pdev, ddev); 2455 2456 amdgpu_init_debug_options(adev); 2457 2458 ret = amdgpu_driver_load_kms(adev, flags); 2459 if (ret) 2460 goto err_pci; 2461 2462 retry_init: 2463 ret = drm_dev_register(ddev, flags); 2464 if (ret == -EAGAIN && ++retry <= 3) { 2465 drm_info(adev_to_drm(adev), "retry init %d\n", retry); 2466 /* Don't request EX mode too frequently which is attacking */ 2467 msleep(5000); 2468 goto retry_init; 2469 } else if (ret) { 2470 goto err_pci; 2471 } 2472 2473 ret = amdgpu_xcp_dev_register(adev, ent); 2474 if (ret) 2475 goto err_pci; 2476 2477 ret = amdgpu_amdkfd_drm_client_create(adev); 2478 if (ret) 2479 goto err_pci; 2480 2481 /* 2482 * 1. don't init fbdev on hw without DCE 2483 * 2. don't init fbdev if there are no connectors 2484 */ 2485 if (adev->mode_info.mode_config_initialized && 2486 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2487 const struct drm_format_info *format; 2488 2489 /* select 8 bpp console on low vram cards */ 2490 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2491 format = drm_format_info(DRM_FORMAT_C8); 2492 else 2493 format = NULL; 2494 2495 drm_client_setup(adev_to_drm(adev), format); 2496 } 2497 2498 ret = amdgpu_debugfs_init(adev); 2499 if (ret) 2500 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2501 2502 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2503 /* only need to skip on ATPX */ 2504 if (amdgpu_device_supports_px(adev)) 2505 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2506 /* we want direct complete for BOCO */ 2507 if (amdgpu_device_supports_boco(adev)) 2508 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2509 DPM_FLAG_SMART_SUSPEND | 2510 DPM_FLAG_MAY_SKIP_RESUME); 2511 pm_runtime_use_autosuspend(ddev->dev); 2512 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2513 2514 pm_runtime_allow(ddev->dev); 2515 2516 pm_runtime_put_autosuspend(ddev->dev); 2517 2518 pci_wake_from_d3(pdev, TRUE); 2519 2520 /* 2521 * For runpm implemented via BACO, PMFW will handle the 2522 * timing for BACO in and out: 2523 * - put ASIC into BACO state only when both video and 2524 * audio functions are in D3 state. 2525 * - pull ASIC out of BACO state when either video or 2526 * audio function is in D0 state. 2527 * Also, at startup, PMFW assumes both functions are in 2528 * D0 state. 2529 * 2530 * So if snd driver was loaded prior to amdgpu driver 2531 * and audio function was put into D3 state, there will 2532 * be no PMFW-aware D-state transition(D0->D3) on runpm 2533 * suspend. Thus the BACO will be not correctly kicked in. 2534 * 2535 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2536 * into D0 state. Then there will be a PMFW-aware D-state 2537 * transition(D0->D3) on runpm suspend. 2538 */ 2539 if (amdgpu_device_supports_baco(adev) && 2540 !(adev->flags & AMD_IS_APU) && 2541 adev->asic_type >= CHIP_NAVI10) 2542 amdgpu_get_secondary_funcs(adev); 2543 } 2544 2545 return 0; 2546 2547 err_pci: 2548 pci_disable_device(pdev); 2549 return ret; 2550 } 2551 2552 static void 2553 amdgpu_pci_remove(struct pci_dev *pdev) 2554 { 2555 struct drm_device *dev = pci_get_drvdata(pdev); 2556 struct amdgpu_device *adev = drm_to_adev(dev); 2557 2558 amdgpu_ras_eeprom_check_and_recover(adev); 2559 amdgpu_xcp_dev_unplug(adev); 2560 amdgpu_gmc_prepare_nps_mode_change(adev); 2561 drm_dev_unplug(dev); 2562 2563 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2564 pm_runtime_get_sync(dev->dev); 2565 pm_runtime_forbid(dev->dev); 2566 } 2567 2568 amdgpu_driver_unload_kms(dev); 2569 2570 amdgpu_discovery_sysfs_early_fini(pdev); 2571 2572 /* 2573 * Flush any in flight DMA operations from device. 2574 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2575 * StatusTransactions Pending bit. 2576 */ 2577 pci_disable_device(pdev); 2578 pci_wait_for_pending_transaction(pdev); 2579 } 2580 2581 static void 2582 amdgpu_pci_shutdown(struct pci_dev *pdev) 2583 { 2584 struct drm_device *dev = pci_get_drvdata(pdev); 2585 struct amdgpu_device *adev = drm_to_adev(dev); 2586 2587 if (amdgpu_ras_intr_triggered()) 2588 return; 2589 2590 /* device maybe not resumed here, return immediately in this case */ 2591 if (adev->in_s4 && adev->in_suspend) 2592 return; 2593 2594 /* if we are running in a VM, make sure the device 2595 * torn down properly on reboot/shutdown. 2596 * unfortunately we can't detect certain 2597 * hypervisors so just do this all the time. 2598 */ 2599 if (!amdgpu_passthrough(adev)) 2600 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2601 amdgpu_device_prepare(dev); 2602 amdgpu_device_suspend(dev, true); 2603 adev->mp1_state = PP_MP1_STATE_NONE; 2604 } 2605 2606 static int amdgpu_pmops_prepare(struct device *dev) 2607 { 2608 struct drm_device *drm_dev = dev_get_drvdata(dev); 2609 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2610 2611 /* device maybe not resumed here, return immediately in this case */ 2612 if (adev->in_s4 && adev->in_suspend) 2613 return 0; 2614 2615 /* Return a positive number here so 2616 * DPM_FLAG_SMART_SUSPEND works properly 2617 */ 2618 if (amdgpu_device_supports_boco(adev) && pm_runtime_suspended(dev)) 2619 return 1; 2620 2621 /* if we will not support s3 or s2i for the device 2622 * then skip suspend 2623 */ 2624 if (!amdgpu_acpi_is_s0ix_active(adev) && 2625 !amdgpu_acpi_is_s3_active(adev)) 2626 return 1; 2627 2628 return amdgpu_device_prepare(drm_dev); 2629 } 2630 2631 static void amdgpu_pmops_complete(struct device *dev) 2632 { 2633 amdgpu_device_complete(dev_get_drvdata(dev)); 2634 } 2635 2636 static int amdgpu_pmops_suspend(struct device *dev) 2637 { 2638 struct drm_device *drm_dev = dev_get_drvdata(dev); 2639 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2640 2641 if (amdgpu_acpi_is_s0ix_active(adev)) 2642 adev->in_s0ix = true; 2643 else if (amdgpu_acpi_is_s3_active(adev)) 2644 adev->in_s3 = true; 2645 if (!adev->in_s0ix && !adev->in_s3) { 2646 #if IS_ENABLED(CONFIG_SUSPEND) 2647 /* don't allow going deep first time followed by s2idle the next time */ 2648 if (adev->last_suspend_state != PM_SUSPEND_ON && 2649 adev->last_suspend_state != pm_suspend_target_state) { 2650 drm_err_once(drm_dev, "Unsupported suspend state %d\n", 2651 pm_suspend_target_state); 2652 return -EINVAL; 2653 } 2654 #endif 2655 return 0; 2656 } 2657 2658 #if IS_ENABLED(CONFIG_SUSPEND) 2659 /* cache the state last used for suspend */ 2660 adev->last_suspend_state = pm_suspend_target_state; 2661 #endif 2662 2663 return amdgpu_device_suspend(drm_dev, true); 2664 } 2665 2666 static int amdgpu_pmops_suspend_noirq(struct device *dev) 2667 { 2668 struct drm_device *drm_dev = dev_get_drvdata(dev); 2669 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2670 int r; 2671 2672 if (amdgpu_acpi_should_gpu_reset(adev)) { 2673 amdgpu_device_lock_reset_domain(adev->reset_domain); 2674 r = amdgpu_asic_reset(adev); 2675 amdgpu_device_unlock_reset_domain(adev->reset_domain); 2676 return r; 2677 } 2678 2679 return 0; 2680 } 2681 2682 static int amdgpu_pmops_resume(struct device *dev) 2683 { 2684 struct drm_device *drm_dev = dev_get_drvdata(dev); 2685 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2686 int r; 2687 2688 if (!adev->in_s0ix && !adev->in_s3) 2689 return 0; 2690 2691 /* Avoids registers access if device is physically gone */ 2692 if (!pci_device_is_present(adev->pdev)) 2693 adev->no_hw_access = true; 2694 2695 r = amdgpu_device_resume(drm_dev, true); 2696 if (amdgpu_acpi_is_s0ix_active(adev)) 2697 adev->in_s0ix = false; 2698 else 2699 adev->in_s3 = false; 2700 return r; 2701 } 2702 2703 static int amdgpu_pmops_freeze(struct device *dev) 2704 { 2705 struct drm_device *drm_dev = dev_get_drvdata(dev); 2706 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2707 int r; 2708 2709 r = amdgpu_device_suspend(drm_dev, true); 2710 if (r) 2711 return r; 2712 2713 if (amdgpu_acpi_should_gpu_reset(adev)) { 2714 amdgpu_device_lock_reset_domain(adev->reset_domain); 2715 r = amdgpu_asic_reset(adev); 2716 amdgpu_device_unlock_reset_domain(adev->reset_domain); 2717 return r; 2718 } 2719 return 0; 2720 } 2721 2722 static int amdgpu_pmops_thaw(struct device *dev) 2723 { 2724 struct drm_device *drm_dev = dev_get_drvdata(dev); 2725 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2726 2727 /* do not resume device if it's normal hibernation */ 2728 if (!adev->debug_hibernation_thaw_resume_gpu && 2729 !pm_hibernate_is_recovering() && 2730 !pm_hibernation_mode_is_suspend()) 2731 return 0; 2732 2733 return amdgpu_device_resume(drm_dev, true); 2734 } 2735 2736 static int amdgpu_pmops_poweroff(struct device *dev) 2737 { 2738 struct drm_device *drm_dev = dev_get_drvdata(dev); 2739 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2740 2741 /* device maybe not resumed here, return immediately in this case */ 2742 if (adev->in_s4 && adev->in_suspend) 2743 return 0; 2744 2745 return amdgpu_device_suspend(drm_dev, true); 2746 } 2747 2748 static int amdgpu_pmops_restore(struct device *dev) 2749 { 2750 struct drm_device *drm_dev = dev_get_drvdata(dev); 2751 2752 return amdgpu_device_resume(drm_dev, true); 2753 } 2754 2755 static int amdgpu_runtime_idle_check_display(struct device *dev) 2756 { 2757 struct pci_dev *pdev = to_pci_dev(dev); 2758 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2759 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2760 2761 if (adev->mode_info.num_crtc) { 2762 struct drm_connector *list_connector; 2763 struct drm_connector_list_iter iter; 2764 int ret = 0; 2765 2766 if (amdgpu_runtime_pm != -2) { 2767 /* XXX: Return busy if any displays are connected to avoid 2768 * possible display wakeups after runtime resume due to 2769 * hotplug events in case any displays were connected while 2770 * the GPU was in suspend. Remove this once that is fixed. 2771 */ 2772 mutex_lock(&drm_dev->mode_config.mutex); 2773 drm_connector_list_iter_begin(drm_dev, &iter); 2774 drm_for_each_connector_iter(list_connector, &iter) { 2775 if (list_connector->status == connector_status_connected) { 2776 ret = -EBUSY; 2777 break; 2778 } 2779 } 2780 drm_connector_list_iter_end(&iter); 2781 mutex_unlock(&drm_dev->mode_config.mutex); 2782 2783 if (ret) 2784 return ret; 2785 } 2786 2787 if (adev->dc_enabled) { 2788 struct drm_crtc *crtc; 2789 2790 drm_for_each_crtc(crtc, drm_dev) { 2791 drm_modeset_lock(&crtc->mutex, NULL); 2792 if (crtc->state->active) 2793 ret = -EBUSY; 2794 drm_modeset_unlock(&crtc->mutex); 2795 if (ret < 0) 2796 break; 2797 } 2798 } else { 2799 mutex_lock(&drm_dev->mode_config.mutex); 2800 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2801 2802 drm_connector_list_iter_begin(drm_dev, &iter); 2803 drm_for_each_connector_iter(list_connector, &iter) { 2804 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2805 ret = -EBUSY; 2806 break; 2807 } 2808 } 2809 2810 drm_connector_list_iter_end(&iter); 2811 2812 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2813 mutex_unlock(&drm_dev->mode_config.mutex); 2814 } 2815 if (ret) 2816 return ret; 2817 } 2818 2819 return 0; 2820 } 2821 2822 static int amdgpu_runtime_idle_check_userq(struct device *dev) 2823 { 2824 struct pci_dev *pdev = to_pci_dev(dev); 2825 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2826 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2827 2828 return xa_empty(&adev->userq_doorbell_xa) ? 0 : -EBUSY; 2829 } 2830 2831 static int amdgpu_pmops_runtime_checks(struct device *dev) 2832 { 2833 struct drm_device *drm_dev = dev_get_drvdata(dev); 2834 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2835 int ret; 2836 2837 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2838 pm_runtime_forbid(dev); 2839 return -EBUSY; 2840 } 2841 2842 ret = amdgpu_runtime_idle_check_display(dev); 2843 if (ret) 2844 return ret; 2845 2846 return amdgpu_runtime_idle_check_userq(dev); 2847 } 2848 2849 static int amdgpu_pmops_runtime_idle(struct device *dev) 2850 { 2851 int ret; 2852 2853 ret = amdgpu_pmops_runtime_checks(dev); 2854 pm_runtime_autosuspend(dev); 2855 return ret; 2856 } 2857 2858 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2859 { 2860 struct pci_dev *pdev = to_pci_dev(dev); 2861 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2862 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2863 int ret, i; 2864 2865 ret = amdgpu_pmops_runtime_checks(dev); 2866 if (ret) 2867 return ret; 2868 2869 /* wait for all rings to drain before suspending */ 2870 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2871 struct amdgpu_ring *ring = adev->rings[i]; 2872 2873 if (ring && ring->sched.ready) { 2874 ret = amdgpu_fence_wait_empty(ring); 2875 if (ret) 2876 return -EBUSY; 2877 } 2878 } 2879 2880 adev->in_runpm = true; 2881 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2882 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2883 2884 /* 2885 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2886 * proper cleanups and put itself into a state ready for PNP. That 2887 * can address some random resuming failure observed on BOCO capable 2888 * platforms. 2889 * TODO: this may be also needed for PX capable platform. 2890 */ 2891 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2892 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2893 2894 ret = amdgpu_device_prepare(drm_dev); 2895 if (ret) 2896 return ret; 2897 ret = amdgpu_device_suspend(drm_dev, false); 2898 if (ret) { 2899 adev->in_runpm = false; 2900 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2901 adev->mp1_state = PP_MP1_STATE_NONE; 2902 return ret; 2903 } 2904 2905 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2906 adev->mp1_state = PP_MP1_STATE_NONE; 2907 2908 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) { 2909 /* Only need to handle PCI state in the driver for ATPX 2910 * PCI core handles it for _PR3. 2911 */ 2912 amdgpu_device_cache_pci_state(pdev); 2913 pci_disable_device(pdev); 2914 pci_ignore_hotplug(pdev); 2915 pci_set_power_state(pdev, PCI_D3cold); 2916 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2917 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) { 2918 /* nothing to do */ 2919 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2920 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) { 2921 amdgpu_device_baco_enter(adev); 2922 } 2923 2924 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n"); 2925 2926 return 0; 2927 } 2928 2929 static int amdgpu_pmops_runtime_resume(struct device *dev) 2930 { 2931 struct pci_dev *pdev = to_pci_dev(dev); 2932 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2933 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2934 int ret; 2935 2936 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) 2937 return -EINVAL; 2938 2939 /* Avoids registers access if device is physically gone */ 2940 if (!pci_device_is_present(adev->pdev)) 2941 adev->no_hw_access = true; 2942 2943 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) { 2944 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2945 2946 /* Only need to handle PCI state in the driver for ATPX 2947 * PCI core handles it for _PR3. 2948 */ 2949 pci_set_power_state(pdev, PCI_D0); 2950 amdgpu_device_load_pci_state(pdev); 2951 ret = pci_enable_device(pdev); 2952 if (ret) 2953 return ret; 2954 pci_set_master(pdev); 2955 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) { 2956 /* Only need to handle PCI state in the driver for ATPX 2957 * PCI core handles it for _PR3. 2958 */ 2959 pci_set_master(pdev); 2960 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2961 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) { 2962 amdgpu_device_baco_exit(adev); 2963 } 2964 ret = amdgpu_device_resume(drm_dev, false); 2965 if (ret) { 2966 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2967 pci_disable_device(pdev); 2968 return ret; 2969 } 2970 2971 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2972 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2973 adev->in_runpm = false; 2974 return 0; 2975 } 2976 2977 static int amdgpu_drm_release(struct inode *inode, struct file *filp) 2978 { 2979 struct drm_file *file_priv = filp->private_data; 2980 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2981 struct drm_device *dev = file_priv->minor->dev; 2982 int idx; 2983 2984 if (fpriv && drm_dev_enter(dev, &idx)) { 2985 amdgpu_evf_mgr_shutdown(&fpriv->evf_mgr); 2986 amdgpu_userq_mgr_cancel_resume(&fpriv->userq_mgr); 2987 amdgpu_evf_mgr_flush_suspend(&fpriv->evf_mgr); 2988 amdgpu_userq_mgr_fini(&fpriv->userq_mgr); 2989 amdgpu_evf_mgr_fini(&fpriv->evf_mgr); 2990 drm_dev_exit(idx); 2991 } 2992 2993 return drm_release(inode, filp); 2994 } 2995 2996 long amdgpu_drm_ioctl(struct file *filp, 2997 unsigned int cmd, unsigned long arg) 2998 { 2999 struct drm_file *file_priv = filp->private_data; 3000 struct drm_device *dev; 3001 long ret; 3002 3003 dev = file_priv->minor->dev; 3004 ret = pm_runtime_get_sync(dev->dev); 3005 if (ret < 0) 3006 goto out; 3007 3008 ret = drm_ioctl(filp, cmd, arg); 3009 3010 out: 3011 pm_runtime_put_autosuspend(dev->dev); 3012 return ret; 3013 } 3014 3015 static const struct dev_pm_ops amdgpu_pm_ops = { 3016 .prepare = pm_sleep_ptr(amdgpu_pmops_prepare), 3017 .complete = pm_sleep_ptr(amdgpu_pmops_complete), 3018 .suspend = pm_sleep_ptr(amdgpu_pmops_suspend), 3019 .suspend_noirq = pm_sleep_ptr(amdgpu_pmops_suspend_noirq), 3020 .resume = pm_sleep_ptr(amdgpu_pmops_resume), 3021 .freeze = pm_sleep_ptr(amdgpu_pmops_freeze), 3022 .thaw = pm_sleep_ptr(amdgpu_pmops_thaw), 3023 .poweroff = pm_sleep_ptr(amdgpu_pmops_poweroff), 3024 .restore = pm_sleep_ptr(amdgpu_pmops_restore), 3025 .runtime_suspend = amdgpu_pmops_runtime_suspend, 3026 .runtime_resume = amdgpu_pmops_runtime_resume, 3027 .runtime_idle = amdgpu_pmops_runtime_idle, 3028 }; 3029 3030 static int amdgpu_flush(struct file *f, fl_owner_t id) 3031 { 3032 struct drm_file *file_priv = f->private_data; 3033 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 3034 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 3035 3036 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 3037 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 3038 3039 return timeout >= 0 ? 0 : timeout; 3040 } 3041 3042 static const struct file_operations amdgpu_driver_kms_fops = { 3043 .owner = THIS_MODULE, 3044 .open = drm_open, 3045 .flush = amdgpu_flush, 3046 .release = amdgpu_drm_release, 3047 .unlocked_ioctl = amdgpu_drm_ioctl, 3048 .mmap = drm_gem_mmap, 3049 .poll = drm_poll, 3050 .read = drm_read, 3051 #ifdef CONFIG_COMPAT 3052 .compat_ioctl = amdgpu_kms_compat_ioctl, 3053 #endif 3054 #ifdef CONFIG_PROC_FS 3055 .show_fdinfo = drm_show_fdinfo, 3056 #endif 3057 .fop_flags = FOP_UNSIGNED_OFFSET, 3058 }; 3059 3060 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 3061 { 3062 struct drm_file *file; 3063 3064 if (!filp) 3065 return -EINVAL; 3066 3067 if (filp->f_op != &amdgpu_driver_kms_fops) 3068 return -EINVAL; 3069 3070 file = filp->private_data; 3071 *fpriv = file->driver_priv; 3072 return 0; 3073 } 3074 3075 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 3076 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3077 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3078 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3079 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 3080 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3081 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3082 /* KMS */ 3083 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3084 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3085 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3086 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3087 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3088 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3089 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3090 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3091 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3092 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3093 DRM_IOCTL_DEF_DRV(AMDGPU_USERQ, amdgpu_userq_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3094 DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_SIGNAL, amdgpu_userq_signal_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3095 DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_WAIT, amdgpu_userq_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3096 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_LIST_HANDLES, amdgpu_gem_list_handles_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3097 DRM_IOCTL_DEF_DRV(AMDGPU_PROC_OPTIONS, amdgpu_proc_options_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3098 }; 3099 3100 static const struct drm_driver amdgpu_kms_driver = { 3101 .driver_features = 3102 DRIVER_ATOMIC | 3103 DRIVER_GEM | 3104 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 3105 DRIVER_SYNCOBJ_TIMELINE, 3106 .open = amdgpu_driver_open_kms, 3107 .postclose = amdgpu_driver_postclose_kms, 3108 .ioctls = amdgpu_ioctls_kms, 3109 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 3110 .dumb_create = amdgpu_mode_dumb_create, 3111 .dumb_map_offset = amdgpu_mode_dumb_mmap, 3112 DRM_FBDEV_TTM_DRIVER_OPS, 3113 .fops = &amdgpu_driver_kms_fops, 3114 .release = &amdgpu_driver_release_kms, 3115 #ifdef CONFIG_PROC_FS 3116 .show_fdinfo = amdgpu_show_fdinfo, 3117 #endif 3118 3119 .gem_prime_import = amdgpu_gem_prime_import, 3120 3121 .name = DRIVER_NAME, 3122 .desc = DRIVER_DESC, 3123 .major = KMS_DRIVER_MAJOR, 3124 .minor = KMS_DRIVER_MINOR, 3125 .patchlevel = KMS_DRIVER_PATCHLEVEL, 3126 }; 3127 3128 const struct drm_driver amdgpu_partition_driver = { 3129 .driver_features = 3130 DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ | 3131 DRIVER_SYNCOBJ_TIMELINE, 3132 .open = amdgpu_driver_open_kms, 3133 .postclose = amdgpu_driver_postclose_kms, 3134 .ioctls = amdgpu_ioctls_kms, 3135 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 3136 .dumb_create = amdgpu_mode_dumb_create, 3137 .dumb_map_offset = amdgpu_mode_dumb_mmap, 3138 DRM_FBDEV_TTM_DRIVER_OPS, 3139 .fops = &amdgpu_driver_kms_fops, 3140 .release = &amdgpu_driver_release_kms, 3141 3142 .gem_prime_import = amdgpu_gem_prime_import, 3143 3144 .name = DRIVER_NAME, 3145 .desc = DRIVER_DESC, 3146 .major = KMS_DRIVER_MAJOR, 3147 .minor = KMS_DRIVER_MINOR, 3148 .patchlevel = KMS_DRIVER_PATCHLEVEL, 3149 }; 3150 3151 static struct pci_error_handlers amdgpu_pci_err_handler = { 3152 .error_detected = amdgpu_pci_error_detected, 3153 .mmio_enabled = amdgpu_pci_mmio_enabled, 3154 .slot_reset = amdgpu_pci_slot_reset, 3155 .resume = amdgpu_pci_resume, 3156 }; 3157 3158 static const struct attribute_group *amdgpu_sysfs_groups[] = { 3159 &amdgpu_vram_mgr_attr_group, 3160 &amdgpu_gtt_mgr_attr_group, 3161 &amdgpu_flash_attr_group, 3162 NULL, 3163 }; 3164 3165 static struct pci_driver amdgpu_kms_pci_driver = { 3166 .name = DRIVER_NAME, 3167 .id_table = pciidlist, 3168 .probe = amdgpu_pci_probe, 3169 .remove = amdgpu_pci_remove, 3170 .shutdown = amdgpu_pci_shutdown, 3171 .driver.pm = pm_ptr(&amdgpu_pm_ops), 3172 .err_handler = &amdgpu_pci_err_handler, 3173 .dev_groups = amdgpu_sysfs_groups, 3174 }; 3175 3176 static int __init amdgpu_init(void) 3177 { 3178 int r; 3179 3180 /* Train lockdep on correct lock ordering */ 3181 amdgpu_lockdep_init(); 3182 3183 r = amdgpu_sync_init(); 3184 if (r) 3185 return r; 3186 3187 amdgpu_register_atpx_handler(); 3188 amdgpu_acpi_detect(); 3189 3190 /* Ignore KFD init failures when CONFIG_HSA_AMD is not set. */ 3191 r = amdgpu_amdkfd_init(); 3192 if (r && r != -ENOENT) 3193 goto error_fini_sync; 3194 3195 if (amdgpu_pp_feature_mask & PP_OVERDRIVE_MASK) { 3196 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 3197 pr_crit("Overdrive is enabled, please disable it before " 3198 "reporting any bugs unrelated to overdrive.\n"); 3199 } 3200 3201 /* let modprobe override vga console setting */ 3202 return pci_register_driver(&amdgpu_kms_pci_driver); 3203 3204 error_fini_sync: 3205 amdgpu_sync_fini(); 3206 return r; 3207 } 3208 3209 static void __exit amdgpu_exit(void) 3210 { 3211 amdgpu_amdkfd_fini(); 3212 pci_unregister_driver(&amdgpu_kms_pci_driver); 3213 amdgpu_unregister_atpx_handler(); 3214 amdgpu_acpi_release(); 3215 amdgpu_sync_fini(); 3216 mmu_notifier_synchronize(); 3217 amdgpu_xcp_drv_release(); 3218 3219 /* 3220 * Flush outstanding call_rcu() callbacks before the 3221 * module text is freed. Otherwise a grace period elapsing after 3222 * unload invokes a callback in already-freed module memory and 3223 * faults in rcu_do_batch(). 3224 */ 3225 rcu_barrier(); 3226 } 3227 3228 module_init(amdgpu_init); 3229 module_exit(amdgpu_exit); 3230 3231 MODULE_AUTHOR(DRIVER_AUTHOR); 3232 MODULE_DESCRIPTION(DRIVER_DESC); 3233 MODULE_LICENSE("GPL and additional rights"); 3234