1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/clients/drm_client_setup.h> 27 #include <drm/drm_drv.h> 28 #include <drm/drm_fbdev_ttm.h> 29 #include <drm/drm_gem.h> 30 #include <drm/drm_managed.h> 31 #include <drm/drm_pciids.h> 32 #include <drm/drm_probe_helper.h> 33 #include <drm/drm_vblank.h> 34 35 #include <linux/cc_platform.h> 36 #include <linux/dynamic_debug.h> 37 #include <linux/module.h> 38 #include <linux/mmu_notifier.h> 39 #include <linux/pm_runtime.h> 40 #include <linux/suspend.h> 41 #include <linux/vga_switcheroo.h> 42 43 #include "amdgpu.h" 44 #include "amdgpu_amdkfd.h" 45 #include "amdgpu_dma_buf.h" 46 #include "amdgpu_drv.h" 47 #include "amdgpu_fdinfo.h" 48 #include "amdgpu_irq.h" 49 #include "amdgpu_psp.h" 50 #include "amdgpu_ras.h" 51 #include "amdgpu_reset.h" 52 #include "amdgpu_sched.h" 53 #include "amdgpu_xgmi.h" 54 #include "amdgpu_userqueue.h" 55 #include "amdgpu_userq_fence.h" 56 #include "../amdxcp/amdgpu_xcp_drv.h" 57 58 /* 59 * KMS wrapper. 60 * - 3.0.0 - initial driver 61 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 62 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 63 * at the end of IBs. 64 * - 3.3.0 - Add VM support for UVD on supported hardware. 65 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 66 * - 3.5.0 - Add support for new UVD_NO_OP register. 67 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 68 * - 3.7.0 - Add support for VCE clock list packet 69 * - 3.8.0 - Add support raster config init in the kernel 70 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 71 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 72 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 73 * - 3.12.0 - Add query for double offchip LDS buffers 74 * - 3.13.0 - Add PRT support 75 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 76 * - 3.15.0 - Export more gpu info for gfx9 77 * - 3.16.0 - Add reserved vmid support 78 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 79 * - 3.18.0 - Export gpu always on cu bitmap 80 * - 3.19.0 - Add support for UVD MJPEG decode 81 * - 3.20.0 - Add support for local BOs 82 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 83 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 84 * - 3.23.0 - Add query for VRAM lost counter 85 * - 3.24.0 - Add high priority compute support for gfx9 86 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 87 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 88 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation. 89 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 90 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 91 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 92 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 93 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 94 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 95 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 96 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 97 * - 3.36.0 - Allow reading more status registers on si/cik 98 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 99 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 100 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 101 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 102 * - 3.41.0 - Add video codec query 103 * - 3.42.0 - Add 16bpc fixed point display support 104 * - 3.43.0 - Add device hot plug/unplug support 105 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 106 * - 3.45.0 - Add context ioctl stable pstate interface 107 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm 108 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags 109 * - 3.48.0 - Add IP discovery version info to HW INFO 110 * - 3.49.0 - Add gang submit into CS IOCTL 111 * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock 112 * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock 113 * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl 114 * 3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields: 115 * tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size, 116 * gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi 117 * 3.53.0 - Support for GFX11 CP GFX shadowing 118 * 3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support 119 * - 3.55.0 - Add AMDGPU_INFO_GPUVM_FAULT query 120 * - 3.56.0 - Update IB start address and size alignment for decode and encode 121 * - 3.57.0 - Compute tunneling on GFX10+ 122 * - 3.58.0 - Add GFX12 DCC support 123 * - 3.59.0 - Cleared VRAM 124 * - 3.60.0 - Add AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE (Vulkan requirement) 125 * - 3.61.0 - Contains fix for RV/PCO compute queues 126 * - 3.62.0 - Add AMDGPU_IDS_FLAGS_MODE_PF, AMDGPU_IDS_FLAGS_MODE_VF & AMDGPU_IDS_FLAGS_MODE_PT 127 * - 3.63.0 - GFX12 display DCC supports 256B max compressed block size 128 * - 3.64.0 - Userq IP support query 129 */ 130 #define KMS_DRIVER_MAJOR 3 131 #define KMS_DRIVER_MINOR 64 132 #define KMS_DRIVER_PATCHLEVEL 0 133 134 /* 135 * amdgpu.debug module options. Are all disabled by default 136 */ 137 enum AMDGPU_DEBUG_MASK { 138 AMDGPU_DEBUG_VM = BIT(0), 139 AMDGPU_DEBUG_LARGEBAR = BIT(1), 140 AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY = BIT(2), 141 AMDGPU_DEBUG_USE_VRAM_FW_BUF = BIT(3), 142 AMDGPU_DEBUG_ENABLE_RAS_ACA = BIT(4), 143 AMDGPU_DEBUG_ENABLE_EXP_RESETS = BIT(5), 144 AMDGPU_DEBUG_DISABLE_GPU_RING_RESET = BIT(6), 145 AMDGPU_DEBUG_SMU_POOL = BIT(7), 146 }; 147 148 unsigned int amdgpu_vram_limit = UINT_MAX; 149 int amdgpu_vis_vram_limit; 150 int amdgpu_gart_size = -1; /* auto */ 151 int amdgpu_gtt_size = -1; /* auto */ 152 int amdgpu_moverate = -1; /* auto */ 153 int amdgpu_audio = -1; 154 int amdgpu_disp_priority; 155 int amdgpu_hw_i2c; 156 int amdgpu_pcie_gen2 = -1; 157 int amdgpu_msi = -1; 158 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 159 int amdgpu_dpm = -1; 160 int amdgpu_fw_load_type = -1; 161 int amdgpu_aspm = -1; 162 int amdgpu_runtime_pm = -1; 163 uint amdgpu_ip_block_mask = 0xffffffff; 164 int amdgpu_bapm = -1; 165 int amdgpu_deep_color; 166 int amdgpu_vm_size = -1; 167 int amdgpu_vm_fragment_size = -1; 168 int amdgpu_vm_block_size = -1; 169 int amdgpu_vm_fault_stop; 170 int amdgpu_vm_update_mode = -1; 171 int amdgpu_exp_hw_support; 172 int amdgpu_dc = -1; 173 int amdgpu_sched_jobs = 32; 174 int amdgpu_sched_hw_submission = 2; 175 uint amdgpu_pcie_gen_cap; 176 uint amdgpu_pcie_lane_cap; 177 u64 amdgpu_cg_mask = 0xffffffffffffffff; 178 uint amdgpu_pg_mask = 0xffffffff; 179 uint amdgpu_sdma_phase_quantum = 32; 180 char *amdgpu_disable_cu; 181 char *amdgpu_virtual_display; 182 int amdgpu_enforce_isolation = -1; 183 int amdgpu_modeset = -1; 184 185 /* Specifies the default granularity for SVM, used in buffer 186 * migration and restoration of backing memory when handling 187 * recoverable page faults. 188 * 189 * The value is given as log(numPages(buffer)); for a 2 MiB 190 * buffer it computes to be 9 191 */ 192 uint amdgpu_svm_default_granularity = 9; 193 194 /* 195 * OverDrive(bit 14) disabled by default 196 * GFX DCS(bit 19) disabled by default 197 */ 198 uint amdgpu_pp_feature_mask = 0xfff7bfff; 199 uint amdgpu_force_long_training; 200 int amdgpu_lbpw = -1; 201 int amdgpu_compute_multipipe = -1; 202 int amdgpu_gpu_recovery = -1; /* auto */ 203 int amdgpu_emu_mode; 204 uint amdgpu_smu_memory_pool_size; 205 int amdgpu_smu_pptable_id = -1; 206 /* 207 * FBC (bit 0) disabled by default 208 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 209 * - With this, for multiple monitors in sync(e.g. with the same model), 210 * mclk switching will be allowed. And the mclk will be not foced to the 211 * highest. That helps saving some idle power. 212 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 213 * PSR (bit 3) disabled by default 214 * EDP NO POWER SEQUENCING (bit 4) disabled by default 215 */ 216 uint amdgpu_dc_feature_mask = 2; 217 uint amdgpu_dc_debug_mask; 218 uint amdgpu_dc_visual_confirm; 219 int amdgpu_async_gfx_ring = 1; 220 int amdgpu_mcbp = -1; 221 int amdgpu_discovery = -1; 222 int amdgpu_mes; 223 int amdgpu_mes_log_enable = 0; 224 int amdgpu_mes_kiq; 225 int amdgpu_uni_mes = 1; 226 int amdgpu_noretry = -1; 227 int amdgpu_force_asic_type = -1; 228 int amdgpu_tmz = -1; /* auto */ 229 uint amdgpu_freesync_vid_mode; 230 int amdgpu_reset_method = -1; /* auto */ 231 int amdgpu_num_kcq = -1; 232 int amdgpu_smartshift_bias; 233 int amdgpu_use_xgmi_p2p = 1; 234 int amdgpu_vcnfw_log; 235 int amdgpu_sg_display = -1; /* auto */ 236 int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE; 237 int amdgpu_umsch_mm; 238 int amdgpu_seamless = -1; /* auto */ 239 uint amdgpu_debug_mask; 240 int amdgpu_agp = -1; /* auto */ 241 int amdgpu_wbrf = -1; 242 int amdgpu_damage_clips = -1; /* auto */ 243 int amdgpu_umsch_mm_fwlog; 244 int amdgpu_rebar = -1; /* auto */ 245 int amdgpu_disable_kq = -1; 246 247 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 248 "DRM_UT_CORE", 249 "DRM_UT_DRIVER", 250 "DRM_UT_KMS", 251 "DRM_UT_PRIME", 252 "DRM_UT_ATOMIC", 253 "DRM_UT_VBL", 254 "DRM_UT_STATE", 255 "DRM_UT_LEASE", 256 "DRM_UT_DP", 257 "DRM_UT_DRMRES"); 258 259 struct amdgpu_mgpu_info mgpu_info = { 260 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 261 }; 262 int amdgpu_ras_enable = -1; 263 uint amdgpu_ras_mask = 0xffffffff; 264 int amdgpu_bad_page_threshold = -1; 265 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 266 .timeout_fatal_disable = false, 267 .period = 0x0, /* default to 0x0 (timeout disable) */ 268 }; 269 270 /** 271 * DOC: vramlimit (int) 272 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 273 */ 274 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 275 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 276 277 /** 278 * DOC: vis_vramlimit (int) 279 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 280 */ 281 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 282 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 283 284 /** 285 * DOC: gartsize (uint) 286 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing. 287 * The default is -1 (The size depends on asic). 288 */ 289 MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)"); 290 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 291 292 /** 293 * DOC: gttsize (int) 294 * Restrict the size of GTT domain (for userspace use) in MiB for testing. 295 * The default is -1 (Use value specified by TTM). 296 * This parameter is deprecated and will be removed in the future. 297 */ 298 MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)"); 299 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 300 301 /** 302 * DOC: moverate (int) 303 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 304 */ 305 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 306 module_param_named(moverate, amdgpu_moverate, int, 0600); 307 308 /** 309 * DOC: audio (int) 310 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 311 */ 312 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 313 module_param_named(audio, amdgpu_audio, int, 0444); 314 315 /** 316 * DOC: disp_priority (int) 317 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 318 */ 319 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 320 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 321 322 /** 323 * DOC: hw_i2c (int) 324 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 325 */ 326 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 327 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 328 329 /** 330 * DOC: pcie_gen2 (int) 331 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 332 */ 333 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 334 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 335 336 /** 337 * DOC: msi (int) 338 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 339 */ 340 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 341 module_param_named(msi, amdgpu_msi, int, 0444); 342 343 /** 344 * DOC: svm_default_granularity (uint) 345 * Used in buffer migration and handling of recoverable page faults 346 */ 347 MODULE_PARM_DESC(svm_default_granularity, "SVM's default granularity in log(2^Pages), default 9 = 2^9 = 2 MiB"); 348 module_param_named(svm_default_granularity, amdgpu_svm_default_granularity, uint, 0644); 349 350 /** 351 * DOC: lockup_timeout (string) 352 * Set GPU scheduler timeout value in ms. 353 * 354 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 355 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 356 * to the default timeout. 357 * 358 * - With one value specified, the setting will apply to all non-compute jobs. 359 * - With multiple values specified, the first one will be for GFX. 360 * The second one is for Compute. The third and fourth ones are 361 * for SDMA and Video. 362 * 363 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 364 * jobs is 10000. The timeout for compute is 60000. 365 */ 366 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 367 "for passthrough or sriov, 10000 for all jobs. 0: keep default value. negative: infinity timeout), format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 368 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 369 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 370 371 /** 372 * DOC: dpm (int) 373 * Override for dynamic power management setting 374 * (0 = disable, 1 = enable) 375 * The default is -1 (auto). 376 */ 377 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 378 module_param_named(dpm, amdgpu_dpm, int, 0444); 379 380 /** 381 * DOC: fw_load_type (int) 382 * Set different firmware loading type for debugging, if supported. 383 * Set to 0 to force direct loading if supported by the ASIC. Set 384 * to -1 to select the default loading mode for the ASIC, as defined 385 * by the driver. The default is -1 (auto). 386 */ 387 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); 388 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 389 390 /** 391 * DOC: aspm (int) 392 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 393 */ 394 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 395 module_param_named(aspm, amdgpu_aspm, int, 0444); 396 397 /** 398 * DOC: runpm (int) 399 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 400 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 401 * Setting the value to 0 disables this functionality. 402 * Setting the value to -2 is auto enabled with power down when displays are attached. 403 */ 404 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto, -2 = auto with displays)"); 405 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 406 407 /** 408 * DOC: ip_block_mask (uint) 409 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 410 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 411 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 412 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 413 */ 414 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 415 module_param_named_unsafe(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 416 417 /** 418 * DOC: bapm (int) 419 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 420 * The default -1 (auto, enabled) 421 */ 422 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 423 module_param_named(bapm, amdgpu_bapm, int, 0444); 424 425 /** 426 * DOC: deep_color (int) 427 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 428 */ 429 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 430 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 431 432 /** 433 * DOC: vm_size (int) 434 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 435 */ 436 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 437 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 438 439 /** 440 * DOC: vm_fragment_size (int) 441 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 442 */ 443 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 444 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 445 446 /** 447 * DOC: vm_block_size (int) 448 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 449 */ 450 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 451 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 452 453 /** 454 * DOC: vm_fault_stop (int) 455 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 456 */ 457 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 458 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 459 460 /** 461 * DOC: vm_update_mode (int) 462 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 463 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 464 */ 465 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 466 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 467 468 /** 469 * DOC: exp_hw_support (int) 470 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 471 */ 472 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 473 module_param_named_unsafe(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 474 475 /** 476 * DOC: dc (int) 477 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 478 */ 479 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 480 module_param_named(dc, amdgpu_dc, int, 0444); 481 482 /** 483 * DOC: sched_jobs (int) 484 * Override the max number of jobs supported in the sw queue. The default is 32. 485 */ 486 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 487 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 488 489 /** 490 * DOC: sched_hw_submission (int) 491 * Override the max number of HW submissions. The default is 2. 492 */ 493 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 494 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 495 496 /** 497 * DOC: ppfeaturemask (hexint) 498 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 499 * The default is the current set of stable power features. 500 */ 501 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 502 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 503 504 /** 505 * DOC: forcelongtraining (uint) 506 * Force long memory training in resume. 507 * The default is zero, indicates short training in resume. 508 */ 509 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 510 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 511 512 /** 513 * DOC: pcie_gen_cap (uint) 514 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 515 * The default is 0 (automatic for each asic). 516 */ 517 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 518 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 519 520 /** 521 * DOC: pcie_lane_cap (uint) 522 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 523 * The default is 0 (automatic for each asic). 524 */ 525 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 526 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 527 528 /** 529 * DOC: cg_mask (ullong) 530 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 531 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 532 */ 533 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 534 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 535 536 /** 537 * DOC: pg_mask (uint) 538 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 539 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 540 */ 541 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 542 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 543 544 /** 545 * DOC: sdma_phase_quantum (uint) 546 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 547 */ 548 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 549 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 550 551 /** 552 * DOC: disable_cu (charp) 553 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 554 */ 555 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 556 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 557 558 /** 559 * DOC: virtual_display (charp) 560 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 561 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 562 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 563 * device at 26:00.0. The default is NULL. 564 */ 565 MODULE_PARM_DESC(virtual_display, 566 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 567 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 568 569 /** 570 * DOC: lbpw (int) 571 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 572 */ 573 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 574 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 575 576 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 577 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 578 579 /** 580 * DOC: gpu_recovery (int) 581 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 582 */ 583 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 584 module_param_named_unsafe(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 585 586 /** 587 * DOC: emu_mode (int) 588 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 589 */ 590 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 591 module_param_named_unsafe(emu_mode, amdgpu_emu_mode, int, 0444); 592 593 /** 594 * DOC: ras_enable (int) 595 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 596 */ 597 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 598 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 599 600 /** 601 * DOC: ras_mask (uint) 602 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 603 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 604 */ 605 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 606 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 607 608 /** 609 * DOC: timeout_fatal_disable (bool) 610 * Disable Watchdog timeout fatal error event 611 */ 612 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 613 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 614 615 /** 616 * DOC: timeout_period (uint) 617 * Modify the watchdog timeout max_cycles as (1 << period) 618 */ 619 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 620 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 621 622 /** 623 * DOC: si_support (int) 624 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 625 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 626 * otherwise using amdgpu driver. 627 */ 628 #ifdef CONFIG_DRM_AMDGPU_SI 629 630 #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) 631 int amdgpu_si_support; 632 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 633 #else 634 int amdgpu_si_support = 1; 635 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 636 #endif 637 638 module_param_named(si_support, amdgpu_si_support, int, 0444); 639 #endif 640 641 /** 642 * DOC: cik_support (int) 643 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 644 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 645 * otherwise using amdgpu driver. 646 */ 647 #ifdef CONFIG_DRM_AMDGPU_CIK 648 649 #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) 650 int amdgpu_cik_support; 651 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 652 #else 653 int amdgpu_cik_support = 1; 654 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 655 #endif 656 657 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 658 #endif 659 660 /** 661 * DOC: smu_memory_pool_size (uint) 662 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 663 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 664 */ 665 MODULE_PARM_DESC(smu_memory_pool_size, 666 "reserve gtt for smu debug usage, 0 = disable,0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 667 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 668 669 /** 670 * DOC: async_gfx_ring (int) 671 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 672 */ 673 MODULE_PARM_DESC(async_gfx_ring, 674 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 675 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 676 677 /** 678 * DOC: mcbp (int) 679 * It is used to enable mid command buffer preemption. (0 = disabled, 1 = enabled, -1 auto (default)) 680 */ 681 MODULE_PARM_DESC(mcbp, 682 "Enable Mid-command buffer preemption (0 = disabled, 1 = enabled), -1 = auto (default)"); 683 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 684 685 /** 686 * DOC: discovery (int) 687 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 688 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 689 */ 690 MODULE_PARM_DESC(discovery, 691 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 692 module_param_named(discovery, amdgpu_discovery, int, 0444); 693 694 /** 695 * DOC: mes (int) 696 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 697 * (0 = disabled (default), 1 = enabled) 698 */ 699 MODULE_PARM_DESC(mes, 700 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 701 module_param_named(mes, amdgpu_mes, int, 0444); 702 703 /** 704 * DOC: mes_log_enable (int) 705 * Enable Micro Engine Scheduler log. This is used to enable/disable MES internal log. 706 * (0 = disabled (default), 1 = enabled) 707 */ 708 MODULE_PARM_DESC(mes_log_enable, 709 "Enable Micro Engine Scheduler log (0 = disabled (default), 1 = enabled)"); 710 module_param_named(mes_log_enable, amdgpu_mes_log_enable, int, 0444); 711 712 /** 713 * DOC: mes_kiq (int) 714 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq. 715 * (0 = disabled (default), 1 = enabled) 716 */ 717 MODULE_PARM_DESC(mes_kiq, 718 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)"); 719 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444); 720 721 /** 722 * DOC: uni_mes (int) 723 * Enable Unified Micro Engine Scheduler. This is a new engine pipe for unified scheduler. 724 * (0 = disabled (default), 1 = enabled) 725 */ 726 MODULE_PARM_DESC(uni_mes, 727 "Enable Unified Micro Engine Scheduler (0 = disabled, 1 = enabled(default)"); 728 module_param_named(uni_mes, amdgpu_uni_mes, int, 0444); 729 730 /** 731 * DOC: noretry (int) 732 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 733 * do not support per-process XNACK this also disables retry page faults. 734 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 735 */ 736 MODULE_PARM_DESC(noretry, 737 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 738 module_param_named(noretry, amdgpu_noretry, int, 0644); 739 740 /** 741 * DOC: force_asic_type (int) 742 * A non negative value used to specify the asic type for all supported GPUs. 743 */ 744 MODULE_PARM_DESC(force_asic_type, 745 "A non negative value used to specify the asic type for all supported GPUs"); 746 module_param_named_unsafe(force_asic_type, amdgpu_force_asic_type, int, 0444); 747 748 /** 749 * DOC: use_xgmi_p2p (int) 750 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 751 */ 752 MODULE_PARM_DESC(use_xgmi_p2p, 753 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 754 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 755 756 757 #ifdef CONFIG_HSA_AMD 758 /** 759 * DOC: sched_policy (int) 760 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 761 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 762 * assigns queues to HQDs. 763 */ 764 int sched_policy = KFD_SCHED_POLICY_HWS; 765 module_param_unsafe(sched_policy, int, 0444); 766 MODULE_PARM_DESC(sched_policy, 767 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 768 769 /** 770 * DOC: hws_max_conc_proc (int) 771 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 772 * number of VMIDs assigned to the HWS, which is also the default. 773 */ 774 int hws_max_conc_proc = -1; 775 module_param(hws_max_conc_proc, int, 0444); 776 MODULE_PARM_DESC(hws_max_conc_proc, 777 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 778 779 /** 780 * DOC: cwsr_enable (int) 781 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 782 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 783 * disables it. 784 */ 785 int cwsr_enable = 1; 786 module_param(cwsr_enable, int, 0444); 787 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 788 789 /** 790 * DOC: max_num_of_queues_per_device (int) 791 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 792 * is 4096. 793 */ 794 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 795 module_param(max_num_of_queues_per_device, int, 0444); 796 MODULE_PARM_DESC(max_num_of_queues_per_device, 797 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 798 799 /** 800 * DOC: send_sigterm (int) 801 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 802 * but just print errors on dmesg. Setting 1 enables sending sigterm. 803 */ 804 int send_sigterm; 805 module_param(send_sigterm, int, 0444); 806 MODULE_PARM_DESC(send_sigterm, 807 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 808 809 /** 810 * DOC: halt_if_hws_hang (int) 811 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 812 * Setting 1 enables halt on hang. 813 */ 814 int halt_if_hws_hang; 815 module_param_unsafe(halt_if_hws_hang, int, 0644); 816 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 817 818 /** 819 * DOC: hws_gws_support(bool) 820 * Assume that HWS supports GWS barriers regardless of what firmware version 821 * check says. Default value: false (rely on MEC2 firmware version check). 822 */ 823 bool hws_gws_support; 824 module_param_unsafe(hws_gws_support, bool, 0444); 825 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 826 827 /** 828 * DOC: queue_preemption_timeout_ms (int) 829 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 830 */ 831 int queue_preemption_timeout_ms = 9000; 832 module_param(queue_preemption_timeout_ms, int, 0644); 833 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 834 835 /** 836 * DOC: debug_evictions(bool) 837 * Enable extra debug messages to help determine the cause of evictions 838 */ 839 bool debug_evictions; 840 module_param(debug_evictions, bool, 0644); 841 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 842 843 /** 844 * DOC: no_system_mem_limit(bool) 845 * Disable system memory limit, to support multiple process shared memory 846 */ 847 bool no_system_mem_limit; 848 module_param(no_system_mem_limit, bool, 0644); 849 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 850 851 /** 852 * DOC: no_queue_eviction_on_vm_fault (int) 853 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 854 */ 855 int amdgpu_no_queue_eviction_on_vm_fault; 856 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 857 module_param_named_unsafe(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 858 #endif 859 860 /** 861 * DOC: mtype_local (int) 862 */ 863 int amdgpu_mtype_local; 864 MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (0 = MTYPE_RW (default), 1 = MTYPE_NC, 2 = MTYPE_CC)"); 865 module_param_named_unsafe(mtype_local, amdgpu_mtype_local, int, 0444); 866 867 /** 868 * DOC: pcie_p2p (bool) 869 * Enable PCIe P2P (requires large-BAR). Default value: true (on) 870 */ 871 #ifdef CONFIG_HSA_AMD_P2P 872 bool pcie_p2p = true; 873 module_param(pcie_p2p, bool, 0444); 874 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); 875 #endif 876 877 /** 878 * DOC: dcfeaturemask (uint) 879 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 880 * The default is the current set of stable display features. 881 */ 882 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 883 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 884 885 /** 886 * DOC: dcdebugmask (uint) 887 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 888 */ 889 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 890 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 891 892 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)"); 893 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444); 894 895 /** 896 * DOC: abmlevel (uint) 897 * Override the default ABM (Adaptive Backlight Management) level used for DC 898 * enabled hardware. Requires DMCU to be supported and loaded. 899 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 900 * default. Values 1-4 control the maximum allowable brightness reduction via 901 * the ABM algorithm, with 1 being the least reduction and 4 being the most 902 * reduction. 903 * 904 * Defaults to -1, or auto. Userspace can only override this level after 905 * boot if it's set to auto. 906 */ 907 int amdgpu_dm_abm_level = -1; 908 MODULE_PARM_DESC(abmlevel, 909 "ABM level (0 = off, 1-4 = backlight reduction level, -1 auto (default))"); 910 module_param_named(abmlevel, amdgpu_dm_abm_level, int, 0444); 911 912 int amdgpu_backlight = -1; 913 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 914 module_param_named(backlight, amdgpu_backlight, bint, 0444); 915 916 /** 917 * DOC: damageclips (int) 918 * Enable or disable damage clips support. If damage clips support is disabled, 919 * we will force full frame updates, irrespective of what user space sends to 920 * us. 921 * 922 * Defaults to -1 (where it is enabled unless a PSR-SU display is detected). 923 */ 924 MODULE_PARM_DESC(damageclips, 925 "Damage clips support (0 = disable, 1 = enable, -1 auto (default))"); 926 module_param_named(damageclips, amdgpu_damage_clips, int, 0444); 927 928 /** 929 * DOC: tmz (int) 930 * Trusted Memory Zone (TMZ) is a method to protect data being written 931 * to or read from memory. 932 * 933 * The default value: 0 (off). TODO: change to auto till it is completed. 934 */ 935 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 936 module_param_named(tmz, amdgpu_tmz, int, 0444); 937 938 /** 939 * DOC: freesync_video (uint) 940 * Enable the optimization to adjust front porch timing to achieve seamless 941 * mode change experience when setting a freesync supported mode for which full 942 * modeset is not needed. 943 * 944 * The Display Core will add a set of modes derived from the base FreeSync 945 * video mode into the corresponding connector's mode list based on commonly 946 * used refresh rates and VRR range of the connected display, when users enable 947 * this feature. From the userspace perspective, they can see a seamless mode 948 * change experience when the change between different refresh rates under the 949 * same resolution. Additionally, userspace applications such as Video playback 950 * can read this modeset list and change the refresh rate based on the video 951 * frame rate. Finally, the userspace can also derive an appropriate mode for a 952 * particular refresh rate based on the FreeSync Mode and add it to the 953 * connector's mode list. 954 * 955 * Note: This is an experimental feature. 956 * 957 * The default value: 0 (off). 958 */ 959 MODULE_PARM_DESC( 960 freesync_video, 961 "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)"); 962 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); 963 964 /** 965 * DOC: reset_method (int) 966 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 967 */ 968 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 969 module_param_named_unsafe(reset_method, amdgpu_reset_method, int, 0644); 970 971 /** 972 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 973 * threshold value of faulty pages detected by RAS ECC, which may 974 * result in the GPU entering bad status when the number of total 975 * faulty pages by ECC exceeds the threshold value. 976 */ 977 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = threshold determined by a formula, 0 < threshold < max records, user-defined threshold)"); 978 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 979 980 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 981 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 982 983 /** 984 * DOC: vcnfw_log (int) 985 * Enable vcnfw log output for debugging, the default is disabled. 986 */ 987 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 988 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 989 990 /** 991 * DOC: sg_display (int) 992 * Disable S/G (scatter/gather) display (i.e., display from system memory). 993 * This option is only relevant on APUs. Set this option to 0 to disable 994 * S/G display if you experience flickering or other issues under memory 995 * pressure and report the issue. 996 */ 997 MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)"); 998 module_param_named(sg_display, amdgpu_sg_display, int, 0444); 999 1000 /** 1001 * DOC: umsch_mm (int) 1002 * Enable Multi Media User Mode Scheduler. This is a HW scheduling engine for VCN and VPE. 1003 * (0 = disabled (default), 1 = enabled) 1004 */ 1005 MODULE_PARM_DESC(umsch_mm, 1006 "Enable Multi Media User Mode Scheduler (0 = disabled (default), 1 = enabled)"); 1007 module_param_named(umsch_mm, amdgpu_umsch_mm, int, 0444); 1008 1009 /** 1010 * DOC: umsch_mm_fwlog (int) 1011 * Enable umschfw log output for debugging, the default is disabled. 1012 */ 1013 MODULE_PARM_DESC(umsch_mm_fwlog, "Enable umschfw log(0 = disable (default value), 1 = enable)"); 1014 module_param_named(umsch_mm_fwlog, amdgpu_umsch_mm_fwlog, int, 0444); 1015 1016 /** 1017 * DOC: smu_pptable_id (int) 1018 * Used to override pptable id. id = 0 use VBIOS pptable. 1019 * id > 0 use the soft pptable with specicfied id. 1020 */ 1021 MODULE_PARM_DESC(smu_pptable_id, 1022 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 1023 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 1024 1025 /** 1026 * DOC: partition_mode (int) 1027 * Used to override the default SPX mode. 1028 */ 1029 MODULE_PARM_DESC( 1030 user_partt_mode, 1031 "specify partition mode to be used (-2 = AMDGPU_AUTO_COMPUTE_PARTITION_MODE(default value) \ 1032 0 = AMDGPU_SPX_PARTITION_MODE, \ 1033 1 = AMDGPU_DPX_PARTITION_MODE, \ 1034 2 = AMDGPU_TPX_PARTITION_MODE, \ 1035 3 = AMDGPU_QPX_PARTITION_MODE, \ 1036 4 = AMDGPU_CPX_PARTITION_MODE)"); 1037 module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint, 0444); 1038 1039 1040 /** 1041 * DOC: enforce_isolation (int) 1042 * enforce process isolation between graphics and compute. 1043 * (-1 = auto, 0 = disable, 1 = enable, 2 = enable legacy mode) 1044 */ 1045 module_param_named(enforce_isolation, amdgpu_enforce_isolation, int, 0444); 1046 MODULE_PARM_DESC(enforce_isolation, 1047 "enforce process isolation between graphics and compute. (-1 = auto, 0 = disable, 1 = enable, 2 = enable legacy mode)"); 1048 1049 /** 1050 * DOC: modeset (int) 1051 * Override nomodeset (1 = override, -1 = auto). The default is -1 (auto). 1052 */ 1053 MODULE_PARM_DESC(modeset, "Override nomodeset (1 = enable, -1 = auto)"); 1054 module_param_named(modeset, amdgpu_modeset, int, 0444); 1055 1056 /** 1057 * DOC: seamless (int) 1058 * Seamless boot will keep the image on the screen during the boot process. 1059 */ 1060 MODULE_PARM_DESC(seamless, "Seamless boot (-1 = auto (default), 0 = disable, 1 = enable)"); 1061 module_param_named(seamless, amdgpu_seamless, int, 0444); 1062 1063 /** 1064 * DOC: debug_mask (uint) 1065 * Debug options for amdgpu, work as a binary mask with the following options: 1066 * 1067 * - 0x1: Debug VM handling 1068 * - 0x2: Enable simulating large-bar capability on non-large bar system. This 1069 * limits the VRAM size reported to ROCm applications to the visible 1070 * size, usually 256MB. 1071 * - 0x4: Disable GPU soft recovery, always do a full reset 1072 * - 0x8: Use VRAM for firmware loading 1073 * - 0x10: Enable ACA based RAS logging 1074 * - 0x20: Enable experimental resets 1075 * - 0x40: Disable ring resets 1076 * - 0x80: Use VRAM for SMU pool 1077 */ 1078 MODULE_PARM_DESC(debug_mask, "debug options for amdgpu, disabled by default"); 1079 module_param_named_unsafe(debug_mask, amdgpu_debug_mask, uint, 0444); 1080 1081 /** 1082 * DOC: agp (int) 1083 * Enable the AGP aperture. This provides an aperture in the GPU's internal 1084 * address space for direct access to system memory. Note that these accesses 1085 * are non-snooped, so they are only used for access to uncached memory. 1086 */ 1087 MODULE_PARM_DESC(agp, "AGP (-1 = auto (default), 0 = disable, 1 = enable)"); 1088 module_param_named(agp, amdgpu_agp, int, 0444); 1089 1090 /** 1091 * DOC: wbrf (int) 1092 * Enable Wifi RFI interference mitigation feature. 1093 * Due to electrical and mechanical constraints there may be likely interference of 1094 * relatively high-powered harmonics of the (G-)DDR memory clocks with local radio 1095 * module frequency bands used by Wifi 6/6e/7. To mitigate the possible RFI interference, 1096 * with this feature enabled, PMFW will use either “shadowed P-State” or “P-State” based 1097 * on active list of frequencies in-use (to be avoided) as part of initial setting or 1098 * P-state transition. However, there may be potential performance impact with this 1099 * feature enabled. 1100 * (0 = disabled, 1 = enabled, -1 = auto (default setting, will be enabled if supported)) 1101 */ 1102 MODULE_PARM_DESC(wbrf, 1103 "Enable Wifi RFI interference mitigation (0 = disabled, 1 = enabled, -1 = auto(default)"); 1104 module_param_named(wbrf, amdgpu_wbrf, int, 0444); 1105 1106 /** 1107 * DOC: rebar (int) 1108 * Allow BAR resizing. Disable this to prevent the driver from attempting 1109 * to resize the BAR if the GPU supports it and there is available MMIO space. 1110 * Note that this just prevents the driver from resizing the BAR. The BIOS 1111 * may have already resized the BAR at boot time. 1112 */ 1113 MODULE_PARM_DESC(rebar, "Resizable BAR (-1 = auto (default), 0 = disable, 1 = enable)"); 1114 module_param_named(rebar, amdgpu_rebar, int, 0444); 1115 1116 /** 1117 * DOC: disable_kq (int) 1118 * Disable kernel queues on systems that support user queues. 1119 * (0 = kernel queues enabled, 1 = kernel queues disabled, -1 = auto (default setting)) 1120 */ 1121 MODULE_PARM_DESC(disable_kq, "Disable kernel queues (-1 = auto (default), 0 = enable KQ, 1 = disable KQ)"); 1122 module_param_named(disable_kq, amdgpu_disable_kq, int, 0444); 1123 1124 /* These devices are not supported by amdgpu. 1125 * They are supported by the mach64, r128, radeon drivers 1126 */ 1127 static const u16 amdgpu_unsupported_pciidlist[] = { 1128 /* mach64 */ 1129 0x4354, 1130 0x4358, 1131 0x4554, 1132 0x4742, 1133 0x4744, 1134 0x4749, 1135 0x474C, 1136 0x474D, 1137 0x474E, 1138 0x474F, 1139 0x4750, 1140 0x4751, 1141 0x4752, 1142 0x4753, 1143 0x4754, 1144 0x4755, 1145 0x4756, 1146 0x4757, 1147 0x4758, 1148 0x4759, 1149 0x475A, 1150 0x4C42, 1151 0x4C44, 1152 0x4C47, 1153 0x4C49, 1154 0x4C4D, 1155 0x4C4E, 1156 0x4C50, 1157 0x4C51, 1158 0x4C52, 1159 0x4C53, 1160 0x5654, 1161 0x5655, 1162 0x5656, 1163 /* r128 */ 1164 0x4c45, 1165 0x4c46, 1166 0x4d46, 1167 0x4d4c, 1168 0x5041, 1169 0x5042, 1170 0x5043, 1171 0x5044, 1172 0x5045, 1173 0x5046, 1174 0x5047, 1175 0x5048, 1176 0x5049, 1177 0x504A, 1178 0x504B, 1179 0x504C, 1180 0x504D, 1181 0x504E, 1182 0x504F, 1183 0x5050, 1184 0x5051, 1185 0x5052, 1186 0x5053, 1187 0x5054, 1188 0x5055, 1189 0x5056, 1190 0x5057, 1191 0x5058, 1192 0x5245, 1193 0x5246, 1194 0x5247, 1195 0x524b, 1196 0x524c, 1197 0x534d, 1198 0x5446, 1199 0x544C, 1200 0x5452, 1201 /* radeon */ 1202 0x3150, 1203 0x3151, 1204 0x3152, 1205 0x3154, 1206 0x3155, 1207 0x3E50, 1208 0x3E54, 1209 0x4136, 1210 0x4137, 1211 0x4144, 1212 0x4145, 1213 0x4146, 1214 0x4147, 1215 0x4148, 1216 0x4149, 1217 0x414A, 1218 0x414B, 1219 0x4150, 1220 0x4151, 1221 0x4152, 1222 0x4153, 1223 0x4154, 1224 0x4155, 1225 0x4156, 1226 0x4237, 1227 0x4242, 1228 0x4336, 1229 0x4337, 1230 0x4437, 1231 0x4966, 1232 0x4967, 1233 0x4A48, 1234 0x4A49, 1235 0x4A4A, 1236 0x4A4B, 1237 0x4A4C, 1238 0x4A4D, 1239 0x4A4E, 1240 0x4A4F, 1241 0x4A50, 1242 0x4A54, 1243 0x4B48, 1244 0x4B49, 1245 0x4B4A, 1246 0x4B4B, 1247 0x4B4C, 1248 0x4C57, 1249 0x4C58, 1250 0x4C59, 1251 0x4C5A, 1252 0x4C64, 1253 0x4C66, 1254 0x4C67, 1255 0x4E44, 1256 0x4E45, 1257 0x4E46, 1258 0x4E47, 1259 0x4E48, 1260 0x4E49, 1261 0x4E4A, 1262 0x4E4B, 1263 0x4E50, 1264 0x4E51, 1265 0x4E52, 1266 0x4E53, 1267 0x4E54, 1268 0x4E56, 1269 0x5144, 1270 0x5145, 1271 0x5146, 1272 0x5147, 1273 0x5148, 1274 0x514C, 1275 0x514D, 1276 0x5157, 1277 0x5158, 1278 0x5159, 1279 0x515A, 1280 0x515E, 1281 0x5460, 1282 0x5462, 1283 0x5464, 1284 0x5548, 1285 0x5549, 1286 0x554A, 1287 0x554B, 1288 0x554C, 1289 0x554D, 1290 0x554E, 1291 0x554F, 1292 0x5550, 1293 0x5551, 1294 0x5552, 1295 0x5554, 1296 0x564A, 1297 0x564B, 1298 0x564F, 1299 0x5652, 1300 0x5653, 1301 0x5657, 1302 0x5834, 1303 0x5835, 1304 0x5954, 1305 0x5955, 1306 0x5974, 1307 0x5975, 1308 0x5960, 1309 0x5961, 1310 0x5962, 1311 0x5964, 1312 0x5965, 1313 0x5969, 1314 0x5a41, 1315 0x5a42, 1316 0x5a61, 1317 0x5a62, 1318 0x5b60, 1319 0x5b62, 1320 0x5b63, 1321 0x5b64, 1322 0x5b65, 1323 0x5c61, 1324 0x5c63, 1325 0x5d48, 1326 0x5d49, 1327 0x5d4a, 1328 0x5d4c, 1329 0x5d4d, 1330 0x5d4e, 1331 0x5d4f, 1332 0x5d50, 1333 0x5d52, 1334 0x5d57, 1335 0x5e48, 1336 0x5e4a, 1337 0x5e4b, 1338 0x5e4c, 1339 0x5e4d, 1340 0x5e4f, 1341 0x6700, 1342 0x6701, 1343 0x6702, 1344 0x6703, 1345 0x6704, 1346 0x6705, 1347 0x6706, 1348 0x6707, 1349 0x6708, 1350 0x6709, 1351 0x6718, 1352 0x6719, 1353 0x671c, 1354 0x671d, 1355 0x671f, 1356 0x6720, 1357 0x6721, 1358 0x6722, 1359 0x6723, 1360 0x6724, 1361 0x6725, 1362 0x6726, 1363 0x6727, 1364 0x6728, 1365 0x6729, 1366 0x6738, 1367 0x6739, 1368 0x673e, 1369 0x6740, 1370 0x6741, 1371 0x6742, 1372 0x6743, 1373 0x6744, 1374 0x6745, 1375 0x6746, 1376 0x6747, 1377 0x6748, 1378 0x6749, 1379 0x674A, 1380 0x6750, 1381 0x6751, 1382 0x6758, 1383 0x6759, 1384 0x675B, 1385 0x675D, 1386 0x675F, 1387 0x6760, 1388 0x6761, 1389 0x6762, 1390 0x6763, 1391 0x6764, 1392 0x6765, 1393 0x6766, 1394 0x6767, 1395 0x6768, 1396 0x6770, 1397 0x6771, 1398 0x6772, 1399 0x6778, 1400 0x6779, 1401 0x677B, 1402 0x6840, 1403 0x6841, 1404 0x6842, 1405 0x6843, 1406 0x6849, 1407 0x684C, 1408 0x6850, 1409 0x6858, 1410 0x6859, 1411 0x6880, 1412 0x6888, 1413 0x6889, 1414 0x688A, 1415 0x688C, 1416 0x688D, 1417 0x6898, 1418 0x6899, 1419 0x689b, 1420 0x689c, 1421 0x689d, 1422 0x689e, 1423 0x68a0, 1424 0x68a1, 1425 0x68a8, 1426 0x68a9, 1427 0x68b0, 1428 0x68b8, 1429 0x68b9, 1430 0x68ba, 1431 0x68be, 1432 0x68bf, 1433 0x68c0, 1434 0x68c1, 1435 0x68c7, 1436 0x68c8, 1437 0x68c9, 1438 0x68d8, 1439 0x68d9, 1440 0x68da, 1441 0x68de, 1442 0x68e0, 1443 0x68e1, 1444 0x68e4, 1445 0x68e5, 1446 0x68e8, 1447 0x68e9, 1448 0x68f1, 1449 0x68f2, 1450 0x68f8, 1451 0x68f9, 1452 0x68fa, 1453 0x68fe, 1454 0x7100, 1455 0x7101, 1456 0x7102, 1457 0x7103, 1458 0x7104, 1459 0x7105, 1460 0x7106, 1461 0x7108, 1462 0x7109, 1463 0x710A, 1464 0x710B, 1465 0x710C, 1466 0x710E, 1467 0x710F, 1468 0x7140, 1469 0x7141, 1470 0x7142, 1471 0x7143, 1472 0x7144, 1473 0x7145, 1474 0x7146, 1475 0x7147, 1476 0x7149, 1477 0x714A, 1478 0x714B, 1479 0x714C, 1480 0x714D, 1481 0x714E, 1482 0x714F, 1483 0x7151, 1484 0x7152, 1485 0x7153, 1486 0x715E, 1487 0x715F, 1488 0x7180, 1489 0x7181, 1490 0x7183, 1491 0x7186, 1492 0x7187, 1493 0x7188, 1494 0x718A, 1495 0x718B, 1496 0x718C, 1497 0x718D, 1498 0x718F, 1499 0x7193, 1500 0x7196, 1501 0x719B, 1502 0x719F, 1503 0x71C0, 1504 0x71C1, 1505 0x71C2, 1506 0x71C3, 1507 0x71C4, 1508 0x71C5, 1509 0x71C6, 1510 0x71C7, 1511 0x71CD, 1512 0x71CE, 1513 0x71D2, 1514 0x71D4, 1515 0x71D5, 1516 0x71D6, 1517 0x71DA, 1518 0x71DE, 1519 0x7200, 1520 0x7210, 1521 0x7211, 1522 0x7240, 1523 0x7243, 1524 0x7244, 1525 0x7245, 1526 0x7246, 1527 0x7247, 1528 0x7248, 1529 0x7249, 1530 0x724A, 1531 0x724B, 1532 0x724C, 1533 0x724D, 1534 0x724E, 1535 0x724F, 1536 0x7280, 1537 0x7281, 1538 0x7283, 1539 0x7284, 1540 0x7287, 1541 0x7288, 1542 0x7289, 1543 0x728B, 1544 0x728C, 1545 0x7290, 1546 0x7291, 1547 0x7293, 1548 0x7297, 1549 0x7834, 1550 0x7835, 1551 0x791e, 1552 0x791f, 1553 0x793f, 1554 0x7941, 1555 0x7942, 1556 0x796c, 1557 0x796d, 1558 0x796e, 1559 0x796f, 1560 0x9400, 1561 0x9401, 1562 0x9402, 1563 0x9403, 1564 0x9405, 1565 0x940A, 1566 0x940B, 1567 0x940F, 1568 0x94A0, 1569 0x94A1, 1570 0x94A3, 1571 0x94B1, 1572 0x94B3, 1573 0x94B4, 1574 0x94B5, 1575 0x94B9, 1576 0x9440, 1577 0x9441, 1578 0x9442, 1579 0x9443, 1580 0x9444, 1581 0x9446, 1582 0x944A, 1583 0x944B, 1584 0x944C, 1585 0x944E, 1586 0x9450, 1587 0x9452, 1588 0x9456, 1589 0x945A, 1590 0x945B, 1591 0x945E, 1592 0x9460, 1593 0x9462, 1594 0x946A, 1595 0x946B, 1596 0x947A, 1597 0x947B, 1598 0x9480, 1599 0x9487, 1600 0x9488, 1601 0x9489, 1602 0x948A, 1603 0x948F, 1604 0x9490, 1605 0x9491, 1606 0x9495, 1607 0x9498, 1608 0x949C, 1609 0x949E, 1610 0x949F, 1611 0x94C0, 1612 0x94C1, 1613 0x94C3, 1614 0x94C4, 1615 0x94C5, 1616 0x94C6, 1617 0x94C7, 1618 0x94C8, 1619 0x94C9, 1620 0x94CB, 1621 0x94CC, 1622 0x94CD, 1623 0x9500, 1624 0x9501, 1625 0x9504, 1626 0x9505, 1627 0x9506, 1628 0x9507, 1629 0x9508, 1630 0x9509, 1631 0x950F, 1632 0x9511, 1633 0x9515, 1634 0x9517, 1635 0x9519, 1636 0x9540, 1637 0x9541, 1638 0x9542, 1639 0x954E, 1640 0x954F, 1641 0x9552, 1642 0x9553, 1643 0x9555, 1644 0x9557, 1645 0x955f, 1646 0x9580, 1647 0x9581, 1648 0x9583, 1649 0x9586, 1650 0x9587, 1651 0x9588, 1652 0x9589, 1653 0x958A, 1654 0x958B, 1655 0x958C, 1656 0x958D, 1657 0x958E, 1658 0x958F, 1659 0x9590, 1660 0x9591, 1661 0x9593, 1662 0x9595, 1663 0x9596, 1664 0x9597, 1665 0x9598, 1666 0x9599, 1667 0x959B, 1668 0x95C0, 1669 0x95C2, 1670 0x95C4, 1671 0x95C5, 1672 0x95C6, 1673 0x95C7, 1674 0x95C9, 1675 0x95CC, 1676 0x95CD, 1677 0x95CE, 1678 0x95CF, 1679 0x9610, 1680 0x9611, 1681 0x9612, 1682 0x9613, 1683 0x9614, 1684 0x9615, 1685 0x9616, 1686 0x9640, 1687 0x9641, 1688 0x9642, 1689 0x9643, 1690 0x9644, 1691 0x9645, 1692 0x9647, 1693 0x9648, 1694 0x9649, 1695 0x964a, 1696 0x964b, 1697 0x964c, 1698 0x964e, 1699 0x964f, 1700 0x9710, 1701 0x9711, 1702 0x9712, 1703 0x9713, 1704 0x9714, 1705 0x9715, 1706 0x9802, 1707 0x9803, 1708 0x9804, 1709 0x9805, 1710 0x9806, 1711 0x9807, 1712 0x9808, 1713 0x9809, 1714 0x980A, 1715 0x9900, 1716 0x9901, 1717 0x9903, 1718 0x9904, 1719 0x9905, 1720 0x9906, 1721 0x9907, 1722 0x9908, 1723 0x9909, 1724 0x990A, 1725 0x990B, 1726 0x990C, 1727 0x990D, 1728 0x990E, 1729 0x990F, 1730 0x9910, 1731 0x9913, 1732 0x9917, 1733 0x9918, 1734 0x9919, 1735 0x9990, 1736 0x9991, 1737 0x9992, 1738 0x9993, 1739 0x9994, 1740 0x9995, 1741 0x9996, 1742 0x9997, 1743 0x9998, 1744 0x9999, 1745 0x999A, 1746 0x999B, 1747 0x999C, 1748 0x999D, 1749 0x99A0, 1750 0x99A2, 1751 0x99A4, 1752 /* radeon secondary ids */ 1753 0x3171, 1754 0x3e70, 1755 0x4164, 1756 0x4165, 1757 0x4166, 1758 0x4168, 1759 0x4170, 1760 0x4171, 1761 0x4172, 1762 0x4173, 1763 0x496e, 1764 0x4a69, 1765 0x4a6a, 1766 0x4a6b, 1767 0x4a70, 1768 0x4a74, 1769 0x4b69, 1770 0x4b6b, 1771 0x4b6c, 1772 0x4c6e, 1773 0x4e64, 1774 0x4e65, 1775 0x4e66, 1776 0x4e67, 1777 0x4e68, 1778 0x4e69, 1779 0x4e6a, 1780 0x4e71, 1781 0x4f73, 1782 0x5569, 1783 0x556b, 1784 0x556d, 1785 0x556f, 1786 0x5571, 1787 0x5854, 1788 0x5874, 1789 0x5940, 1790 0x5941, 1791 0x5b70, 1792 0x5b72, 1793 0x5b73, 1794 0x5b74, 1795 0x5b75, 1796 0x5d44, 1797 0x5d45, 1798 0x5d6d, 1799 0x5d6f, 1800 0x5d72, 1801 0x5d77, 1802 0x5e6b, 1803 0x5e6d, 1804 0x7120, 1805 0x7124, 1806 0x7129, 1807 0x712e, 1808 0x712f, 1809 0x7162, 1810 0x7163, 1811 0x7166, 1812 0x7167, 1813 0x7172, 1814 0x7173, 1815 0x71a0, 1816 0x71a1, 1817 0x71a3, 1818 0x71a7, 1819 0x71bb, 1820 0x71e0, 1821 0x71e1, 1822 0x71e2, 1823 0x71e6, 1824 0x71e7, 1825 0x71f2, 1826 0x7269, 1827 0x726b, 1828 0x726e, 1829 0x72a0, 1830 0x72a8, 1831 0x72b1, 1832 0x72b3, 1833 0x793f, 1834 }; 1835 1836 static const struct pci_device_id pciidlist[] = { 1837 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1838 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1839 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1840 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1841 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1842 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1843 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1844 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1845 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1846 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1847 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1848 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1849 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1850 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1851 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1852 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1853 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1854 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1855 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1856 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1857 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1858 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1859 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1860 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1861 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1862 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1863 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1864 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1865 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1866 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1867 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1868 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1869 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1870 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1871 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1872 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1873 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1874 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1875 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1876 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1877 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1878 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1879 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1880 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1881 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1882 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1883 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1884 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1885 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1886 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1887 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1888 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1889 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1890 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1891 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1892 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1893 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1894 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1895 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1896 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1897 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1898 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1899 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1900 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1901 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1902 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1903 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1904 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1905 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1906 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1907 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1908 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1909 /* Kaveri */ 1910 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1911 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1912 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1913 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1914 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1915 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1916 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1917 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1918 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1919 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1920 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1921 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1922 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1923 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1924 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1925 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1926 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1927 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1928 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1929 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1930 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1931 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1932 /* Bonaire */ 1933 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1934 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1935 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1936 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1937 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1938 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1939 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1940 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1941 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1942 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1943 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1944 /* Hawaii */ 1945 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1946 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1947 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1948 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1949 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1950 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1951 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1952 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1953 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1954 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1955 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1956 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1957 /* Kabini */ 1958 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1959 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1960 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1961 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1962 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1963 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1964 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1965 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1966 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1967 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1968 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1969 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1970 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1971 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1972 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1973 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1974 /* mullins */ 1975 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1976 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1977 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1978 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1979 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1980 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1981 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1982 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1983 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1984 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1985 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1986 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1987 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1988 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1989 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1990 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1991 /* topaz */ 1992 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1993 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1994 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1995 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1996 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1997 /* tonga */ 1998 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1999 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2000 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2001 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2002 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2003 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2004 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2005 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2006 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2007 /* fiji */ 2008 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 2009 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 2010 /* carrizo */ 2011 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 2012 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 2013 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 2014 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 2015 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 2016 /* stoney */ 2017 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 2018 /* Polaris11 */ 2019 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2020 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2021 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2022 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2023 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2024 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2025 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2026 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2027 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2028 /* Polaris10 */ 2029 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2030 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2031 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2032 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2033 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2034 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2035 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2036 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2037 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2038 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2039 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2040 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2041 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2042 /* Polaris12 */ 2043 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2044 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2045 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2046 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2047 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2048 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2049 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2050 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2051 /* VEGAM */ 2052 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 2053 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 2054 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 2055 /* Vega 10 */ 2056 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2057 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2058 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2059 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2060 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2061 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2062 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2063 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2064 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2065 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2066 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2067 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2068 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2069 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2070 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2071 /* Vega 12 */ 2072 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2073 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2074 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2075 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2076 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2077 /* Vega 20 */ 2078 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2079 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2080 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2081 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2082 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2083 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2084 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2085 /* Raven */ 2086 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 2087 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 2088 /* Arcturus */ 2089 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2090 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2091 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2092 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2093 /* Navi10 */ 2094 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2095 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2096 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2097 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2098 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2099 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2100 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2101 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2102 /* Navi14 */ 2103 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2104 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2105 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2106 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2107 2108 /* Renoir */ 2109 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2110 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2111 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2112 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2113 2114 /* Navi12 */ 2115 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 2116 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 2117 2118 /* Sienna_Cichlid */ 2119 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2120 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2121 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2122 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2123 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2124 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2125 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2126 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2127 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2128 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2129 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2130 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2131 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2132 2133 /* Yellow Carp */ 2134 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 2135 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 2136 2137 /* Navy_Flounder */ 2138 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2139 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2140 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2141 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2142 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2143 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2144 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2145 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2146 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2147 2148 /* DIMGREY_CAVEFISH */ 2149 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2150 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2151 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2152 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2153 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2154 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2155 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2156 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2157 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2158 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2159 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2160 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2161 2162 /* Aldebaran */ 2163 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2164 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2165 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2166 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2167 2168 /* CYAN_SKILLFISH */ 2169 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2170 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2171 2172 /* BEIGE_GOBY */ 2173 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2174 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2175 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2176 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2177 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2178 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2179 2180 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2181 .class = PCI_CLASS_DISPLAY_VGA << 8, 2182 .class_mask = 0xffffff, 2183 .driver_data = CHIP_IP_DISCOVERY }, 2184 2185 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2186 .class = PCI_CLASS_DISPLAY_OTHER << 8, 2187 .class_mask = 0xffffff, 2188 .driver_data = CHIP_IP_DISCOVERY }, 2189 2190 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2191 .class = PCI_CLASS_ACCELERATOR_PROCESSING << 8, 2192 .class_mask = 0xffffff, 2193 .driver_data = CHIP_IP_DISCOVERY }, 2194 2195 {0, 0, 0} 2196 }; 2197 2198 MODULE_DEVICE_TABLE(pci, pciidlist); 2199 2200 static const struct amdgpu_asic_type_quirk asic_type_quirks[] = { 2201 /* differentiate between P10 and P11 asics with the same DID */ 2202 {0x67FF, 0xE3, CHIP_POLARIS10}, 2203 {0x67FF, 0xE7, CHIP_POLARIS10}, 2204 {0x67FF, 0xF3, CHIP_POLARIS10}, 2205 {0x67FF, 0xF7, CHIP_POLARIS10}, 2206 }; 2207 2208 static const struct drm_driver amdgpu_kms_driver; 2209 2210 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 2211 { 2212 struct pci_dev *p = NULL; 2213 int i; 2214 2215 /* 0 - GPU 2216 * 1 - audio 2217 * 2 - USB 2218 * 3 - UCSI 2219 */ 2220 for (i = 1; i < 4; i++) { 2221 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 2222 adev->pdev->bus->number, i); 2223 if (p) { 2224 pm_runtime_get_sync(&p->dev); 2225 pm_runtime_mark_last_busy(&p->dev); 2226 pm_runtime_put_autosuspend(&p->dev); 2227 pci_dev_put(p); 2228 } 2229 } 2230 } 2231 2232 static void amdgpu_init_debug_options(struct amdgpu_device *adev) 2233 { 2234 if (amdgpu_debug_mask & AMDGPU_DEBUG_VM) { 2235 pr_info("debug: VM handling debug enabled\n"); 2236 adev->debug_vm = true; 2237 } 2238 2239 if (amdgpu_debug_mask & AMDGPU_DEBUG_LARGEBAR) { 2240 pr_info("debug: enabled simulating large-bar capability on non-large bar system\n"); 2241 adev->debug_largebar = true; 2242 } 2243 2244 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY) { 2245 pr_info("debug: soft reset for GPU recovery disabled\n"); 2246 adev->debug_disable_soft_recovery = true; 2247 } 2248 2249 if (amdgpu_debug_mask & AMDGPU_DEBUG_USE_VRAM_FW_BUF) { 2250 pr_info("debug: place fw in vram for frontdoor loading\n"); 2251 adev->debug_use_vram_fw_buf = true; 2252 } 2253 2254 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_RAS_ACA) { 2255 pr_info("debug: enable RAS ACA\n"); 2256 adev->debug_enable_ras_aca = true; 2257 } 2258 2259 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_EXP_RESETS) { 2260 pr_info("debug: enable experimental reset features\n"); 2261 adev->debug_exp_resets = true; 2262 } 2263 2264 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_RING_RESET) { 2265 pr_info("debug: ring reset disabled\n"); 2266 adev->debug_disable_gpu_ring_reset = true; 2267 } 2268 if (amdgpu_debug_mask & AMDGPU_DEBUG_SMU_POOL) { 2269 pr_info("debug: use vram for smu pool\n"); 2270 adev->pm.smu_debug_mask |= SMU_DEBUG_POOL_USE_VRAM; 2271 } 2272 } 2273 2274 static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long flags) 2275 { 2276 int i; 2277 2278 for (i = 0; i < ARRAY_SIZE(asic_type_quirks); i++) { 2279 if (pdev->device == asic_type_quirks[i].device && 2280 pdev->revision == asic_type_quirks[i].revision) { 2281 flags &= ~AMD_ASIC_MASK; 2282 flags |= asic_type_quirks[i].type; 2283 break; 2284 } 2285 } 2286 2287 return flags; 2288 } 2289 2290 static int amdgpu_pci_probe(struct pci_dev *pdev, 2291 const struct pci_device_id *ent) 2292 { 2293 struct drm_device *ddev; 2294 struct amdgpu_device *adev; 2295 unsigned long flags = ent->driver_data; 2296 int ret, retry = 0, i; 2297 bool supports_atomic = false; 2298 2299 if ((pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA || 2300 (pdev->class >> 8) == PCI_CLASS_DISPLAY_OTHER) { 2301 if (drm_firmware_drivers_only() && amdgpu_modeset == -1) 2302 return -EINVAL; 2303 } 2304 2305 /* skip devices which are owned by radeon */ 2306 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2307 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2308 return -ENODEV; 2309 } 2310 2311 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) 2312 amdgpu_aspm = 0; 2313 2314 if (amdgpu_virtual_display || 2315 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 2316 supports_atomic = true; 2317 2318 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2319 DRM_INFO("This hardware requires experimental hardware support.\n" 2320 "See modparam exp_hw_support\n"); 2321 return -ENODEV; 2322 } 2323 2324 flags = amdgpu_fix_asic_type(pdev, flags); 2325 2326 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2327 * however, SME requires an indirect IOMMU mapping because the encryption 2328 * bit is beyond the DMA mask of the chip. 2329 */ 2330 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2331 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2332 dev_info(&pdev->dev, 2333 "SME is not compatible with RAVEN\n"); 2334 return -ENOTSUPP; 2335 } 2336 2337 switch (flags & AMD_ASIC_MASK) { 2338 case CHIP_TAHITI: 2339 case CHIP_PITCAIRN: 2340 case CHIP_VERDE: 2341 case CHIP_OLAND: 2342 case CHIP_HAINAN: 2343 #ifdef CONFIG_DRM_AMDGPU_SI 2344 if (!amdgpu_si_support) { 2345 dev_info(&pdev->dev, 2346 "SI support provided by radeon.\n"); 2347 dev_info(&pdev->dev, 2348 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 2349 ); 2350 return -ENODEV; 2351 } 2352 break; 2353 #else 2354 dev_info(&pdev->dev, "amdgpu is built without SI support.\n"); 2355 return -ENODEV; 2356 #endif 2357 case CHIP_KAVERI: 2358 case CHIP_BONAIRE: 2359 case CHIP_HAWAII: 2360 case CHIP_KABINI: 2361 case CHIP_MULLINS: 2362 #ifdef CONFIG_DRM_AMDGPU_CIK 2363 if (!amdgpu_cik_support) { 2364 dev_info(&pdev->dev, 2365 "CIK support provided by radeon.\n"); 2366 dev_info(&pdev->dev, 2367 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 2368 ); 2369 return -ENODEV; 2370 } 2371 break; 2372 #else 2373 dev_info(&pdev->dev, "amdgpu is built without CIK support.\n"); 2374 return -ENODEV; 2375 #endif 2376 default: 2377 break; 2378 } 2379 2380 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2381 if (IS_ERR(adev)) 2382 return PTR_ERR(adev); 2383 2384 adev->dev = &pdev->dev; 2385 adev->pdev = pdev; 2386 ddev = adev_to_drm(adev); 2387 2388 if (!supports_atomic) 2389 ddev->driver_features &= ~DRIVER_ATOMIC; 2390 2391 ret = pci_enable_device(pdev); 2392 if (ret) 2393 return ret; 2394 2395 pci_set_drvdata(pdev, ddev); 2396 2397 amdgpu_init_debug_options(adev); 2398 2399 ret = amdgpu_driver_load_kms(adev, flags); 2400 if (ret) 2401 goto err_pci; 2402 2403 retry_init: 2404 ret = drm_dev_register(ddev, flags); 2405 if (ret == -EAGAIN && ++retry <= 3) { 2406 DRM_INFO("retry init %d\n", retry); 2407 /* Don't request EX mode too frequently which is attacking */ 2408 msleep(5000); 2409 goto retry_init; 2410 } else if (ret) { 2411 goto err_pci; 2412 } 2413 2414 ret = amdgpu_xcp_dev_register(adev, ent); 2415 if (ret) 2416 goto err_pci; 2417 2418 ret = amdgpu_amdkfd_drm_client_create(adev); 2419 if (ret) 2420 goto err_pci; 2421 2422 /* 2423 * 1. don't init fbdev on hw without DCE 2424 * 2. don't init fbdev if there are no connectors 2425 */ 2426 if (adev->mode_info.mode_config_initialized && 2427 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2428 const struct drm_format_info *format; 2429 2430 /* select 8 bpp console on low vram cards */ 2431 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2432 format = drm_format_info(DRM_FORMAT_C8); 2433 else 2434 format = NULL; 2435 2436 drm_client_setup(adev_to_drm(adev), format); 2437 } 2438 2439 ret = amdgpu_debugfs_init(adev); 2440 if (ret) 2441 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2442 2443 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2444 /* only need to skip on ATPX */ 2445 if (amdgpu_device_supports_px(ddev)) 2446 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2447 /* we want direct complete for BOCO */ 2448 if (amdgpu_device_supports_boco(ddev)) 2449 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2450 DPM_FLAG_SMART_SUSPEND | 2451 DPM_FLAG_MAY_SKIP_RESUME); 2452 pm_runtime_use_autosuspend(ddev->dev); 2453 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2454 2455 pm_runtime_allow(ddev->dev); 2456 2457 pm_runtime_mark_last_busy(ddev->dev); 2458 pm_runtime_put_autosuspend(ddev->dev); 2459 2460 pci_wake_from_d3(pdev, TRUE); 2461 2462 /* 2463 * For runpm implemented via BACO, PMFW will handle the 2464 * timing for BACO in and out: 2465 * - put ASIC into BACO state only when both video and 2466 * audio functions are in D3 state. 2467 * - pull ASIC out of BACO state when either video or 2468 * audio function is in D0 state. 2469 * Also, at startup, PMFW assumes both functions are in 2470 * D0 state. 2471 * 2472 * So if snd driver was loaded prior to amdgpu driver 2473 * and audio function was put into D3 state, there will 2474 * be no PMFW-aware D-state transition(D0->D3) on runpm 2475 * suspend. Thus the BACO will be not correctly kicked in. 2476 * 2477 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2478 * into D0 state. Then there will be a PMFW-aware D-state 2479 * transition(D0->D3) on runpm suspend. 2480 */ 2481 if (amdgpu_device_supports_baco(ddev) && 2482 !(adev->flags & AMD_IS_APU) && 2483 (adev->asic_type >= CHIP_NAVI10)) 2484 amdgpu_get_secondary_funcs(adev); 2485 } 2486 2487 return 0; 2488 2489 err_pci: 2490 pci_disable_device(pdev); 2491 return ret; 2492 } 2493 2494 static void 2495 amdgpu_pci_remove(struct pci_dev *pdev) 2496 { 2497 struct drm_device *dev = pci_get_drvdata(pdev); 2498 struct amdgpu_device *adev = drm_to_adev(dev); 2499 2500 amdgpu_xcp_dev_unplug(adev); 2501 amdgpu_gmc_prepare_nps_mode_change(adev); 2502 drm_dev_unplug(dev); 2503 2504 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2505 pm_runtime_get_sync(dev->dev); 2506 pm_runtime_forbid(dev->dev); 2507 } 2508 2509 amdgpu_driver_unload_kms(dev); 2510 2511 /* 2512 * Flush any in flight DMA operations from device. 2513 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2514 * StatusTransactions Pending bit. 2515 */ 2516 pci_disable_device(pdev); 2517 pci_wait_for_pending_transaction(pdev); 2518 } 2519 2520 static void 2521 amdgpu_pci_shutdown(struct pci_dev *pdev) 2522 { 2523 struct drm_device *dev = pci_get_drvdata(pdev); 2524 struct amdgpu_device *adev = drm_to_adev(dev); 2525 2526 if (amdgpu_ras_intr_triggered()) 2527 return; 2528 2529 /* if we are running in a VM, make sure the device 2530 * torn down properly on reboot/shutdown. 2531 * unfortunately we can't detect certain 2532 * hypervisors so just do this all the time. 2533 */ 2534 if (!amdgpu_passthrough(adev)) 2535 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2536 amdgpu_device_ip_suspend(adev); 2537 adev->mp1_state = PP_MP1_STATE_NONE; 2538 } 2539 2540 static int amdgpu_pmops_prepare(struct device *dev) 2541 { 2542 struct drm_device *drm_dev = dev_get_drvdata(dev); 2543 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2544 2545 /* Return a positive number here so 2546 * DPM_FLAG_SMART_SUSPEND works properly 2547 */ 2548 if (amdgpu_device_supports_boco(drm_dev) && 2549 pm_runtime_suspended(dev)) 2550 return 1; 2551 2552 /* if we will not support s3 or s2i for the device 2553 * then skip suspend 2554 */ 2555 if (!amdgpu_acpi_is_s0ix_active(adev) && 2556 !amdgpu_acpi_is_s3_active(adev)) 2557 return 1; 2558 2559 return amdgpu_device_prepare(drm_dev); 2560 } 2561 2562 static void amdgpu_pmops_complete(struct device *dev) 2563 { 2564 /* nothing to do */ 2565 } 2566 2567 static int amdgpu_pmops_suspend(struct device *dev) 2568 { 2569 struct drm_device *drm_dev = dev_get_drvdata(dev); 2570 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2571 2572 if (amdgpu_acpi_is_s0ix_active(adev)) 2573 adev->in_s0ix = true; 2574 else if (amdgpu_acpi_is_s3_active(adev)) 2575 adev->in_s3 = true; 2576 if (!adev->in_s0ix && !adev->in_s3) { 2577 /* don't allow going deep first time followed by s2idle the next time */ 2578 if (adev->last_suspend_state != PM_SUSPEND_ON && 2579 adev->last_suspend_state != pm_suspend_target_state) { 2580 drm_err_once(drm_dev, "Unsupported suspend state %d\n", 2581 pm_suspend_target_state); 2582 return -EINVAL; 2583 } 2584 return 0; 2585 } 2586 2587 /* cache the state last used for suspend */ 2588 adev->last_suspend_state = pm_suspend_target_state; 2589 2590 return amdgpu_device_suspend(drm_dev, true); 2591 } 2592 2593 static int amdgpu_pmops_suspend_noirq(struct device *dev) 2594 { 2595 struct drm_device *drm_dev = dev_get_drvdata(dev); 2596 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2597 2598 if (amdgpu_acpi_should_gpu_reset(adev)) 2599 return amdgpu_asic_reset(adev); 2600 2601 return 0; 2602 } 2603 2604 static int amdgpu_pmops_resume(struct device *dev) 2605 { 2606 struct drm_device *drm_dev = dev_get_drvdata(dev); 2607 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2608 int r; 2609 2610 if (!adev->in_s0ix && !adev->in_s3) 2611 return 0; 2612 2613 /* Avoids registers access if device is physically gone */ 2614 if (!pci_device_is_present(adev->pdev)) 2615 adev->no_hw_access = true; 2616 2617 r = amdgpu_device_resume(drm_dev, true); 2618 if (amdgpu_acpi_is_s0ix_active(adev)) 2619 adev->in_s0ix = false; 2620 else 2621 adev->in_s3 = false; 2622 return r; 2623 } 2624 2625 static int amdgpu_pmops_freeze(struct device *dev) 2626 { 2627 struct drm_device *drm_dev = dev_get_drvdata(dev); 2628 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2629 int r; 2630 2631 r = amdgpu_device_suspend(drm_dev, true); 2632 if (r) 2633 return r; 2634 2635 if (amdgpu_acpi_should_gpu_reset(adev)) 2636 return amdgpu_asic_reset(adev); 2637 return 0; 2638 } 2639 2640 static int amdgpu_pmops_thaw(struct device *dev) 2641 { 2642 struct drm_device *drm_dev = dev_get_drvdata(dev); 2643 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2644 int r; 2645 2646 r = amdgpu_device_resume(drm_dev, true); 2647 adev->in_s4 = false; 2648 2649 return r; 2650 } 2651 2652 static int amdgpu_pmops_poweroff(struct device *dev) 2653 { 2654 struct drm_device *drm_dev = dev_get_drvdata(dev); 2655 2656 return amdgpu_device_suspend(drm_dev, true); 2657 } 2658 2659 static int amdgpu_pmops_restore(struct device *dev) 2660 { 2661 struct drm_device *drm_dev = dev_get_drvdata(dev); 2662 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2663 2664 adev->in_s4 = false; 2665 2666 return amdgpu_device_resume(drm_dev, true); 2667 } 2668 2669 static int amdgpu_runtime_idle_check_display(struct device *dev) 2670 { 2671 struct pci_dev *pdev = to_pci_dev(dev); 2672 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2673 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2674 2675 if (adev->mode_info.num_crtc) { 2676 struct drm_connector *list_connector; 2677 struct drm_connector_list_iter iter; 2678 int ret = 0; 2679 2680 if (amdgpu_runtime_pm != -2) { 2681 /* XXX: Return busy if any displays are connected to avoid 2682 * possible display wakeups after runtime resume due to 2683 * hotplug events in case any displays were connected while 2684 * the GPU was in suspend. Remove this once that is fixed. 2685 */ 2686 mutex_lock(&drm_dev->mode_config.mutex); 2687 drm_connector_list_iter_begin(drm_dev, &iter); 2688 drm_for_each_connector_iter(list_connector, &iter) { 2689 if (list_connector->status == connector_status_connected) { 2690 ret = -EBUSY; 2691 break; 2692 } 2693 } 2694 drm_connector_list_iter_end(&iter); 2695 mutex_unlock(&drm_dev->mode_config.mutex); 2696 2697 if (ret) 2698 return ret; 2699 } 2700 2701 if (adev->dc_enabled) { 2702 struct drm_crtc *crtc; 2703 2704 drm_for_each_crtc(crtc, drm_dev) { 2705 drm_modeset_lock(&crtc->mutex, NULL); 2706 if (crtc->state->active) 2707 ret = -EBUSY; 2708 drm_modeset_unlock(&crtc->mutex); 2709 if (ret < 0) 2710 break; 2711 } 2712 } else { 2713 mutex_lock(&drm_dev->mode_config.mutex); 2714 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2715 2716 drm_connector_list_iter_begin(drm_dev, &iter); 2717 drm_for_each_connector_iter(list_connector, &iter) { 2718 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2719 ret = -EBUSY; 2720 break; 2721 } 2722 } 2723 2724 drm_connector_list_iter_end(&iter); 2725 2726 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2727 mutex_unlock(&drm_dev->mode_config.mutex); 2728 } 2729 if (ret) 2730 return ret; 2731 } 2732 2733 return 0; 2734 } 2735 2736 static int amdgpu_runtime_idle_check_userq(struct device *dev) 2737 { 2738 struct pci_dev *pdev = to_pci_dev(dev); 2739 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2740 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2741 struct amdgpu_usermode_queue *queue; 2742 struct amdgpu_userq_mgr *uqm, *tmp; 2743 int queue_id; 2744 int ret = 0; 2745 2746 mutex_lock(&adev->userq_mutex); 2747 list_for_each_entry_safe(uqm, tmp, &adev->userq_mgr_list, list) { 2748 idr_for_each_entry(&uqm->userq_idr, queue, queue_id) { 2749 ret = -EBUSY; 2750 goto done; 2751 } 2752 } 2753 done: 2754 mutex_unlock(&adev->userq_mutex); 2755 2756 return ret; 2757 } 2758 2759 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2760 { 2761 struct pci_dev *pdev = to_pci_dev(dev); 2762 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2763 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2764 int ret, i; 2765 2766 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2767 pm_runtime_forbid(dev); 2768 return -EBUSY; 2769 } 2770 2771 ret = amdgpu_runtime_idle_check_display(dev); 2772 if (ret) 2773 return ret; 2774 ret = amdgpu_runtime_idle_check_userq(dev); 2775 if (ret) 2776 return ret; 2777 2778 /* wait for all rings to drain before suspending */ 2779 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2780 struct amdgpu_ring *ring = adev->rings[i]; 2781 2782 if (ring && ring->sched.ready) { 2783 ret = amdgpu_fence_wait_empty(ring); 2784 if (ret) 2785 return -EBUSY; 2786 } 2787 } 2788 2789 adev->in_runpm = true; 2790 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2791 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2792 2793 /* 2794 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2795 * proper cleanups and put itself into a state ready for PNP. That 2796 * can address some random resuming failure observed on BOCO capable 2797 * platforms. 2798 * TODO: this may be also needed for PX capable platform. 2799 */ 2800 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2801 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2802 2803 ret = amdgpu_device_prepare(drm_dev); 2804 if (ret) 2805 return ret; 2806 ret = amdgpu_device_suspend(drm_dev, false); 2807 if (ret) { 2808 adev->in_runpm = false; 2809 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2810 adev->mp1_state = PP_MP1_STATE_NONE; 2811 return ret; 2812 } 2813 2814 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2815 adev->mp1_state = PP_MP1_STATE_NONE; 2816 2817 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) { 2818 /* Only need to handle PCI state in the driver for ATPX 2819 * PCI core handles it for _PR3. 2820 */ 2821 amdgpu_device_cache_pci_state(pdev); 2822 pci_disable_device(pdev); 2823 pci_ignore_hotplug(pdev); 2824 pci_set_power_state(pdev, PCI_D3cold); 2825 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2826 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) { 2827 /* nothing to do */ 2828 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2829 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) { 2830 amdgpu_device_baco_enter(drm_dev); 2831 } 2832 2833 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n"); 2834 2835 return 0; 2836 } 2837 2838 static int amdgpu_pmops_runtime_resume(struct device *dev) 2839 { 2840 struct pci_dev *pdev = to_pci_dev(dev); 2841 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2842 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2843 int ret; 2844 2845 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) 2846 return -EINVAL; 2847 2848 /* Avoids registers access if device is physically gone */ 2849 if (!pci_device_is_present(adev->pdev)) 2850 adev->no_hw_access = true; 2851 2852 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) { 2853 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2854 2855 /* Only need to handle PCI state in the driver for ATPX 2856 * PCI core handles it for _PR3. 2857 */ 2858 pci_set_power_state(pdev, PCI_D0); 2859 amdgpu_device_load_pci_state(pdev); 2860 ret = pci_enable_device(pdev); 2861 if (ret) 2862 return ret; 2863 pci_set_master(pdev); 2864 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) { 2865 /* Only need to handle PCI state in the driver for ATPX 2866 * PCI core handles it for _PR3. 2867 */ 2868 pci_set_master(pdev); 2869 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2870 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) { 2871 amdgpu_device_baco_exit(drm_dev); 2872 } 2873 ret = amdgpu_device_resume(drm_dev, false); 2874 if (ret) { 2875 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2876 pci_disable_device(pdev); 2877 return ret; 2878 } 2879 2880 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2881 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2882 adev->in_runpm = false; 2883 return 0; 2884 } 2885 2886 static int amdgpu_pmops_runtime_idle(struct device *dev) 2887 { 2888 struct drm_device *drm_dev = dev_get_drvdata(dev); 2889 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2890 int ret; 2891 2892 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2893 pm_runtime_forbid(dev); 2894 return -EBUSY; 2895 } 2896 2897 ret = amdgpu_runtime_idle_check_display(dev); 2898 if (ret) 2899 goto done; 2900 2901 ret = amdgpu_runtime_idle_check_userq(dev); 2902 done: 2903 pm_runtime_mark_last_busy(dev); 2904 pm_runtime_autosuspend(dev); 2905 return ret; 2906 } 2907 2908 static int amdgpu_drm_release(struct inode *inode, struct file *filp) 2909 { 2910 struct drm_file *file_priv = filp->private_data; 2911 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2912 2913 if (fpriv) { 2914 fpriv->evf_mgr.fd_closing = true; 2915 amdgpu_userq_mgr_fini(&fpriv->userq_mgr); 2916 amdgpu_eviction_fence_destroy(&fpriv->evf_mgr); 2917 } 2918 2919 return drm_release(inode, filp); 2920 } 2921 2922 long amdgpu_drm_ioctl(struct file *filp, 2923 unsigned int cmd, unsigned long arg) 2924 { 2925 struct drm_file *file_priv = filp->private_data; 2926 struct drm_device *dev; 2927 long ret; 2928 2929 dev = file_priv->minor->dev; 2930 ret = pm_runtime_get_sync(dev->dev); 2931 if (ret < 0) 2932 goto out; 2933 2934 ret = drm_ioctl(filp, cmd, arg); 2935 2936 pm_runtime_mark_last_busy(dev->dev); 2937 out: 2938 pm_runtime_put_autosuspend(dev->dev); 2939 return ret; 2940 } 2941 2942 static const struct dev_pm_ops amdgpu_pm_ops = { 2943 .prepare = amdgpu_pmops_prepare, 2944 .complete = amdgpu_pmops_complete, 2945 .suspend = amdgpu_pmops_suspend, 2946 .suspend_noirq = amdgpu_pmops_suspend_noirq, 2947 .resume = amdgpu_pmops_resume, 2948 .freeze = amdgpu_pmops_freeze, 2949 .thaw = amdgpu_pmops_thaw, 2950 .poweroff = amdgpu_pmops_poweroff, 2951 .restore = amdgpu_pmops_restore, 2952 .runtime_suspend = amdgpu_pmops_runtime_suspend, 2953 .runtime_resume = amdgpu_pmops_runtime_resume, 2954 .runtime_idle = amdgpu_pmops_runtime_idle, 2955 }; 2956 2957 static int amdgpu_flush(struct file *f, fl_owner_t id) 2958 { 2959 struct drm_file *file_priv = f->private_data; 2960 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2961 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2962 2963 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 2964 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 2965 2966 return timeout >= 0 ? 0 : timeout; 2967 } 2968 2969 static const struct file_operations amdgpu_driver_kms_fops = { 2970 .owner = THIS_MODULE, 2971 .open = drm_open, 2972 .flush = amdgpu_flush, 2973 .release = amdgpu_drm_release, 2974 .unlocked_ioctl = amdgpu_drm_ioctl, 2975 .mmap = drm_gem_mmap, 2976 .poll = drm_poll, 2977 .read = drm_read, 2978 #ifdef CONFIG_COMPAT 2979 .compat_ioctl = amdgpu_kms_compat_ioctl, 2980 #endif 2981 #ifdef CONFIG_PROC_FS 2982 .show_fdinfo = drm_show_fdinfo, 2983 #endif 2984 .fop_flags = FOP_UNSIGNED_OFFSET, 2985 }; 2986 2987 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 2988 { 2989 struct drm_file *file; 2990 2991 if (!filp) 2992 return -EINVAL; 2993 2994 if (filp->f_op != &amdgpu_driver_kms_fops) 2995 return -EINVAL; 2996 2997 file = filp->private_data; 2998 *fpriv = file->driver_priv; 2999 return 0; 3000 } 3001 3002 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 3003 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3004 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3005 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3006 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 3007 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3008 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3009 /* KMS */ 3010 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3011 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3012 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3013 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3014 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3015 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3016 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3017 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3018 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3019 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3020 DRM_IOCTL_DEF_DRV(AMDGPU_USERQ, amdgpu_userq_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3021 DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_SIGNAL, amdgpu_userq_signal_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3022 DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_WAIT, amdgpu_userq_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3023 }; 3024 3025 static const struct drm_driver amdgpu_kms_driver = { 3026 .driver_features = 3027 DRIVER_ATOMIC | 3028 DRIVER_GEM | 3029 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 3030 DRIVER_SYNCOBJ_TIMELINE, 3031 .open = amdgpu_driver_open_kms, 3032 .postclose = amdgpu_driver_postclose_kms, 3033 .ioctls = amdgpu_ioctls_kms, 3034 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 3035 .dumb_create = amdgpu_mode_dumb_create, 3036 .dumb_map_offset = amdgpu_mode_dumb_mmap, 3037 DRM_FBDEV_TTM_DRIVER_OPS, 3038 .fops = &amdgpu_driver_kms_fops, 3039 .release = &amdgpu_driver_release_kms, 3040 #ifdef CONFIG_PROC_FS 3041 .show_fdinfo = amdgpu_show_fdinfo, 3042 #endif 3043 3044 .gem_prime_import = amdgpu_gem_prime_import, 3045 3046 .name = DRIVER_NAME, 3047 .desc = DRIVER_DESC, 3048 .major = KMS_DRIVER_MAJOR, 3049 .minor = KMS_DRIVER_MINOR, 3050 .patchlevel = KMS_DRIVER_PATCHLEVEL, 3051 }; 3052 3053 const struct drm_driver amdgpu_partition_driver = { 3054 .driver_features = 3055 DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ | 3056 DRIVER_SYNCOBJ_TIMELINE, 3057 .open = amdgpu_driver_open_kms, 3058 .postclose = amdgpu_driver_postclose_kms, 3059 .ioctls = amdgpu_ioctls_kms, 3060 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 3061 .dumb_create = amdgpu_mode_dumb_create, 3062 .dumb_map_offset = amdgpu_mode_dumb_mmap, 3063 DRM_FBDEV_TTM_DRIVER_OPS, 3064 .fops = &amdgpu_driver_kms_fops, 3065 .release = &amdgpu_driver_release_kms, 3066 3067 .gem_prime_import = amdgpu_gem_prime_import, 3068 3069 .name = DRIVER_NAME, 3070 .desc = DRIVER_DESC, 3071 .major = KMS_DRIVER_MAJOR, 3072 .minor = KMS_DRIVER_MINOR, 3073 .patchlevel = KMS_DRIVER_PATCHLEVEL, 3074 }; 3075 3076 static struct pci_error_handlers amdgpu_pci_err_handler = { 3077 .error_detected = amdgpu_pci_error_detected, 3078 .mmio_enabled = amdgpu_pci_mmio_enabled, 3079 .slot_reset = amdgpu_pci_slot_reset, 3080 .resume = amdgpu_pci_resume, 3081 }; 3082 3083 static const struct attribute_group *amdgpu_sysfs_groups[] = { 3084 &amdgpu_vram_mgr_attr_group, 3085 &amdgpu_gtt_mgr_attr_group, 3086 &amdgpu_flash_attr_group, 3087 NULL, 3088 }; 3089 3090 static struct pci_driver amdgpu_kms_pci_driver = { 3091 .name = DRIVER_NAME, 3092 .id_table = pciidlist, 3093 .probe = amdgpu_pci_probe, 3094 .remove = amdgpu_pci_remove, 3095 .shutdown = amdgpu_pci_shutdown, 3096 .driver.pm = &amdgpu_pm_ops, 3097 .err_handler = &amdgpu_pci_err_handler, 3098 .dev_groups = amdgpu_sysfs_groups, 3099 }; 3100 3101 static int __init amdgpu_init(void) 3102 { 3103 int r; 3104 3105 r = amdgpu_sync_init(); 3106 if (r) 3107 goto error_sync; 3108 3109 r = amdgpu_fence_slab_init(); 3110 if (r) 3111 goto error_fence; 3112 3113 r = amdgpu_userq_fence_slab_init(); 3114 if (r) 3115 goto error_fence; 3116 3117 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 3118 amdgpu_register_atpx_handler(); 3119 amdgpu_acpi_detect(); 3120 3121 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 3122 amdgpu_amdkfd_init(); 3123 3124 if (amdgpu_pp_feature_mask & PP_OVERDRIVE_MASK) { 3125 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 3126 pr_crit("Overdrive is enabled, please disable it before " 3127 "reporting any bugs unrelated to overdrive.\n"); 3128 } 3129 3130 /* let modprobe override vga console setting */ 3131 return pci_register_driver(&amdgpu_kms_pci_driver); 3132 3133 error_fence: 3134 amdgpu_sync_fini(); 3135 3136 error_sync: 3137 return r; 3138 } 3139 3140 static void __exit amdgpu_exit(void) 3141 { 3142 amdgpu_amdkfd_fini(); 3143 pci_unregister_driver(&amdgpu_kms_pci_driver); 3144 amdgpu_unregister_atpx_handler(); 3145 amdgpu_acpi_release(); 3146 amdgpu_sync_fini(); 3147 amdgpu_fence_slab_fini(); 3148 amdgpu_userq_fence_slab_fini(); 3149 mmu_notifier_synchronize(); 3150 amdgpu_xcp_drv_release(); 3151 } 3152 3153 module_init(amdgpu_init); 3154 module_exit(amdgpu_exit); 3155 3156 MODULE_AUTHOR(DRIVER_AUTHOR); 3157 MODULE_DESCRIPTION(DRIVER_DESC); 3158 MODULE_LICENSE("GPL and additional rights"); 3159