1 /** 2 * \file amdgpu_drv.c 3 * AMD Amdgpu driver 4 * 5 * \author Gareth Hughes <gareth@valinux.com> 6 */ 7 8 /* 9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 10 * All Rights Reserved. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a 13 * copy of this software and associated documentation files (the "Software"), 14 * to deal in the Software without restriction, including without limitation 15 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 16 * and/or sell copies of the Software, and to permit persons to whom the 17 * Software is furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice (including the next 20 * paragraph) shall be included in all copies or substantial portions of the 21 * Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 29 * OTHER DEALINGS IN THE SOFTWARE. 30 */ 31 32 #include <drm/drmP.h> 33 #include <drm/amdgpu_drm.h> 34 #include <drm/drm_gem.h> 35 #include "amdgpu_drv.h" 36 37 #include <drm/drm_pciids.h> 38 #include <linux/console.h> 39 #include <linux/module.h> 40 #include <linux/pm_runtime.h> 41 #include <linux/vga_switcheroo.h> 42 #include "drm_crtc_helper.h" 43 44 #include "amdgpu.h" 45 #include "amdgpu_irq.h" 46 47 #include "amdgpu_amdkfd.h" 48 49 /* 50 * KMS wrapper. 51 * - 3.0.0 - initial driver 52 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 53 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 54 * at the end of IBs. 55 * - 3.3.0 - Add VM support for UVD on supported hardware. 56 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 57 * - 3.5.0 - Add support for new UVD_NO_OP register. 58 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 59 * - 3.7.0 - Add support for VCE clock list packet 60 * - 3.8.0 - Add support raster config init in the kernel 61 */ 62 #define KMS_DRIVER_MAJOR 3 63 #define KMS_DRIVER_MINOR 8 64 #define KMS_DRIVER_PATCHLEVEL 0 65 66 int amdgpu_vram_limit = 0; 67 int amdgpu_gart_size = -1; /* auto */ 68 int amdgpu_moverate = -1; /* auto */ 69 int amdgpu_benchmarking = 0; 70 int amdgpu_testing = 0; 71 int amdgpu_audio = -1; 72 int amdgpu_disp_priority = 0; 73 int amdgpu_hw_i2c = 0; 74 int amdgpu_pcie_gen2 = -1; 75 int amdgpu_msi = -1; 76 int amdgpu_lockup_timeout = 0; 77 int amdgpu_dpm = -1; 78 int amdgpu_smc_load_fw = 1; 79 int amdgpu_aspm = -1; 80 int amdgpu_runtime_pm = -1; 81 unsigned amdgpu_ip_block_mask = 0xffffffff; 82 int amdgpu_bapm = -1; 83 int amdgpu_deep_color = 0; 84 int amdgpu_vm_size = 64; 85 int amdgpu_vm_block_size = -1; 86 int amdgpu_vm_fault_stop = 0; 87 int amdgpu_vm_debug = 0; 88 int amdgpu_exp_hw_support = 0; 89 int amdgpu_sched_jobs = 32; 90 int amdgpu_sched_hw_submission = 2; 91 int amdgpu_powerplay = -1; 92 int amdgpu_powercontainment = 1; 93 int amdgpu_sclk_deep_sleep_en = 1; 94 unsigned amdgpu_pcie_gen_cap = 0; 95 unsigned amdgpu_pcie_lane_cap = 0; 96 unsigned amdgpu_cg_mask = 0xffffffff; 97 unsigned amdgpu_pg_mask = 0xffffffff; 98 char *amdgpu_disable_cu = NULL; 99 char *amdgpu_virtual_display = NULL; 100 unsigned amdgpu_pp_feature_mask = 0xffffffff; 101 102 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 103 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 104 105 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)"); 106 module_param_named(gartsize, amdgpu_gart_size, int, 0600); 107 108 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 109 module_param_named(moverate, amdgpu_moverate, int, 0600); 110 111 MODULE_PARM_DESC(benchmark, "Run benchmark"); 112 module_param_named(benchmark, amdgpu_benchmarking, int, 0444); 113 114 MODULE_PARM_DESC(test, "Run tests"); 115 module_param_named(test, amdgpu_testing, int, 0444); 116 117 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 118 module_param_named(audio, amdgpu_audio, int, 0444); 119 120 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 121 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 122 123 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 124 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 125 126 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 127 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 128 129 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 130 module_param_named(msi, amdgpu_msi, int, 0444); 131 132 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 0 = disable)"); 133 module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444); 134 135 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 136 module_param_named(dpm, amdgpu_dpm, int, 0444); 137 138 MODULE_PARM_DESC(smc_load_fw, "SMC firmware loading(1 = enable, 0 = disable)"); 139 module_param_named(smc_load_fw, amdgpu_smc_load_fw, int, 0444); 140 141 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 142 module_param_named(aspm, amdgpu_aspm, int, 0444); 143 144 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 145 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 146 147 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 148 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 149 150 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 151 module_param_named(bapm, amdgpu_bapm, int, 0444); 152 153 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 154 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 155 156 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 157 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 158 159 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 160 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 161 162 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 163 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 164 165 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 166 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 167 168 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 169 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 170 171 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 172 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 173 174 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 175 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 176 177 MODULE_PARM_DESC(powerplay, "Powerplay component (1 = enable, 0 = disable, -1 = auto (default))"); 178 module_param_named(powerplay, amdgpu_powerplay, int, 0444); 179 180 MODULE_PARM_DESC(powercontainment, "Power Containment (1 = enable (default), 0 = disable)"); 181 module_param_named(powercontainment, amdgpu_powercontainment, int, 0444); 182 183 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 184 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, int, 0444); 185 186 MODULE_PARM_DESC(sclkdeepsleep, "SCLK Deep Sleep (1 = enable (default), 0 = disable)"); 187 module_param_named(sclkdeepsleep, amdgpu_sclk_deep_sleep_en, int, 0444); 188 189 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 190 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 191 192 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 193 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 194 195 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 196 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); 197 198 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 199 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 200 201 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 202 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 203 204 MODULE_PARM_DESC(virtual_display, "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x;xxxx:xx:xx.x)"); 205 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 206 207 static const struct pci_device_id pciidlist[] = { 208 #ifdef CONFIG_DRM_AMDGPU_SI 209 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 210 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 211 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 212 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 213 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 214 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 215 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 216 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 217 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 218 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 219 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 220 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 221 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 222 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 223 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 224 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 225 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 226 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 227 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 228 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 229 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 230 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 231 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 232 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 233 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 234 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 235 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 236 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 237 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 238 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 239 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 240 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 241 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 242 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 243 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 244 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 245 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 246 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 247 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 248 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 249 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 250 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 251 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 252 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 253 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 254 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 255 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 256 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 257 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 258 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 259 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 260 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 261 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 262 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 263 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 264 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 265 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 266 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 267 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 268 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 269 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 270 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 271 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 272 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 273 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 274 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 275 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 276 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 277 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 278 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 279 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 280 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 281 #endif 282 #ifdef CONFIG_DRM_AMDGPU_CIK 283 /* Kaveri */ 284 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 285 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 286 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 287 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 288 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 289 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 290 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 291 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 292 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 293 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 294 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 295 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 296 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 297 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 298 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 299 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 300 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 301 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 302 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 303 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 304 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 305 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 306 /* Bonaire */ 307 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 308 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 309 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 310 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 311 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 312 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 313 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 314 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 315 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 316 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 317 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 318 /* Hawaii */ 319 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 320 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 321 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 322 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 323 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 324 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 325 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 326 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 327 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 328 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 329 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 330 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 331 /* Kabini */ 332 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 333 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 334 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 335 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 336 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 337 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 338 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 339 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 340 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 341 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 342 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 343 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 344 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 345 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 346 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 347 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 348 /* mullins */ 349 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 350 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 351 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 352 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 353 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 354 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 355 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 356 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 357 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 358 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 359 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 360 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 361 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 362 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 363 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 364 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 365 #endif 366 /* topaz */ 367 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 368 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 369 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 370 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 371 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 372 /* tonga */ 373 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 374 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 375 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 376 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 377 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 378 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 379 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 380 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 381 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 382 /* fiji */ 383 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 384 /* carrizo */ 385 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 386 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 387 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 388 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 389 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 390 /* stoney */ 391 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 392 /* Polaris11 */ 393 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 394 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 395 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 396 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 397 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 398 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 399 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 400 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 401 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 402 /* Polaris10 */ 403 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 404 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 405 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 406 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 407 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 408 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 409 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 410 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 411 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 412 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 413 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 414 415 {0, 0, 0} 416 }; 417 418 MODULE_DEVICE_TABLE(pci, pciidlist); 419 420 static struct drm_driver kms_driver; 421 422 static int amdgpu_kick_out_firmware_fb(struct pci_dev *pdev) 423 { 424 struct apertures_struct *ap; 425 bool primary = false; 426 427 ap = alloc_apertures(1); 428 if (!ap) 429 return -ENOMEM; 430 431 ap->ranges[0].base = pci_resource_start(pdev, 0); 432 ap->ranges[0].size = pci_resource_len(pdev, 0); 433 434 #ifdef CONFIG_X86 435 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; 436 #endif 437 drm_fb_helper_remove_conflicting_framebuffers(ap, "amdgpudrmfb", primary); 438 kfree(ap); 439 440 return 0; 441 } 442 443 static int amdgpu_pci_probe(struct pci_dev *pdev, 444 const struct pci_device_id *ent) 445 { 446 unsigned long flags = ent->driver_data; 447 int ret; 448 449 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 450 DRM_INFO("This hardware requires experimental hardware support.\n" 451 "See modparam exp_hw_support\n"); 452 return -ENODEV; 453 } 454 455 /* 456 * Initialize amdkfd before starting radeon. If it was not loaded yet, 457 * defer radeon probing 458 */ 459 ret = amdgpu_amdkfd_init(); 460 if (ret == -EPROBE_DEFER) 461 return ret; 462 463 /* Get rid of things like offb */ 464 ret = amdgpu_kick_out_firmware_fb(pdev); 465 if (ret) 466 return ret; 467 468 return drm_get_pci_dev(pdev, ent, &kms_driver); 469 } 470 471 static void 472 amdgpu_pci_remove(struct pci_dev *pdev) 473 { 474 struct drm_device *dev = pci_get_drvdata(pdev); 475 476 drm_put_dev(dev); 477 } 478 479 static void 480 amdgpu_pci_shutdown(struct pci_dev *pdev) 481 { 482 struct drm_device *dev = pci_get_drvdata(pdev); 483 struct amdgpu_device *adev = dev->dev_private; 484 485 /* if we are running in a VM, make sure the device 486 * torn down properly on reboot/shutdown. 487 * unfortunately we can't detect certain 488 * hypervisors so just do this all the time. 489 */ 490 amdgpu_suspend(adev); 491 } 492 493 static int amdgpu_pmops_suspend(struct device *dev) 494 { 495 struct pci_dev *pdev = to_pci_dev(dev); 496 497 struct drm_device *drm_dev = pci_get_drvdata(pdev); 498 return amdgpu_device_suspend(drm_dev, true, true); 499 } 500 501 static int amdgpu_pmops_resume(struct device *dev) 502 { 503 struct pci_dev *pdev = to_pci_dev(dev); 504 struct drm_device *drm_dev = pci_get_drvdata(pdev); 505 506 /* GPU comes up enabled by the bios on resume */ 507 if (amdgpu_device_is_px(drm_dev)) { 508 pm_runtime_disable(dev); 509 pm_runtime_set_active(dev); 510 pm_runtime_enable(dev); 511 } 512 513 return amdgpu_device_resume(drm_dev, true, true); 514 } 515 516 static int amdgpu_pmops_freeze(struct device *dev) 517 { 518 struct pci_dev *pdev = to_pci_dev(dev); 519 520 struct drm_device *drm_dev = pci_get_drvdata(pdev); 521 return amdgpu_device_suspend(drm_dev, false, true); 522 } 523 524 static int amdgpu_pmops_thaw(struct device *dev) 525 { 526 struct pci_dev *pdev = to_pci_dev(dev); 527 528 struct drm_device *drm_dev = pci_get_drvdata(pdev); 529 return amdgpu_device_resume(drm_dev, false, true); 530 } 531 532 static int amdgpu_pmops_poweroff(struct device *dev) 533 { 534 struct pci_dev *pdev = to_pci_dev(dev); 535 536 struct drm_device *drm_dev = pci_get_drvdata(pdev); 537 return amdgpu_device_suspend(drm_dev, true, true); 538 } 539 540 static int amdgpu_pmops_restore(struct device *dev) 541 { 542 struct pci_dev *pdev = to_pci_dev(dev); 543 544 struct drm_device *drm_dev = pci_get_drvdata(pdev); 545 return amdgpu_device_resume(drm_dev, false, true); 546 } 547 548 static int amdgpu_pmops_runtime_suspend(struct device *dev) 549 { 550 struct pci_dev *pdev = to_pci_dev(dev); 551 struct drm_device *drm_dev = pci_get_drvdata(pdev); 552 int ret; 553 554 if (!amdgpu_device_is_px(drm_dev)) { 555 pm_runtime_forbid(dev); 556 return -EBUSY; 557 } 558 559 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 560 drm_kms_helper_poll_disable(drm_dev); 561 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF); 562 563 ret = amdgpu_device_suspend(drm_dev, false, false); 564 pci_save_state(pdev); 565 pci_disable_device(pdev); 566 pci_ignore_hotplug(pdev); 567 if (amdgpu_is_atpx_hybrid()) 568 pci_set_power_state(pdev, PCI_D3cold); 569 else if (!amdgpu_has_atpx_dgpu_power_cntl()) 570 pci_set_power_state(pdev, PCI_D3hot); 571 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 572 573 return 0; 574 } 575 576 static int amdgpu_pmops_runtime_resume(struct device *dev) 577 { 578 struct pci_dev *pdev = to_pci_dev(dev); 579 struct drm_device *drm_dev = pci_get_drvdata(pdev); 580 int ret; 581 582 if (!amdgpu_device_is_px(drm_dev)) 583 return -EINVAL; 584 585 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 586 587 if (amdgpu_is_atpx_hybrid() || 588 !amdgpu_has_atpx_dgpu_power_cntl()) 589 pci_set_power_state(pdev, PCI_D0); 590 pci_restore_state(pdev); 591 ret = pci_enable_device(pdev); 592 if (ret) 593 return ret; 594 pci_set_master(pdev); 595 596 ret = amdgpu_device_resume(drm_dev, false, false); 597 drm_kms_helper_poll_enable(drm_dev); 598 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON); 599 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 600 return 0; 601 } 602 603 static int amdgpu_pmops_runtime_idle(struct device *dev) 604 { 605 struct pci_dev *pdev = to_pci_dev(dev); 606 struct drm_device *drm_dev = pci_get_drvdata(pdev); 607 struct drm_crtc *crtc; 608 609 if (!amdgpu_device_is_px(drm_dev)) { 610 pm_runtime_forbid(dev); 611 return -EBUSY; 612 } 613 614 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 615 if (crtc->enabled) { 616 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 617 return -EBUSY; 618 } 619 } 620 621 pm_runtime_mark_last_busy(dev); 622 pm_runtime_autosuspend(dev); 623 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 624 return 1; 625 } 626 627 long amdgpu_drm_ioctl(struct file *filp, 628 unsigned int cmd, unsigned long arg) 629 { 630 struct drm_file *file_priv = filp->private_data; 631 struct drm_device *dev; 632 long ret; 633 dev = file_priv->minor->dev; 634 ret = pm_runtime_get_sync(dev->dev); 635 if (ret < 0) 636 return ret; 637 638 ret = drm_ioctl(filp, cmd, arg); 639 640 pm_runtime_mark_last_busy(dev->dev); 641 pm_runtime_put_autosuspend(dev->dev); 642 return ret; 643 } 644 645 static const struct dev_pm_ops amdgpu_pm_ops = { 646 .suspend = amdgpu_pmops_suspend, 647 .resume = amdgpu_pmops_resume, 648 .freeze = amdgpu_pmops_freeze, 649 .thaw = amdgpu_pmops_thaw, 650 .poweroff = amdgpu_pmops_poweroff, 651 .restore = amdgpu_pmops_restore, 652 .runtime_suspend = amdgpu_pmops_runtime_suspend, 653 .runtime_resume = amdgpu_pmops_runtime_resume, 654 .runtime_idle = amdgpu_pmops_runtime_idle, 655 }; 656 657 static const struct file_operations amdgpu_driver_kms_fops = { 658 .owner = THIS_MODULE, 659 .open = drm_open, 660 .release = drm_release, 661 .unlocked_ioctl = amdgpu_drm_ioctl, 662 .mmap = amdgpu_mmap, 663 .poll = drm_poll, 664 .read = drm_read, 665 #ifdef CONFIG_COMPAT 666 .compat_ioctl = amdgpu_kms_compat_ioctl, 667 #endif 668 }; 669 670 static struct drm_driver kms_driver = { 671 .driver_features = 672 DRIVER_USE_AGP | 673 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | 674 DRIVER_PRIME | DRIVER_RENDER | DRIVER_MODESET, 675 .dev_priv_size = 0, 676 .load = amdgpu_driver_load_kms, 677 .open = amdgpu_driver_open_kms, 678 .preclose = amdgpu_driver_preclose_kms, 679 .postclose = amdgpu_driver_postclose_kms, 680 .lastclose = amdgpu_driver_lastclose_kms, 681 .set_busid = drm_pci_set_busid, 682 .unload = amdgpu_driver_unload_kms, 683 .get_vblank_counter = amdgpu_get_vblank_counter_kms, 684 .enable_vblank = amdgpu_enable_vblank_kms, 685 .disable_vblank = amdgpu_disable_vblank_kms, 686 .get_vblank_timestamp = amdgpu_get_vblank_timestamp_kms, 687 .get_scanout_position = amdgpu_get_crtc_scanoutpos, 688 #if defined(CONFIG_DEBUG_FS) 689 .debugfs_init = amdgpu_debugfs_init, 690 .debugfs_cleanup = amdgpu_debugfs_cleanup, 691 #endif 692 .irq_preinstall = amdgpu_irq_preinstall, 693 .irq_postinstall = amdgpu_irq_postinstall, 694 .irq_uninstall = amdgpu_irq_uninstall, 695 .irq_handler = amdgpu_irq_handler, 696 .ioctls = amdgpu_ioctls_kms, 697 .gem_free_object_unlocked = amdgpu_gem_object_free, 698 .gem_open_object = amdgpu_gem_object_open, 699 .gem_close_object = amdgpu_gem_object_close, 700 .dumb_create = amdgpu_mode_dumb_create, 701 .dumb_map_offset = amdgpu_mode_dumb_mmap, 702 .dumb_destroy = drm_gem_dumb_destroy, 703 .fops = &amdgpu_driver_kms_fops, 704 705 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 706 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 707 .gem_prime_export = amdgpu_gem_prime_export, 708 .gem_prime_import = drm_gem_prime_import, 709 .gem_prime_pin = amdgpu_gem_prime_pin, 710 .gem_prime_unpin = amdgpu_gem_prime_unpin, 711 .gem_prime_res_obj = amdgpu_gem_prime_res_obj, 712 .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table, 713 .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table, 714 .gem_prime_vmap = amdgpu_gem_prime_vmap, 715 .gem_prime_vunmap = amdgpu_gem_prime_vunmap, 716 717 .name = DRIVER_NAME, 718 .desc = DRIVER_DESC, 719 .date = DRIVER_DATE, 720 .major = KMS_DRIVER_MAJOR, 721 .minor = KMS_DRIVER_MINOR, 722 .patchlevel = KMS_DRIVER_PATCHLEVEL, 723 }; 724 725 static struct drm_driver *driver; 726 static struct pci_driver *pdriver; 727 728 static struct pci_driver amdgpu_kms_pci_driver = { 729 .name = DRIVER_NAME, 730 .id_table = pciidlist, 731 .probe = amdgpu_pci_probe, 732 .remove = amdgpu_pci_remove, 733 .shutdown = amdgpu_pci_shutdown, 734 .driver.pm = &amdgpu_pm_ops, 735 }; 736 737 738 739 static int __init amdgpu_init(void) 740 { 741 int r; 742 743 r = amdgpu_sync_init(); 744 if (r) 745 goto error_sync; 746 747 r = amdgpu_fence_slab_init(); 748 if (r) 749 goto error_fence; 750 751 r = amd_sched_fence_slab_init(); 752 if (r) 753 goto error_sched; 754 755 if (vgacon_text_force()) { 756 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); 757 return -EINVAL; 758 } 759 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 760 driver = &kms_driver; 761 pdriver = &amdgpu_kms_pci_driver; 762 driver->num_ioctls = amdgpu_max_kms_ioctl; 763 amdgpu_register_atpx_handler(); 764 /* let modprobe override vga console setting */ 765 return drm_pci_init(driver, pdriver); 766 767 error_sched: 768 amdgpu_fence_slab_fini(); 769 770 error_fence: 771 amdgpu_sync_fini(); 772 773 error_sync: 774 return r; 775 } 776 777 static void __exit amdgpu_exit(void) 778 { 779 amdgpu_amdkfd_fini(); 780 drm_pci_exit(driver, pdriver); 781 amdgpu_unregister_atpx_handler(); 782 amdgpu_sync_fini(); 783 amd_sched_fence_slab_fini(); 784 amdgpu_fence_slab_fini(); 785 } 786 787 module_init(amdgpu_init); 788 module_exit(amdgpu_exit); 789 790 MODULE_AUTHOR(DRIVER_AUTHOR); 791 MODULE_DESCRIPTION(DRIVER_DESC); 792 MODULE_LICENSE("GPL and additional rights"); 793