1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_drv.h> 27 #include <drm/drm_fbdev_ttm.h> 28 #include <drm/drm_gem.h> 29 #include <drm/drm_managed.h> 30 #include <drm/drm_pciids.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/drm_vblank.h> 33 34 #include <linux/cc_platform.h> 35 #include <linux/dynamic_debug.h> 36 #include <linux/module.h> 37 #include <linux/mmu_notifier.h> 38 #include <linux/pm_runtime.h> 39 #include <linux/suspend.h> 40 #include <linux/vga_switcheroo.h> 41 42 #include "amdgpu.h" 43 #include "amdgpu_amdkfd.h" 44 #include "amdgpu_dma_buf.h" 45 #include "amdgpu_drv.h" 46 #include "amdgpu_fdinfo.h" 47 #include "amdgpu_irq.h" 48 #include "amdgpu_psp.h" 49 #include "amdgpu_ras.h" 50 #include "amdgpu_reset.h" 51 #include "amdgpu_sched.h" 52 #include "amdgpu_xgmi.h" 53 #include "../amdxcp/amdgpu_xcp_drv.h" 54 55 /* 56 * KMS wrapper. 57 * - 3.0.0 - initial driver 58 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 59 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 60 * at the end of IBs. 61 * - 3.3.0 - Add VM support for UVD on supported hardware. 62 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 63 * - 3.5.0 - Add support for new UVD_NO_OP register. 64 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 65 * - 3.7.0 - Add support for VCE clock list packet 66 * - 3.8.0 - Add support raster config init in the kernel 67 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 68 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 69 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 70 * - 3.12.0 - Add query for double offchip LDS buffers 71 * - 3.13.0 - Add PRT support 72 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 73 * - 3.15.0 - Export more gpu info for gfx9 74 * - 3.16.0 - Add reserved vmid support 75 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 76 * - 3.18.0 - Export gpu always on cu bitmap 77 * - 3.19.0 - Add support for UVD MJPEG decode 78 * - 3.20.0 - Add support for local BOs 79 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 80 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 81 * - 3.23.0 - Add query for VRAM lost counter 82 * - 3.24.0 - Add high priority compute support for gfx9 83 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 84 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 85 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation. 86 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 87 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 88 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 89 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 90 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 91 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 92 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 93 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 94 * - 3.36.0 - Allow reading more status registers on si/cik 95 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 96 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 97 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 98 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 99 * - 3.41.0 - Add video codec query 100 * - 3.42.0 - Add 16bpc fixed point display support 101 * - 3.43.0 - Add device hot plug/unplug support 102 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 103 * - 3.45.0 - Add context ioctl stable pstate interface 104 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm 105 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags 106 * - 3.48.0 - Add IP discovery version info to HW INFO 107 * - 3.49.0 - Add gang submit into CS IOCTL 108 * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock 109 * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock 110 * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl 111 * 3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields: 112 * tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size, 113 * gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi 114 * 3.53.0 - Support for GFX11 CP GFX shadowing 115 * 3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support 116 * - 3.55.0 - Add AMDGPU_INFO_GPUVM_FAULT query 117 * - 3.56.0 - Update IB start address and size alignment for decode and encode 118 * - 3.57.0 - Compute tunneling on GFX10+ 119 * - 3.58.0 - Add GFX12 DCC support 120 */ 121 #define KMS_DRIVER_MAJOR 3 122 #define KMS_DRIVER_MINOR 58 123 #define KMS_DRIVER_PATCHLEVEL 0 124 125 /* 126 * amdgpu.debug module options. Are all disabled by default 127 */ 128 enum AMDGPU_DEBUG_MASK { 129 AMDGPU_DEBUG_VM = BIT(0), 130 AMDGPU_DEBUG_LARGEBAR = BIT(1), 131 AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY = BIT(2), 132 AMDGPU_DEBUG_USE_VRAM_FW_BUF = BIT(3), 133 AMDGPU_DEBUG_ENABLE_RAS_ACA = BIT(4), 134 AMDGPU_DEBUG_ENABLE_EXP_RESETS = BIT(5), 135 }; 136 137 unsigned int amdgpu_vram_limit = UINT_MAX; 138 int amdgpu_vis_vram_limit; 139 int amdgpu_gart_size = -1; /* auto */ 140 int amdgpu_gtt_size = -1; /* auto */ 141 int amdgpu_moverate = -1; /* auto */ 142 int amdgpu_audio = -1; 143 int amdgpu_disp_priority; 144 int amdgpu_hw_i2c; 145 int amdgpu_pcie_gen2 = -1; 146 int amdgpu_msi = -1; 147 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 148 int amdgpu_dpm = -1; 149 int amdgpu_fw_load_type = -1; 150 int amdgpu_aspm = -1; 151 int amdgpu_runtime_pm = -1; 152 uint amdgpu_ip_block_mask = 0xffffffff; 153 int amdgpu_bapm = -1; 154 int amdgpu_deep_color; 155 int amdgpu_vm_size = -1; 156 int amdgpu_vm_fragment_size = -1; 157 int amdgpu_vm_block_size = -1; 158 int amdgpu_vm_fault_stop; 159 int amdgpu_vm_update_mode = -1; 160 int amdgpu_exp_hw_support; 161 int amdgpu_dc = -1; 162 int amdgpu_sched_jobs = 32; 163 int amdgpu_sched_hw_submission = 2; 164 uint amdgpu_pcie_gen_cap; 165 uint amdgpu_pcie_lane_cap; 166 u64 amdgpu_cg_mask = 0xffffffffffffffff; 167 uint amdgpu_pg_mask = 0xffffffff; 168 uint amdgpu_sdma_phase_quantum = 32; 169 char *amdgpu_disable_cu; 170 char *amdgpu_virtual_display; 171 bool enforce_isolation; 172 /* 173 * OverDrive(bit 14) disabled by default 174 * GFX DCS(bit 19) disabled by default 175 */ 176 uint amdgpu_pp_feature_mask = 0xfff7bfff; 177 uint amdgpu_force_long_training; 178 int amdgpu_lbpw = -1; 179 int amdgpu_compute_multipipe = -1; 180 int amdgpu_gpu_recovery = -1; /* auto */ 181 int amdgpu_emu_mode; 182 uint amdgpu_smu_memory_pool_size; 183 int amdgpu_smu_pptable_id = -1; 184 /* 185 * FBC (bit 0) disabled by default 186 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 187 * - With this, for multiple monitors in sync(e.g. with the same model), 188 * mclk switching will be allowed. And the mclk will be not foced to the 189 * highest. That helps saving some idle power. 190 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 191 * PSR (bit 3) disabled by default 192 * EDP NO POWER SEQUENCING (bit 4) disabled by default 193 */ 194 uint amdgpu_dc_feature_mask = 2; 195 uint amdgpu_dc_debug_mask; 196 uint amdgpu_dc_visual_confirm; 197 int amdgpu_async_gfx_ring = 1; 198 int amdgpu_mcbp = -1; 199 int amdgpu_discovery = -1; 200 int amdgpu_mes; 201 int amdgpu_mes_log_enable = 0; 202 int amdgpu_mes_kiq; 203 int amdgpu_uni_mes = 1; 204 int amdgpu_noretry = -1; 205 int amdgpu_force_asic_type = -1; 206 int amdgpu_tmz = -1; /* auto */ 207 uint amdgpu_freesync_vid_mode; 208 int amdgpu_reset_method = -1; /* auto */ 209 int amdgpu_num_kcq = -1; 210 int amdgpu_smartshift_bias; 211 int amdgpu_use_xgmi_p2p = 1; 212 int amdgpu_vcnfw_log; 213 int amdgpu_sg_display = -1; /* auto */ 214 int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE; 215 int amdgpu_umsch_mm; 216 int amdgpu_seamless = -1; /* auto */ 217 uint amdgpu_debug_mask; 218 int amdgpu_agp = -1; /* auto */ 219 int amdgpu_wbrf = -1; 220 int amdgpu_damage_clips = -1; /* auto */ 221 int amdgpu_umsch_mm_fwlog; 222 223 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 224 225 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 226 "DRM_UT_CORE", 227 "DRM_UT_DRIVER", 228 "DRM_UT_KMS", 229 "DRM_UT_PRIME", 230 "DRM_UT_ATOMIC", 231 "DRM_UT_VBL", 232 "DRM_UT_STATE", 233 "DRM_UT_LEASE", 234 "DRM_UT_DP", 235 "DRM_UT_DRMRES"); 236 237 struct amdgpu_mgpu_info mgpu_info = { 238 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 239 .delayed_reset_work = __DELAYED_WORK_INITIALIZER( 240 mgpu_info.delayed_reset_work, 241 amdgpu_drv_delayed_reset_work_handler, 0), 242 }; 243 int amdgpu_ras_enable = -1; 244 uint amdgpu_ras_mask = 0xffffffff; 245 int amdgpu_bad_page_threshold = -1; 246 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 247 .timeout_fatal_disable = false, 248 .period = 0x0, /* default to 0x0 (timeout disable) */ 249 }; 250 251 /** 252 * DOC: vramlimit (int) 253 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 254 */ 255 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 256 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 257 258 /** 259 * DOC: vis_vramlimit (int) 260 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 261 */ 262 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 263 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 264 265 /** 266 * DOC: gartsize (uint) 267 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing. 268 * The default is -1 (The size depends on asic). 269 */ 270 MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)"); 271 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 272 273 /** 274 * DOC: gttsize (int) 275 * Restrict the size of GTT domain (for userspace use) in MiB for testing. 276 * The default is -1 (Use 1/2 RAM, minimum value is 3GB). 277 */ 278 MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)"); 279 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 280 281 /** 282 * DOC: moverate (int) 283 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 284 */ 285 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 286 module_param_named(moverate, amdgpu_moverate, int, 0600); 287 288 /** 289 * DOC: audio (int) 290 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 291 */ 292 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 293 module_param_named(audio, amdgpu_audio, int, 0444); 294 295 /** 296 * DOC: disp_priority (int) 297 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 298 */ 299 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 300 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 301 302 /** 303 * DOC: hw_i2c (int) 304 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 305 */ 306 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 307 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 308 309 /** 310 * DOC: pcie_gen2 (int) 311 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 312 */ 313 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 314 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 315 316 /** 317 * DOC: msi (int) 318 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 319 */ 320 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 321 module_param_named(msi, amdgpu_msi, int, 0444); 322 323 /** 324 * DOC: lockup_timeout (string) 325 * Set GPU scheduler timeout value in ms. 326 * 327 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 328 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 329 * to the default timeout. 330 * 331 * - With one value specified, the setting will apply to all non-compute jobs. 332 * - With multiple values specified, the first one will be for GFX. 333 * The second one is for Compute. The third and fourth ones are 334 * for SDMA and Video. 335 * 336 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 337 * jobs is 10000. The timeout for compute is 60000. 338 */ 339 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 340 "for passthrough or sriov, 10000 for all jobs. 0: keep default value. negative: infinity timeout), format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 341 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 342 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 343 344 /** 345 * DOC: dpm (int) 346 * Override for dynamic power management setting 347 * (0 = disable, 1 = enable) 348 * The default is -1 (auto). 349 */ 350 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 351 module_param_named(dpm, amdgpu_dpm, int, 0444); 352 353 /** 354 * DOC: fw_load_type (int) 355 * Set different firmware loading type for debugging, if supported. 356 * Set to 0 to force direct loading if supported by the ASIC. Set 357 * to -1 to select the default loading mode for the ASIC, as defined 358 * by the driver. The default is -1 (auto). 359 */ 360 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); 361 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 362 363 /** 364 * DOC: aspm (int) 365 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 366 */ 367 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 368 module_param_named(aspm, amdgpu_aspm, int, 0444); 369 370 /** 371 * DOC: runpm (int) 372 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 373 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 374 * Setting the value to 0 disables this functionality. 375 * Setting the value to -2 is auto enabled with power down when displays are attached. 376 */ 377 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto, -2 = auto with displays)"); 378 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 379 380 /** 381 * DOC: ip_block_mask (uint) 382 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 383 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 384 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 385 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 386 */ 387 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 388 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 389 390 /** 391 * DOC: bapm (int) 392 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 393 * The default -1 (auto, enabled) 394 */ 395 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 396 module_param_named(bapm, amdgpu_bapm, int, 0444); 397 398 /** 399 * DOC: deep_color (int) 400 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 401 */ 402 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 403 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 404 405 /** 406 * DOC: vm_size (int) 407 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 408 */ 409 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 410 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 411 412 /** 413 * DOC: vm_fragment_size (int) 414 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 415 */ 416 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 417 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 418 419 /** 420 * DOC: vm_block_size (int) 421 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 422 */ 423 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 424 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 425 426 /** 427 * DOC: vm_fault_stop (int) 428 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 429 */ 430 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 431 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 432 433 /** 434 * DOC: vm_update_mode (int) 435 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 436 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 437 */ 438 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 439 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 440 441 /** 442 * DOC: exp_hw_support (int) 443 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 444 */ 445 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 446 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 447 448 /** 449 * DOC: dc (int) 450 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 451 */ 452 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 453 module_param_named(dc, amdgpu_dc, int, 0444); 454 455 /** 456 * DOC: sched_jobs (int) 457 * Override the max number of jobs supported in the sw queue. The default is 32. 458 */ 459 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 460 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 461 462 /** 463 * DOC: sched_hw_submission (int) 464 * Override the max number of HW submissions. The default is 2. 465 */ 466 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 467 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 468 469 /** 470 * DOC: ppfeaturemask (hexint) 471 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 472 * The default is the current set of stable power features. 473 */ 474 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 475 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 476 477 /** 478 * DOC: forcelongtraining (uint) 479 * Force long memory training in resume. 480 * The default is zero, indicates short training in resume. 481 */ 482 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 483 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 484 485 /** 486 * DOC: pcie_gen_cap (uint) 487 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 488 * The default is 0 (automatic for each asic). 489 */ 490 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 491 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 492 493 /** 494 * DOC: pcie_lane_cap (uint) 495 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 496 * The default is 0 (automatic for each asic). 497 */ 498 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 499 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 500 501 /** 502 * DOC: cg_mask (ullong) 503 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 504 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 505 */ 506 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 507 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 508 509 /** 510 * DOC: pg_mask (uint) 511 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 512 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 513 */ 514 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 515 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 516 517 /** 518 * DOC: sdma_phase_quantum (uint) 519 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 520 */ 521 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 522 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 523 524 /** 525 * DOC: disable_cu (charp) 526 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 527 */ 528 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 529 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 530 531 /** 532 * DOC: virtual_display (charp) 533 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 534 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 535 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 536 * device at 26:00.0. The default is NULL. 537 */ 538 MODULE_PARM_DESC(virtual_display, 539 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 540 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 541 542 /** 543 * DOC: lbpw (int) 544 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 545 */ 546 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 547 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 548 549 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 550 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 551 552 /** 553 * DOC: gpu_recovery (int) 554 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 555 */ 556 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 557 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 558 559 /** 560 * DOC: emu_mode (int) 561 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 562 */ 563 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 564 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 565 566 /** 567 * DOC: ras_enable (int) 568 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 569 */ 570 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 571 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 572 573 /** 574 * DOC: ras_mask (uint) 575 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 576 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 577 */ 578 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 579 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 580 581 /** 582 * DOC: timeout_fatal_disable (bool) 583 * Disable Watchdog timeout fatal error event 584 */ 585 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 586 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 587 588 /** 589 * DOC: timeout_period (uint) 590 * Modify the watchdog timeout max_cycles as (1 << period) 591 */ 592 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 593 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 594 595 /** 596 * DOC: si_support (int) 597 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 598 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 599 * otherwise using amdgpu driver. 600 */ 601 #ifdef CONFIG_DRM_AMDGPU_SI 602 603 #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) 604 int amdgpu_si_support; 605 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 606 #else 607 int amdgpu_si_support = 1; 608 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 609 #endif 610 611 module_param_named(si_support, amdgpu_si_support, int, 0444); 612 #endif 613 614 /** 615 * DOC: cik_support (int) 616 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 617 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 618 * otherwise using amdgpu driver. 619 */ 620 #ifdef CONFIG_DRM_AMDGPU_CIK 621 622 #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) 623 int amdgpu_cik_support; 624 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 625 #else 626 int amdgpu_cik_support = 1; 627 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 628 #endif 629 630 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 631 #endif 632 633 /** 634 * DOC: smu_memory_pool_size (uint) 635 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 636 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 637 */ 638 MODULE_PARM_DESC(smu_memory_pool_size, 639 "reserve gtt for smu debug usage, 0 = disable,0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 640 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 641 642 /** 643 * DOC: async_gfx_ring (int) 644 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 645 */ 646 MODULE_PARM_DESC(async_gfx_ring, 647 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 648 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 649 650 /** 651 * DOC: mcbp (int) 652 * It is used to enable mid command buffer preemption. (0 = disabled, 1 = enabled, -1 auto (default)) 653 */ 654 MODULE_PARM_DESC(mcbp, 655 "Enable Mid-command buffer preemption (0 = disabled, 1 = enabled), -1 = auto (default)"); 656 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 657 658 /** 659 * DOC: discovery (int) 660 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 661 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 662 */ 663 MODULE_PARM_DESC(discovery, 664 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 665 module_param_named(discovery, amdgpu_discovery, int, 0444); 666 667 /** 668 * DOC: mes (int) 669 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 670 * (0 = disabled (default), 1 = enabled) 671 */ 672 MODULE_PARM_DESC(mes, 673 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 674 module_param_named(mes, amdgpu_mes, int, 0444); 675 676 /** 677 * DOC: mes_log_enable (int) 678 * Enable Micro Engine Scheduler log. This is used to enable/disable MES internal log. 679 * (0 = disabled (default), 1 = enabled) 680 */ 681 MODULE_PARM_DESC(mes_log_enable, 682 "Enable Micro Engine Scheduler log (0 = disabled (default), 1 = enabled)"); 683 module_param_named(mes_log_enable, amdgpu_mes_log_enable, int, 0444); 684 685 /** 686 * DOC: mes_kiq (int) 687 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq. 688 * (0 = disabled (default), 1 = enabled) 689 */ 690 MODULE_PARM_DESC(mes_kiq, 691 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)"); 692 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444); 693 694 /** 695 * DOC: uni_mes (int) 696 * Enable Unified Micro Engine Scheduler. This is a new engine pipe for unified scheduler. 697 * (0 = disabled (default), 1 = enabled) 698 */ 699 MODULE_PARM_DESC(uni_mes, 700 "Enable Unified Micro Engine Scheduler (0 = disabled, 1 = enabled(default)"); 701 module_param_named(uni_mes, amdgpu_uni_mes, int, 0444); 702 703 /** 704 * DOC: noretry (int) 705 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 706 * do not support per-process XNACK this also disables retry page faults. 707 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 708 */ 709 MODULE_PARM_DESC(noretry, 710 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 711 module_param_named(noretry, amdgpu_noretry, int, 0644); 712 713 /** 714 * DOC: force_asic_type (int) 715 * A non negative value used to specify the asic type for all supported GPUs. 716 */ 717 MODULE_PARM_DESC(force_asic_type, 718 "A non negative value used to specify the asic type for all supported GPUs"); 719 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 720 721 /** 722 * DOC: use_xgmi_p2p (int) 723 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 724 */ 725 MODULE_PARM_DESC(use_xgmi_p2p, 726 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 727 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 728 729 730 #ifdef CONFIG_HSA_AMD 731 /** 732 * DOC: sched_policy (int) 733 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 734 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 735 * assigns queues to HQDs. 736 */ 737 int sched_policy = KFD_SCHED_POLICY_HWS; 738 module_param(sched_policy, int, 0444); 739 MODULE_PARM_DESC(sched_policy, 740 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 741 742 /** 743 * DOC: hws_max_conc_proc (int) 744 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 745 * number of VMIDs assigned to the HWS, which is also the default. 746 */ 747 int hws_max_conc_proc = -1; 748 module_param(hws_max_conc_proc, int, 0444); 749 MODULE_PARM_DESC(hws_max_conc_proc, 750 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 751 752 /** 753 * DOC: cwsr_enable (int) 754 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 755 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 756 * disables it. 757 */ 758 int cwsr_enable = 1; 759 module_param(cwsr_enable, int, 0444); 760 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 761 762 /** 763 * DOC: max_num_of_queues_per_device (int) 764 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 765 * is 4096. 766 */ 767 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 768 module_param(max_num_of_queues_per_device, int, 0444); 769 MODULE_PARM_DESC(max_num_of_queues_per_device, 770 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 771 772 /** 773 * DOC: send_sigterm (int) 774 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 775 * but just print errors on dmesg. Setting 1 enables sending sigterm. 776 */ 777 int send_sigterm; 778 module_param(send_sigterm, int, 0444); 779 MODULE_PARM_DESC(send_sigterm, 780 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 781 782 /** 783 * DOC: halt_if_hws_hang (int) 784 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 785 * Setting 1 enables halt on hang. 786 */ 787 int halt_if_hws_hang; 788 module_param(halt_if_hws_hang, int, 0644); 789 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 790 791 /** 792 * DOC: hws_gws_support(bool) 793 * Assume that HWS supports GWS barriers regardless of what firmware version 794 * check says. Default value: false (rely on MEC2 firmware version check). 795 */ 796 bool hws_gws_support; 797 module_param(hws_gws_support, bool, 0444); 798 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 799 800 /** 801 * DOC: queue_preemption_timeout_ms (int) 802 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 803 */ 804 int queue_preemption_timeout_ms = 9000; 805 module_param(queue_preemption_timeout_ms, int, 0644); 806 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 807 808 /** 809 * DOC: debug_evictions(bool) 810 * Enable extra debug messages to help determine the cause of evictions 811 */ 812 bool debug_evictions; 813 module_param(debug_evictions, bool, 0644); 814 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 815 816 /** 817 * DOC: no_system_mem_limit(bool) 818 * Disable system memory limit, to support multiple process shared memory 819 */ 820 bool no_system_mem_limit; 821 module_param(no_system_mem_limit, bool, 0644); 822 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 823 824 /** 825 * DOC: no_queue_eviction_on_vm_fault (int) 826 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 827 */ 828 int amdgpu_no_queue_eviction_on_vm_fault; 829 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 830 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 831 #endif 832 833 /** 834 * DOC: mtype_local (int) 835 */ 836 int amdgpu_mtype_local; 837 MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (0 = MTYPE_RW (default), 1 = MTYPE_NC, 2 = MTYPE_CC)"); 838 module_param_named(mtype_local, amdgpu_mtype_local, int, 0444); 839 840 /** 841 * DOC: pcie_p2p (bool) 842 * Enable PCIe P2P (requires large-BAR). Default value: true (on) 843 */ 844 #ifdef CONFIG_HSA_AMD_P2P 845 bool pcie_p2p = true; 846 module_param(pcie_p2p, bool, 0444); 847 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); 848 #endif 849 850 /** 851 * DOC: dcfeaturemask (uint) 852 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 853 * The default is the current set of stable display features. 854 */ 855 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 856 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 857 858 /** 859 * DOC: dcdebugmask (uint) 860 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 861 */ 862 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 863 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 864 865 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)"); 866 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444); 867 868 /** 869 * DOC: abmlevel (uint) 870 * Override the default ABM (Adaptive Backlight Management) level used for DC 871 * enabled hardware. Requires DMCU to be supported and loaded. 872 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 873 * default. Values 1-4 control the maximum allowable brightness reduction via 874 * the ABM algorithm, with 1 being the least reduction and 4 being the most 875 * reduction. 876 * 877 * Defaults to -1, or disabled. Userspace can only override this level after 878 * boot if it's set to auto. 879 */ 880 int amdgpu_dm_abm_level = -1; 881 MODULE_PARM_DESC(abmlevel, 882 "ABM level (0 = off, 1-4 = backlight reduction level, -1 auto (default))"); 883 module_param_named(abmlevel, amdgpu_dm_abm_level, int, 0444); 884 885 int amdgpu_backlight = -1; 886 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 887 module_param_named(backlight, amdgpu_backlight, bint, 0444); 888 889 /** 890 * DOC: damageclips (int) 891 * Enable or disable damage clips support. If damage clips support is disabled, 892 * we will force full frame updates, irrespective of what user space sends to 893 * us. 894 * 895 * Defaults to -1 (where it is enabled unless a PSR-SU display is detected). 896 */ 897 MODULE_PARM_DESC(damageclips, 898 "Damage clips support (0 = disable, 1 = enable, -1 auto (default))"); 899 module_param_named(damageclips, amdgpu_damage_clips, int, 0444); 900 901 /** 902 * DOC: tmz (int) 903 * Trusted Memory Zone (TMZ) is a method to protect data being written 904 * to or read from memory. 905 * 906 * The default value: 0 (off). TODO: change to auto till it is completed. 907 */ 908 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 909 module_param_named(tmz, amdgpu_tmz, int, 0444); 910 911 /** 912 * DOC: freesync_video (uint) 913 * Enable the optimization to adjust front porch timing to achieve seamless 914 * mode change experience when setting a freesync supported mode for which full 915 * modeset is not needed. 916 * 917 * The Display Core will add a set of modes derived from the base FreeSync 918 * video mode into the corresponding connector's mode list based on commonly 919 * used refresh rates and VRR range of the connected display, when users enable 920 * this feature. From the userspace perspective, they can see a seamless mode 921 * change experience when the change between different refresh rates under the 922 * same resolution. Additionally, userspace applications such as Video playback 923 * can read this modeset list and change the refresh rate based on the video 924 * frame rate. Finally, the userspace can also derive an appropriate mode for a 925 * particular refresh rate based on the FreeSync Mode and add it to the 926 * connector's mode list. 927 * 928 * Note: This is an experimental feature. 929 * 930 * The default value: 0 (off). 931 */ 932 MODULE_PARM_DESC( 933 freesync_video, 934 "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)"); 935 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); 936 937 /** 938 * DOC: reset_method (int) 939 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 940 */ 941 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 942 module_param_named(reset_method, amdgpu_reset_method, int, 0644); 943 944 /** 945 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 946 * threshold value of faulty pages detected by RAS ECC, which may 947 * result in the GPU entering bad status when the number of total 948 * faulty pages by ECC exceeds the threshold value. 949 */ 950 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = driver sets threshold)"); 951 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 952 953 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 954 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 955 956 /** 957 * DOC: vcnfw_log (int) 958 * Enable vcnfw log output for debugging, the default is disabled. 959 */ 960 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 961 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 962 963 /** 964 * DOC: sg_display (int) 965 * Disable S/G (scatter/gather) display (i.e., display from system memory). 966 * This option is only relevant on APUs. Set this option to 0 to disable 967 * S/G display if you experience flickering or other issues under memory 968 * pressure and report the issue. 969 */ 970 MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)"); 971 module_param_named(sg_display, amdgpu_sg_display, int, 0444); 972 973 /** 974 * DOC: umsch_mm (int) 975 * Enable Multi Media User Mode Scheduler. This is a HW scheduling engine for VCN and VPE. 976 * (0 = disabled (default), 1 = enabled) 977 */ 978 MODULE_PARM_DESC(umsch_mm, 979 "Enable Multi Media User Mode Scheduler (0 = disabled (default), 1 = enabled)"); 980 module_param_named(umsch_mm, amdgpu_umsch_mm, int, 0444); 981 982 /** 983 * DOC: umsch_mm_fwlog (int) 984 * Enable umschfw log output for debugging, the default is disabled. 985 */ 986 MODULE_PARM_DESC(umsch_mm_fwlog, "Enable umschfw log(0 = disable (default value), 1 = enable)"); 987 module_param_named(umsch_mm_fwlog, amdgpu_umsch_mm_fwlog, int, 0444); 988 989 /** 990 * DOC: smu_pptable_id (int) 991 * Used to override pptable id. id = 0 use VBIOS pptable. 992 * id > 0 use the soft pptable with specicfied id. 993 */ 994 MODULE_PARM_DESC(smu_pptable_id, 995 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 996 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 997 998 /** 999 * DOC: partition_mode (int) 1000 * Used to override the default SPX mode. 1001 */ 1002 MODULE_PARM_DESC( 1003 user_partt_mode, 1004 "specify partition mode to be used (-2 = AMDGPU_AUTO_COMPUTE_PARTITION_MODE(default value) \ 1005 0 = AMDGPU_SPX_PARTITION_MODE, \ 1006 1 = AMDGPU_DPX_PARTITION_MODE, \ 1007 2 = AMDGPU_TPX_PARTITION_MODE, \ 1008 3 = AMDGPU_QPX_PARTITION_MODE, \ 1009 4 = AMDGPU_CPX_PARTITION_MODE)"); 1010 module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint, 0444); 1011 1012 1013 /** 1014 * DOC: enforce_isolation (bool) 1015 * enforce process isolation between graphics and compute via using the same reserved vmid. 1016 */ 1017 module_param(enforce_isolation, bool, 0444); 1018 MODULE_PARM_DESC(enforce_isolation, "enforce process isolation between graphics and compute . enforce_isolation = on"); 1019 1020 /** 1021 * DOC: seamless (int) 1022 * Seamless boot will keep the image on the screen during the boot process. 1023 */ 1024 MODULE_PARM_DESC(seamless, "Seamless boot (-1 = auto (default), 0 = disable, 1 = enable)"); 1025 module_param_named(seamless, amdgpu_seamless, int, 0444); 1026 1027 /** 1028 * DOC: debug_mask (uint) 1029 * Debug options for amdgpu, work as a binary mask with the following options: 1030 * 1031 * - 0x1: Debug VM handling 1032 * - 0x2: Enable simulating large-bar capability on non-large bar system. This 1033 * limits the VRAM size reported to ROCm applications to the visible 1034 * size, usually 256MB. 1035 * - 0x4: Disable GPU soft recovery, always do a full reset 1036 */ 1037 MODULE_PARM_DESC(debug_mask, "debug options for amdgpu, disabled by default"); 1038 module_param_named(debug_mask, amdgpu_debug_mask, uint, 0444); 1039 1040 /** 1041 * DOC: agp (int) 1042 * Enable the AGP aperture. This provides an aperture in the GPU's internal 1043 * address space for direct access to system memory. Note that these accesses 1044 * are non-snooped, so they are only used for access to uncached memory. 1045 */ 1046 MODULE_PARM_DESC(agp, "AGP (-1 = auto (default), 0 = disable, 1 = enable)"); 1047 module_param_named(agp, amdgpu_agp, int, 0444); 1048 1049 /** 1050 * DOC: wbrf (int) 1051 * Enable Wifi RFI interference mitigation feature. 1052 * Due to electrical and mechanical constraints there may be likely interference of 1053 * relatively high-powered harmonics of the (G-)DDR memory clocks with local radio 1054 * module frequency bands used by Wifi 6/6e/7. To mitigate the possible RFI interference, 1055 * with this feature enabled, PMFW will use either “shadowed P-State” or “P-State” based 1056 * on active list of frequencies in-use (to be avoided) as part of initial setting or 1057 * P-state transition. However, there may be potential performance impact with this 1058 * feature enabled. 1059 * (0 = disabled, 1 = enabled, -1 = auto (default setting, will be enabled if supported)) 1060 */ 1061 MODULE_PARM_DESC(wbrf, 1062 "Enable Wifi RFI interference mitigation (0 = disabled, 1 = enabled, -1 = auto(default)"); 1063 module_param_named(wbrf, amdgpu_wbrf, int, 0444); 1064 1065 /* These devices are not supported by amdgpu. 1066 * They are supported by the mach64, r128, radeon drivers 1067 */ 1068 static const u16 amdgpu_unsupported_pciidlist[] = { 1069 /* mach64 */ 1070 0x4354, 1071 0x4358, 1072 0x4554, 1073 0x4742, 1074 0x4744, 1075 0x4749, 1076 0x474C, 1077 0x474D, 1078 0x474E, 1079 0x474F, 1080 0x4750, 1081 0x4751, 1082 0x4752, 1083 0x4753, 1084 0x4754, 1085 0x4755, 1086 0x4756, 1087 0x4757, 1088 0x4758, 1089 0x4759, 1090 0x475A, 1091 0x4C42, 1092 0x4C44, 1093 0x4C47, 1094 0x4C49, 1095 0x4C4D, 1096 0x4C4E, 1097 0x4C50, 1098 0x4C51, 1099 0x4C52, 1100 0x4C53, 1101 0x5654, 1102 0x5655, 1103 0x5656, 1104 /* r128 */ 1105 0x4c45, 1106 0x4c46, 1107 0x4d46, 1108 0x4d4c, 1109 0x5041, 1110 0x5042, 1111 0x5043, 1112 0x5044, 1113 0x5045, 1114 0x5046, 1115 0x5047, 1116 0x5048, 1117 0x5049, 1118 0x504A, 1119 0x504B, 1120 0x504C, 1121 0x504D, 1122 0x504E, 1123 0x504F, 1124 0x5050, 1125 0x5051, 1126 0x5052, 1127 0x5053, 1128 0x5054, 1129 0x5055, 1130 0x5056, 1131 0x5057, 1132 0x5058, 1133 0x5245, 1134 0x5246, 1135 0x5247, 1136 0x524b, 1137 0x524c, 1138 0x534d, 1139 0x5446, 1140 0x544C, 1141 0x5452, 1142 /* radeon */ 1143 0x3150, 1144 0x3151, 1145 0x3152, 1146 0x3154, 1147 0x3155, 1148 0x3E50, 1149 0x3E54, 1150 0x4136, 1151 0x4137, 1152 0x4144, 1153 0x4145, 1154 0x4146, 1155 0x4147, 1156 0x4148, 1157 0x4149, 1158 0x414A, 1159 0x414B, 1160 0x4150, 1161 0x4151, 1162 0x4152, 1163 0x4153, 1164 0x4154, 1165 0x4155, 1166 0x4156, 1167 0x4237, 1168 0x4242, 1169 0x4336, 1170 0x4337, 1171 0x4437, 1172 0x4966, 1173 0x4967, 1174 0x4A48, 1175 0x4A49, 1176 0x4A4A, 1177 0x4A4B, 1178 0x4A4C, 1179 0x4A4D, 1180 0x4A4E, 1181 0x4A4F, 1182 0x4A50, 1183 0x4A54, 1184 0x4B48, 1185 0x4B49, 1186 0x4B4A, 1187 0x4B4B, 1188 0x4B4C, 1189 0x4C57, 1190 0x4C58, 1191 0x4C59, 1192 0x4C5A, 1193 0x4C64, 1194 0x4C66, 1195 0x4C67, 1196 0x4E44, 1197 0x4E45, 1198 0x4E46, 1199 0x4E47, 1200 0x4E48, 1201 0x4E49, 1202 0x4E4A, 1203 0x4E4B, 1204 0x4E50, 1205 0x4E51, 1206 0x4E52, 1207 0x4E53, 1208 0x4E54, 1209 0x4E56, 1210 0x5144, 1211 0x5145, 1212 0x5146, 1213 0x5147, 1214 0x5148, 1215 0x514C, 1216 0x514D, 1217 0x5157, 1218 0x5158, 1219 0x5159, 1220 0x515A, 1221 0x515E, 1222 0x5460, 1223 0x5462, 1224 0x5464, 1225 0x5548, 1226 0x5549, 1227 0x554A, 1228 0x554B, 1229 0x554C, 1230 0x554D, 1231 0x554E, 1232 0x554F, 1233 0x5550, 1234 0x5551, 1235 0x5552, 1236 0x5554, 1237 0x564A, 1238 0x564B, 1239 0x564F, 1240 0x5652, 1241 0x5653, 1242 0x5657, 1243 0x5834, 1244 0x5835, 1245 0x5954, 1246 0x5955, 1247 0x5974, 1248 0x5975, 1249 0x5960, 1250 0x5961, 1251 0x5962, 1252 0x5964, 1253 0x5965, 1254 0x5969, 1255 0x5a41, 1256 0x5a42, 1257 0x5a61, 1258 0x5a62, 1259 0x5b60, 1260 0x5b62, 1261 0x5b63, 1262 0x5b64, 1263 0x5b65, 1264 0x5c61, 1265 0x5c63, 1266 0x5d48, 1267 0x5d49, 1268 0x5d4a, 1269 0x5d4c, 1270 0x5d4d, 1271 0x5d4e, 1272 0x5d4f, 1273 0x5d50, 1274 0x5d52, 1275 0x5d57, 1276 0x5e48, 1277 0x5e4a, 1278 0x5e4b, 1279 0x5e4c, 1280 0x5e4d, 1281 0x5e4f, 1282 0x6700, 1283 0x6701, 1284 0x6702, 1285 0x6703, 1286 0x6704, 1287 0x6705, 1288 0x6706, 1289 0x6707, 1290 0x6708, 1291 0x6709, 1292 0x6718, 1293 0x6719, 1294 0x671c, 1295 0x671d, 1296 0x671f, 1297 0x6720, 1298 0x6721, 1299 0x6722, 1300 0x6723, 1301 0x6724, 1302 0x6725, 1303 0x6726, 1304 0x6727, 1305 0x6728, 1306 0x6729, 1307 0x6738, 1308 0x6739, 1309 0x673e, 1310 0x6740, 1311 0x6741, 1312 0x6742, 1313 0x6743, 1314 0x6744, 1315 0x6745, 1316 0x6746, 1317 0x6747, 1318 0x6748, 1319 0x6749, 1320 0x674A, 1321 0x6750, 1322 0x6751, 1323 0x6758, 1324 0x6759, 1325 0x675B, 1326 0x675D, 1327 0x675F, 1328 0x6760, 1329 0x6761, 1330 0x6762, 1331 0x6763, 1332 0x6764, 1333 0x6765, 1334 0x6766, 1335 0x6767, 1336 0x6768, 1337 0x6770, 1338 0x6771, 1339 0x6772, 1340 0x6778, 1341 0x6779, 1342 0x677B, 1343 0x6840, 1344 0x6841, 1345 0x6842, 1346 0x6843, 1347 0x6849, 1348 0x684C, 1349 0x6850, 1350 0x6858, 1351 0x6859, 1352 0x6880, 1353 0x6888, 1354 0x6889, 1355 0x688A, 1356 0x688C, 1357 0x688D, 1358 0x6898, 1359 0x6899, 1360 0x689b, 1361 0x689c, 1362 0x689d, 1363 0x689e, 1364 0x68a0, 1365 0x68a1, 1366 0x68a8, 1367 0x68a9, 1368 0x68b0, 1369 0x68b8, 1370 0x68b9, 1371 0x68ba, 1372 0x68be, 1373 0x68bf, 1374 0x68c0, 1375 0x68c1, 1376 0x68c7, 1377 0x68c8, 1378 0x68c9, 1379 0x68d8, 1380 0x68d9, 1381 0x68da, 1382 0x68de, 1383 0x68e0, 1384 0x68e1, 1385 0x68e4, 1386 0x68e5, 1387 0x68e8, 1388 0x68e9, 1389 0x68f1, 1390 0x68f2, 1391 0x68f8, 1392 0x68f9, 1393 0x68fa, 1394 0x68fe, 1395 0x7100, 1396 0x7101, 1397 0x7102, 1398 0x7103, 1399 0x7104, 1400 0x7105, 1401 0x7106, 1402 0x7108, 1403 0x7109, 1404 0x710A, 1405 0x710B, 1406 0x710C, 1407 0x710E, 1408 0x710F, 1409 0x7140, 1410 0x7141, 1411 0x7142, 1412 0x7143, 1413 0x7144, 1414 0x7145, 1415 0x7146, 1416 0x7147, 1417 0x7149, 1418 0x714A, 1419 0x714B, 1420 0x714C, 1421 0x714D, 1422 0x714E, 1423 0x714F, 1424 0x7151, 1425 0x7152, 1426 0x7153, 1427 0x715E, 1428 0x715F, 1429 0x7180, 1430 0x7181, 1431 0x7183, 1432 0x7186, 1433 0x7187, 1434 0x7188, 1435 0x718A, 1436 0x718B, 1437 0x718C, 1438 0x718D, 1439 0x718F, 1440 0x7193, 1441 0x7196, 1442 0x719B, 1443 0x719F, 1444 0x71C0, 1445 0x71C1, 1446 0x71C2, 1447 0x71C3, 1448 0x71C4, 1449 0x71C5, 1450 0x71C6, 1451 0x71C7, 1452 0x71CD, 1453 0x71CE, 1454 0x71D2, 1455 0x71D4, 1456 0x71D5, 1457 0x71D6, 1458 0x71DA, 1459 0x71DE, 1460 0x7200, 1461 0x7210, 1462 0x7211, 1463 0x7240, 1464 0x7243, 1465 0x7244, 1466 0x7245, 1467 0x7246, 1468 0x7247, 1469 0x7248, 1470 0x7249, 1471 0x724A, 1472 0x724B, 1473 0x724C, 1474 0x724D, 1475 0x724E, 1476 0x724F, 1477 0x7280, 1478 0x7281, 1479 0x7283, 1480 0x7284, 1481 0x7287, 1482 0x7288, 1483 0x7289, 1484 0x728B, 1485 0x728C, 1486 0x7290, 1487 0x7291, 1488 0x7293, 1489 0x7297, 1490 0x7834, 1491 0x7835, 1492 0x791e, 1493 0x791f, 1494 0x793f, 1495 0x7941, 1496 0x7942, 1497 0x796c, 1498 0x796d, 1499 0x796e, 1500 0x796f, 1501 0x9400, 1502 0x9401, 1503 0x9402, 1504 0x9403, 1505 0x9405, 1506 0x940A, 1507 0x940B, 1508 0x940F, 1509 0x94A0, 1510 0x94A1, 1511 0x94A3, 1512 0x94B1, 1513 0x94B3, 1514 0x94B4, 1515 0x94B5, 1516 0x94B9, 1517 0x9440, 1518 0x9441, 1519 0x9442, 1520 0x9443, 1521 0x9444, 1522 0x9446, 1523 0x944A, 1524 0x944B, 1525 0x944C, 1526 0x944E, 1527 0x9450, 1528 0x9452, 1529 0x9456, 1530 0x945A, 1531 0x945B, 1532 0x945E, 1533 0x9460, 1534 0x9462, 1535 0x946A, 1536 0x946B, 1537 0x947A, 1538 0x947B, 1539 0x9480, 1540 0x9487, 1541 0x9488, 1542 0x9489, 1543 0x948A, 1544 0x948F, 1545 0x9490, 1546 0x9491, 1547 0x9495, 1548 0x9498, 1549 0x949C, 1550 0x949E, 1551 0x949F, 1552 0x94C0, 1553 0x94C1, 1554 0x94C3, 1555 0x94C4, 1556 0x94C5, 1557 0x94C6, 1558 0x94C7, 1559 0x94C8, 1560 0x94C9, 1561 0x94CB, 1562 0x94CC, 1563 0x94CD, 1564 0x9500, 1565 0x9501, 1566 0x9504, 1567 0x9505, 1568 0x9506, 1569 0x9507, 1570 0x9508, 1571 0x9509, 1572 0x950F, 1573 0x9511, 1574 0x9515, 1575 0x9517, 1576 0x9519, 1577 0x9540, 1578 0x9541, 1579 0x9542, 1580 0x954E, 1581 0x954F, 1582 0x9552, 1583 0x9553, 1584 0x9555, 1585 0x9557, 1586 0x955f, 1587 0x9580, 1588 0x9581, 1589 0x9583, 1590 0x9586, 1591 0x9587, 1592 0x9588, 1593 0x9589, 1594 0x958A, 1595 0x958B, 1596 0x958C, 1597 0x958D, 1598 0x958E, 1599 0x958F, 1600 0x9590, 1601 0x9591, 1602 0x9593, 1603 0x9595, 1604 0x9596, 1605 0x9597, 1606 0x9598, 1607 0x9599, 1608 0x959B, 1609 0x95C0, 1610 0x95C2, 1611 0x95C4, 1612 0x95C5, 1613 0x95C6, 1614 0x95C7, 1615 0x95C9, 1616 0x95CC, 1617 0x95CD, 1618 0x95CE, 1619 0x95CF, 1620 0x9610, 1621 0x9611, 1622 0x9612, 1623 0x9613, 1624 0x9614, 1625 0x9615, 1626 0x9616, 1627 0x9640, 1628 0x9641, 1629 0x9642, 1630 0x9643, 1631 0x9644, 1632 0x9645, 1633 0x9647, 1634 0x9648, 1635 0x9649, 1636 0x964a, 1637 0x964b, 1638 0x964c, 1639 0x964e, 1640 0x964f, 1641 0x9710, 1642 0x9711, 1643 0x9712, 1644 0x9713, 1645 0x9714, 1646 0x9715, 1647 0x9802, 1648 0x9803, 1649 0x9804, 1650 0x9805, 1651 0x9806, 1652 0x9807, 1653 0x9808, 1654 0x9809, 1655 0x980A, 1656 0x9900, 1657 0x9901, 1658 0x9903, 1659 0x9904, 1660 0x9905, 1661 0x9906, 1662 0x9907, 1663 0x9908, 1664 0x9909, 1665 0x990A, 1666 0x990B, 1667 0x990C, 1668 0x990D, 1669 0x990E, 1670 0x990F, 1671 0x9910, 1672 0x9913, 1673 0x9917, 1674 0x9918, 1675 0x9919, 1676 0x9990, 1677 0x9991, 1678 0x9992, 1679 0x9993, 1680 0x9994, 1681 0x9995, 1682 0x9996, 1683 0x9997, 1684 0x9998, 1685 0x9999, 1686 0x999A, 1687 0x999B, 1688 0x999C, 1689 0x999D, 1690 0x99A0, 1691 0x99A2, 1692 0x99A4, 1693 /* radeon secondary ids */ 1694 0x3171, 1695 0x3e70, 1696 0x4164, 1697 0x4165, 1698 0x4166, 1699 0x4168, 1700 0x4170, 1701 0x4171, 1702 0x4172, 1703 0x4173, 1704 0x496e, 1705 0x4a69, 1706 0x4a6a, 1707 0x4a6b, 1708 0x4a70, 1709 0x4a74, 1710 0x4b69, 1711 0x4b6b, 1712 0x4b6c, 1713 0x4c6e, 1714 0x4e64, 1715 0x4e65, 1716 0x4e66, 1717 0x4e67, 1718 0x4e68, 1719 0x4e69, 1720 0x4e6a, 1721 0x4e71, 1722 0x4f73, 1723 0x5569, 1724 0x556b, 1725 0x556d, 1726 0x556f, 1727 0x5571, 1728 0x5854, 1729 0x5874, 1730 0x5940, 1731 0x5941, 1732 0x5b70, 1733 0x5b72, 1734 0x5b73, 1735 0x5b74, 1736 0x5b75, 1737 0x5d44, 1738 0x5d45, 1739 0x5d6d, 1740 0x5d6f, 1741 0x5d72, 1742 0x5d77, 1743 0x5e6b, 1744 0x5e6d, 1745 0x7120, 1746 0x7124, 1747 0x7129, 1748 0x712e, 1749 0x712f, 1750 0x7162, 1751 0x7163, 1752 0x7166, 1753 0x7167, 1754 0x7172, 1755 0x7173, 1756 0x71a0, 1757 0x71a1, 1758 0x71a3, 1759 0x71a7, 1760 0x71bb, 1761 0x71e0, 1762 0x71e1, 1763 0x71e2, 1764 0x71e6, 1765 0x71e7, 1766 0x71f2, 1767 0x7269, 1768 0x726b, 1769 0x726e, 1770 0x72a0, 1771 0x72a8, 1772 0x72b1, 1773 0x72b3, 1774 0x793f, 1775 }; 1776 1777 static const struct pci_device_id pciidlist[] = { 1778 #ifdef CONFIG_DRM_AMDGPU_SI 1779 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1780 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1781 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1782 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1783 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1784 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1785 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1786 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1787 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1788 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1789 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1790 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1791 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1792 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1793 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1794 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1795 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1796 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1797 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1798 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1799 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1800 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1801 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1802 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1803 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1804 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1805 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1806 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1807 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1808 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1809 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1810 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1811 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1812 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1813 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1814 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1815 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1816 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1817 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1818 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1819 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1820 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1821 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1822 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1823 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1824 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1825 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1826 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1827 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1828 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1829 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1830 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1831 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1832 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1833 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1834 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1835 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1836 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1837 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1838 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1839 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1840 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1841 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1842 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1843 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1844 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1845 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1846 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1847 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1848 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1849 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1850 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1851 #endif 1852 #ifdef CONFIG_DRM_AMDGPU_CIK 1853 /* Kaveri */ 1854 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1855 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1856 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1857 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1858 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1859 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1860 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1861 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1862 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1863 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1864 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1865 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1866 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1867 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1868 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1869 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1870 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1871 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1872 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1873 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1874 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1875 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1876 /* Bonaire */ 1877 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1878 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1879 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1880 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1881 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1882 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1883 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1884 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1885 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1886 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1887 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1888 /* Hawaii */ 1889 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1890 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1891 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1892 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1893 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1894 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1895 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1896 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1897 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1898 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1899 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1900 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1901 /* Kabini */ 1902 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1903 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1904 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1905 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1906 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1907 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1908 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1909 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1910 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1911 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1912 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1913 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1914 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1915 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1916 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1917 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1918 /* mullins */ 1919 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1920 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1921 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1922 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1923 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1924 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1925 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1926 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1927 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1928 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1929 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1930 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1931 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1932 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1933 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1934 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1935 #endif 1936 /* topaz */ 1937 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1938 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1939 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1940 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1941 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1942 /* tonga */ 1943 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1944 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1945 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1946 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1947 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1948 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1949 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1950 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1951 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1952 /* fiji */ 1953 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1954 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1955 /* carrizo */ 1956 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1957 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1958 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1959 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1960 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1961 /* stoney */ 1962 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1963 /* Polaris11 */ 1964 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1965 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1966 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1967 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1968 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1969 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1970 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1971 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1972 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1973 /* Polaris10 */ 1974 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1975 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1976 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1977 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1978 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1979 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1980 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1981 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1982 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1983 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1984 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1985 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1986 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1987 /* Polaris12 */ 1988 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1989 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1990 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1991 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1992 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1993 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1994 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1995 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1996 /* VEGAM */ 1997 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1998 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1999 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 2000 /* Vega 10 */ 2001 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2002 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2003 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2004 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2005 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2006 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2007 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2008 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2009 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2010 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2011 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2012 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2013 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2014 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2015 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2016 /* Vega 12 */ 2017 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2018 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2019 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2020 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2021 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2022 /* Vega 20 */ 2023 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2024 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2025 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2026 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2027 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2028 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2029 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2030 /* Raven */ 2031 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 2032 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 2033 /* Arcturus */ 2034 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2035 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2036 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2037 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2038 /* Navi10 */ 2039 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2040 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2041 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2042 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2043 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2044 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2045 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2046 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2047 /* Navi14 */ 2048 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2049 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2050 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2051 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2052 2053 /* Renoir */ 2054 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2055 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2056 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2057 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2058 2059 /* Navi12 */ 2060 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 2061 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 2062 2063 /* Sienna_Cichlid */ 2064 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2065 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2066 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2067 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2068 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2069 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2070 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2071 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2072 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2073 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2074 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2075 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2076 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2077 2078 /* Yellow Carp */ 2079 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 2080 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 2081 2082 /* Navy_Flounder */ 2083 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2084 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2085 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2086 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2087 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2088 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2089 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2090 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2091 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2092 2093 /* DIMGREY_CAVEFISH */ 2094 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2095 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2096 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2097 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2098 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2099 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2100 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2101 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2102 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2103 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2104 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2105 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2106 2107 /* Aldebaran */ 2108 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2109 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2110 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2111 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2112 2113 /* CYAN_SKILLFISH */ 2114 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2115 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2116 2117 /* BEIGE_GOBY */ 2118 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2119 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2120 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2121 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2122 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2123 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2124 2125 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2126 .class = PCI_CLASS_DISPLAY_VGA << 8, 2127 .class_mask = 0xffffff, 2128 .driver_data = CHIP_IP_DISCOVERY }, 2129 2130 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2131 .class = PCI_CLASS_DISPLAY_OTHER << 8, 2132 .class_mask = 0xffffff, 2133 .driver_data = CHIP_IP_DISCOVERY }, 2134 2135 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2136 .class = PCI_CLASS_ACCELERATOR_PROCESSING << 8, 2137 .class_mask = 0xffffff, 2138 .driver_data = CHIP_IP_DISCOVERY }, 2139 2140 {0, 0, 0} 2141 }; 2142 2143 MODULE_DEVICE_TABLE(pci, pciidlist); 2144 2145 static const struct amdgpu_asic_type_quirk asic_type_quirks[] = { 2146 /* differentiate between P10 and P11 asics with the same DID */ 2147 {0x67FF, 0xE3, CHIP_POLARIS10}, 2148 {0x67FF, 0xE7, CHIP_POLARIS10}, 2149 {0x67FF, 0xF3, CHIP_POLARIS10}, 2150 {0x67FF, 0xF7, CHIP_POLARIS10}, 2151 }; 2152 2153 static const struct drm_driver amdgpu_kms_driver; 2154 2155 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 2156 { 2157 struct pci_dev *p = NULL; 2158 int i; 2159 2160 /* 0 - GPU 2161 * 1 - audio 2162 * 2 - USB 2163 * 3 - UCSI 2164 */ 2165 for (i = 1; i < 4; i++) { 2166 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 2167 adev->pdev->bus->number, i); 2168 if (p) { 2169 pm_runtime_get_sync(&p->dev); 2170 pm_runtime_mark_last_busy(&p->dev); 2171 pm_runtime_put_autosuspend(&p->dev); 2172 pci_dev_put(p); 2173 } 2174 } 2175 } 2176 2177 static void amdgpu_init_debug_options(struct amdgpu_device *adev) 2178 { 2179 if (amdgpu_debug_mask & AMDGPU_DEBUG_VM) { 2180 pr_info("debug: VM handling debug enabled\n"); 2181 adev->debug_vm = true; 2182 } 2183 2184 if (amdgpu_debug_mask & AMDGPU_DEBUG_LARGEBAR) { 2185 pr_info("debug: enabled simulating large-bar capability on non-large bar system\n"); 2186 adev->debug_largebar = true; 2187 } 2188 2189 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY) { 2190 pr_info("debug: soft reset for GPU recovery disabled\n"); 2191 adev->debug_disable_soft_recovery = true; 2192 } 2193 2194 if (amdgpu_debug_mask & AMDGPU_DEBUG_USE_VRAM_FW_BUF) { 2195 pr_info("debug: place fw in vram for frontdoor loading\n"); 2196 adev->debug_use_vram_fw_buf = true; 2197 } 2198 2199 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_RAS_ACA) { 2200 pr_info("debug: enable RAS ACA\n"); 2201 adev->debug_enable_ras_aca = true; 2202 } 2203 2204 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_EXP_RESETS) { 2205 pr_info("debug: enable experimental reset features\n"); 2206 adev->debug_exp_resets = true; 2207 } 2208 } 2209 2210 static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long flags) 2211 { 2212 int i; 2213 2214 for (i = 0; i < ARRAY_SIZE(asic_type_quirks); i++) { 2215 if (pdev->device == asic_type_quirks[i].device && 2216 pdev->revision == asic_type_quirks[i].revision) { 2217 flags &= ~AMD_ASIC_MASK; 2218 flags |= asic_type_quirks[i].type; 2219 break; 2220 } 2221 } 2222 2223 return flags; 2224 } 2225 2226 static int amdgpu_pci_probe(struct pci_dev *pdev, 2227 const struct pci_device_id *ent) 2228 { 2229 struct drm_device *ddev; 2230 struct amdgpu_device *adev; 2231 unsigned long flags = ent->driver_data; 2232 int ret, retry = 0, i; 2233 bool supports_atomic = false; 2234 2235 /* skip devices which are owned by radeon */ 2236 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2237 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2238 return -ENODEV; 2239 } 2240 2241 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) 2242 amdgpu_aspm = 0; 2243 2244 if (amdgpu_virtual_display || 2245 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 2246 supports_atomic = true; 2247 2248 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2249 DRM_INFO("This hardware requires experimental hardware support.\n" 2250 "See modparam exp_hw_support\n"); 2251 return -ENODEV; 2252 } 2253 2254 flags = amdgpu_fix_asic_type(pdev, flags); 2255 2256 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2257 * however, SME requires an indirect IOMMU mapping because the encryption 2258 * bit is beyond the DMA mask of the chip. 2259 */ 2260 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2261 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2262 dev_info(&pdev->dev, 2263 "SME is not compatible with RAVEN\n"); 2264 return -ENOTSUPP; 2265 } 2266 2267 #ifdef CONFIG_DRM_AMDGPU_SI 2268 if (!amdgpu_si_support) { 2269 switch (flags & AMD_ASIC_MASK) { 2270 case CHIP_TAHITI: 2271 case CHIP_PITCAIRN: 2272 case CHIP_VERDE: 2273 case CHIP_OLAND: 2274 case CHIP_HAINAN: 2275 dev_info(&pdev->dev, 2276 "SI support provided by radeon.\n"); 2277 dev_info(&pdev->dev, 2278 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 2279 ); 2280 return -ENODEV; 2281 } 2282 } 2283 #endif 2284 #ifdef CONFIG_DRM_AMDGPU_CIK 2285 if (!amdgpu_cik_support) { 2286 switch (flags & AMD_ASIC_MASK) { 2287 case CHIP_KAVERI: 2288 case CHIP_BONAIRE: 2289 case CHIP_HAWAII: 2290 case CHIP_KABINI: 2291 case CHIP_MULLINS: 2292 dev_info(&pdev->dev, 2293 "CIK support provided by radeon.\n"); 2294 dev_info(&pdev->dev, 2295 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 2296 ); 2297 return -ENODEV; 2298 } 2299 } 2300 #endif 2301 2302 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2303 if (IS_ERR(adev)) 2304 return PTR_ERR(adev); 2305 2306 adev->dev = &pdev->dev; 2307 adev->pdev = pdev; 2308 ddev = adev_to_drm(adev); 2309 2310 if (!supports_atomic) 2311 ddev->driver_features &= ~DRIVER_ATOMIC; 2312 2313 ret = pci_enable_device(pdev); 2314 if (ret) 2315 return ret; 2316 2317 pci_set_drvdata(pdev, ddev); 2318 2319 amdgpu_init_debug_options(adev); 2320 2321 ret = amdgpu_driver_load_kms(adev, flags); 2322 if (ret) 2323 goto err_pci; 2324 2325 retry_init: 2326 ret = drm_dev_register(ddev, flags); 2327 if (ret == -EAGAIN && ++retry <= 3) { 2328 DRM_INFO("retry init %d\n", retry); 2329 /* Don't request EX mode too frequently which is attacking */ 2330 msleep(5000); 2331 goto retry_init; 2332 } else if (ret) { 2333 goto err_pci; 2334 } 2335 2336 ret = amdgpu_xcp_dev_register(adev, ent); 2337 if (ret) 2338 goto err_pci; 2339 2340 ret = amdgpu_amdkfd_drm_client_create(adev); 2341 if (ret) 2342 goto err_pci; 2343 2344 /* 2345 * 1. don't init fbdev on hw without DCE 2346 * 2. don't init fbdev if there are no connectors 2347 */ 2348 if (adev->mode_info.mode_config_initialized && 2349 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2350 /* select 8 bpp console on low vram cards */ 2351 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2352 drm_fbdev_ttm_setup(adev_to_drm(adev), 8); 2353 else 2354 drm_fbdev_ttm_setup(adev_to_drm(adev), 32); 2355 } 2356 2357 ret = amdgpu_debugfs_init(adev); 2358 if (ret) 2359 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2360 2361 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2362 /* only need to skip on ATPX */ 2363 if (amdgpu_device_supports_px(ddev)) 2364 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2365 /* we want direct complete for BOCO */ 2366 if (amdgpu_device_supports_boco(ddev)) 2367 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2368 DPM_FLAG_SMART_SUSPEND | 2369 DPM_FLAG_MAY_SKIP_RESUME); 2370 pm_runtime_use_autosuspend(ddev->dev); 2371 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2372 2373 pm_runtime_allow(ddev->dev); 2374 2375 pm_runtime_mark_last_busy(ddev->dev); 2376 pm_runtime_put_autosuspend(ddev->dev); 2377 2378 pci_wake_from_d3(pdev, TRUE); 2379 2380 /* 2381 * For runpm implemented via BACO, PMFW will handle the 2382 * timing for BACO in and out: 2383 * - put ASIC into BACO state only when both video and 2384 * audio functions are in D3 state. 2385 * - pull ASIC out of BACO state when either video or 2386 * audio function is in D0 state. 2387 * Also, at startup, PMFW assumes both functions are in 2388 * D0 state. 2389 * 2390 * So if snd driver was loaded prior to amdgpu driver 2391 * and audio function was put into D3 state, there will 2392 * be no PMFW-aware D-state transition(D0->D3) on runpm 2393 * suspend. Thus the BACO will be not correctly kicked in. 2394 * 2395 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2396 * into D0 state. Then there will be a PMFW-aware D-state 2397 * transition(D0->D3) on runpm suspend. 2398 */ 2399 if (amdgpu_device_supports_baco(ddev) && 2400 !(adev->flags & AMD_IS_APU) && 2401 (adev->asic_type >= CHIP_NAVI10)) 2402 amdgpu_get_secondary_funcs(adev); 2403 } 2404 2405 return 0; 2406 2407 err_pci: 2408 pci_disable_device(pdev); 2409 return ret; 2410 } 2411 2412 static void 2413 amdgpu_pci_remove(struct pci_dev *pdev) 2414 { 2415 struct drm_device *dev = pci_get_drvdata(pdev); 2416 struct amdgpu_device *adev = drm_to_adev(dev); 2417 2418 amdgpu_xcp_dev_unplug(adev); 2419 drm_dev_unplug(dev); 2420 2421 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2422 pm_runtime_get_sync(dev->dev); 2423 pm_runtime_forbid(dev->dev); 2424 } 2425 2426 amdgpu_driver_unload_kms(dev); 2427 2428 /* 2429 * Flush any in flight DMA operations from device. 2430 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2431 * StatusTransactions Pending bit. 2432 */ 2433 pci_disable_device(pdev); 2434 pci_wait_for_pending_transaction(pdev); 2435 } 2436 2437 static void 2438 amdgpu_pci_shutdown(struct pci_dev *pdev) 2439 { 2440 struct drm_device *dev = pci_get_drvdata(pdev); 2441 struct amdgpu_device *adev = drm_to_adev(dev); 2442 2443 if (amdgpu_ras_intr_triggered()) 2444 return; 2445 2446 /* if we are running in a VM, make sure the device 2447 * torn down properly on reboot/shutdown. 2448 * unfortunately we can't detect certain 2449 * hypervisors so just do this all the time. 2450 */ 2451 if (!amdgpu_passthrough(adev)) 2452 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2453 amdgpu_device_ip_suspend(adev); 2454 adev->mp1_state = PP_MP1_STATE_NONE; 2455 } 2456 2457 /** 2458 * amdgpu_drv_delayed_reset_work_handler - work handler for reset 2459 * 2460 * @work: work_struct. 2461 */ 2462 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) 2463 { 2464 struct list_head device_list; 2465 struct amdgpu_device *adev; 2466 int i, r; 2467 struct amdgpu_reset_context reset_context; 2468 2469 memset(&reset_context, 0, sizeof(reset_context)); 2470 2471 mutex_lock(&mgpu_info.mutex); 2472 if (mgpu_info.pending_reset == true) { 2473 mutex_unlock(&mgpu_info.mutex); 2474 return; 2475 } 2476 mgpu_info.pending_reset = true; 2477 mutex_unlock(&mgpu_info.mutex); 2478 2479 /* Use a common context, just need to make sure full reset is done */ 2480 reset_context.method = AMD_RESET_METHOD_NONE; 2481 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2482 2483 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2484 adev = mgpu_info.gpu_ins[i].adev; 2485 reset_context.reset_req_dev = adev; 2486 r = amdgpu_device_pre_asic_reset(adev, &reset_context); 2487 if (r) { 2488 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", 2489 r, adev_to_drm(adev)->unique); 2490 } 2491 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) 2492 r = -EALREADY; 2493 } 2494 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2495 adev = mgpu_info.gpu_ins[i].adev; 2496 flush_work(&adev->xgmi_reset_work); 2497 adev->gmc.xgmi.pending_reset = false; 2498 } 2499 2500 /* reset function will rebuild the xgmi hive info , clear it now */ 2501 for (i = 0; i < mgpu_info.num_dgpu; i++) 2502 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); 2503 2504 INIT_LIST_HEAD(&device_list); 2505 2506 for (i = 0; i < mgpu_info.num_dgpu; i++) 2507 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); 2508 2509 /* unregister the GPU first, reset function will add them back */ 2510 list_for_each_entry(adev, &device_list, reset_list) 2511 amdgpu_unregister_gpu_instance(adev); 2512 2513 /* Use a common context, just need to make sure full reset is done */ 2514 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); 2515 set_bit(AMDGPU_SKIP_COREDUMP, &reset_context.flags); 2516 r = amdgpu_do_asic_reset(&device_list, &reset_context); 2517 2518 if (r) { 2519 DRM_ERROR("reinit gpus failure"); 2520 return; 2521 } 2522 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2523 adev = mgpu_info.gpu_ins[i].adev; 2524 if (!adev->kfd.init_complete) { 2525 kgd2kfd_init_zone_device(adev); 2526 amdgpu_amdkfd_device_init(adev); 2527 amdgpu_amdkfd_drm_client_create(adev); 2528 } 2529 amdgpu_ttm_set_buffer_funcs_status(adev, true); 2530 } 2531 } 2532 2533 static int amdgpu_pmops_prepare(struct device *dev) 2534 { 2535 struct drm_device *drm_dev = dev_get_drvdata(dev); 2536 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2537 2538 /* Return a positive number here so 2539 * DPM_FLAG_SMART_SUSPEND works properly 2540 */ 2541 if (amdgpu_device_supports_boco(drm_dev) && 2542 pm_runtime_suspended(dev)) 2543 return 1; 2544 2545 /* if we will not support s3 or s2i for the device 2546 * then skip suspend 2547 */ 2548 if (!amdgpu_acpi_is_s0ix_active(adev) && 2549 !amdgpu_acpi_is_s3_active(adev)) 2550 return 1; 2551 2552 return amdgpu_device_prepare(drm_dev); 2553 } 2554 2555 static void amdgpu_pmops_complete(struct device *dev) 2556 { 2557 /* nothing to do */ 2558 } 2559 2560 static int amdgpu_pmops_suspend(struct device *dev) 2561 { 2562 struct drm_device *drm_dev = dev_get_drvdata(dev); 2563 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2564 2565 adev->suspend_complete = false; 2566 if (amdgpu_acpi_is_s0ix_active(adev)) 2567 adev->in_s0ix = true; 2568 else if (amdgpu_acpi_is_s3_active(adev)) 2569 adev->in_s3 = true; 2570 if (!adev->in_s0ix && !adev->in_s3) 2571 return 0; 2572 return amdgpu_device_suspend(drm_dev, true); 2573 } 2574 2575 static int amdgpu_pmops_suspend_noirq(struct device *dev) 2576 { 2577 struct drm_device *drm_dev = dev_get_drvdata(dev); 2578 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2579 2580 adev->suspend_complete = true; 2581 if (amdgpu_acpi_should_gpu_reset(adev)) 2582 return amdgpu_asic_reset(adev); 2583 2584 return 0; 2585 } 2586 2587 static int amdgpu_pmops_resume(struct device *dev) 2588 { 2589 struct drm_device *drm_dev = dev_get_drvdata(dev); 2590 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2591 int r; 2592 2593 if (!adev->in_s0ix && !adev->in_s3) 2594 return 0; 2595 2596 /* Avoids registers access if device is physically gone */ 2597 if (!pci_device_is_present(adev->pdev)) 2598 adev->no_hw_access = true; 2599 2600 r = amdgpu_device_resume(drm_dev, true); 2601 if (amdgpu_acpi_is_s0ix_active(adev)) 2602 adev->in_s0ix = false; 2603 else 2604 adev->in_s3 = false; 2605 return r; 2606 } 2607 2608 static int amdgpu_pmops_freeze(struct device *dev) 2609 { 2610 struct drm_device *drm_dev = dev_get_drvdata(dev); 2611 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2612 int r; 2613 2614 adev->in_s4 = true; 2615 r = amdgpu_device_suspend(drm_dev, true); 2616 adev->in_s4 = false; 2617 if (r) 2618 return r; 2619 2620 if (amdgpu_acpi_should_gpu_reset(adev)) 2621 return amdgpu_asic_reset(adev); 2622 return 0; 2623 } 2624 2625 static int amdgpu_pmops_thaw(struct device *dev) 2626 { 2627 struct drm_device *drm_dev = dev_get_drvdata(dev); 2628 2629 return amdgpu_device_resume(drm_dev, true); 2630 } 2631 2632 static int amdgpu_pmops_poweroff(struct device *dev) 2633 { 2634 struct drm_device *drm_dev = dev_get_drvdata(dev); 2635 2636 return amdgpu_device_suspend(drm_dev, true); 2637 } 2638 2639 static int amdgpu_pmops_restore(struct device *dev) 2640 { 2641 struct drm_device *drm_dev = dev_get_drvdata(dev); 2642 2643 return amdgpu_device_resume(drm_dev, true); 2644 } 2645 2646 static int amdgpu_runtime_idle_check_display(struct device *dev) 2647 { 2648 struct pci_dev *pdev = to_pci_dev(dev); 2649 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2650 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2651 2652 if (adev->mode_info.num_crtc) { 2653 struct drm_connector *list_connector; 2654 struct drm_connector_list_iter iter; 2655 int ret = 0; 2656 2657 if (amdgpu_runtime_pm != -2) { 2658 /* XXX: Return busy if any displays are connected to avoid 2659 * possible display wakeups after runtime resume due to 2660 * hotplug events in case any displays were connected while 2661 * the GPU was in suspend. Remove this once that is fixed. 2662 */ 2663 mutex_lock(&drm_dev->mode_config.mutex); 2664 drm_connector_list_iter_begin(drm_dev, &iter); 2665 drm_for_each_connector_iter(list_connector, &iter) { 2666 if (list_connector->status == connector_status_connected) { 2667 ret = -EBUSY; 2668 break; 2669 } 2670 } 2671 drm_connector_list_iter_end(&iter); 2672 mutex_unlock(&drm_dev->mode_config.mutex); 2673 2674 if (ret) 2675 return ret; 2676 } 2677 2678 if (adev->dc_enabled) { 2679 struct drm_crtc *crtc; 2680 2681 drm_for_each_crtc(crtc, drm_dev) { 2682 drm_modeset_lock(&crtc->mutex, NULL); 2683 if (crtc->state->active) 2684 ret = -EBUSY; 2685 drm_modeset_unlock(&crtc->mutex); 2686 if (ret < 0) 2687 break; 2688 } 2689 } else { 2690 mutex_lock(&drm_dev->mode_config.mutex); 2691 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2692 2693 drm_connector_list_iter_begin(drm_dev, &iter); 2694 drm_for_each_connector_iter(list_connector, &iter) { 2695 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2696 ret = -EBUSY; 2697 break; 2698 } 2699 } 2700 2701 drm_connector_list_iter_end(&iter); 2702 2703 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2704 mutex_unlock(&drm_dev->mode_config.mutex); 2705 } 2706 if (ret) 2707 return ret; 2708 } 2709 2710 return 0; 2711 } 2712 2713 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2714 { 2715 struct pci_dev *pdev = to_pci_dev(dev); 2716 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2717 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2718 int ret, i; 2719 2720 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2721 pm_runtime_forbid(dev); 2722 return -EBUSY; 2723 } 2724 2725 ret = amdgpu_runtime_idle_check_display(dev); 2726 if (ret) 2727 return ret; 2728 2729 /* wait for all rings to drain before suspending */ 2730 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2731 struct amdgpu_ring *ring = adev->rings[i]; 2732 2733 if (ring && ring->sched.ready) { 2734 ret = amdgpu_fence_wait_empty(ring); 2735 if (ret) 2736 return -EBUSY; 2737 } 2738 } 2739 2740 adev->in_runpm = true; 2741 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2742 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2743 2744 /* 2745 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2746 * proper cleanups and put itself into a state ready for PNP. That 2747 * can address some random resuming failure observed on BOCO capable 2748 * platforms. 2749 * TODO: this may be also needed for PX capable platform. 2750 */ 2751 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2752 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2753 2754 ret = amdgpu_device_prepare(drm_dev); 2755 if (ret) 2756 return ret; 2757 ret = amdgpu_device_suspend(drm_dev, false); 2758 if (ret) { 2759 adev->in_runpm = false; 2760 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2761 adev->mp1_state = PP_MP1_STATE_NONE; 2762 return ret; 2763 } 2764 2765 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2766 adev->mp1_state = PP_MP1_STATE_NONE; 2767 2768 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) { 2769 /* Only need to handle PCI state in the driver for ATPX 2770 * PCI core handles it for _PR3. 2771 */ 2772 amdgpu_device_cache_pci_state(pdev); 2773 pci_disable_device(pdev); 2774 pci_ignore_hotplug(pdev); 2775 pci_set_power_state(pdev, PCI_D3cold); 2776 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2777 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) { 2778 /* nothing to do */ 2779 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2780 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) { 2781 amdgpu_device_baco_enter(drm_dev); 2782 } 2783 2784 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n"); 2785 2786 return 0; 2787 } 2788 2789 static int amdgpu_pmops_runtime_resume(struct device *dev) 2790 { 2791 struct pci_dev *pdev = to_pci_dev(dev); 2792 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2793 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2794 int ret; 2795 2796 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) 2797 return -EINVAL; 2798 2799 /* Avoids registers access if device is physically gone */ 2800 if (!pci_device_is_present(adev->pdev)) 2801 adev->no_hw_access = true; 2802 2803 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) { 2804 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2805 2806 /* Only need to handle PCI state in the driver for ATPX 2807 * PCI core handles it for _PR3. 2808 */ 2809 pci_set_power_state(pdev, PCI_D0); 2810 amdgpu_device_load_pci_state(pdev); 2811 ret = pci_enable_device(pdev); 2812 if (ret) 2813 return ret; 2814 pci_set_master(pdev); 2815 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) { 2816 /* Only need to handle PCI state in the driver for ATPX 2817 * PCI core handles it for _PR3. 2818 */ 2819 pci_set_master(pdev); 2820 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2821 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) { 2822 amdgpu_device_baco_exit(drm_dev); 2823 } 2824 ret = amdgpu_device_resume(drm_dev, false); 2825 if (ret) { 2826 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2827 pci_disable_device(pdev); 2828 return ret; 2829 } 2830 2831 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2832 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2833 adev->in_runpm = false; 2834 return 0; 2835 } 2836 2837 static int amdgpu_pmops_runtime_idle(struct device *dev) 2838 { 2839 struct drm_device *drm_dev = dev_get_drvdata(dev); 2840 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2841 int ret; 2842 2843 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2844 pm_runtime_forbid(dev); 2845 return -EBUSY; 2846 } 2847 2848 ret = amdgpu_runtime_idle_check_display(dev); 2849 2850 pm_runtime_mark_last_busy(dev); 2851 pm_runtime_autosuspend(dev); 2852 return ret; 2853 } 2854 2855 long amdgpu_drm_ioctl(struct file *filp, 2856 unsigned int cmd, unsigned long arg) 2857 { 2858 struct drm_file *file_priv = filp->private_data; 2859 struct drm_device *dev; 2860 long ret; 2861 2862 dev = file_priv->minor->dev; 2863 ret = pm_runtime_get_sync(dev->dev); 2864 if (ret < 0) 2865 goto out; 2866 2867 ret = drm_ioctl(filp, cmd, arg); 2868 2869 pm_runtime_mark_last_busy(dev->dev); 2870 out: 2871 pm_runtime_put_autosuspend(dev->dev); 2872 return ret; 2873 } 2874 2875 static const struct dev_pm_ops amdgpu_pm_ops = { 2876 .prepare = amdgpu_pmops_prepare, 2877 .complete = amdgpu_pmops_complete, 2878 .suspend = amdgpu_pmops_suspend, 2879 .suspend_noirq = amdgpu_pmops_suspend_noirq, 2880 .resume = amdgpu_pmops_resume, 2881 .freeze = amdgpu_pmops_freeze, 2882 .thaw = amdgpu_pmops_thaw, 2883 .poweroff = amdgpu_pmops_poweroff, 2884 .restore = amdgpu_pmops_restore, 2885 .runtime_suspend = amdgpu_pmops_runtime_suspend, 2886 .runtime_resume = amdgpu_pmops_runtime_resume, 2887 .runtime_idle = amdgpu_pmops_runtime_idle, 2888 }; 2889 2890 static int amdgpu_flush(struct file *f, fl_owner_t id) 2891 { 2892 struct drm_file *file_priv = f->private_data; 2893 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2894 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2895 2896 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 2897 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 2898 2899 return timeout >= 0 ? 0 : timeout; 2900 } 2901 2902 static const struct file_operations amdgpu_driver_kms_fops = { 2903 .owner = THIS_MODULE, 2904 .open = drm_open, 2905 .flush = amdgpu_flush, 2906 .release = drm_release, 2907 .unlocked_ioctl = amdgpu_drm_ioctl, 2908 .mmap = drm_gem_mmap, 2909 .poll = drm_poll, 2910 .read = drm_read, 2911 #ifdef CONFIG_COMPAT 2912 .compat_ioctl = amdgpu_kms_compat_ioctl, 2913 #endif 2914 #ifdef CONFIG_PROC_FS 2915 .show_fdinfo = drm_show_fdinfo, 2916 #endif 2917 }; 2918 2919 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 2920 { 2921 struct drm_file *file; 2922 2923 if (!filp) 2924 return -EINVAL; 2925 2926 if (filp->f_op != &amdgpu_driver_kms_fops) 2927 return -EINVAL; 2928 2929 file = filp->private_data; 2930 *fpriv = file->driver_priv; 2931 return 0; 2932 } 2933 2934 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 2935 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2936 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2937 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2938 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 2939 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2940 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2941 /* KMS */ 2942 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2943 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2944 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2945 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2946 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2947 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2948 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2949 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2950 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2951 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2952 }; 2953 2954 static const struct drm_driver amdgpu_kms_driver = { 2955 .driver_features = 2956 DRIVER_ATOMIC | 2957 DRIVER_GEM | 2958 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 2959 DRIVER_SYNCOBJ_TIMELINE, 2960 .open = amdgpu_driver_open_kms, 2961 .postclose = amdgpu_driver_postclose_kms, 2962 .ioctls = amdgpu_ioctls_kms, 2963 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2964 .dumb_create = amdgpu_mode_dumb_create, 2965 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2966 .fops = &amdgpu_driver_kms_fops, 2967 .release = &amdgpu_driver_release_kms, 2968 #ifdef CONFIG_PROC_FS 2969 .show_fdinfo = amdgpu_show_fdinfo, 2970 #endif 2971 2972 .gem_prime_import = amdgpu_gem_prime_import, 2973 2974 .name = DRIVER_NAME, 2975 .desc = DRIVER_DESC, 2976 .date = DRIVER_DATE, 2977 .major = KMS_DRIVER_MAJOR, 2978 .minor = KMS_DRIVER_MINOR, 2979 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2980 }; 2981 2982 const struct drm_driver amdgpu_partition_driver = { 2983 .driver_features = 2984 DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ | 2985 DRIVER_SYNCOBJ_TIMELINE, 2986 .open = amdgpu_driver_open_kms, 2987 .postclose = amdgpu_driver_postclose_kms, 2988 .ioctls = amdgpu_ioctls_kms, 2989 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2990 .dumb_create = amdgpu_mode_dumb_create, 2991 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2992 .fops = &amdgpu_driver_kms_fops, 2993 .release = &amdgpu_driver_release_kms, 2994 2995 .gem_prime_import = amdgpu_gem_prime_import, 2996 2997 .name = DRIVER_NAME, 2998 .desc = DRIVER_DESC, 2999 .date = DRIVER_DATE, 3000 .major = KMS_DRIVER_MAJOR, 3001 .minor = KMS_DRIVER_MINOR, 3002 .patchlevel = KMS_DRIVER_PATCHLEVEL, 3003 }; 3004 3005 static struct pci_error_handlers amdgpu_pci_err_handler = { 3006 .error_detected = amdgpu_pci_error_detected, 3007 .mmio_enabled = amdgpu_pci_mmio_enabled, 3008 .slot_reset = amdgpu_pci_slot_reset, 3009 .resume = amdgpu_pci_resume, 3010 }; 3011 3012 static const struct attribute_group *amdgpu_sysfs_groups[] = { 3013 &amdgpu_vram_mgr_attr_group, 3014 &amdgpu_gtt_mgr_attr_group, 3015 &amdgpu_flash_attr_group, 3016 NULL, 3017 }; 3018 3019 static struct pci_driver amdgpu_kms_pci_driver = { 3020 .name = DRIVER_NAME, 3021 .id_table = pciidlist, 3022 .probe = amdgpu_pci_probe, 3023 .remove = amdgpu_pci_remove, 3024 .shutdown = amdgpu_pci_shutdown, 3025 .driver.pm = &amdgpu_pm_ops, 3026 .err_handler = &amdgpu_pci_err_handler, 3027 .dev_groups = amdgpu_sysfs_groups, 3028 }; 3029 3030 static int __init amdgpu_init(void) 3031 { 3032 int r; 3033 3034 if (drm_firmware_drivers_only()) 3035 return -EINVAL; 3036 3037 r = amdgpu_sync_init(); 3038 if (r) 3039 goto error_sync; 3040 3041 r = amdgpu_fence_slab_init(); 3042 if (r) 3043 goto error_fence; 3044 3045 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 3046 amdgpu_register_atpx_handler(); 3047 amdgpu_acpi_detect(); 3048 3049 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 3050 amdgpu_amdkfd_init(); 3051 3052 /* let modprobe override vga console setting */ 3053 return pci_register_driver(&amdgpu_kms_pci_driver); 3054 3055 error_fence: 3056 amdgpu_sync_fini(); 3057 3058 error_sync: 3059 return r; 3060 } 3061 3062 static void __exit amdgpu_exit(void) 3063 { 3064 amdgpu_amdkfd_fini(); 3065 pci_unregister_driver(&amdgpu_kms_pci_driver); 3066 amdgpu_unregister_atpx_handler(); 3067 amdgpu_acpi_release(); 3068 amdgpu_sync_fini(); 3069 amdgpu_fence_slab_fini(); 3070 mmu_notifier_synchronize(); 3071 amdgpu_xcp_drv_release(); 3072 } 3073 3074 module_init(amdgpu_init); 3075 module_exit(amdgpu_exit); 3076 3077 MODULE_AUTHOR(DRIVER_AUTHOR); 3078 MODULE_DESCRIPTION(DRIVER_DESC); 3079 MODULE_LICENSE("GPL and additional rights"); 3080