1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_aperture.h> 27 #include <drm/drm_drv.h> 28 #include <drm/drm_gem.h> 29 #include <drm/drm_vblank.h> 30 #include <drm/drm_managed.h> 31 #include "amdgpu_drv.h" 32 33 #include <drm/drm_pciids.h> 34 #include <linux/console.h> 35 #include <linux/module.h> 36 #include <linux/pm_runtime.h> 37 #include <linux/vga_switcheroo.h> 38 #include <drm/drm_probe_helper.h> 39 #include <linux/mmu_notifier.h> 40 #include <linux/suspend.h> 41 42 #include "amdgpu.h" 43 #include "amdgpu_irq.h" 44 #include "amdgpu_dma_buf.h" 45 #include "amdgpu_sched.h" 46 #include "amdgpu_fdinfo.h" 47 #include "amdgpu_amdkfd.h" 48 49 #include "amdgpu_ras.h" 50 #include "amdgpu_xgmi.h" 51 #include "amdgpu_reset.h" 52 53 /* 54 * KMS wrapper. 55 * - 3.0.0 - initial driver 56 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 57 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 58 * at the end of IBs. 59 * - 3.3.0 - Add VM support for UVD on supported hardware. 60 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 61 * - 3.5.0 - Add support for new UVD_NO_OP register. 62 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 63 * - 3.7.0 - Add support for VCE clock list packet 64 * - 3.8.0 - Add support raster config init in the kernel 65 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 66 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 67 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 68 * - 3.12.0 - Add query for double offchip LDS buffers 69 * - 3.13.0 - Add PRT support 70 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 71 * - 3.15.0 - Export more gpu info for gfx9 72 * - 3.16.0 - Add reserved vmid support 73 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 74 * - 3.18.0 - Export gpu always on cu bitmap 75 * - 3.19.0 - Add support for UVD MJPEG decode 76 * - 3.20.0 - Add support for local BOs 77 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 78 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 79 * - 3.23.0 - Add query for VRAM lost counter 80 * - 3.24.0 - Add high priority compute support for gfx9 81 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 82 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 83 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation. 84 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 85 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 86 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 87 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 88 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 89 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 90 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 91 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 92 * - 3.36.0 - Allow reading more status registers on si/cik 93 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 94 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 95 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 96 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 97 * - 3.41.0 - Add video codec query 98 */ 99 #define KMS_DRIVER_MAJOR 3 100 #define KMS_DRIVER_MINOR 41 101 #define KMS_DRIVER_PATCHLEVEL 0 102 103 int amdgpu_vram_limit; 104 int amdgpu_vis_vram_limit; 105 int amdgpu_gart_size = -1; /* auto */ 106 int amdgpu_gtt_size = -1; /* auto */ 107 int amdgpu_moverate = -1; /* auto */ 108 int amdgpu_benchmarking; 109 int amdgpu_testing; 110 int amdgpu_audio = -1; 111 int amdgpu_disp_priority; 112 int amdgpu_hw_i2c; 113 int amdgpu_pcie_gen2 = -1; 114 int amdgpu_msi = -1; 115 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 116 int amdgpu_dpm = -1; 117 int amdgpu_fw_load_type = -1; 118 int amdgpu_aspm = -1; 119 int amdgpu_runtime_pm = -1; 120 uint amdgpu_ip_block_mask = 0xffffffff; 121 int amdgpu_bapm = -1; 122 int amdgpu_deep_color; 123 int amdgpu_vm_size = -1; 124 int amdgpu_vm_fragment_size = -1; 125 int amdgpu_vm_block_size = -1; 126 int amdgpu_vm_fault_stop; 127 int amdgpu_vm_debug; 128 int amdgpu_vm_update_mode = -1; 129 int amdgpu_exp_hw_support; 130 int amdgpu_dc = -1; 131 int amdgpu_sched_jobs = 32; 132 int amdgpu_sched_hw_submission = 2; 133 uint amdgpu_pcie_gen_cap; 134 uint amdgpu_pcie_lane_cap; 135 uint amdgpu_cg_mask = 0xffffffff; 136 uint amdgpu_pg_mask = 0xffffffff; 137 uint amdgpu_sdma_phase_quantum = 32; 138 char *amdgpu_disable_cu = NULL; 139 char *amdgpu_virtual_display = NULL; 140 141 /* 142 * OverDrive(bit 14) disabled by default 143 * GFX DCS(bit 19) disabled by default 144 */ 145 uint amdgpu_pp_feature_mask = 0xfff7bfff; 146 uint amdgpu_force_long_training; 147 int amdgpu_job_hang_limit; 148 int amdgpu_lbpw = -1; 149 int amdgpu_compute_multipipe = -1; 150 int amdgpu_gpu_recovery = -1; /* auto */ 151 int amdgpu_emu_mode; 152 uint amdgpu_smu_memory_pool_size; 153 int amdgpu_smu_pptable_id = -1; 154 /* 155 * FBC (bit 0) disabled by default 156 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 157 * - With this, for multiple monitors in sync(e.g. with the same model), 158 * mclk switching will be allowed. And the mclk will be not foced to the 159 * highest. That helps saving some idle power. 160 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 161 * PSR (bit 3) disabled by default 162 */ 163 uint amdgpu_dc_feature_mask = 2; 164 uint amdgpu_dc_debug_mask; 165 int amdgpu_async_gfx_ring = 1; 166 int amdgpu_mcbp; 167 int amdgpu_discovery = -1; 168 int amdgpu_mes; 169 int amdgpu_noretry = -1; 170 int amdgpu_force_asic_type = -1; 171 int amdgpu_tmz = -1; /* auto */ 172 uint amdgpu_freesync_vid_mode; 173 int amdgpu_reset_method = -1; /* auto */ 174 int amdgpu_num_kcq = -1; 175 176 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 177 178 struct amdgpu_mgpu_info mgpu_info = { 179 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 180 .delayed_reset_work = __DELAYED_WORK_INITIALIZER( 181 mgpu_info.delayed_reset_work, 182 amdgpu_drv_delayed_reset_work_handler, 0), 183 }; 184 int amdgpu_ras_enable = -1; 185 uint amdgpu_ras_mask = 0xffffffff; 186 int amdgpu_bad_page_threshold = -1; 187 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 188 .timeout_fatal_disable = false, 189 .period = 0x0, /* default to 0x0 (timeout disable) */ 190 }; 191 192 /** 193 * DOC: vramlimit (int) 194 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 195 */ 196 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 197 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 198 199 /** 200 * DOC: vis_vramlimit (int) 201 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 202 */ 203 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 204 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 205 206 /** 207 * DOC: gartsize (uint) 208 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic). 209 */ 210 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); 211 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 212 213 /** 214 * DOC: gttsize (int) 215 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM, 216 * otherwise 3/4 RAM size). 217 */ 218 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); 219 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 220 221 /** 222 * DOC: moverate (int) 223 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 224 */ 225 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 226 module_param_named(moverate, amdgpu_moverate, int, 0600); 227 228 /** 229 * DOC: benchmark (int) 230 * Run benchmarks. The default is 0 (Skip benchmarks). 231 */ 232 MODULE_PARM_DESC(benchmark, "Run benchmark"); 233 module_param_named(benchmark, amdgpu_benchmarking, int, 0444); 234 235 /** 236 * DOC: test (int) 237 * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test). 238 */ 239 MODULE_PARM_DESC(test, "Run tests"); 240 module_param_named(test, amdgpu_testing, int, 0444); 241 242 /** 243 * DOC: audio (int) 244 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 245 */ 246 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 247 module_param_named(audio, amdgpu_audio, int, 0444); 248 249 /** 250 * DOC: disp_priority (int) 251 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 252 */ 253 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 254 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 255 256 /** 257 * DOC: hw_i2c (int) 258 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 259 */ 260 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 261 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 262 263 /** 264 * DOC: pcie_gen2 (int) 265 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 266 */ 267 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 268 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 269 270 /** 271 * DOC: msi (int) 272 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 273 */ 274 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 275 module_param_named(msi, amdgpu_msi, int, 0444); 276 277 /** 278 * DOC: lockup_timeout (string) 279 * Set GPU scheduler timeout value in ms. 280 * 281 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 282 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 283 * to the default timeout. 284 * 285 * - With one value specified, the setting will apply to all non-compute jobs. 286 * - With multiple values specified, the first one will be for GFX. 287 * The second one is for Compute. The third and fourth ones are 288 * for SDMA and Video. 289 * 290 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 291 * jobs is 10000. The timeout for compute is 60000. 292 */ 293 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 294 "for passthrough or sriov, 10000 for all jobs." 295 " 0: keep default value. negative: infinity timeout), " 296 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 297 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 298 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 299 300 /** 301 * DOC: dpm (int) 302 * Override for dynamic power management setting 303 * (0 = disable, 1 = enable) 304 * The default is -1 (auto). 305 */ 306 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 307 module_param_named(dpm, amdgpu_dpm, int, 0444); 308 309 /** 310 * DOC: fw_load_type (int) 311 * Set different firmware loading type for debugging (0 = direct, 1 = SMU, 2 = PSP). The default is -1 (auto). 312 */ 313 MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)"); 314 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 315 316 /** 317 * DOC: aspm (int) 318 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 319 */ 320 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 321 module_param_named(aspm, amdgpu_aspm, int, 0444); 322 323 /** 324 * DOC: runpm (int) 325 * Override for runtime power management control for dGPUs in PX/HG laptops. The amdgpu driver can dynamically power down 326 * the dGPU on PX/HG laptops when it is idle. The default is -1 (auto enable). Setting the value to 0 disables this functionality. 327 */ 328 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = PX only default)"); 329 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 330 331 /** 332 * DOC: ip_block_mask (uint) 333 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 334 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 335 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 336 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 337 */ 338 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 339 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 340 341 /** 342 * DOC: bapm (int) 343 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 344 * The default -1 (auto, enabled) 345 */ 346 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 347 module_param_named(bapm, amdgpu_bapm, int, 0444); 348 349 /** 350 * DOC: deep_color (int) 351 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 352 */ 353 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 354 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 355 356 /** 357 * DOC: vm_size (int) 358 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 359 */ 360 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 361 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 362 363 /** 364 * DOC: vm_fragment_size (int) 365 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 366 */ 367 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 368 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 369 370 /** 371 * DOC: vm_block_size (int) 372 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 373 */ 374 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 375 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 376 377 /** 378 * DOC: vm_fault_stop (int) 379 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 380 */ 381 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 382 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 383 384 /** 385 * DOC: vm_debug (int) 386 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 387 */ 388 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 389 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 390 391 /** 392 * DOC: vm_update_mode (int) 393 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 394 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 395 */ 396 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 397 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 398 399 /** 400 * DOC: exp_hw_support (int) 401 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 402 */ 403 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 404 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 405 406 /** 407 * DOC: dc (int) 408 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 409 */ 410 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 411 module_param_named(dc, amdgpu_dc, int, 0444); 412 413 /** 414 * DOC: sched_jobs (int) 415 * Override the max number of jobs supported in the sw queue. The default is 32. 416 */ 417 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 418 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 419 420 /** 421 * DOC: sched_hw_submission (int) 422 * Override the max number of HW submissions. The default is 2. 423 */ 424 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 425 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 426 427 /** 428 * DOC: ppfeaturemask (hexint) 429 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 430 * The default is the current set of stable power features. 431 */ 432 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 433 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 434 435 /** 436 * DOC: forcelongtraining (uint) 437 * Force long memory training in resume. 438 * The default is zero, indicates short training in resume. 439 */ 440 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 441 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 442 443 /** 444 * DOC: pcie_gen_cap (uint) 445 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 446 * The default is 0 (automatic for each asic). 447 */ 448 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 449 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 450 451 /** 452 * DOC: pcie_lane_cap (uint) 453 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 454 * The default is 0 (automatic for each asic). 455 */ 456 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 457 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 458 459 /** 460 * DOC: cg_mask (uint) 461 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 462 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 463 */ 464 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 465 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); 466 467 /** 468 * DOC: pg_mask (uint) 469 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 470 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 471 */ 472 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 473 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 474 475 /** 476 * DOC: sdma_phase_quantum (uint) 477 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 478 */ 479 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 480 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 481 482 /** 483 * DOC: disable_cu (charp) 484 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 485 */ 486 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 487 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 488 489 /** 490 * DOC: virtual_display (charp) 491 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 492 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 493 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 494 * device at 26:00.0. The default is NULL. 495 */ 496 MODULE_PARM_DESC(virtual_display, 497 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 498 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 499 500 /** 501 * DOC: job_hang_limit (int) 502 * Set how much time allow a job hang and not drop it. The default is 0. 503 */ 504 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 505 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 506 507 /** 508 * DOC: lbpw (int) 509 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 510 */ 511 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 512 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 513 514 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 515 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 516 517 /** 518 * DOC: gpu_recovery (int) 519 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 520 */ 521 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (2 = advanced tdr mode, 1 = enable, 0 = disable, -1 = auto)"); 522 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 523 524 /** 525 * DOC: emu_mode (int) 526 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 527 */ 528 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 529 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 530 531 /** 532 * DOC: ras_enable (int) 533 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 534 */ 535 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 536 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 537 538 /** 539 * DOC: ras_mask (uint) 540 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 541 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 542 */ 543 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 544 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 545 546 /** 547 * DOC: timeout_fatal_disable (bool) 548 * Disable Watchdog timeout fatal error event 549 */ 550 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 551 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 552 553 /** 554 * DOC: timeout_period (uint) 555 * Modify the watchdog timeout max_cycles as (1 << period) 556 */ 557 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 558 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 559 560 /** 561 * DOC: si_support (int) 562 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 563 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 564 * otherwise using amdgpu driver. 565 */ 566 #ifdef CONFIG_DRM_AMDGPU_SI 567 568 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 569 int amdgpu_si_support = 0; 570 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 571 #else 572 int amdgpu_si_support = 1; 573 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 574 #endif 575 576 module_param_named(si_support, amdgpu_si_support, int, 0444); 577 #endif 578 579 /** 580 * DOC: cik_support (int) 581 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 582 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 583 * otherwise using amdgpu driver. 584 */ 585 #ifdef CONFIG_DRM_AMDGPU_CIK 586 587 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 588 int amdgpu_cik_support = 0; 589 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 590 #else 591 int amdgpu_cik_support = 1; 592 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 593 #endif 594 595 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 596 #endif 597 598 /** 599 * DOC: smu_memory_pool_size (uint) 600 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 601 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 602 */ 603 MODULE_PARM_DESC(smu_memory_pool_size, 604 "reserve gtt for smu debug usage, 0 = disable," 605 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 606 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 607 608 /** 609 * DOC: async_gfx_ring (int) 610 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 611 */ 612 MODULE_PARM_DESC(async_gfx_ring, 613 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 614 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 615 616 /** 617 * DOC: mcbp (int) 618 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled) 619 */ 620 MODULE_PARM_DESC(mcbp, 621 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); 622 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 623 624 /** 625 * DOC: discovery (int) 626 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 627 * (-1 = auto (default), 0 = disabled, 1 = enabled) 628 */ 629 MODULE_PARM_DESC(discovery, 630 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 631 module_param_named(discovery, amdgpu_discovery, int, 0444); 632 633 /** 634 * DOC: mes (int) 635 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 636 * (0 = disabled (default), 1 = enabled) 637 */ 638 MODULE_PARM_DESC(mes, 639 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 640 module_param_named(mes, amdgpu_mes, int, 0444); 641 642 /** 643 * DOC: noretry (int) 644 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 645 * do not support per-process XNACK this also disables retry page faults. 646 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 647 */ 648 MODULE_PARM_DESC(noretry, 649 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 650 module_param_named(noretry, amdgpu_noretry, int, 0644); 651 652 /** 653 * DOC: force_asic_type (int) 654 * A non negative value used to specify the asic type for all supported GPUs. 655 */ 656 MODULE_PARM_DESC(force_asic_type, 657 "A non negative value used to specify the asic type for all supported GPUs"); 658 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 659 660 661 662 #ifdef CONFIG_HSA_AMD 663 /** 664 * DOC: sched_policy (int) 665 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 666 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 667 * assigns queues to HQDs. 668 */ 669 int sched_policy = KFD_SCHED_POLICY_HWS; 670 module_param(sched_policy, int, 0444); 671 MODULE_PARM_DESC(sched_policy, 672 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 673 674 /** 675 * DOC: hws_max_conc_proc (int) 676 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 677 * number of VMIDs assigned to the HWS, which is also the default. 678 */ 679 int hws_max_conc_proc = 8; 680 module_param(hws_max_conc_proc, int, 0444); 681 MODULE_PARM_DESC(hws_max_conc_proc, 682 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 683 684 /** 685 * DOC: cwsr_enable (int) 686 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 687 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 688 * disables it. 689 */ 690 int cwsr_enable = 1; 691 module_param(cwsr_enable, int, 0444); 692 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 693 694 /** 695 * DOC: max_num_of_queues_per_device (int) 696 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 697 * is 4096. 698 */ 699 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 700 module_param(max_num_of_queues_per_device, int, 0444); 701 MODULE_PARM_DESC(max_num_of_queues_per_device, 702 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 703 704 /** 705 * DOC: send_sigterm (int) 706 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 707 * but just print errors on dmesg. Setting 1 enables sending sigterm. 708 */ 709 int send_sigterm; 710 module_param(send_sigterm, int, 0444); 711 MODULE_PARM_DESC(send_sigterm, 712 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 713 714 /** 715 * DOC: debug_largebar (int) 716 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 717 * system. This limits the VRAM size reported to ROCm applications to the visible 718 * size, usually 256MB. 719 * Default value is 0, diabled. 720 */ 721 int debug_largebar; 722 module_param(debug_largebar, int, 0444); 723 MODULE_PARM_DESC(debug_largebar, 724 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 725 726 /** 727 * DOC: ignore_crat (int) 728 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 729 * table to get information about AMD APUs. This option can serve as a workaround on 730 * systems with a broken CRAT table. 731 * 732 * Default is auto (according to asic type, iommu_v2, and crat table, to decide 733 * whehter use CRAT) 734 */ 735 int ignore_crat; 736 module_param(ignore_crat, int, 0444); 737 MODULE_PARM_DESC(ignore_crat, 738 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)"); 739 740 /** 741 * DOC: halt_if_hws_hang (int) 742 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 743 * Setting 1 enables halt on hang. 744 */ 745 int halt_if_hws_hang; 746 module_param(halt_if_hws_hang, int, 0644); 747 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 748 749 /** 750 * DOC: hws_gws_support(bool) 751 * Assume that HWS supports GWS barriers regardless of what firmware version 752 * check says. Default value: false (rely on MEC2 firmware version check). 753 */ 754 bool hws_gws_support; 755 module_param(hws_gws_support, bool, 0444); 756 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 757 758 /** 759 * DOC: queue_preemption_timeout_ms (int) 760 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 761 */ 762 int queue_preemption_timeout_ms = 9000; 763 module_param(queue_preemption_timeout_ms, int, 0644); 764 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 765 766 /** 767 * DOC: debug_evictions(bool) 768 * Enable extra debug messages to help determine the cause of evictions 769 */ 770 bool debug_evictions; 771 module_param(debug_evictions, bool, 0644); 772 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 773 774 /** 775 * DOC: no_system_mem_limit(bool) 776 * Disable system memory limit, to support multiple process shared memory 777 */ 778 bool no_system_mem_limit; 779 module_param(no_system_mem_limit, bool, 0644); 780 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 781 782 /** 783 * DOC: no_queue_eviction_on_vm_fault (int) 784 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 785 */ 786 int amdgpu_no_queue_eviction_on_vm_fault = 0; 787 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 788 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 789 #endif 790 791 /** 792 * DOC: dcfeaturemask (uint) 793 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 794 * The default is the current set of stable display features. 795 */ 796 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 797 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 798 799 /** 800 * DOC: dcdebugmask (uint) 801 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 802 */ 803 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 804 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 805 806 /** 807 * DOC: abmlevel (uint) 808 * Override the default ABM (Adaptive Backlight Management) level used for DC 809 * enabled hardware. Requires DMCU to be supported and loaded. 810 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 811 * default. Values 1-4 control the maximum allowable brightness reduction via 812 * the ABM algorithm, with 1 being the least reduction and 4 being the most 813 * reduction. 814 * 815 * Defaults to 0, or disabled. Userspace can still override this level later 816 * after boot. 817 */ 818 uint amdgpu_dm_abm_level; 819 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 820 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 821 822 int amdgpu_backlight = -1; 823 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 824 module_param_named(backlight, amdgpu_backlight, bint, 0444); 825 826 /** 827 * DOC: tmz (int) 828 * Trusted Memory Zone (TMZ) is a method to protect data being written 829 * to or read from memory. 830 * 831 * The default value: 0 (off). TODO: change to auto till it is completed. 832 */ 833 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 834 module_param_named(tmz, amdgpu_tmz, int, 0444); 835 836 /** 837 * DOC: freesync_video (uint) 838 * Enabled the optimization to adjust front porch timing to achieve seamless mode change experience 839 * when setting a freesync supported mode for which full modeset is not needed. 840 * The default value: 0 (off). 841 */ 842 MODULE_PARM_DESC( 843 freesync_video, 844 "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)"); 845 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); 846 847 /** 848 * DOC: reset_method (int) 849 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco, 5 = pci) 850 */ 851 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco, 5 = pci)"); 852 module_param_named(reset_method, amdgpu_reset_method, int, 0444); 853 854 /** 855 * DOC: bad_page_threshold (int) 856 * Bad page threshold is to specify the threshold value of faulty pages 857 * detected by RAS ECC, that may result in GPU entering bad status if total 858 * faulty pages by ECC exceed threshold value and leave it for user's further 859 * check. 860 */ 861 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement)"); 862 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 863 864 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 865 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 866 867 /** 868 * DOC: smu_pptable_id (int) 869 * Used to override pptable id. id = 0 use VBIOS pptable. 870 * id > 0 use the soft pptable with specicfied id. 871 */ 872 MODULE_PARM_DESC(smu_pptable_id, 873 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 874 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 875 876 static const struct pci_device_id pciidlist[] = { 877 #ifdef CONFIG_DRM_AMDGPU_SI 878 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 879 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 880 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 881 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 882 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 883 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 884 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 885 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 886 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 887 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 888 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 889 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 890 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 891 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 892 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 893 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 894 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 895 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 896 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 897 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 898 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 899 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 900 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 901 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 902 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 903 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 904 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 905 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 906 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 907 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 908 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 909 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 910 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 911 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 912 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 913 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 914 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 915 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 916 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 917 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 918 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 919 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 920 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 921 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 922 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 923 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 924 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 925 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 926 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 927 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 928 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 929 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 930 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 931 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 932 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 933 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 934 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 935 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 936 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 937 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 938 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 939 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 940 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 941 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 942 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 943 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 944 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 945 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 946 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 947 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 948 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 949 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 950 #endif 951 #ifdef CONFIG_DRM_AMDGPU_CIK 952 /* Kaveri */ 953 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 954 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 955 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 956 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 957 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 958 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 959 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 960 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 961 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 962 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 963 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 964 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 965 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 966 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 967 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 968 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 969 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 970 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 971 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 972 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 973 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 974 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 975 /* Bonaire */ 976 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 977 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 978 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 979 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 980 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 981 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 982 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 983 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 984 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 985 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 986 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 987 /* Hawaii */ 988 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 989 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 990 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 991 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 992 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 993 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 994 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 995 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 996 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 997 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 998 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 999 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1000 /* Kabini */ 1001 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1002 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1003 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1004 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1005 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1006 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1007 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1008 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1009 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1010 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1011 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1012 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1013 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1014 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1015 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1016 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1017 /* mullins */ 1018 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1019 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1020 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1021 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1022 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1023 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1024 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1025 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1026 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1027 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1028 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1029 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1030 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1031 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1032 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1033 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1034 #endif 1035 /* topaz */ 1036 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1037 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1038 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1039 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1040 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1041 /* tonga */ 1042 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1043 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1044 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1045 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1046 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1047 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1048 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1049 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1050 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1051 /* fiji */ 1052 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1053 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1054 /* carrizo */ 1055 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1056 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1057 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1058 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1059 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1060 /* stoney */ 1061 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1062 /* Polaris11 */ 1063 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1064 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1065 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1066 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1067 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1068 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1069 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1070 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1071 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1072 /* Polaris10 */ 1073 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1074 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1075 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1076 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1077 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1078 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1079 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1080 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1081 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1082 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1083 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1084 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1085 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1086 /* Polaris12 */ 1087 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1088 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1089 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1090 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1091 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1092 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1093 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1094 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1095 /* VEGAM */ 1096 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1097 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1098 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1099 /* Vega 10 */ 1100 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1101 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1102 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1103 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1104 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1105 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1106 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1107 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1108 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1109 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1110 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1111 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1112 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1113 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1114 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1115 /* Vega 12 */ 1116 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1117 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1118 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1119 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1120 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1121 /* Vega 20 */ 1122 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1123 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1124 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1125 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1126 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1127 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1128 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1129 /* Raven */ 1130 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1131 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1132 /* Arcturus */ 1133 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1134 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1135 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1136 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1137 /* Navi10 */ 1138 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1139 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1140 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1141 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1142 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1143 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1144 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1145 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1146 /* Navi14 */ 1147 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1148 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1149 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1150 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1151 1152 /* Renoir */ 1153 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1154 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1155 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1156 1157 /* Navi12 */ 1158 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1159 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1160 1161 /* Sienna_Cichlid */ 1162 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1163 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1164 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1165 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1166 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1167 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1168 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1169 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1170 1171 /* Van Gogh */ 1172 {0x1002, 0x163F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VANGOGH|AMD_IS_APU}, 1173 1174 /* Navy_Flounder */ 1175 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1176 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1177 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1178 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1179 1180 /* DIMGREY_CAVEFISH */ 1181 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1182 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1183 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1184 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1185 1186 /* Aldebaran */ 1187 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT}, 1188 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT}, 1189 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT}, 1190 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT}, 1191 1192 {0, 0, 0} 1193 }; 1194 1195 MODULE_DEVICE_TABLE(pci, pciidlist); 1196 1197 static const struct drm_driver amdgpu_kms_driver; 1198 1199 static int amdgpu_pci_probe(struct pci_dev *pdev, 1200 const struct pci_device_id *ent) 1201 { 1202 struct drm_device *ddev; 1203 struct amdgpu_device *adev; 1204 unsigned long flags = ent->driver_data; 1205 int ret, retry = 0; 1206 bool supports_atomic = false; 1207 1208 if (!amdgpu_virtual_display && 1209 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 1210 supports_atomic = true; 1211 1212 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 1213 DRM_INFO("This hardware requires experimental hardware support.\n" 1214 "See modparam exp_hw_support\n"); 1215 return -ENODEV; 1216 } 1217 1218 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 1219 * however, SME requires an indirect IOMMU mapping because the encryption 1220 * bit is beyond the DMA mask of the chip. 1221 */ 1222 if (mem_encrypt_active() && ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 1223 dev_info(&pdev->dev, 1224 "SME is not compatible with RAVEN\n"); 1225 return -ENOTSUPP; 1226 } 1227 1228 #ifdef CONFIG_DRM_AMDGPU_SI 1229 if (!amdgpu_si_support) { 1230 switch (flags & AMD_ASIC_MASK) { 1231 case CHIP_TAHITI: 1232 case CHIP_PITCAIRN: 1233 case CHIP_VERDE: 1234 case CHIP_OLAND: 1235 case CHIP_HAINAN: 1236 dev_info(&pdev->dev, 1237 "SI support provided by radeon.\n"); 1238 dev_info(&pdev->dev, 1239 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 1240 ); 1241 return -ENODEV; 1242 } 1243 } 1244 #endif 1245 #ifdef CONFIG_DRM_AMDGPU_CIK 1246 if (!amdgpu_cik_support) { 1247 switch (flags & AMD_ASIC_MASK) { 1248 case CHIP_KAVERI: 1249 case CHIP_BONAIRE: 1250 case CHIP_HAWAII: 1251 case CHIP_KABINI: 1252 case CHIP_MULLINS: 1253 dev_info(&pdev->dev, 1254 "CIK support provided by radeon.\n"); 1255 dev_info(&pdev->dev, 1256 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 1257 ); 1258 return -ENODEV; 1259 } 1260 } 1261 #endif 1262 1263 /* Get rid of things like offb */ 1264 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, "amdgpudrmfb"); 1265 if (ret) 1266 return ret; 1267 1268 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 1269 if (IS_ERR(adev)) 1270 return PTR_ERR(adev); 1271 1272 adev->dev = &pdev->dev; 1273 adev->pdev = pdev; 1274 ddev = adev_to_drm(adev); 1275 1276 if (!supports_atomic) 1277 ddev->driver_features &= ~DRIVER_ATOMIC; 1278 1279 ret = pci_enable_device(pdev); 1280 if (ret) 1281 return ret; 1282 1283 pci_set_drvdata(pdev, ddev); 1284 1285 ret = amdgpu_driver_load_kms(adev, ent->driver_data); 1286 if (ret) 1287 goto err_pci; 1288 1289 retry_init: 1290 ret = drm_dev_register(ddev, ent->driver_data); 1291 if (ret == -EAGAIN && ++retry <= 3) { 1292 DRM_INFO("retry init %d\n", retry); 1293 /* Don't request EX mode too frequently which is attacking */ 1294 msleep(5000); 1295 goto retry_init; 1296 } else if (ret) { 1297 goto err_pci; 1298 } 1299 1300 ret = amdgpu_debugfs_init(adev); 1301 if (ret) 1302 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 1303 1304 return 0; 1305 1306 err_pci: 1307 pci_disable_device(pdev); 1308 return ret; 1309 } 1310 1311 static void 1312 amdgpu_pci_remove(struct pci_dev *pdev) 1313 { 1314 struct drm_device *dev = pci_get_drvdata(pdev); 1315 1316 drm_dev_unplug(dev); 1317 amdgpu_driver_unload_kms(dev); 1318 1319 /* 1320 * Flush any in flight DMA operations from device. 1321 * Clear the Bus Master Enable bit and then wait on the PCIe Device 1322 * StatusTransactions Pending bit. 1323 */ 1324 pci_disable_device(pdev); 1325 pci_wait_for_pending_transaction(pdev); 1326 } 1327 1328 static void 1329 amdgpu_pci_shutdown(struct pci_dev *pdev) 1330 { 1331 struct drm_device *dev = pci_get_drvdata(pdev); 1332 struct amdgpu_device *adev = drm_to_adev(dev); 1333 1334 if (amdgpu_ras_intr_triggered()) 1335 return; 1336 1337 /* if we are running in a VM, make sure the device 1338 * torn down properly on reboot/shutdown. 1339 * unfortunately we can't detect certain 1340 * hypervisors so just do this all the time. 1341 */ 1342 if (!amdgpu_passthrough(adev)) 1343 adev->mp1_state = PP_MP1_STATE_UNLOAD; 1344 amdgpu_device_ip_suspend(adev); 1345 adev->mp1_state = PP_MP1_STATE_NONE; 1346 } 1347 1348 /** 1349 * amdgpu_drv_delayed_reset_work_handler - work handler for reset 1350 * 1351 * @work: work_struct. 1352 */ 1353 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) 1354 { 1355 struct list_head device_list; 1356 struct amdgpu_device *adev; 1357 int i, r; 1358 struct amdgpu_reset_context reset_context; 1359 1360 memset(&reset_context, 0, sizeof(reset_context)); 1361 1362 mutex_lock(&mgpu_info.mutex); 1363 if (mgpu_info.pending_reset == true) { 1364 mutex_unlock(&mgpu_info.mutex); 1365 return; 1366 } 1367 mgpu_info.pending_reset = true; 1368 mutex_unlock(&mgpu_info.mutex); 1369 1370 /* Use a common context, just need to make sure full reset is done */ 1371 reset_context.method = AMD_RESET_METHOD_NONE; 1372 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 1373 1374 for (i = 0; i < mgpu_info.num_dgpu; i++) { 1375 adev = mgpu_info.gpu_ins[i].adev; 1376 reset_context.reset_req_dev = adev; 1377 r = amdgpu_device_pre_asic_reset(adev, &reset_context); 1378 if (r) { 1379 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", 1380 r, adev_to_drm(adev)->unique); 1381 } 1382 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) 1383 r = -EALREADY; 1384 } 1385 for (i = 0; i < mgpu_info.num_dgpu; i++) { 1386 adev = mgpu_info.gpu_ins[i].adev; 1387 flush_work(&adev->xgmi_reset_work); 1388 adev->gmc.xgmi.pending_reset = false; 1389 } 1390 1391 /* reset function will rebuild the xgmi hive info , clear it now */ 1392 for (i = 0; i < mgpu_info.num_dgpu; i++) 1393 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); 1394 1395 INIT_LIST_HEAD(&device_list); 1396 1397 for (i = 0; i < mgpu_info.num_dgpu; i++) 1398 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); 1399 1400 /* unregister the GPU first, reset function will add them back */ 1401 list_for_each_entry(adev, &device_list, reset_list) 1402 amdgpu_unregister_gpu_instance(adev); 1403 1404 /* Use a common context, just need to make sure full reset is done */ 1405 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); 1406 r = amdgpu_do_asic_reset(&device_list, &reset_context); 1407 1408 if (r) { 1409 DRM_ERROR("reinit gpus failure"); 1410 return; 1411 } 1412 for (i = 0; i < mgpu_info.num_dgpu; i++) { 1413 adev = mgpu_info.gpu_ins[i].adev; 1414 if (!adev->kfd.init_complete) 1415 amdgpu_amdkfd_device_init(adev); 1416 amdgpu_ttm_set_buffer_funcs_status(adev, true); 1417 } 1418 return; 1419 } 1420 1421 static int amdgpu_pmops_prepare(struct device *dev) 1422 { 1423 struct drm_device *drm_dev = dev_get_drvdata(dev); 1424 1425 /* Return a positive number here so 1426 * DPM_FLAG_SMART_SUSPEND works properly 1427 */ 1428 if (amdgpu_device_supports_boco(drm_dev)) 1429 return pm_runtime_suspended(dev) && 1430 pm_suspend_via_firmware(); 1431 1432 return 0; 1433 } 1434 1435 static void amdgpu_pmops_complete(struct device *dev) 1436 { 1437 /* nothing to do */ 1438 } 1439 1440 static int amdgpu_pmops_suspend(struct device *dev) 1441 { 1442 struct drm_device *drm_dev = dev_get_drvdata(dev); 1443 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1444 int r; 1445 1446 if (amdgpu_acpi_is_s0ix_supported(adev)) 1447 adev->in_s0ix = true; 1448 adev->in_s3 = true; 1449 r = amdgpu_device_suspend(drm_dev, true); 1450 adev->in_s3 = false; 1451 1452 return r; 1453 } 1454 1455 static int amdgpu_pmops_resume(struct device *dev) 1456 { 1457 struct drm_device *drm_dev = dev_get_drvdata(dev); 1458 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1459 int r; 1460 1461 r = amdgpu_device_resume(drm_dev, true); 1462 if (amdgpu_acpi_is_s0ix_supported(adev)) 1463 adev->in_s0ix = false; 1464 return r; 1465 } 1466 1467 static int amdgpu_pmops_freeze(struct device *dev) 1468 { 1469 struct drm_device *drm_dev = dev_get_drvdata(dev); 1470 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1471 int r; 1472 1473 adev->in_s4 = true; 1474 r = amdgpu_device_suspend(drm_dev, true); 1475 adev->in_s4 = false; 1476 if (r) 1477 return r; 1478 return amdgpu_asic_reset(adev); 1479 } 1480 1481 static int amdgpu_pmops_thaw(struct device *dev) 1482 { 1483 struct drm_device *drm_dev = dev_get_drvdata(dev); 1484 1485 return amdgpu_device_resume(drm_dev, true); 1486 } 1487 1488 static int amdgpu_pmops_poweroff(struct device *dev) 1489 { 1490 struct drm_device *drm_dev = dev_get_drvdata(dev); 1491 1492 return amdgpu_device_suspend(drm_dev, true); 1493 } 1494 1495 static int amdgpu_pmops_restore(struct device *dev) 1496 { 1497 struct drm_device *drm_dev = dev_get_drvdata(dev); 1498 1499 return amdgpu_device_resume(drm_dev, true); 1500 } 1501 1502 static int amdgpu_pmops_runtime_suspend(struct device *dev) 1503 { 1504 struct pci_dev *pdev = to_pci_dev(dev); 1505 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1506 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1507 int ret, i; 1508 1509 if (!adev->runpm) { 1510 pm_runtime_forbid(dev); 1511 return -EBUSY; 1512 } 1513 1514 /* wait for all rings to drain before suspending */ 1515 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 1516 struct amdgpu_ring *ring = adev->rings[i]; 1517 if (ring && ring->sched.ready) { 1518 ret = amdgpu_fence_wait_empty(ring); 1519 if (ret) 1520 return -EBUSY; 1521 } 1522 } 1523 1524 adev->in_runpm = true; 1525 if (amdgpu_device_supports_px(drm_dev)) 1526 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1527 1528 ret = amdgpu_device_suspend(drm_dev, false); 1529 if (ret) { 1530 adev->in_runpm = false; 1531 return ret; 1532 } 1533 1534 if (amdgpu_device_supports_px(drm_dev)) { 1535 /* Only need to handle PCI state in the driver for ATPX 1536 * PCI core handles it for _PR3. 1537 */ 1538 amdgpu_device_cache_pci_state(pdev); 1539 pci_disable_device(pdev); 1540 pci_ignore_hotplug(pdev); 1541 pci_set_power_state(pdev, PCI_D3cold); 1542 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 1543 } else if (amdgpu_device_supports_baco(drm_dev)) { 1544 amdgpu_device_baco_enter(drm_dev); 1545 } 1546 1547 return 0; 1548 } 1549 1550 static int amdgpu_pmops_runtime_resume(struct device *dev) 1551 { 1552 struct pci_dev *pdev = to_pci_dev(dev); 1553 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1554 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1555 int ret; 1556 1557 if (!adev->runpm) 1558 return -EINVAL; 1559 1560 /* Avoids registers access if device is physically gone */ 1561 if (!pci_device_is_present(adev->pdev)) 1562 adev->no_hw_access = true; 1563 1564 if (amdgpu_device_supports_px(drm_dev)) { 1565 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1566 1567 /* Only need to handle PCI state in the driver for ATPX 1568 * PCI core handles it for _PR3. 1569 */ 1570 pci_set_power_state(pdev, PCI_D0); 1571 amdgpu_device_load_pci_state(pdev); 1572 ret = pci_enable_device(pdev); 1573 if (ret) 1574 return ret; 1575 pci_set_master(pdev); 1576 } else if (amdgpu_device_supports_boco(drm_dev)) { 1577 /* Only need to handle PCI state in the driver for ATPX 1578 * PCI core handles it for _PR3. 1579 */ 1580 pci_set_master(pdev); 1581 } else if (amdgpu_device_supports_baco(drm_dev)) { 1582 amdgpu_device_baco_exit(drm_dev); 1583 } 1584 ret = amdgpu_device_resume(drm_dev, false); 1585 if (ret) 1586 return ret; 1587 1588 if (amdgpu_device_supports_px(drm_dev)) 1589 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 1590 adev->in_runpm = false; 1591 return 0; 1592 } 1593 1594 static int amdgpu_pmops_runtime_idle(struct device *dev) 1595 { 1596 struct drm_device *drm_dev = dev_get_drvdata(dev); 1597 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1598 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 1599 int ret = 1; 1600 1601 if (!adev->runpm) { 1602 pm_runtime_forbid(dev); 1603 return -EBUSY; 1604 } 1605 1606 if (amdgpu_device_has_dc_support(adev)) { 1607 struct drm_crtc *crtc; 1608 1609 drm_for_each_crtc(crtc, drm_dev) { 1610 drm_modeset_lock(&crtc->mutex, NULL); 1611 if (crtc->state->active) 1612 ret = -EBUSY; 1613 drm_modeset_unlock(&crtc->mutex); 1614 if (ret < 0) 1615 break; 1616 } 1617 1618 } else { 1619 struct drm_connector *list_connector; 1620 struct drm_connector_list_iter iter; 1621 1622 mutex_lock(&drm_dev->mode_config.mutex); 1623 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 1624 1625 drm_connector_list_iter_begin(drm_dev, &iter); 1626 drm_for_each_connector_iter(list_connector, &iter) { 1627 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 1628 ret = -EBUSY; 1629 break; 1630 } 1631 } 1632 1633 drm_connector_list_iter_end(&iter); 1634 1635 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 1636 mutex_unlock(&drm_dev->mode_config.mutex); 1637 } 1638 1639 if (ret == -EBUSY) 1640 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 1641 1642 pm_runtime_mark_last_busy(dev); 1643 pm_runtime_autosuspend(dev); 1644 return ret; 1645 } 1646 1647 long amdgpu_drm_ioctl(struct file *filp, 1648 unsigned int cmd, unsigned long arg) 1649 { 1650 struct drm_file *file_priv = filp->private_data; 1651 struct drm_device *dev; 1652 long ret; 1653 dev = file_priv->minor->dev; 1654 ret = pm_runtime_get_sync(dev->dev); 1655 if (ret < 0) 1656 goto out; 1657 1658 ret = drm_ioctl(filp, cmd, arg); 1659 1660 pm_runtime_mark_last_busy(dev->dev); 1661 out: 1662 pm_runtime_put_autosuspend(dev->dev); 1663 return ret; 1664 } 1665 1666 static const struct dev_pm_ops amdgpu_pm_ops = { 1667 .prepare = amdgpu_pmops_prepare, 1668 .complete = amdgpu_pmops_complete, 1669 .suspend = amdgpu_pmops_suspend, 1670 .resume = amdgpu_pmops_resume, 1671 .freeze = amdgpu_pmops_freeze, 1672 .thaw = amdgpu_pmops_thaw, 1673 .poweroff = amdgpu_pmops_poweroff, 1674 .restore = amdgpu_pmops_restore, 1675 .runtime_suspend = amdgpu_pmops_runtime_suspend, 1676 .runtime_resume = amdgpu_pmops_runtime_resume, 1677 .runtime_idle = amdgpu_pmops_runtime_idle, 1678 }; 1679 1680 static int amdgpu_flush(struct file *f, fl_owner_t id) 1681 { 1682 struct drm_file *file_priv = f->private_data; 1683 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1684 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 1685 1686 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 1687 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 1688 1689 return timeout >= 0 ? 0 : timeout; 1690 } 1691 1692 static const struct file_operations amdgpu_driver_kms_fops = { 1693 .owner = THIS_MODULE, 1694 .open = drm_open, 1695 .flush = amdgpu_flush, 1696 .release = drm_release, 1697 .unlocked_ioctl = amdgpu_drm_ioctl, 1698 .mmap = drm_gem_mmap, 1699 .poll = drm_poll, 1700 .read = drm_read, 1701 #ifdef CONFIG_COMPAT 1702 .compat_ioctl = amdgpu_kms_compat_ioctl, 1703 #endif 1704 #ifdef CONFIG_PROC_FS 1705 .show_fdinfo = amdgpu_show_fdinfo 1706 #endif 1707 }; 1708 1709 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 1710 { 1711 struct drm_file *file; 1712 1713 if (!filp) 1714 return -EINVAL; 1715 1716 if (filp->f_op != &amdgpu_driver_kms_fops) { 1717 return -EINVAL; 1718 } 1719 1720 file = filp->private_data; 1721 *fpriv = file->driver_priv; 1722 return 0; 1723 } 1724 1725 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 1726 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1727 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1728 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1729 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 1730 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1731 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1732 /* KMS */ 1733 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1734 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1735 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1736 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1737 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1738 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1739 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1740 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1741 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1742 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1743 }; 1744 1745 static const struct drm_driver amdgpu_kms_driver = { 1746 .driver_features = 1747 DRIVER_ATOMIC | 1748 DRIVER_GEM | 1749 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 1750 DRIVER_SYNCOBJ_TIMELINE, 1751 .open = amdgpu_driver_open_kms, 1752 .postclose = amdgpu_driver_postclose_kms, 1753 .lastclose = amdgpu_driver_lastclose_kms, 1754 .irq_handler = amdgpu_irq_handler, 1755 .ioctls = amdgpu_ioctls_kms, 1756 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 1757 .dumb_create = amdgpu_mode_dumb_create, 1758 .dumb_map_offset = amdgpu_mode_dumb_mmap, 1759 .fops = &amdgpu_driver_kms_fops, 1760 .release = &amdgpu_driver_release_kms, 1761 1762 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 1763 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 1764 .gem_prime_import = amdgpu_gem_prime_import, 1765 .gem_prime_mmap = drm_gem_prime_mmap, 1766 1767 .name = DRIVER_NAME, 1768 .desc = DRIVER_DESC, 1769 .date = DRIVER_DATE, 1770 .major = KMS_DRIVER_MAJOR, 1771 .minor = KMS_DRIVER_MINOR, 1772 .patchlevel = KMS_DRIVER_PATCHLEVEL, 1773 }; 1774 1775 static struct pci_error_handlers amdgpu_pci_err_handler = { 1776 .error_detected = amdgpu_pci_error_detected, 1777 .mmio_enabled = amdgpu_pci_mmio_enabled, 1778 .slot_reset = amdgpu_pci_slot_reset, 1779 .resume = amdgpu_pci_resume, 1780 }; 1781 1782 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 1783 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 1784 extern const struct attribute_group amdgpu_vbios_version_attr_group; 1785 1786 static const struct attribute_group *amdgpu_sysfs_groups[] = { 1787 &amdgpu_vram_mgr_attr_group, 1788 &amdgpu_gtt_mgr_attr_group, 1789 &amdgpu_vbios_version_attr_group, 1790 NULL, 1791 }; 1792 1793 1794 static struct pci_driver amdgpu_kms_pci_driver = { 1795 .name = DRIVER_NAME, 1796 .id_table = pciidlist, 1797 .probe = amdgpu_pci_probe, 1798 .remove = amdgpu_pci_remove, 1799 .shutdown = amdgpu_pci_shutdown, 1800 .driver.pm = &amdgpu_pm_ops, 1801 .err_handler = &amdgpu_pci_err_handler, 1802 .dev_groups = amdgpu_sysfs_groups, 1803 }; 1804 1805 static int __init amdgpu_init(void) 1806 { 1807 int r; 1808 1809 if (vgacon_text_force()) { 1810 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); 1811 return -EINVAL; 1812 } 1813 1814 r = amdgpu_sync_init(); 1815 if (r) 1816 goto error_sync; 1817 1818 r = amdgpu_fence_slab_init(); 1819 if (r) 1820 goto error_fence; 1821 1822 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 1823 amdgpu_register_atpx_handler(); 1824 1825 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 1826 amdgpu_amdkfd_init(); 1827 1828 /* let modprobe override vga console setting */ 1829 return pci_register_driver(&amdgpu_kms_pci_driver); 1830 1831 error_fence: 1832 amdgpu_sync_fini(); 1833 1834 error_sync: 1835 return r; 1836 } 1837 1838 static void __exit amdgpu_exit(void) 1839 { 1840 amdgpu_amdkfd_fini(); 1841 pci_unregister_driver(&amdgpu_kms_pci_driver); 1842 amdgpu_unregister_atpx_handler(); 1843 amdgpu_sync_fini(); 1844 amdgpu_fence_slab_fini(); 1845 mmu_notifier_synchronize(); 1846 } 1847 1848 module_init(amdgpu_init); 1849 module_exit(amdgpu_exit); 1850 1851 MODULE_AUTHOR(DRIVER_AUTHOR); 1852 MODULE_DESCRIPTION(DRIVER_DESC); 1853 MODULE_LICENSE("GPL and additional rights"); 1854