1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/clients/drm_client_setup.h> 27 #include <drm/drm_drv.h> 28 #include <drm/drm_fbdev_ttm.h> 29 #include <drm/drm_gem.h> 30 #include <drm/drm_managed.h> 31 #include <drm/drm_pciids.h> 32 #include <drm/drm_probe_helper.h> 33 #include <drm/drm_vblank.h> 34 35 #include <linux/cc_platform.h> 36 #include <linux/dynamic_debug.h> 37 #include <linux/module.h> 38 #include <linux/mmu_notifier.h> 39 #include <linux/pm_runtime.h> 40 #include <linux/suspend.h> 41 #include <linux/vga_switcheroo.h> 42 43 #include "amdgpu.h" 44 #include "amdgpu_amdkfd.h" 45 #include "amdgpu_dma_buf.h" 46 #include "amdgpu_drv.h" 47 #include "amdgpu_fdinfo.h" 48 #include "amdgpu_irq.h" 49 #include "amdgpu_psp.h" 50 #include "amdgpu_ras.h" 51 #include "amdgpu_reset.h" 52 #include "amdgpu_sched.h" 53 #include "amdgpu_xgmi.h" 54 #include "../amdxcp/amdgpu_xcp_drv.h" 55 56 /* 57 * KMS wrapper. 58 * - 3.0.0 - initial driver 59 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 60 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 61 * at the end of IBs. 62 * - 3.3.0 - Add VM support for UVD on supported hardware. 63 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 64 * - 3.5.0 - Add support for new UVD_NO_OP register. 65 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 66 * - 3.7.0 - Add support for VCE clock list packet 67 * - 3.8.0 - Add support raster config init in the kernel 68 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 69 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 70 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 71 * - 3.12.0 - Add query for double offchip LDS buffers 72 * - 3.13.0 - Add PRT support 73 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 74 * - 3.15.0 - Export more gpu info for gfx9 75 * - 3.16.0 - Add reserved vmid support 76 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 77 * - 3.18.0 - Export gpu always on cu bitmap 78 * - 3.19.0 - Add support for UVD MJPEG decode 79 * - 3.20.0 - Add support for local BOs 80 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 81 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 82 * - 3.23.0 - Add query for VRAM lost counter 83 * - 3.24.0 - Add high priority compute support for gfx9 84 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 85 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 86 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation. 87 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 88 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 89 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 90 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 91 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 92 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 93 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 94 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 95 * - 3.36.0 - Allow reading more status registers on si/cik 96 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 97 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 98 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 99 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 100 * - 3.41.0 - Add video codec query 101 * - 3.42.0 - Add 16bpc fixed point display support 102 * - 3.43.0 - Add device hot plug/unplug support 103 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 104 * - 3.45.0 - Add context ioctl stable pstate interface 105 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm 106 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags 107 * - 3.48.0 - Add IP discovery version info to HW INFO 108 * - 3.49.0 - Add gang submit into CS IOCTL 109 * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock 110 * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock 111 * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl 112 * 3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields: 113 * tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size, 114 * gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi 115 * 3.53.0 - Support for GFX11 CP GFX shadowing 116 * 3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support 117 * - 3.55.0 - Add AMDGPU_INFO_GPUVM_FAULT query 118 * - 3.56.0 - Update IB start address and size alignment for decode and encode 119 * - 3.57.0 - Compute tunneling on GFX10+ 120 * - 3.58.0 - Add GFX12 DCC support 121 * - 3.59.0 - Cleared VRAM 122 * - 3.60.0 - Add AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE (Vulkan requirement) 123 */ 124 #define KMS_DRIVER_MAJOR 3 125 #define KMS_DRIVER_MINOR 60 126 #define KMS_DRIVER_PATCHLEVEL 0 127 128 /* 129 * amdgpu.debug module options. Are all disabled by default 130 */ 131 enum AMDGPU_DEBUG_MASK { 132 AMDGPU_DEBUG_VM = BIT(0), 133 AMDGPU_DEBUG_LARGEBAR = BIT(1), 134 AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY = BIT(2), 135 AMDGPU_DEBUG_USE_VRAM_FW_BUF = BIT(3), 136 AMDGPU_DEBUG_ENABLE_RAS_ACA = BIT(4), 137 AMDGPU_DEBUG_ENABLE_EXP_RESETS = BIT(5), 138 }; 139 140 unsigned int amdgpu_vram_limit = UINT_MAX; 141 int amdgpu_vis_vram_limit; 142 int amdgpu_gart_size = -1; /* auto */ 143 int amdgpu_gtt_size = -1; /* auto */ 144 int amdgpu_moverate = -1; /* auto */ 145 int amdgpu_audio = -1; 146 int amdgpu_disp_priority; 147 int amdgpu_hw_i2c; 148 int amdgpu_pcie_gen2 = -1; 149 int amdgpu_msi = -1; 150 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 151 int amdgpu_dpm = -1; 152 int amdgpu_fw_load_type = -1; 153 int amdgpu_aspm = -1; 154 int amdgpu_runtime_pm = -1; 155 uint amdgpu_ip_block_mask = 0xffffffff; 156 int amdgpu_bapm = -1; 157 int amdgpu_deep_color; 158 int amdgpu_vm_size = -1; 159 int amdgpu_vm_fragment_size = -1; 160 int amdgpu_vm_block_size = -1; 161 int amdgpu_vm_fault_stop; 162 int amdgpu_vm_update_mode = -1; 163 int amdgpu_exp_hw_support; 164 int amdgpu_dc = -1; 165 int amdgpu_sched_jobs = 32; 166 int amdgpu_sched_hw_submission = 2; 167 uint amdgpu_pcie_gen_cap; 168 uint amdgpu_pcie_lane_cap; 169 u64 amdgpu_cg_mask = 0xffffffffffffffff; 170 uint amdgpu_pg_mask = 0xffffffff; 171 uint amdgpu_sdma_phase_quantum = 32; 172 char *amdgpu_disable_cu; 173 char *amdgpu_virtual_display; 174 bool enforce_isolation; 175 176 /* Specifies the default granularity for SVM, used in buffer 177 * migration and restoration of backing memory when handling 178 * recoverable page faults. 179 * 180 * The value is given as log(numPages(buffer)); for a 2 MiB 181 * buffer it computes to be 9 182 */ 183 uint amdgpu_svm_default_granularity = 9; 184 185 /* 186 * OverDrive(bit 14) disabled by default 187 * GFX DCS(bit 19) disabled by default 188 */ 189 uint amdgpu_pp_feature_mask = 0xfff7bfff; 190 uint amdgpu_force_long_training; 191 int amdgpu_lbpw = -1; 192 int amdgpu_compute_multipipe = -1; 193 int amdgpu_gpu_recovery = -1; /* auto */ 194 int amdgpu_emu_mode; 195 uint amdgpu_smu_memory_pool_size; 196 int amdgpu_smu_pptable_id = -1; 197 /* 198 * FBC (bit 0) disabled by default 199 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 200 * - With this, for multiple monitors in sync(e.g. with the same model), 201 * mclk switching will be allowed. And the mclk will be not foced to the 202 * highest. That helps saving some idle power. 203 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 204 * PSR (bit 3) disabled by default 205 * EDP NO POWER SEQUENCING (bit 4) disabled by default 206 */ 207 uint amdgpu_dc_feature_mask = 2; 208 uint amdgpu_dc_debug_mask; 209 uint amdgpu_dc_visual_confirm; 210 int amdgpu_async_gfx_ring = 1; 211 int amdgpu_mcbp = -1; 212 int amdgpu_discovery = -1; 213 int amdgpu_mes; 214 int amdgpu_mes_log_enable = 0; 215 int amdgpu_mes_kiq; 216 int amdgpu_uni_mes = 1; 217 int amdgpu_noretry = -1; 218 int amdgpu_force_asic_type = -1; 219 int amdgpu_tmz = -1; /* auto */ 220 uint amdgpu_freesync_vid_mode; 221 int amdgpu_reset_method = -1; /* auto */ 222 int amdgpu_num_kcq = -1; 223 int amdgpu_smartshift_bias; 224 int amdgpu_use_xgmi_p2p = 1; 225 int amdgpu_vcnfw_log; 226 int amdgpu_sg_display = -1; /* auto */ 227 int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE; 228 int amdgpu_umsch_mm; 229 int amdgpu_seamless = -1; /* auto */ 230 uint amdgpu_debug_mask; 231 int amdgpu_agp = -1; /* auto */ 232 int amdgpu_wbrf = -1; 233 int amdgpu_damage_clips = -1; /* auto */ 234 int amdgpu_umsch_mm_fwlog; 235 236 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 237 "DRM_UT_CORE", 238 "DRM_UT_DRIVER", 239 "DRM_UT_KMS", 240 "DRM_UT_PRIME", 241 "DRM_UT_ATOMIC", 242 "DRM_UT_VBL", 243 "DRM_UT_STATE", 244 "DRM_UT_LEASE", 245 "DRM_UT_DP", 246 "DRM_UT_DRMRES"); 247 248 struct amdgpu_mgpu_info mgpu_info = { 249 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 250 }; 251 int amdgpu_ras_enable = -1; 252 uint amdgpu_ras_mask = 0xffffffff; 253 int amdgpu_bad_page_threshold = -1; 254 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 255 .timeout_fatal_disable = false, 256 .period = 0x0, /* default to 0x0 (timeout disable) */ 257 }; 258 259 /** 260 * DOC: vramlimit (int) 261 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 262 */ 263 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 264 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 265 266 /** 267 * DOC: vis_vramlimit (int) 268 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 269 */ 270 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 271 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 272 273 /** 274 * DOC: gartsize (uint) 275 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing. 276 * The default is -1 (The size depends on asic). 277 */ 278 MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)"); 279 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 280 281 /** 282 * DOC: gttsize (int) 283 * Restrict the size of GTT domain (for userspace use) in MiB for testing. 284 * The default is -1 (Use value specified by TTM). 285 */ 286 MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)"); 287 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 288 289 /** 290 * DOC: moverate (int) 291 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 292 */ 293 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 294 module_param_named(moverate, amdgpu_moverate, int, 0600); 295 296 /** 297 * DOC: audio (int) 298 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 299 */ 300 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 301 module_param_named(audio, amdgpu_audio, int, 0444); 302 303 /** 304 * DOC: disp_priority (int) 305 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 306 */ 307 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 308 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 309 310 /** 311 * DOC: hw_i2c (int) 312 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 313 */ 314 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 315 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 316 317 /** 318 * DOC: pcie_gen2 (int) 319 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 320 */ 321 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 322 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 323 324 /** 325 * DOC: msi (int) 326 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 327 */ 328 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 329 module_param_named(msi, amdgpu_msi, int, 0444); 330 331 /** 332 * DOC: svm_default_granularity (uint) 333 * Used in buffer migration and handling of recoverable page faults 334 */ 335 MODULE_PARM_DESC(svm_default_granularity, "SVM's default granularity in log(2^Pages), default 9 = 2^9 = 2 MiB"); 336 module_param_named(svm_default_granularity, amdgpu_svm_default_granularity, uint, 0644); 337 338 /** 339 * DOC: lockup_timeout (string) 340 * Set GPU scheduler timeout value in ms. 341 * 342 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 343 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 344 * to the default timeout. 345 * 346 * - With one value specified, the setting will apply to all non-compute jobs. 347 * - With multiple values specified, the first one will be for GFX. 348 * The second one is for Compute. The third and fourth ones are 349 * for SDMA and Video. 350 * 351 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 352 * jobs is 10000. The timeout for compute is 60000. 353 */ 354 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 355 "for passthrough or sriov, 10000 for all jobs. 0: keep default value. negative: infinity timeout), format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 356 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 357 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 358 359 /** 360 * DOC: dpm (int) 361 * Override for dynamic power management setting 362 * (0 = disable, 1 = enable) 363 * The default is -1 (auto). 364 */ 365 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 366 module_param_named(dpm, amdgpu_dpm, int, 0444); 367 368 /** 369 * DOC: fw_load_type (int) 370 * Set different firmware loading type for debugging, if supported. 371 * Set to 0 to force direct loading if supported by the ASIC. Set 372 * to -1 to select the default loading mode for the ASIC, as defined 373 * by the driver. The default is -1 (auto). 374 */ 375 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); 376 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 377 378 /** 379 * DOC: aspm (int) 380 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 381 */ 382 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 383 module_param_named(aspm, amdgpu_aspm, int, 0444); 384 385 /** 386 * DOC: runpm (int) 387 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 388 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 389 * Setting the value to 0 disables this functionality. 390 * Setting the value to -2 is auto enabled with power down when displays are attached. 391 */ 392 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto, -2 = auto with displays)"); 393 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 394 395 /** 396 * DOC: ip_block_mask (uint) 397 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 398 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 399 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 400 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 401 */ 402 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 403 module_param_named_unsafe(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 404 405 /** 406 * DOC: bapm (int) 407 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 408 * The default -1 (auto, enabled) 409 */ 410 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 411 module_param_named(bapm, amdgpu_bapm, int, 0444); 412 413 /** 414 * DOC: deep_color (int) 415 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 416 */ 417 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 418 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 419 420 /** 421 * DOC: vm_size (int) 422 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 423 */ 424 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 425 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 426 427 /** 428 * DOC: vm_fragment_size (int) 429 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 430 */ 431 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 432 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 433 434 /** 435 * DOC: vm_block_size (int) 436 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 437 */ 438 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 439 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 440 441 /** 442 * DOC: vm_fault_stop (int) 443 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 444 */ 445 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 446 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 447 448 /** 449 * DOC: vm_update_mode (int) 450 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 451 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 452 */ 453 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 454 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 455 456 /** 457 * DOC: exp_hw_support (int) 458 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 459 */ 460 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 461 module_param_named_unsafe(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 462 463 /** 464 * DOC: dc (int) 465 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 466 */ 467 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 468 module_param_named(dc, amdgpu_dc, int, 0444); 469 470 /** 471 * DOC: sched_jobs (int) 472 * Override the max number of jobs supported in the sw queue. The default is 32. 473 */ 474 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 475 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 476 477 /** 478 * DOC: sched_hw_submission (int) 479 * Override the max number of HW submissions. The default is 2. 480 */ 481 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 482 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 483 484 /** 485 * DOC: ppfeaturemask (hexint) 486 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 487 * The default is the current set of stable power features. 488 */ 489 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 490 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 491 492 /** 493 * DOC: forcelongtraining (uint) 494 * Force long memory training in resume. 495 * The default is zero, indicates short training in resume. 496 */ 497 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 498 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 499 500 /** 501 * DOC: pcie_gen_cap (uint) 502 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 503 * The default is 0 (automatic for each asic). 504 */ 505 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 506 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 507 508 /** 509 * DOC: pcie_lane_cap (uint) 510 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 511 * The default is 0 (automatic for each asic). 512 */ 513 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 514 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 515 516 /** 517 * DOC: cg_mask (ullong) 518 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 519 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 520 */ 521 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 522 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 523 524 /** 525 * DOC: pg_mask (uint) 526 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 527 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 528 */ 529 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 530 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 531 532 /** 533 * DOC: sdma_phase_quantum (uint) 534 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 535 */ 536 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 537 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 538 539 /** 540 * DOC: disable_cu (charp) 541 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 542 */ 543 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 544 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 545 546 /** 547 * DOC: virtual_display (charp) 548 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 549 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 550 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 551 * device at 26:00.0. The default is NULL. 552 */ 553 MODULE_PARM_DESC(virtual_display, 554 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 555 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 556 557 /** 558 * DOC: lbpw (int) 559 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 560 */ 561 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 562 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 563 564 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 565 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 566 567 /** 568 * DOC: gpu_recovery (int) 569 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 570 */ 571 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 572 module_param_named_unsafe(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 573 574 /** 575 * DOC: emu_mode (int) 576 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 577 */ 578 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 579 module_param_named_unsafe(emu_mode, amdgpu_emu_mode, int, 0444); 580 581 /** 582 * DOC: ras_enable (int) 583 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 584 */ 585 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 586 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 587 588 /** 589 * DOC: ras_mask (uint) 590 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 591 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 592 */ 593 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 594 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 595 596 /** 597 * DOC: timeout_fatal_disable (bool) 598 * Disable Watchdog timeout fatal error event 599 */ 600 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 601 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 602 603 /** 604 * DOC: timeout_period (uint) 605 * Modify the watchdog timeout max_cycles as (1 << period) 606 */ 607 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 608 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 609 610 /** 611 * DOC: si_support (int) 612 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 613 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 614 * otherwise using amdgpu driver. 615 */ 616 #ifdef CONFIG_DRM_AMDGPU_SI 617 618 #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) 619 int amdgpu_si_support; 620 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 621 #else 622 int amdgpu_si_support = 1; 623 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 624 #endif 625 626 module_param_named(si_support, amdgpu_si_support, int, 0444); 627 #endif 628 629 /** 630 * DOC: cik_support (int) 631 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 632 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 633 * otherwise using amdgpu driver. 634 */ 635 #ifdef CONFIG_DRM_AMDGPU_CIK 636 637 #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) 638 int amdgpu_cik_support; 639 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 640 #else 641 int amdgpu_cik_support = 1; 642 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 643 #endif 644 645 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 646 #endif 647 648 /** 649 * DOC: smu_memory_pool_size (uint) 650 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 651 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 652 */ 653 MODULE_PARM_DESC(smu_memory_pool_size, 654 "reserve gtt for smu debug usage, 0 = disable,0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 655 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 656 657 /** 658 * DOC: async_gfx_ring (int) 659 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 660 */ 661 MODULE_PARM_DESC(async_gfx_ring, 662 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 663 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 664 665 /** 666 * DOC: mcbp (int) 667 * It is used to enable mid command buffer preemption. (0 = disabled, 1 = enabled, -1 auto (default)) 668 */ 669 MODULE_PARM_DESC(mcbp, 670 "Enable Mid-command buffer preemption (0 = disabled, 1 = enabled), -1 = auto (default)"); 671 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 672 673 /** 674 * DOC: discovery (int) 675 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 676 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 677 */ 678 MODULE_PARM_DESC(discovery, 679 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 680 module_param_named(discovery, amdgpu_discovery, int, 0444); 681 682 /** 683 * DOC: mes (int) 684 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 685 * (0 = disabled (default), 1 = enabled) 686 */ 687 MODULE_PARM_DESC(mes, 688 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 689 module_param_named(mes, amdgpu_mes, int, 0444); 690 691 /** 692 * DOC: mes_log_enable (int) 693 * Enable Micro Engine Scheduler log. This is used to enable/disable MES internal log. 694 * (0 = disabled (default), 1 = enabled) 695 */ 696 MODULE_PARM_DESC(mes_log_enable, 697 "Enable Micro Engine Scheduler log (0 = disabled (default), 1 = enabled)"); 698 module_param_named(mes_log_enable, amdgpu_mes_log_enable, int, 0444); 699 700 /** 701 * DOC: mes_kiq (int) 702 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq. 703 * (0 = disabled (default), 1 = enabled) 704 */ 705 MODULE_PARM_DESC(mes_kiq, 706 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)"); 707 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444); 708 709 /** 710 * DOC: uni_mes (int) 711 * Enable Unified Micro Engine Scheduler. This is a new engine pipe for unified scheduler. 712 * (0 = disabled (default), 1 = enabled) 713 */ 714 MODULE_PARM_DESC(uni_mes, 715 "Enable Unified Micro Engine Scheduler (0 = disabled, 1 = enabled(default)"); 716 module_param_named(uni_mes, amdgpu_uni_mes, int, 0444); 717 718 /** 719 * DOC: noretry (int) 720 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 721 * do not support per-process XNACK this also disables retry page faults. 722 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 723 */ 724 MODULE_PARM_DESC(noretry, 725 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 726 module_param_named(noretry, amdgpu_noretry, int, 0644); 727 728 /** 729 * DOC: force_asic_type (int) 730 * A non negative value used to specify the asic type for all supported GPUs. 731 */ 732 MODULE_PARM_DESC(force_asic_type, 733 "A non negative value used to specify the asic type for all supported GPUs"); 734 module_param_named_unsafe(force_asic_type, amdgpu_force_asic_type, int, 0444); 735 736 /** 737 * DOC: use_xgmi_p2p (int) 738 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 739 */ 740 MODULE_PARM_DESC(use_xgmi_p2p, 741 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 742 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 743 744 745 #ifdef CONFIG_HSA_AMD 746 /** 747 * DOC: sched_policy (int) 748 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 749 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 750 * assigns queues to HQDs. 751 */ 752 int sched_policy = KFD_SCHED_POLICY_HWS; 753 module_param_unsafe(sched_policy, int, 0444); 754 MODULE_PARM_DESC(sched_policy, 755 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 756 757 /** 758 * DOC: hws_max_conc_proc (int) 759 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 760 * number of VMIDs assigned to the HWS, which is also the default. 761 */ 762 int hws_max_conc_proc = -1; 763 module_param(hws_max_conc_proc, int, 0444); 764 MODULE_PARM_DESC(hws_max_conc_proc, 765 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 766 767 /** 768 * DOC: cwsr_enable (int) 769 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 770 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 771 * disables it. 772 */ 773 int cwsr_enable = 1; 774 module_param(cwsr_enable, int, 0444); 775 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 776 777 /** 778 * DOC: max_num_of_queues_per_device (int) 779 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 780 * is 4096. 781 */ 782 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 783 module_param(max_num_of_queues_per_device, int, 0444); 784 MODULE_PARM_DESC(max_num_of_queues_per_device, 785 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 786 787 /** 788 * DOC: send_sigterm (int) 789 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 790 * but just print errors on dmesg. Setting 1 enables sending sigterm. 791 */ 792 int send_sigterm; 793 module_param(send_sigterm, int, 0444); 794 MODULE_PARM_DESC(send_sigterm, 795 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 796 797 /** 798 * DOC: halt_if_hws_hang (int) 799 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 800 * Setting 1 enables halt on hang. 801 */ 802 int halt_if_hws_hang; 803 module_param_unsafe(halt_if_hws_hang, int, 0644); 804 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 805 806 /** 807 * DOC: hws_gws_support(bool) 808 * Assume that HWS supports GWS barriers regardless of what firmware version 809 * check says. Default value: false (rely on MEC2 firmware version check). 810 */ 811 bool hws_gws_support; 812 module_param_unsafe(hws_gws_support, bool, 0444); 813 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 814 815 /** 816 * DOC: queue_preemption_timeout_ms (int) 817 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 818 */ 819 int queue_preemption_timeout_ms = 9000; 820 module_param(queue_preemption_timeout_ms, int, 0644); 821 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 822 823 /** 824 * DOC: debug_evictions(bool) 825 * Enable extra debug messages to help determine the cause of evictions 826 */ 827 bool debug_evictions; 828 module_param(debug_evictions, bool, 0644); 829 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 830 831 /** 832 * DOC: no_system_mem_limit(bool) 833 * Disable system memory limit, to support multiple process shared memory 834 */ 835 bool no_system_mem_limit; 836 module_param(no_system_mem_limit, bool, 0644); 837 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 838 839 /** 840 * DOC: no_queue_eviction_on_vm_fault (int) 841 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 842 */ 843 int amdgpu_no_queue_eviction_on_vm_fault; 844 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 845 module_param_named_unsafe(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 846 #endif 847 848 /** 849 * DOC: mtype_local (int) 850 */ 851 int amdgpu_mtype_local; 852 MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (0 = MTYPE_RW (default), 1 = MTYPE_NC, 2 = MTYPE_CC)"); 853 module_param_named_unsafe(mtype_local, amdgpu_mtype_local, int, 0444); 854 855 /** 856 * DOC: pcie_p2p (bool) 857 * Enable PCIe P2P (requires large-BAR). Default value: true (on) 858 */ 859 #ifdef CONFIG_HSA_AMD_P2P 860 bool pcie_p2p = true; 861 module_param(pcie_p2p, bool, 0444); 862 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); 863 #endif 864 865 /** 866 * DOC: dcfeaturemask (uint) 867 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 868 * The default is the current set of stable display features. 869 */ 870 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 871 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 872 873 /** 874 * DOC: dcdebugmask (uint) 875 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 876 */ 877 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 878 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 879 880 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)"); 881 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444); 882 883 /** 884 * DOC: abmlevel (uint) 885 * Override the default ABM (Adaptive Backlight Management) level used for DC 886 * enabled hardware. Requires DMCU to be supported and loaded. 887 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 888 * default. Values 1-4 control the maximum allowable brightness reduction via 889 * the ABM algorithm, with 1 being the least reduction and 4 being the most 890 * reduction. 891 * 892 * Defaults to -1, or auto. Userspace can only override this level after 893 * boot if it's set to auto. 894 */ 895 int amdgpu_dm_abm_level = -1; 896 MODULE_PARM_DESC(abmlevel, 897 "ABM level (0 = off, 1-4 = backlight reduction level, -1 auto (default))"); 898 module_param_named(abmlevel, amdgpu_dm_abm_level, int, 0444); 899 900 int amdgpu_backlight = -1; 901 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 902 module_param_named(backlight, amdgpu_backlight, bint, 0444); 903 904 /** 905 * DOC: damageclips (int) 906 * Enable or disable damage clips support. If damage clips support is disabled, 907 * we will force full frame updates, irrespective of what user space sends to 908 * us. 909 * 910 * Defaults to -1 (where it is enabled unless a PSR-SU display is detected). 911 */ 912 MODULE_PARM_DESC(damageclips, 913 "Damage clips support (0 = disable, 1 = enable, -1 auto (default))"); 914 module_param_named(damageclips, amdgpu_damage_clips, int, 0444); 915 916 /** 917 * DOC: tmz (int) 918 * Trusted Memory Zone (TMZ) is a method to protect data being written 919 * to or read from memory. 920 * 921 * The default value: 0 (off). TODO: change to auto till it is completed. 922 */ 923 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 924 module_param_named(tmz, amdgpu_tmz, int, 0444); 925 926 /** 927 * DOC: freesync_video (uint) 928 * Enable the optimization to adjust front porch timing to achieve seamless 929 * mode change experience when setting a freesync supported mode for which full 930 * modeset is not needed. 931 * 932 * The Display Core will add a set of modes derived from the base FreeSync 933 * video mode into the corresponding connector's mode list based on commonly 934 * used refresh rates and VRR range of the connected display, when users enable 935 * this feature. From the userspace perspective, they can see a seamless mode 936 * change experience when the change between different refresh rates under the 937 * same resolution. Additionally, userspace applications such as Video playback 938 * can read this modeset list and change the refresh rate based on the video 939 * frame rate. Finally, the userspace can also derive an appropriate mode for a 940 * particular refresh rate based on the FreeSync Mode and add it to the 941 * connector's mode list. 942 * 943 * Note: This is an experimental feature. 944 * 945 * The default value: 0 (off). 946 */ 947 MODULE_PARM_DESC( 948 freesync_video, 949 "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)"); 950 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); 951 952 /** 953 * DOC: reset_method (int) 954 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 955 */ 956 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 957 module_param_named_unsafe(reset_method, amdgpu_reset_method, int, 0644); 958 959 /** 960 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 961 * threshold value of faulty pages detected by RAS ECC, which may 962 * result in the GPU entering bad status when the number of total 963 * faulty pages by ECC exceeds the threshold value. 964 */ 965 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = driver sets threshold)"); 966 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 967 968 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 969 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 970 971 /** 972 * DOC: vcnfw_log (int) 973 * Enable vcnfw log output for debugging, the default is disabled. 974 */ 975 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 976 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 977 978 /** 979 * DOC: sg_display (int) 980 * Disable S/G (scatter/gather) display (i.e., display from system memory). 981 * This option is only relevant on APUs. Set this option to 0 to disable 982 * S/G display if you experience flickering or other issues under memory 983 * pressure and report the issue. 984 */ 985 MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)"); 986 module_param_named(sg_display, amdgpu_sg_display, int, 0444); 987 988 /** 989 * DOC: umsch_mm (int) 990 * Enable Multi Media User Mode Scheduler. This is a HW scheduling engine for VCN and VPE. 991 * (0 = disabled (default), 1 = enabled) 992 */ 993 MODULE_PARM_DESC(umsch_mm, 994 "Enable Multi Media User Mode Scheduler (0 = disabled (default), 1 = enabled)"); 995 module_param_named(umsch_mm, amdgpu_umsch_mm, int, 0444); 996 997 /** 998 * DOC: umsch_mm_fwlog (int) 999 * Enable umschfw log output for debugging, the default is disabled. 1000 */ 1001 MODULE_PARM_DESC(umsch_mm_fwlog, "Enable umschfw log(0 = disable (default value), 1 = enable)"); 1002 module_param_named(umsch_mm_fwlog, amdgpu_umsch_mm_fwlog, int, 0444); 1003 1004 /** 1005 * DOC: smu_pptable_id (int) 1006 * Used to override pptable id. id = 0 use VBIOS pptable. 1007 * id > 0 use the soft pptable with specicfied id. 1008 */ 1009 MODULE_PARM_DESC(smu_pptable_id, 1010 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 1011 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 1012 1013 /** 1014 * DOC: partition_mode (int) 1015 * Used to override the default SPX mode. 1016 */ 1017 MODULE_PARM_DESC( 1018 user_partt_mode, 1019 "specify partition mode to be used (-2 = AMDGPU_AUTO_COMPUTE_PARTITION_MODE(default value) \ 1020 0 = AMDGPU_SPX_PARTITION_MODE, \ 1021 1 = AMDGPU_DPX_PARTITION_MODE, \ 1022 2 = AMDGPU_TPX_PARTITION_MODE, \ 1023 3 = AMDGPU_QPX_PARTITION_MODE, \ 1024 4 = AMDGPU_CPX_PARTITION_MODE)"); 1025 module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint, 0444); 1026 1027 1028 /** 1029 * DOC: enforce_isolation (bool) 1030 * enforce process isolation between graphics and compute via using the same reserved vmid. 1031 */ 1032 module_param(enforce_isolation, bool, 0444); 1033 MODULE_PARM_DESC(enforce_isolation, "enforce process isolation between graphics and compute . enforce_isolation = on"); 1034 1035 /** 1036 * DOC: seamless (int) 1037 * Seamless boot will keep the image on the screen during the boot process. 1038 */ 1039 MODULE_PARM_DESC(seamless, "Seamless boot (-1 = auto (default), 0 = disable, 1 = enable)"); 1040 module_param_named(seamless, amdgpu_seamless, int, 0444); 1041 1042 /** 1043 * DOC: debug_mask (uint) 1044 * Debug options for amdgpu, work as a binary mask with the following options: 1045 * 1046 * - 0x1: Debug VM handling 1047 * - 0x2: Enable simulating large-bar capability on non-large bar system. This 1048 * limits the VRAM size reported to ROCm applications to the visible 1049 * size, usually 256MB. 1050 * - 0x4: Disable GPU soft recovery, always do a full reset 1051 */ 1052 MODULE_PARM_DESC(debug_mask, "debug options for amdgpu, disabled by default"); 1053 module_param_named_unsafe(debug_mask, amdgpu_debug_mask, uint, 0444); 1054 1055 /** 1056 * DOC: agp (int) 1057 * Enable the AGP aperture. This provides an aperture in the GPU's internal 1058 * address space for direct access to system memory. Note that these accesses 1059 * are non-snooped, so they are only used for access to uncached memory. 1060 */ 1061 MODULE_PARM_DESC(agp, "AGP (-1 = auto (default), 0 = disable, 1 = enable)"); 1062 module_param_named(agp, amdgpu_agp, int, 0444); 1063 1064 /** 1065 * DOC: wbrf (int) 1066 * Enable Wifi RFI interference mitigation feature. 1067 * Due to electrical and mechanical constraints there may be likely interference of 1068 * relatively high-powered harmonics of the (G-)DDR memory clocks with local radio 1069 * module frequency bands used by Wifi 6/6e/7. To mitigate the possible RFI interference, 1070 * with this feature enabled, PMFW will use either “shadowed P-State” or “P-State” based 1071 * on active list of frequencies in-use (to be avoided) as part of initial setting or 1072 * P-state transition. However, there may be potential performance impact with this 1073 * feature enabled. 1074 * (0 = disabled, 1 = enabled, -1 = auto (default setting, will be enabled if supported)) 1075 */ 1076 MODULE_PARM_DESC(wbrf, 1077 "Enable Wifi RFI interference mitigation (0 = disabled, 1 = enabled, -1 = auto(default)"); 1078 module_param_named(wbrf, amdgpu_wbrf, int, 0444); 1079 1080 /* These devices are not supported by amdgpu. 1081 * They are supported by the mach64, r128, radeon drivers 1082 */ 1083 static const u16 amdgpu_unsupported_pciidlist[] = { 1084 /* mach64 */ 1085 0x4354, 1086 0x4358, 1087 0x4554, 1088 0x4742, 1089 0x4744, 1090 0x4749, 1091 0x474C, 1092 0x474D, 1093 0x474E, 1094 0x474F, 1095 0x4750, 1096 0x4751, 1097 0x4752, 1098 0x4753, 1099 0x4754, 1100 0x4755, 1101 0x4756, 1102 0x4757, 1103 0x4758, 1104 0x4759, 1105 0x475A, 1106 0x4C42, 1107 0x4C44, 1108 0x4C47, 1109 0x4C49, 1110 0x4C4D, 1111 0x4C4E, 1112 0x4C50, 1113 0x4C51, 1114 0x4C52, 1115 0x4C53, 1116 0x5654, 1117 0x5655, 1118 0x5656, 1119 /* r128 */ 1120 0x4c45, 1121 0x4c46, 1122 0x4d46, 1123 0x4d4c, 1124 0x5041, 1125 0x5042, 1126 0x5043, 1127 0x5044, 1128 0x5045, 1129 0x5046, 1130 0x5047, 1131 0x5048, 1132 0x5049, 1133 0x504A, 1134 0x504B, 1135 0x504C, 1136 0x504D, 1137 0x504E, 1138 0x504F, 1139 0x5050, 1140 0x5051, 1141 0x5052, 1142 0x5053, 1143 0x5054, 1144 0x5055, 1145 0x5056, 1146 0x5057, 1147 0x5058, 1148 0x5245, 1149 0x5246, 1150 0x5247, 1151 0x524b, 1152 0x524c, 1153 0x534d, 1154 0x5446, 1155 0x544C, 1156 0x5452, 1157 /* radeon */ 1158 0x3150, 1159 0x3151, 1160 0x3152, 1161 0x3154, 1162 0x3155, 1163 0x3E50, 1164 0x3E54, 1165 0x4136, 1166 0x4137, 1167 0x4144, 1168 0x4145, 1169 0x4146, 1170 0x4147, 1171 0x4148, 1172 0x4149, 1173 0x414A, 1174 0x414B, 1175 0x4150, 1176 0x4151, 1177 0x4152, 1178 0x4153, 1179 0x4154, 1180 0x4155, 1181 0x4156, 1182 0x4237, 1183 0x4242, 1184 0x4336, 1185 0x4337, 1186 0x4437, 1187 0x4966, 1188 0x4967, 1189 0x4A48, 1190 0x4A49, 1191 0x4A4A, 1192 0x4A4B, 1193 0x4A4C, 1194 0x4A4D, 1195 0x4A4E, 1196 0x4A4F, 1197 0x4A50, 1198 0x4A54, 1199 0x4B48, 1200 0x4B49, 1201 0x4B4A, 1202 0x4B4B, 1203 0x4B4C, 1204 0x4C57, 1205 0x4C58, 1206 0x4C59, 1207 0x4C5A, 1208 0x4C64, 1209 0x4C66, 1210 0x4C67, 1211 0x4E44, 1212 0x4E45, 1213 0x4E46, 1214 0x4E47, 1215 0x4E48, 1216 0x4E49, 1217 0x4E4A, 1218 0x4E4B, 1219 0x4E50, 1220 0x4E51, 1221 0x4E52, 1222 0x4E53, 1223 0x4E54, 1224 0x4E56, 1225 0x5144, 1226 0x5145, 1227 0x5146, 1228 0x5147, 1229 0x5148, 1230 0x514C, 1231 0x514D, 1232 0x5157, 1233 0x5158, 1234 0x5159, 1235 0x515A, 1236 0x515E, 1237 0x5460, 1238 0x5462, 1239 0x5464, 1240 0x5548, 1241 0x5549, 1242 0x554A, 1243 0x554B, 1244 0x554C, 1245 0x554D, 1246 0x554E, 1247 0x554F, 1248 0x5550, 1249 0x5551, 1250 0x5552, 1251 0x5554, 1252 0x564A, 1253 0x564B, 1254 0x564F, 1255 0x5652, 1256 0x5653, 1257 0x5657, 1258 0x5834, 1259 0x5835, 1260 0x5954, 1261 0x5955, 1262 0x5974, 1263 0x5975, 1264 0x5960, 1265 0x5961, 1266 0x5962, 1267 0x5964, 1268 0x5965, 1269 0x5969, 1270 0x5a41, 1271 0x5a42, 1272 0x5a61, 1273 0x5a62, 1274 0x5b60, 1275 0x5b62, 1276 0x5b63, 1277 0x5b64, 1278 0x5b65, 1279 0x5c61, 1280 0x5c63, 1281 0x5d48, 1282 0x5d49, 1283 0x5d4a, 1284 0x5d4c, 1285 0x5d4d, 1286 0x5d4e, 1287 0x5d4f, 1288 0x5d50, 1289 0x5d52, 1290 0x5d57, 1291 0x5e48, 1292 0x5e4a, 1293 0x5e4b, 1294 0x5e4c, 1295 0x5e4d, 1296 0x5e4f, 1297 0x6700, 1298 0x6701, 1299 0x6702, 1300 0x6703, 1301 0x6704, 1302 0x6705, 1303 0x6706, 1304 0x6707, 1305 0x6708, 1306 0x6709, 1307 0x6718, 1308 0x6719, 1309 0x671c, 1310 0x671d, 1311 0x671f, 1312 0x6720, 1313 0x6721, 1314 0x6722, 1315 0x6723, 1316 0x6724, 1317 0x6725, 1318 0x6726, 1319 0x6727, 1320 0x6728, 1321 0x6729, 1322 0x6738, 1323 0x6739, 1324 0x673e, 1325 0x6740, 1326 0x6741, 1327 0x6742, 1328 0x6743, 1329 0x6744, 1330 0x6745, 1331 0x6746, 1332 0x6747, 1333 0x6748, 1334 0x6749, 1335 0x674A, 1336 0x6750, 1337 0x6751, 1338 0x6758, 1339 0x6759, 1340 0x675B, 1341 0x675D, 1342 0x675F, 1343 0x6760, 1344 0x6761, 1345 0x6762, 1346 0x6763, 1347 0x6764, 1348 0x6765, 1349 0x6766, 1350 0x6767, 1351 0x6768, 1352 0x6770, 1353 0x6771, 1354 0x6772, 1355 0x6778, 1356 0x6779, 1357 0x677B, 1358 0x6840, 1359 0x6841, 1360 0x6842, 1361 0x6843, 1362 0x6849, 1363 0x684C, 1364 0x6850, 1365 0x6858, 1366 0x6859, 1367 0x6880, 1368 0x6888, 1369 0x6889, 1370 0x688A, 1371 0x688C, 1372 0x688D, 1373 0x6898, 1374 0x6899, 1375 0x689b, 1376 0x689c, 1377 0x689d, 1378 0x689e, 1379 0x68a0, 1380 0x68a1, 1381 0x68a8, 1382 0x68a9, 1383 0x68b0, 1384 0x68b8, 1385 0x68b9, 1386 0x68ba, 1387 0x68be, 1388 0x68bf, 1389 0x68c0, 1390 0x68c1, 1391 0x68c7, 1392 0x68c8, 1393 0x68c9, 1394 0x68d8, 1395 0x68d9, 1396 0x68da, 1397 0x68de, 1398 0x68e0, 1399 0x68e1, 1400 0x68e4, 1401 0x68e5, 1402 0x68e8, 1403 0x68e9, 1404 0x68f1, 1405 0x68f2, 1406 0x68f8, 1407 0x68f9, 1408 0x68fa, 1409 0x68fe, 1410 0x7100, 1411 0x7101, 1412 0x7102, 1413 0x7103, 1414 0x7104, 1415 0x7105, 1416 0x7106, 1417 0x7108, 1418 0x7109, 1419 0x710A, 1420 0x710B, 1421 0x710C, 1422 0x710E, 1423 0x710F, 1424 0x7140, 1425 0x7141, 1426 0x7142, 1427 0x7143, 1428 0x7144, 1429 0x7145, 1430 0x7146, 1431 0x7147, 1432 0x7149, 1433 0x714A, 1434 0x714B, 1435 0x714C, 1436 0x714D, 1437 0x714E, 1438 0x714F, 1439 0x7151, 1440 0x7152, 1441 0x7153, 1442 0x715E, 1443 0x715F, 1444 0x7180, 1445 0x7181, 1446 0x7183, 1447 0x7186, 1448 0x7187, 1449 0x7188, 1450 0x718A, 1451 0x718B, 1452 0x718C, 1453 0x718D, 1454 0x718F, 1455 0x7193, 1456 0x7196, 1457 0x719B, 1458 0x719F, 1459 0x71C0, 1460 0x71C1, 1461 0x71C2, 1462 0x71C3, 1463 0x71C4, 1464 0x71C5, 1465 0x71C6, 1466 0x71C7, 1467 0x71CD, 1468 0x71CE, 1469 0x71D2, 1470 0x71D4, 1471 0x71D5, 1472 0x71D6, 1473 0x71DA, 1474 0x71DE, 1475 0x7200, 1476 0x7210, 1477 0x7211, 1478 0x7240, 1479 0x7243, 1480 0x7244, 1481 0x7245, 1482 0x7246, 1483 0x7247, 1484 0x7248, 1485 0x7249, 1486 0x724A, 1487 0x724B, 1488 0x724C, 1489 0x724D, 1490 0x724E, 1491 0x724F, 1492 0x7280, 1493 0x7281, 1494 0x7283, 1495 0x7284, 1496 0x7287, 1497 0x7288, 1498 0x7289, 1499 0x728B, 1500 0x728C, 1501 0x7290, 1502 0x7291, 1503 0x7293, 1504 0x7297, 1505 0x7834, 1506 0x7835, 1507 0x791e, 1508 0x791f, 1509 0x793f, 1510 0x7941, 1511 0x7942, 1512 0x796c, 1513 0x796d, 1514 0x796e, 1515 0x796f, 1516 0x9400, 1517 0x9401, 1518 0x9402, 1519 0x9403, 1520 0x9405, 1521 0x940A, 1522 0x940B, 1523 0x940F, 1524 0x94A0, 1525 0x94A1, 1526 0x94A3, 1527 0x94B1, 1528 0x94B3, 1529 0x94B4, 1530 0x94B5, 1531 0x94B9, 1532 0x9440, 1533 0x9441, 1534 0x9442, 1535 0x9443, 1536 0x9444, 1537 0x9446, 1538 0x944A, 1539 0x944B, 1540 0x944C, 1541 0x944E, 1542 0x9450, 1543 0x9452, 1544 0x9456, 1545 0x945A, 1546 0x945B, 1547 0x945E, 1548 0x9460, 1549 0x9462, 1550 0x946A, 1551 0x946B, 1552 0x947A, 1553 0x947B, 1554 0x9480, 1555 0x9487, 1556 0x9488, 1557 0x9489, 1558 0x948A, 1559 0x948F, 1560 0x9490, 1561 0x9491, 1562 0x9495, 1563 0x9498, 1564 0x949C, 1565 0x949E, 1566 0x949F, 1567 0x94C0, 1568 0x94C1, 1569 0x94C3, 1570 0x94C4, 1571 0x94C5, 1572 0x94C6, 1573 0x94C7, 1574 0x94C8, 1575 0x94C9, 1576 0x94CB, 1577 0x94CC, 1578 0x94CD, 1579 0x9500, 1580 0x9501, 1581 0x9504, 1582 0x9505, 1583 0x9506, 1584 0x9507, 1585 0x9508, 1586 0x9509, 1587 0x950F, 1588 0x9511, 1589 0x9515, 1590 0x9517, 1591 0x9519, 1592 0x9540, 1593 0x9541, 1594 0x9542, 1595 0x954E, 1596 0x954F, 1597 0x9552, 1598 0x9553, 1599 0x9555, 1600 0x9557, 1601 0x955f, 1602 0x9580, 1603 0x9581, 1604 0x9583, 1605 0x9586, 1606 0x9587, 1607 0x9588, 1608 0x9589, 1609 0x958A, 1610 0x958B, 1611 0x958C, 1612 0x958D, 1613 0x958E, 1614 0x958F, 1615 0x9590, 1616 0x9591, 1617 0x9593, 1618 0x9595, 1619 0x9596, 1620 0x9597, 1621 0x9598, 1622 0x9599, 1623 0x959B, 1624 0x95C0, 1625 0x95C2, 1626 0x95C4, 1627 0x95C5, 1628 0x95C6, 1629 0x95C7, 1630 0x95C9, 1631 0x95CC, 1632 0x95CD, 1633 0x95CE, 1634 0x95CF, 1635 0x9610, 1636 0x9611, 1637 0x9612, 1638 0x9613, 1639 0x9614, 1640 0x9615, 1641 0x9616, 1642 0x9640, 1643 0x9641, 1644 0x9642, 1645 0x9643, 1646 0x9644, 1647 0x9645, 1648 0x9647, 1649 0x9648, 1650 0x9649, 1651 0x964a, 1652 0x964b, 1653 0x964c, 1654 0x964e, 1655 0x964f, 1656 0x9710, 1657 0x9711, 1658 0x9712, 1659 0x9713, 1660 0x9714, 1661 0x9715, 1662 0x9802, 1663 0x9803, 1664 0x9804, 1665 0x9805, 1666 0x9806, 1667 0x9807, 1668 0x9808, 1669 0x9809, 1670 0x980A, 1671 0x9900, 1672 0x9901, 1673 0x9903, 1674 0x9904, 1675 0x9905, 1676 0x9906, 1677 0x9907, 1678 0x9908, 1679 0x9909, 1680 0x990A, 1681 0x990B, 1682 0x990C, 1683 0x990D, 1684 0x990E, 1685 0x990F, 1686 0x9910, 1687 0x9913, 1688 0x9917, 1689 0x9918, 1690 0x9919, 1691 0x9990, 1692 0x9991, 1693 0x9992, 1694 0x9993, 1695 0x9994, 1696 0x9995, 1697 0x9996, 1698 0x9997, 1699 0x9998, 1700 0x9999, 1701 0x999A, 1702 0x999B, 1703 0x999C, 1704 0x999D, 1705 0x99A0, 1706 0x99A2, 1707 0x99A4, 1708 /* radeon secondary ids */ 1709 0x3171, 1710 0x3e70, 1711 0x4164, 1712 0x4165, 1713 0x4166, 1714 0x4168, 1715 0x4170, 1716 0x4171, 1717 0x4172, 1718 0x4173, 1719 0x496e, 1720 0x4a69, 1721 0x4a6a, 1722 0x4a6b, 1723 0x4a70, 1724 0x4a74, 1725 0x4b69, 1726 0x4b6b, 1727 0x4b6c, 1728 0x4c6e, 1729 0x4e64, 1730 0x4e65, 1731 0x4e66, 1732 0x4e67, 1733 0x4e68, 1734 0x4e69, 1735 0x4e6a, 1736 0x4e71, 1737 0x4f73, 1738 0x5569, 1739 0x556b, 1740 0x556d, 1741 0x556f, 1742 0x5571, 1743 0x5854, 1744 0x5874, 1745 0x5940, 1746 0x5941, 1747 0x5b70, 1748 0x5b72, 1749 0x5b73, 1750 0x5b74, 1751 0x5b75, 1752 0x5d44, 1753 0x5d45, 1754 0x5d6d, 1755 0x5d6f, 1756 0x5d72, 1757 0x5d77, 1758 0x5e6b, 1759 0x5e6d, 1760 0x7120, 1761 0x7124, 1762 0x7129, 1763 0x712e, 1764 0x712f, 1765 0x7162, 1766 0x7163, 1767 0x7166, 1768 0x7167, 1769 0x7172, 1770 0x7173, 1771 0x71a0, 1772 0x71a1, 1773 0x71a3, 1774 0x71a7, 1775 0x71bb, 1776 0x71e0, 1777 0x71e1, 1778 0x71e2, 1779 0x71e6, 1780 0x71e7, 1781 0x71f2, 1782 0x7269, 1783 0x726b, 1784 0x726e, 1785 0x72a0, 1786 0x72a8, 1787 0x72b1, 1788 0x72b3, 1789 0x793f, 1790 }; 1791 1792 static const struct pci_device_id pciidlist[] = { 1793 #ifdef CONFIG_DRM_AMDGPU_SI 1794 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1795 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1796 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1797 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1798 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1799 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1800 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1801 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1802 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1803 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1804 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1805 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1806 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1807 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1808 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1809 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1810 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1811 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1812 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1813 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1814 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1815 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1816 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1817 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1818 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1819 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1820 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1821 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1822 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1823 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1824 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1825 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1826 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1827 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1828 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1829 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1830 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1831 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1832 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1833 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1834 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1835 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1836 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1837 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1838 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1839 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1840 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1841 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1842 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1843 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1844 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1845 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1846 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1847 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1848 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1849 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1850 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1851 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1852 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1853 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1854 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1855 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1856 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1857 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1858 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1859 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1860 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1861 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1862 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1863 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1864 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1865 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1866 #endif 1867 #ifdef CONFIG_DRM_AMDGPU_CIK 1868 /* Kaveri */ 1869 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1870 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1871 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1872 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1873 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1874 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1875 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1876 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1877 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1878 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1879 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1880 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1881 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1882 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1883 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1884 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1885 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1886 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1887 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1888 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1889 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1890 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1891 /* Bonaire */ 1892 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1893 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1894 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1895 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1896 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1897 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1898 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1899 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1900 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1901 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1902 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1903 /* Hawaii */ 1904 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1905 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1906 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1907 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1908 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1909 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1910 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1911 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1912 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1913 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1914 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1915 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1916 /* Kabini */ 1917 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1918 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1919 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1920 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1921 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1922 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1923 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1924 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1925 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1926 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1927 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1928 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1929 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1930 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1931 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1932 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1933 /* mullins */ 1934 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1935 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1936 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1937 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1938 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1939 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1940 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1941 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1942 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1943 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1944 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1945 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1946 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1947 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1948 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1949 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1950 #endif 1951 /* topaz */ 1952 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1953 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1954 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1955 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1956 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1957 /* tonga */ 1958 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1959 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1960 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1961 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1962 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1963 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1964 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1965 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1966 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1967 /* fiji */ 1968 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1969 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1970 /* carrizo */ 1971 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1972 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1973 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1974 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1975 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1976 /* stoney */ 1977 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1978 /* Polaris11 */ 1979 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1980 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1981 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1982 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1983 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1984 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1985 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1986 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1987 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1988 /* Polaris10 */ 1989 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1990 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1991 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1992 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1993 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1994 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1995 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1996 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1997 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1998 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1999 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2000 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2001 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2002 /* Polaris12 */ 2003 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2004 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2005 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2006 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2007 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2008 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2009 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2010 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2011 /* VEGAM */ 2012 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 2013 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 2014 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 2015 /* Vega 10 */ 2016 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2017 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2018 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2019 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2020 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2021 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2022 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2023 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2024 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2025 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2026 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2027 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2028 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2029 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2030 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2031 /* Vega 12 */ 2032 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2033 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2034 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2035 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2036 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2037 /* Vega 20 */ 2038 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2039 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2040 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2041 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2042 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2043 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2044 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2045 /* Raven */ 2046 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 2047 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 2048 /* Arcturus */ 2049 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2050 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2051 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2052 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2053 /* Navi10 */ 2054 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2055 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2056 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2057 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2058 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2059 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2060 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2061 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2062 /* Navi14 */ 2063 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2064 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2065 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2066 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2067 2068 /* Renoir */ 2069 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2070 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2071 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2072 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2073 2074 /* Navi12 */ 2075 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 2076 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 2077 2078 /* Sienna_Cichlid */ 2079 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2080 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2081 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2082 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2083 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2084 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2085 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2086 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2087 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2088 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2089 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2090 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2091 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2092 2093 /* Yellow Carp */ 2094 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 2095 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 2096 2097 /* Navy_Flounder */ 2098 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2099 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2100 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2101 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2102 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2103 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2104 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2105 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2106 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2107 2108 /* DIMGREY_CAVEFISH */ 2109 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2110 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2111 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2112 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2113 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2114 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2115 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2116 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2117 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2118 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2119 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2120 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2121 2122 /* Aldebaran */ 2123 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2124 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2125 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2126 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2127 2128 /* CYAN_SKILLFISH */ 2129 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2130 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2131 2132 /* BEIGE_GOBY */ 2133 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2134 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2135 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2136 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2137 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2138 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2139 2140 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2141 .class = PCI_CLASS_DISPLAY_VGA << 8, 2142 .class_mask = 0xffffff, 2143 .driver_data = CHIP_IP_DISCOVERY }, 2144 2145 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2146 .class = PCI_CLASS_DISPLAY_OTHER << 8, 2147 .class_mask = 0xffffff, 2148 .driver_data = CHIP_IP_DISCOVERY }, 2149 2150 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2151 .class = PCI_CLASS_ACCELERATOR_PROCESSING << 8, 2152 .class_mask = 0xffffff, 2153 .driver_data = CHIP_IP_DISCOVERY }, 2154 2155 {0, 0, 0} 2156 }; 2157 2158 MODULE_DEVICE_TABLE(pci, pciidlist); 2159 2160 static const struct amdgpu_asic_type_quirk asic_type_quirks[] = { 2161 /* differentiate between P10 and P11 asics with the same DID */ 2162 {0x67FF, 0xE3, CHIP_POLARIS10}, 2163 {0x67FF, 0xE7, CHIP_POLARIS10}, 2164 {0x67FF, 0xF3, CHIP_POLARIS10}, 2165 {0x67FF, 0xF7, CHIP_POLARIS10}, 2166 }; 2167 2168 static const struct drm_driver amdgpu_kms_driver; 2169 2170 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 2171 { 2172 struct pci_dev *p = NULL; 2173 int i; 2174 2175 /* 0 - GPU 2176 * 1 - audio 2177 * 2 - USB 2178 * 3 - UCSI 2179 */ 2180 for (i = 1; i < 4; i++) { 2181 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 2182 adev->pdev->bus->number, i); 2183 if (p) { 2184 pm_runtime_get_sync(&p->dev); 2185 pm_runtime_mark_last_busy(&p->dev); 2186 pm_runtime_put_autosuspend(&p->dev); 2187 pci_dev_put(p); 2188 } 2189 } 2190 } 2191 2192 static void amdgpu_init_debug_options(struct amdgpu_device *adev) 2193 { 2194 if (amdgpu_debug_mask & AMDGPU_DEBUG_VM) { 2195 pr_info("debug: VM handling debug enabled\n"); 2196 adev->debug_vm = true; 2197 } 2198 2199 if (amdgpu_debug_mask & AMDGPU_DEBUG_LARGEBAR) { 2200 pr_info("debug: enabled simulating large-bar capability on non-large bar system\n"); 2201 adev->debug_largebar = true; 2202 } 2203 2204 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY) { 2205 pr_info("debug: soft reset for GPU recovery disabled\n"); 2206 adev->debug_disable_soft_recovery = true; 2207 } 2208 2209 if (amdgpu_debug_mask & AMDGPU_DEBUG_USE_VRAM_FW_BUF) { 2210 pr_info("debug: place fw in vram for frontdoor loading\n"); 2211 adev->debug_use_vram_fw_buf = true; 2212 } 2213 2214 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_RAS_ACA) { 2215 pr_info("debug: enable RAS ACA\n"); 2216 adev->debug_enable_ras_aca = true; 2217 } 2218 2219 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_EXP_RESETS) { 2220 pr_info("debug: enable experimental reset features\n"); 2221 adev->debug_exp_resets = true; 2222 } 2223 } 2224 2225 static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long flags) 2226 { 2227 int i; 2228 2229 for (i = 0; i < ARRAY_SIZE(asic_type_quirks); i++) { 2230 if (pdev->device == asic_type_quirks[i].device && 2231 pdev->revision == asic_type_quirks[i].revision) { 2232 flags &= ~AMD_ASIC_MASK; 2233 flags |= asic_type_quirks[i].type; 2234 break; 2235 } 2236 } 2237 2238 return flags; 2239 } 2240 2241 static int amdgpu_pci_probe(struct pci_dev *pdev, 2242 const struct pci_device_id *ent) 2243 { 2244 struct drm_device *ddev; 2245 struct amdgpu_device *adev; 2246 unsigned long flags = ent->driver_data; 2247 int ret, retry = 0, i; 2248 bool supports_atomic = false; 2249 2250 /* skip devices which are owned by radeon */ 2251 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2252 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2253 return -ENODEV; 2254 } 2255 2256 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) 2257 amdgpu_aspm = 0; 2258 2259 if (amdgpu_virtual_display || 2260 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 2261 supports_atomic = true; 2262 2263 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2264 DRM_INFO("This hardware requires experimental hardware support.\n" 2265 "See modparam exp_hw_support\n"); 2266 return -ENODEV; 2267 } 2268 2269 flags = amdgpu_fix_asic_type(pdev, flags); 2270 2271 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2272 * however, SME requires an indirect IOMMU mapping because the encryption 2273 * bit is beyond the DMA mask of the chip. 2274 */ 2275 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2276 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2277 dev_info(&pdev->dev, 2278 "SME is not compatible with RAVEN\n"); 2279 return -ENOTSUPP; 2280 } 2281 2282 #ifdef CONFIG_DRM_AMDGPU_SI 2283 if (!amdgpu_si_support) { 2284 switch (flags & AMD_ASIC_MASK) { 2285 case CHIP_TAHITI: 2286 case CHIP_PITCAIRN: 2287 case CHIP_VERDE: 2288 case CHIP_OLAND: 2289 case CHIP_HAINAN: 2290 dev_info(&pdev->dev, 2291 "SI support provided by radeon.\n"); 2292 dev_info(&pdev->dev, 2293 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 2294 ); 2295 return -ENODEV; 2296 } 2297 } 2298 #endif 2299 #ifdef CONFIG_DRM_AMDGPU_CIK 2300 if (!amdgpu_cik_support) { 2301 switch (flags & AMD_ASIC_MASK) { 2302 case CHIP_KAVERI: 2303 case CHIP_BONAIRE: 2304 case CHIP_HAWAII: 2305 case CHIP_KABINI: 2306 case CHIP_MULLINS: 2307 dev_info(&pdev->dev, 2308 "CIK support provided by radeon.\n"); 2309 dev_info(&pdev->dev, 2310 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 2311 ); 2312 return -ENODEV; 2313 } 2314 } 2315 #endif 2316 2317 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2318 if (IS_ERR(adev)) 2319 return PTR_ERR(adev); 2320 2321 adev->dev = &pdev->dev; 2322 adev->pdev = pdev; 2323 ddev = adev_to_drm(adev); 2324 2325 if (!supports_atomic) 2326 ddev->driver_features &= ~DRIVER_ATOMIC; 2327 2328 ret = pci_enable_device(pdev); 2329 if (ret) 2330 return ret; 2331 2332 pci_set_drvdata(pdev, ddev); 2333 2334 amdgpu_init_debug_options(adev); 2335 2336 ret = amdgpu_driver_load_kms(adev, flags); 2337 if (ret) 2338 goto err_pci; 2339 2340 retry_init: 2341 ret = drm_dev_register(ddev, flags); 2342 if (ret == -EAGAIN && ++retry <= 3) { 2343 DRM_INFO("retry init %d\n", retry); 2344 /* Don't request EX mode too frequently which is attacking */ 2345 msleep(5000); 2346 goto retry_init; 2347 } else if (ret) { 2348 goto err_pci; 2349 } 2350 2351 ret = amdgpu_xcp_dev_register(adev, ent); 2352 if (ret) 2353 goto err_pci; 2354 2355 ret = amdgpu_amdkfd_drm_client_create(adev); 2356 if (ret) 2357 goto err_pci; 2358 2359 /* 2360 * 1. don't init fbdev on hw without DCE 2361 * 2. don't init fbdev if there are no connectors 2362 */ 2363 if (adev->mode_info.mode_config_initialized && 2364 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2365 const struct drm_format_info *format; 2366 2367 /* select 8 bpp console on low vram cards */ 2368 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2369 format = drm_format_info(DRM_FORMAT_C8); 2370 else 2371 format = NULL; 2372 2373 drm_client_setup(adev_to_drm(adev), format); 2374 } 2375 2376 ret = amdgpu_debugfs_init(adev); 2377 if (ret) 2378 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2379 2380 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2381 /* only need to skip on ATPX */ 2382 if (amdgpu_device_supports_px(ddev)) 2383 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2384 /* we want direct complete for BOCO */ 2385 if (amdgpu_device_supports_boco(ddev)) 2386 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2387 DPM_FLAG_SMART_SUSPEND | 2388 DPM_FLAG_MAY_SKIP_RESUME); 2389 pm_runtime_use_autosuspend(ddev->dev); 2390 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2391 2392 pm_runtime_allow(ddev->dev); 2393 2394 pm_runtime_mark_last_busy(ddev->dev); 2395 pm_runtime_put_autosuspend(ddev->dev); 2396 2397 pci_wake_from_d3(pdev, TRUE); 2398 2399 /* 2400 * For runpm implemented via BACO, PMFW will handle the 2401 * timing for BACO in and out: 2402 * - put ASIC into BACO state only when both video and 2403 * audio functions are in D3 state. 2404 * - pull ASIC out of BACO state when either video or 2405 * audio function is in D0 state. 2406 * Also, at startup, PMFW assumes both functions are in 2407 * D0 state. 2408 * 2409 * So if snd driver was loaded prior to amdgpu driver 2410 * and audio function was put into D3 state, there will 2411 * be no PMFW-aware D-state transition(D0->D3) on runpm 2412 * suspend. Thus the BACO will be not correctly kicked in. 2413 * 2414 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2415 * into D0 state. Then there will be a PMFW-aware D-state 2416 * transition(D0->D3) on runpm suspend. 2417 */ 2418 if (amdgpu_device_supports_baco(ddev) && 2419 !(adev->flags & AMD_IS_APU) && 2420 (adev->asic_type >= CHIP_NAVI10)) 2421 amdgpu_get_secondary_funcs(adev); 2422 } 2423 2424 return 0; 2425 2426 err_pci: 2427 pci_disable_device(pdev); 2428 return ret; 2429 } 2430 2431 static void 2432 amdgpu_pci_remove(struct pci_dev *pdev) 2433 { 2434 struct drm_device *dev = pci_get_drvdata(pdev); 2435 struct amdgpu_device *adev = drm_to_adev(dev); 2436 2437 amdgpu_xcp_dev_unplug(adev); 2438 amdgpu_gmc_prepare_nps_mode_change(adev); 2439 drm_dev_unplug(dev); 2440 2441 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2442 pm_runtime_get_sync(dev->dev); 2443 pm_runtime_forbid(dev->dev); 2444 } 2445 2446 amdgpu_driver_unload_kms(dev); 2447 2448 /* 2449 * Flush any in flight DMA operations from device. 2450 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2451 * StatusTransactions Pending bit. 2452 */ 2453 pci_disable_device(pdev); 2454 pci_wait_for_pending_transaction(pdev); 2455 } 2456 2457 static void 2458 amdgpu_pci_shutdown(struct pci_dev *pdev) 2459 { 2460 struct drm_device *dev = pci_get_drvdata(pdev); 2461 struct amdgpu_device *adev = drm_to_adev(dev); 2462 2463 if (amdgpu_ras_intr_triggered()) 2464 return; 2465 2466 /* if we are running in a VM, make sure the device 2467 * torn down properly on reboot/shutdown. 2468 * unfortunately we can't detect certain 2469 * hypervisors so just do this all the time. 2470 */ 2471 if (!amdgpu_passthrough(adev)) 2472 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2473 amdgpu_device_ip_suspend(adev); 2474 adev->mp1_state = PP_MP1_STATE_NONE; 2475 } 2476 2477 static int amdgpu_pmops_prepare(struct device *dev) 2478 { 2479 struct drm_device *drm_dev = dev_get_drvdata(dev); 2480 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2481 2482 /* Return a positive number here so 2483 * DPM_FLAG_SMART_SUSPEND works properly 2484 */ 2485 if (amdgpu_device_supports_boco(drm_dev) && 2486 pm_runtime_suspended(dev)) 2487 return 1; 2488 2489 /* if we will not support s3 or s2i for the device 2490 * then skip suspend 2491 */ 2492 if (!amdgpu_acpi_is_s0ix_active(adev) && 2493 !amdgpu_acpi_is_s3_active(adev)) 2494 return 1; 2495 2496 return amdgpu_device_prepare(drm_dev); 2497 } 2498 2499 static void amdgpu_pmops_complete(struct device *dev) 2500 { 2501 /* nothing to do */ 2502 } 2503 2504 static int amdgpu_pmops_suspend(struct device *dev) 2505 { 2506 struct drm_device *drm_dev = dev_get_drvdata(dev); 2507 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2508 2509 if (amdgpu_acpi_is_s0ix_active(adev)) 2510 adev->in_s0ix = true; 2511 else if (amdgpu_acpi_is_s3_active(adev)) 2512 adev->in_s3 = true; 2513 if (!adev->in_s0ix && !adev->in_s3) 2514 return 0; 2515 return amdgpu_device_suspend(drm_dev, true); 2516 } 2517 2518 static int amdgpu_pmops_suspend_noirq(struct device *dev) 2519 { 2520 struct drm_device *drm_dev = dev_get_drvdata(dev); 2521 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2522 2523 if (amdgpu_acpi_should_gpu_reset(adev)) 2524 return amdgpu_asic_reset(adev); 2525 2526 return 0; 2527 } 2528 2529 static int amdgpu_pmops_resume(struct device *dev) 2530 { 2531 struct drm_device *drm_dev = dev_get_drvdata(dev); 2532 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2533 int r; 2534 2535 if (!adev->in_s0ix && !adev->in_s3) 2536 return 0; 2537 2538 /* Avoids registers access if device is physically gone */ 2539 if (!pci_device_is_present(adev->pdev)) 2540 adev->no_hw_access = true; 2541 2542 r = amdgpu_device_resume(drm_dev, true); 2543 if (amdgpu_acpi_is_s0ix_active(adev)) 2544 adev->in_s0ix = false; 2545 else 2546 adev->in_s3 = false; 2547 return r; 2548 } 2549 2550 static int amdgpu_pmops_freeze(struct device *dev) 2551 { 2552 struct drm_device *drm_dev = dev_get_drvdata(dev); 2553 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2554 int r; 2555 2556 r = amdgpu_device_suspend(drm_dev, true); 2557 adev->in_s4 = false; 2558 if (r) 2559 return r; 2560 2561 if (amdgpu_acpi_should_gpu_reset(adev)) 2562 return amdgpu_asic_reset(adev); 2563 return 0; 2564 } 2565 2566 static int amdgpu_pmops_thaw(struct device *dev) 2567 { 2568 struct drm_device *drm_dev = dev_get_drvdata(dev); 2569 2570 return amdgpu_device_resume(drm_dev, true); 2571 } 2572 2573 static int amdgpu_pmops_poweroff(struct device *dev) 2574 { 2575 struct drm_device *drm_dev = dev_get_drvdata(dev); 2576 2577 return amdgpu_device_suspend(drm_dev, true); 2578 } 2579 2580 static int amdgpu_pmops_restore(struct device *dev) 2581 { 2582 struct drm_device *drm_dev = dev_get_drvdata(dev); 2583 2584 return amdgpu_device_resume(drm_dev, true); 2585 } 2586 2587 static int amdgpu_runtime_idle_check_display(struct device *dev) 2588 { 2589 struct pci_dev *pdev = to_pci_dev(dev); 2590 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2591 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2592 2593 if (adev->mode_info.num_crtc) { 2594 struct drm_connector *list_connector; 2595 struct drm_connector_list_iter iter; 2596 int ret = 0; 2597 2598 if (amdgpu_runtime_pm != -2) { 2599 /* XXX: Return busy if any displays are connected to avoid 2600 * possible display wakeups after runtime resume due to 2601 * hotplug events in case any displays were connected while 2602 * the GPU was in suspend. Remove this once that is fixed. 2603 */ 2604 mutex_lock(&drm_dev->mode_config.mutex); 2605 drm_connector_list_iter_begin(drm_dev, &iter); 2606 drm_for_each_connector_iter(list_connector, &iter) { 2607 if (list_connector->status == connector_status_connected) { 2608 ret = -EBUSY; 2609 break; 2610 } 2611 } 2612 drm_connector_list_iter_end(&iter); 2613 mutex_unlock(&drm_dev->mode_config.mutex); 2614 2615 if (ret) 2616 return ret; 2617 } 2618 2619 if (adev->dc_enabled) { 2620 struct drm_crtc *crtc; 2621 2622 drm_for_each_crtc(crtc, drm_dev) { 2623 drm_modeset_lock(&crtc->mutex, NULL); 2624 if (crtc->state->active) 2625 ret = -EBUSY; 2626 drm_modeset_unlock(&crtc->mutex); 2627 if (ret < 0) 2628 break; 2629 } 2630 } else { 2631 mutex_lock(&drm_dev->mode_config.mutex); 2632 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2633 2634 drm_connector_list_iter_begin(drm_dev, &iter); 2635 drm_for_each_connector_iter(list_connector, &iter) { 2636 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2637 ret = -EBUSY; 2638 break; 2639 } 2640 } 2641 2642 drm_connector_list_iter_end(&iter); 2643 2644 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2645 mutex_unlock(&drm_dev->mode_config.mutex); 2646 } 2647 if (ret) 2648 return ret; 2649 } 2650 2651 return 0; 2652 } 2653 2654 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2655 { 2656 struct pci_dev *pdev = to_pci_dev(dev); 2657 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2658 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2659 int ret, i; 2660 2661 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2662 pm_runtime_forbid(dev); 2663 return -EBUSY; 2664 } 2665 2666 ret = amdgpu_runtime_idle_check_display(dev); 2667 if (ret) 2668 return ret; 2669 2670 /* wait for all rings to drain before suspending */ 2671 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2672 struct amdgpu_ring *ring = adev->rings[i]; 2673 2674 if (ring && ring->sched.ready) { 2675 ret = amdgpu_fence_wait_empty(ring); 2676 if (ret) 2677 return -EBUSY; 2678 } 2679 } 2680 2681 adev->in_runpm = true; 2682 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2683 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2684 2685 /* 2686 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2687 * proper cleanups and put itself into a state ready for PNP. That 2688 * can address some random resuming failure observed on BOCO capable 2689 * platforms. 2690 * TODO: this may be also needed for PX capable platform. 2691 */ 2692 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2693 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2694 2695 ret = amdgpu_device_prepare(drm_dev); 2696 if (ret) 2697 return ret; 2698 ret = amdgpu_device_suspend(drm_dev, false); 2699 if (ret) { 2700 adev->in_runpm = false; 2701 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2702 adev->mp1_state = PP_MP1_STATE_NONE; 2703 return ret; 2704 } 2705 2706 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2707 adev->mp1_state = PP_MP1_STATE_NONE; 2708 2709 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) { 2710 /* Only need to handle PCI state in the driver for ATPX 2711 * PCI core handles it for _PR3. 2712 */ 2713 amdgpu_device_cache_pci_state(pdev); 2714 pci_disable_device(pdev); 2715 pci_ignore_hotplug(pdev); 2716 pci_set_power_state(pdev, PCI_D3cold); 2717 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2718 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) { 2719 /* nothing to do */ 2720 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2721 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) { 2722 amdgpu_device_baco_enter(drm_dev); 2723 } 2724 2725 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n"); 2726 2727 return 0; 2728 } 2729 2730 static int amdgpu_pmops_runtime_resume(struct device *dev) 2731 { 2732 struct pci_dev *pdev = to_pci_dev(dev); 2733 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2734 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2735 int ret; 2736 2737 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) 2738 return -EINVAL; 2739 2740 /* Avoids registers access if device is physically gone */ 2741 if (!pci_device_is_present(adev->pdev)) 2742 adev->no_hw_access = true; 2743 2744 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) { 2745 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2746 2747 /* Only need to handle PCI state in the driver for ATPX 2748 * PCI core handles it for _PR3. 2749 */ 2750 pci_set_power_state(pdev, PCI_D0); 2751 amdgpu_device_load_pci_state(pdev); 2752 ret = pci_enable_device(pdev); 2753 if (ret) 2754 return ret; 2755 pci_set_master(pdev); 2756 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) { 2757 /* Only need to handle PCI state in the driver for ATPX 2758 * PCI core handles it for _PR3. 2759 */ 2760 pci_set_master(pdev); 2761 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2762 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) { 2763 amdgpu_device_baco_exit(drm_dev); 2764 } 2765 ret = amdgpu_device_resume(drm_dev, false); 2766 if (ret) { 2767 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2768 pci_disable_device(pdev); 2769 return ret; 2770 } 2771 2772 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2773 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2774 adev->in_runpm = false; 2775 return 0; 2776 } 2777 2778 static int amdgpu_pmops_runtime_idle(struct device *dev) 2779 { 2780 struct drm_device *drm_dev = dev_get_drvdata(dev); 2781 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2782 int ret; 2783 2784 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2785 pm_runtime_forbid(dev); 2786 return -EBUSY; 2787 } 2788 2789 ret = amdgpu_runtime_idle_check_display(dev); 2790 2791 pm_runtime_mark_last_busy(dev); 2792 pm_runtime_autosuspend(dev); 2793 return ret; 2794 } 2795 2796 long amdgpu_drm_ioctl(struct file *filp, 2797 unsigned int cmd, unsigned long arg) 2798 { 2799 struct drm_file *file_priv = filp->private_data; 2800 struct drm_device *dev; 2801 long ret; 2802 2803 dev = file_priv->minor->dev; 2804 ret = pm_runtime_get_sync(dev->dev); 2805 if (ret < 0) 2806 goto out; 2807 2808 ret = drm_ioctl(filp, cmd, arg); 2809 2810 pm_runtime_mark_last_busy(dev->dev); 2811 out: 2812 pm_runtime_put_autosuspend(dev->dev); 2813 return ret; 2814 } 2815 2816 static const struct dev_pm_ops amdgpu_pm_ops = { 2817 .prepare = amdgpu_pmops_prepare, 2818 .complete = amdgpu_pmops_complete, 2819 .suspend = amdgpu_pmops_suspend, 2820 .suspend_noirq = amdgpu_pmops_suspend_noirq, 2821 .resume = amdgpu_pmops_resume, 2822 .freeze = amdgpu_pmops_freeze, 2823 .thaw = amdgpu_pmops_thaw, 2824 .poweroff = amdgpu_pmops_poweroff, 2825 .restore = amdgpu_pmops_restore, 2826 .runtime_suspend = amdgpu_pmops_runtime_suspend, 2827 .runtime_resume = amdgpu_pmops_runtime_resume, 2828 .runtime_idle = amdgpu_pmops_runtime_idle, 2829 }; 2830 2831 static int amdgpu_flush(struct file *f, fl_owner_t id) 2832 { 2833 struct drm_file *file_priv = f->private_data; 2834 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2835 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2836 2837 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 2838 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 2839 2840 return timeout >= 0 ? 0 : timeout; 2841 } 2842 2843 static const struct file_operations amdgpu_driver_kms_fops = { 2844 .owner = THIS_MODULE, 2845 .open = drm_open, 2846 .flush = amdgpu_flush, 2847 .release = drm_release, 2848 .unlocked_ioctl = amdgpu_drm_ioctl, 2849 .mmap = drm_gem_mmap, 2850 .poll = drm_poll, 2851 .read = drm_read, 2852 #ifdef CONFIG_COMPAT 2853 .compat_ioctl = amdgpu_kms_compat_ioctl, 2854 #endif 2855 #ifdef CONFIG_PROC_FS 2856 .show_fdinfo = drm_show_fdinfo, 2857 #endif 2858 .fop_flags = FOP_UNSIGNED_OFFSET, 2859 }; 2860 2861 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 2862 { 2863 struct drm_file *file; 2864 2865 if (!filp) 2866 return -EINVAL; 2867 2868 if (filp->f_op != &amdgpu_driver_kms_fops) 2869 return -EINVAL; 2870 2871 file = filp->private_data; 2872 *fpriv = file->driver_priv; 2873 return 0; 2874 } 2875 2876 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 2877 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2878 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2879 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2880 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 2881 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2882 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2883 /* KMS */ 2884 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2885 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2886 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2887 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2888 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2889 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2890 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2891 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2892 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2893 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2894 }; 2895 2896 static const struct drm_driver amdgpu_kms_driver = { 2897 .driver_features = 2898 DRIVER_ATOMIC | 2899 DRIVER_GEM | 2900 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 2901 DRIVER_SYNCOBJ_TIMELINE, 2902 .open = amdgpu_driver_open_kms, 2903 .postclose = amdgpu_driver_postclose_kms, 2904 .ioctls = amdgpu_ioctls_kms, 2905 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2906 .dumb_create = amdgpu_mode_dumb_create, 2907 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2908 DRM_FBDEV_TTM_DRIVER_OPS, 2909 .fops = &amdgpu_driver_kms_fops, 2910 .release = &amdgpu_driver_release_kms, 2911 #ifdef CONFIG_PROC_FS 2912 .show_fdinfo = amdgpu_show_fdinfo, 2913 #endif 2914 2915 .gem_prime_import = amdgpu_gem_prime_import, 2916 2917 .name = DRIVER_NAME, 2918 .desc = DRIVER_DESC, 2919 .major = KMS_DRIVER_MAJOR, 2920 .minor = KMS_DRIVER_MINOR, 2921 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2922 }; 2923 2924 const struct drm_driver amdgpu_partition_driver = { 2925 .driver_features = 2926 DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ | 2927 DRIVER_SYNCOBJ_TIMELINE, 2928 .open = amdgpu_driver_open_kms, 2929 .postclose = amdgpu_driver_postclose_kms, 2930 .ioctls = amdgpu_ioctls_kms, 2931 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2932 .dumb_create = amdgpu_mode_dumb_create, 2933 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2934 DRM_FBDEV_TTM_DRIVER_OPS, 2935 .fops = &amdgpu_driver_kms_fops, 2936 .release = &amdgpu_driver_release_kms, 2937 2938 .gem_prime_import = amdgpu_gem_prime_import, 2939 2940 .name = DRIVER_NAME, 2941 .desc = DRIVER_DESC, 2942 .major = KMS_DRIVER_MAJOR, 2943 .minor = KMS_DRIVER_MINOR, 2944 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2945 }; 2946 2947 static struct pci_error_handlers amdgpu_pci_err_handler = { 2948 .error_detected = amdgpu_pci_error_detected, 2949 .mmio_enabled = amdgpu_pci_mmio_enabled, 2950 .slot_reset = amdgpu_pci_slot_reset, 2951 .resume = amdgpu_pci_resume, 2952 }; 2953 2954 static const struct attribute_group *amdgpu_sysfs_groups[] = { 2955 &amdgpu_vram_mgr_attr_group, 2956 &amdgpu_gtt_mgr_attr_group, 2957 &amdgpu_flash_attr_group, 2958 NULL, 2959 }; 2960 2961 static struct pci_driver amdgpu_kms_pci_driver = { 2962 .name = DRIVER_NAME, 2963 .id_table = pciidlist, 2964 .probe = amdgpu_pci_probe, 2965 .remove = amdgpu_pci_remove, 2966 .shutdown = amdgpu_pci_shutdown, 2967 .driver.pm = &amdgpu_pm_ops, 2968 .err_handler = &amdgpu_pci_err_handler, 2969 .dev_groups = amdgpu_sysfs_groups, 2970 }; 2971 2972 static int __init amdgpu_init(void) 2973 { 2974 int r; 2975 2976 if (drm_firmware_drivers_only()) 2977 return -EINVAL; 2978 2979 r = amdgpu_sync_init(); 2980 if (r) 2981 goto error_sync; 2982 2983 r = amdgpu_fence_slab_init(); 2984 if (r) 2985 goto error_fence; 2986 2987 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 2988 amdgpu_register_atpx_handler(); 2989 amdgpu_acpi_detect(); 2990 2991 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 2992 amdgpu_amdkfd_init(); 2993 2994 if (amdgpu_pp_feature_mask & PP_OVERDRIVE_MASK) { 2995 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 2996 pr_crit("Overdrive is enabled, please disable it before " 2997 "reporting any bugs unrelated to overdrive.\n"); 2998 } 2999 3000 /* let modprobe override vga console setting */ 3001 return pci_register_driver(&amdgpu_kms_pci_driver); 3002 3003 error_fence: 3004 amdgpu_sync_fini(); 3005 3006 error_sync: 3007 return r; 3008 } 3009 3010 static void __exit amdgpu_exit(void) 3011 { 3012 amdgpu_amdkfd_fini(); 3013 pci_unregister_driver(&amdgpu_kms_pci_driver); 3014 amdgpu_unregister_atpx_handler(); 3015 amdgpu_acpi_release(); 3016 amdgpu_sync_fini(); 3017 amdgpu_fence_slab_fini(); 3018 mmu_notifier_synchronize(); 3019 amdgpu_xcp_drv_release(); 3020 } 3021 3022 module_init(amdgpu_init); 3023 module_exit(amdgpu_exit); 3024 3025 MODULE_AUTHOR(DRIVER_AUTHOR); 3026 MODULE_DESCRIPTION(DRIVER_DESC); 3027 MODULE_LICENSE("GPL and additional rights"); 3028