1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_drv.h> 27 #include <drm/drm_fbdev_generic.h> 28 #include <drm/drm_gem.h> 29 #include <drm/drm_managed.h> 30 #include <drm/drm_pciids.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/drm_vblank.h> 33 34 #include <linux/cc_platform.h> 35 #include <linux/dynamic_debug.h> 36 #include <linux/module.h> 37 #include <linux/mmu_notifier.h> 38 #include <linux/pm_runtime.h> 39 #include <linux/suspend.h> 40 #include <linux/vga_switcheroo.h> 41 42 #include "amdgpu.h" 43 #include "amdgpu_amdkfd.h" 44 #include "amdgpu_dma_buf.h" 45 #include "amdgpu_drv.h" 46 #include "amdgpu_fdinfo.h" 47 #include "amdgpu_irq.h" 48 #include "amdgpu_psp.h" 49 #include "amdgpu_ras.h" 50 #include "amdgpu_reset.h" 51 #include "amdgpu_sched.h" 52 #include "amdgpu_xgmi.h" 53 #include "../amdxcp/amdgpu_xcp_drv.h" 54 55 /* 56 * KMS wrapper. 57 * - 3.0.0 - initial driver 58 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 59 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 60 * at the end of IBs. 61 * - 3.3.0 - Add VM support for UVD on supported hardware. 62 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 63 * - 3.5.0 - Add support for new UVD_NO_OP register. 64 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 65 * - 3.7.0 - Add support for VCE clock list packet 66 * - 3.8.0 - Add support raster config init in the kernel 67 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 68 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 69 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 70 * - 3.12.0 - Add query for double offchip LDS buffers 71 * - 3.13.0 - Add PRT support 72 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 73 * - 3.15.0 - Export more gpu info for gfx9 74 * - 3.16.0 - Add reserved vmid support 75 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 76 * - 3.18.0 - Export gpu always on cu bitmap 77 * - 3.19.0 - Add support for UVD MJPEG decode 78 * - 3.20.0 - Add support for local BOs 79 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 80 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 81 * - 3.23.0 - Add query for VRAM lost counter 82 * - 3.24.0 - Add high priority compute support for gfx9 83 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 84 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 85 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation. 86 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 87 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 88 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 89 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 90 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 91 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 92 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 93 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 94 * - 3.36.0 - Allow reading more status registers on si/cik 95 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 96 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 97 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 98 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 99 * - 3.41.0 - Add video codec query 100 * - 3.42.0 - Add 16bpc fixed point display support 101 * - 3.43.0 - Add device hot plug/unplug support 102 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 103 * - 3.45.0 - Add context ioctl stable pstate interface 104 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm 105 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags 106 * - 3.48.0 - Add IP discovery version info to HW INFO 107 * - 3.49.0 - Add gang submit into CS IOCTL 108 * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock 109 * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock 110 * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl 111 * 3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields: 112 * tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size, 113 * gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi 114 * 3.53.0 - Support for GFX11 CP GFX shadowing 115 * 3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support 116 */ 117 #define KMS_DRIVER_MAJOR 3 118 #define KMS_DRIVER_MINOR 54 119 #define KMS_DRIVER_PATCHLEVEL 0 120 121 /* 122 * amdgpu.debug module options. Are all disabled by default 123 */ 124 enum AMDGPU_DEBUG_MASK { 125 AMDGPU_DEBUG_VM = BIT(0), 126 AMDGPU_DEBUG_LARGEBAR = BIT(1), 127 AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY = BIT(2), 128 }; 129 130 unsigned int amdgpu_vram_limit = UINT_MAX; 131 int amdgpu_vis_vram_limit; 132 int amdgpu_gart_size = -1; /* auto */ 133 int amdgpu_gtt_size = -1; /* auto */ 134 int amdgpu_moverate = -1; /* auto */ 135 int amdgpu_audio = -1; 136 int amdgpu_disp_priority; 137 int amdgpu_hw_i2c; 138 int amdgpu_pcie_gen2 = -1; 139 int amdgpu_msi = -1; 140 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 141 int amdgpu_dpm = -1; 142 int amdgpu_fw_load_type = -1; 143 int amdgpu_aspm = -1; 144 int amdgpu_runtime_pm = -1; 145 uint amdgpu_ip_block_mask = 0xffffffff; 146 int amdgpu_bapm = -1; 147 int amdgpu_deep_color; 148 int amdgpu_vm_size = -1; 149 int amdgpu_vm_fragment_size = -1; 150 int amdgpu_vm_block_size = -1; 151 int amdgpu_vm_fault_stop; 152 int amdgpu_vm_update_mode = -1; 153 int amdgpu_exp_hw_support; 154 int amdgpu_dc = -1; 155 int amdgpu_sched_jobs = 32; 156 int amdgpu_sched_hw_submission = 2; 157 uint amdgpu_pcie_gen_cap; 158 uint amdgpu_pcie_lane_cap; 159 u64 amdgpu_cg_mask = 0xffffffffffffffff; 160 uint amdgpu_pg_mask = 0xffffffff; 161 uint amdgpu_sdma_phase_quantum = 32; 162 char *amdgpu_disable_cu; 163 char *amdgpu_virtual_display; 164 bool enforce_isolation; 165 /* 166 * OverDrive(bit 14) disabled by default 167 * GFX DCS(bit 19) disabled by default 168 */ 169 uint amdgpu_pp_feature_mask = 0xfff7bfff; 170 uint amdgpu_force_long_training; 171 int amdgpu_lbpw = -1; 172 int amdgpu_compute_multipipe = -1; 173 int amdgpu_gpu_recovery = -1; /* auto */ 174 int amdgpu_emu_mode; 175 uint amdgpu_smu_memory_pool_size; 176 int amdgpu_smu_pptable_id = -1; 177 /* 178 * FBC (bit 0) disabled by default 179 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 180 * - With this, for multiple monitors in sync(e.g. with the same model), 181 * mclk switching will be allowed. And the mclk will be not foced to the 182 * highest. That helps saving some idle power. 183 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 184 * PSR (bit 3) disabled by default 185 * EDP NO POWER SEQUENCING (bit 4) disabled by default 186 */ 187 uint amdgpu_dc_feature_mask = 2; 188 uint amdgpu_dc_debug_mask; 189 uint amdgpu_dc_visual_confirm; 190 int amdgpu_async_gfx_ring = 1; 191 int amdgpu_mcbp = -1; 192 int amdgpu_discovery = -1; 193 int amdgpu_mes; 194 int amdgpu_mes_kiq; 195 int amdgpu_noretry = -1; 196 int amdgpu_force_asic_type = -1; 197 int amdgpu_tmz = -1; /* auto */ 198 int amdgpu_reset_method = -1; /* auto */ 199 int amdgpu_num_kcq = -1; 200 int amdgpu_smartshift_bias; 201 int amdgpu_use_xgmi_p2p = 1; 202 int amdgpu_vcnfw_log; 203 int amdgpu_sg_display = -1; /* auto */ 204 int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE; 205 int amdgpu_umsch_mm; 206 int amdgpu_seamless = -1; /* auto */ 207 uint amdgpu_debug_mask; 208 209 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 210 211 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 212 "DRM_UT_CORE", 213 "DRM_UT_DRIVER", 214 "DRM_UT_KMS", 215 "DRM_UT_PRIME", 216 "DRM_UT_ATOMIC", 217 "DRM_UT_VBL", 218 "DRM_UT_STATE", 219 "DRM_UT_LEASE", 220 "DRM_UT_DP", 221 "DRM_UT_DRMRES"); 222 223 struct amdgpu_mgpu_info mgpu_info = { 224 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 225 .delayed_reset_work = __DELAYED_WORK_INITIALIZER( 226 mgpu_info.delayed_reset_work, 227 amdgpu_drv_delayed_reset_work_handler, 0), 228 }; 229 int amdgpu_ras_enable = -1; 230 uint amdgpu_ras_mask = 0xffffffff; 231 int amdgpu_bad_page_threshold = -1; 232 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 233 .timeout_fatal_disable = false, 234 .period = 0x0, /* default to 0x0 (timeout disable) */ 235 }; 236 237 /** 238 * DOC: vramlimit (int) 239 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 240 */ 241 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 242 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 243 244 /** 245 * DOC: vis_vramlimit (int) 246 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 247 */ 248 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 249 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 250 251 /** 252 * DOC: gartsize (uint) 253 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing. 254 * The default is -1 (The size depends on asic). 255 */ 256 MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)"); 257 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 258 259 /** 260 * DOC: gttsize (int) 261 * Restrict the size of GTT domain (for userspace use) in MiB for testing. 262 * The default is -1 (Use 1/2 RAM, minimum value is 3GB). 263 */ 264 MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)"); 265 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 266 267 /** 268 * DOC: moverate (int) 269 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 270 */ 271 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 272 module_param_named(moverate, amdgpu_moverate, int, 0600); 273 274 /** 275 * DOC: audio (int) 276 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 277 */ 278 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 279 module_param_named(audio, amdgpu_audio, int, 0444); 280 281 /** 282 * DOC: disp_priority (int) 283 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 284 */ 285 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 286 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 287 288 /** 289 * DOC: hw_i2c (int) 290 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 291 */ 292 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 293 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 294 295 /** 296 * DOC: pcie_gen2 (int) 297 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 298 */ 299 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 300 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 301 302 /** 303 * DOC: msi (int) 304 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 305 */ 306 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 307 module_param_named(msi, amdgpu_msi, int, 0444); 308 309 /** 310 * DOC: lockup_timeout (string) 311 * Set GPU scheduler timeout value in ms. 312 * 313 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 314 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 315 * to the default timeout. 316 * 317 * - With one value specified, the setting will apply to all non-compute jobs. 318 * - With multiple values specified, the first one will be for GFX. 319 * The second one is for Compute. The third and fourth ones are 320 * for SDMA and Video. 321 * 322 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 323 * jobs is 10000. The timeout for compute is 60000. 324 */ 325 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 326 "for passthrough or sriov, 10000 for all jobs. 0: keep default value. negative: infinity timeout), format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 327 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 328 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 329 330 /** 331 * DOC: dpm (int) 332 * Override for dynamic power management setting 333 * (0 = disable, 1 = enable) 334 * The default is -1 (auto). 335 */ 336 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 337 module_param_named(dpm, amdgpu_dpm, int, 0444); 338 339 /** 340 * DOC: fw_load_type (int) 341 * Set different firmware loading type for debugging, if supported. 342 * Set to 0 to force direct loading if supported by the ASIC. Set 343 * to -1 to select the default loading mode for the ASIC, as defined 344 * by the driver. The default is -1 (auto). 345 */ 346 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); 347 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 348 349 /** 350 * DOC: aspm (int) 351 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 352 */ 353 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 354 module_param_named(aspm, amdgpu_aspm, int, 0444); 355 356 /** 357 * DOC: runpm (int) 358 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 359 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 360 * Setting the value to 0 disables this functionality. 361 * Setting the value to -2 is auto enabled with power down when displays are attached. 362 */ 363 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto, -2 = autowith displays)"); 364 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 365 366 /** 367 * DOC: ip_block_mask (uint) 368 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 369 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 370 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 371 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 372 */ 373 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 374 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 375 376 /** 377 * DOC: bapm (int) 378 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 379 * The default -1 (auto, enabled) 380 */ 381 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 382 module_param_named(bapm, amdgpu_bapm, int, 0444); 383 384 /** 385 * DOC: deep_color (int) 386 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 387 */ 388 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 389 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 390 391 /** 392 * DOC: vm_size (int) 393 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 394 */ 395 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 396 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 397 398 /** 399 * DOC: vm_fragment_size (int) 400 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 401 */ 402 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 403 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 404 405 /** 406 * DOC: vm_block_size (int) 407 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 408 */ 409 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 410 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 411 412 /** 413 * DOC: vm_fault_stop (int) 414 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 415 */ 416 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 417 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 418 419 /** 420 * DOC: vm_update_mode (int) 421 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 422 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 423 */ 424 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 425 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 426 427 /** 428 * DOC: exp_hw_support (int) 429 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 430 */ 431 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 432 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 433 434 /** 435 * DOC: dc (int) 436 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 437 */ 438 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 439 module_param_named(dc, amdgpu_dc, int, 0444); 440 441 /** 442 * DOC: sched_jobs (int) 443 * Override the max number of jobs supported in the sw queue. The default is 32. 444 */ 445 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 446 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 447 448 /** 449 * DOC: sched_hw_submission (int) 450 * Override the max number of HW submissions. The default is 2. 451 */ 452 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 453 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 454 455 /** 456 * DOC: ppfeaturemask (hexint) 457 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 458 * The default is the current set of stable power features. 459 */ 460 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 461 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 462 463 /** 464 * DOC: forcelongtraining (uint) 465 * Force long memory training in resume. 466 * The default is zero, indicates short training in resume. 467 */ 468 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 469 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 470 471 /** 472 * DOC: pcie_gen_cap (uint) 473 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 474 * The default is 0 (automatic for each asic). 475 */ 476 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 477 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 478 479 /** 480 * DOC: pcie_lane_cap (uint) 481 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 482 * The default is 0 (automatic for each asic). 483 */ 484 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 485 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 486 487 /** 488 * DOC: cg_mask (ullong) 489 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 490 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 491 */ 492 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 493 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 494 495 /** 496 * DOC: pg_mask (uint) 497 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 498 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 499 */ 500 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 501 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 502 503 /** 504 * DOC: sdma_phase_quantum (uint) 505 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 506 */ 507 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 508 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 509 510 /** 511 * DOC: disable_cu (charp) 512 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 513 */ 514 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 515 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 516 517 /** 518 * DOC: virtual_display (charp) 519 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 520 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 521 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 522 * device at 26:00.0. The default is NULL. 523 */ 524 MODULE_PARM_DESC(virtual_display, 525 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 526 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 527 528 /** 529 * DOC: lbpw (int) 530 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 531 */ 532 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 533 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 534 535 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 536 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 537 538 /** 539 * DOC: gpu_recovery (int) 540 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 541 */ 542 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 543 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 544 545 /** 546 * DOC: emu_mode (int) 547 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 548 */ 549 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 550 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 551 552 /** 553 * DOC: ras_enable (int) 554 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 555 */ 556 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 557 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 558 559 /** 560 * DOC: ras_mask (uint) 561 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 562 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 563 */ 564 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 565 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 566 567 /** 568 * DOC: timeout_fatal_disable (bool) 569 * Disable Watchdog timeout fatal error event 570 */ 571 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 572 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 573 574 /** 575 * DOC: timeout_period (uint) 576 * Modify the watchdog timeout max_cycles as (1 << period) 577 */ 578 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 579 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 580 581 /** 582 * DOC: si_support (int) 583 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 584 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 585 * otherwise using amdgpu driver. 586 */ 587 #ifdef CONFIG_DRM_AMDGPU_SI 588 589 #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) 590 int amdgpu_si_support = 0; 591 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 592 #else 593 int amdgpu_si_support = 1; 594 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 595 #endif 596 597 module_param_named(si_support, amdgpu_si_support, int, 0444); 598 #endif 599 600 /** 601 * DOC: cik_support (int) 602 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 603 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 604 * otherwise using amdgpu driver. 605 */ 606 #ifdef CONFIG_DRM_AMDGPU_CIK 607 608 #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) 609 int amdgpu_cik_support = 0; 610 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 611 #else 612 int amdgpu_cik_support = 1; 613 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 614 #endif 615 616 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 617 #endif 618 619 /** 620 * DOC: smu_memory_pool_size (uint) 621 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 622 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 623 */ 624 MODULE_PARM_DESC(smu_memory_pool_size, 625 "reserve gtt for smu debug usage, 0 = disable,0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 626 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 627 628 /** 629 * DOC: async_gfx_ring (int) 630 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 631 */ 632 MODULE_PARM_DESC(async_gfx_ring, 633 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 634 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 635 636 /** 637 * DOC: mcbp (int) 638 * It is used to enable mid command buffer preemption. (0 = disabled, 1 = enabled, -1 auto (default)) 639 */ 640 MODULE_PARM_DESC(mcbp, 641 "Enable Mid-command buffer preemption (0 = disabled, 1 = enabled), -1 = auto (default)"); 642 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 643 644 /** 645 * DOC: discovery (int) 646 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 647 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 648 */ 649 MODULE_PARM_DESC(discovery, 650 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 651 module_param_named(discovery, amdgpu_discovery, int, 0444); 652 653 /** 654 * DOC: mes (int) 655 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 656 * (0 = disabled (default), 1 = enabled) 657 */ 658 MODULE_PARM_DESC(mes, 659 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 660 module_param_named(mes, amdgpu_mes, int, 0444); 661 662 /** 663 * DOC: mes_kiq (int) 664 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq. 665 * (0 = disabled (default), 1 = enabled) 666 */ 667 MODULE_PARM_DESC(mes_kiq, 668 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)"); 669 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444); 670 671 /** 672 * DOC: noretry (int) 673 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 674 * do not support per-process XNACK this also disables retry page faults. 675 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 676 */ 677 MODULE_PARM_DESC(noretry, 678 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 679 module_param_named(noretry, amdgpu_noretry, int, 0644); 680 681 /** 682 * DOC: force_asic_type (int) 683 * A non negative value used to specify the asic type for all supported GPUs. 684 */ 685 MODULE_PARM_DESC(force_asic_type, 686 "A non negative value used to specify the asic type for all supported GPUs"); 687 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 688 689 /** 690 * DOC: use_xgmi_p2p (int) 691 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 692 */ 693 MODULE_PARM_DESC(use_xgmi_p2p, 694 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 695 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 696 697 698 #ifdef CONFIG_HSA_AMD 699 /** 700 * DOC: sched_policy (int) 701 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 702 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 703 * assigns queues to HQDs. 704 */ 705 int sched_policy = KFD_SCHED_POLICY_HWS; 706 module_param(sched_policy, int, 0444); 707 MODULE_PARM_DESC(sched_policy, 708 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 709 710 /** 711 * DOC: hws_max_conc_proc (int) 712 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 713 * number of VMIDs assigned to the HWS, which is also the default. 714 */ 715 int hws_max_conc_proc = -1; 716 module_param(hws_max_conc_proc, int, 0444); 717 MODULE_PARM_DESC(hws_max_conc_proc, 718 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 719 720 /** 721 * DOC: cwsr_enable (int) 722 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 723 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 724 * disables it. 725 */ 726 int cwsr_enable = 1; 727 module_param(cwsr_enable, int, 0444); 728 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 729 730 /** 731 * DOC: max_num_of_queues_per_device (int) 732 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 733 * is 4096. 734 */ 735 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 736 module_param(max_num_of_queues_per_device, int, 0444); 737 MODULE_PARM_DESC(max_num_of_queues_per_device, 738 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 739 740 /** 741 * DOC: send_sigterm (int) 742 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 743 * but just print errors on dmesg. Setting 1 enables sending sigterm. 744 */ 745 int send_sigterm; 746 module_param(send_sigterm, int, 0444); 747 MODULE_PARM_DESC(send_sigterm, 748 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 749 750 /** 751 * DOC: halt_if_hws_hang (int) 752 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 753 * Setting 1 enables halt on hang. 754 */ 755 int halt_if_hws_hang; 756 module_param(halt_if_hws_hang, int, 0644); 757 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 758 759 /** 760 * DOC: hws_gws_support(bool) 761 * Assume that HWS supports GWS barriers regardless of what firmware version 762 * check says. Default value: false (rely on MEC2 firmware version check). 763 */ 764 bool hws_gws_support; 765 module_param(hws_gws_support, bool, 0444); 766 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 767 768 /** 769 * DOC: queue_preemption_timeout_ms (int) 770 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 771 */ 772 int queue_preemption_timeout_ms = 9000; 773 module_param(queue_preemption_timeout_ms, int, 0644); 774 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 775 776 /** 777 * DOC: debug_evictions(bool) 778 * Enable extra debug messages to help determine the cause of evictions 779 */ 780 bool debug_evictions; 781 module_param(debug_evictions, bool, 0644); 782 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 783 784 /** 785 * DOC: no_system_mem_limit(bool) 786 * Disable system memory limit, to support multiple process shared memory 787 */ 788 bool no_system_mem_limit; 789 module_param(no_system_mem_limit, bool, 0644); 790 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 791 792 /** 793 * DOC: no_queue_eviction_on_vm_fault (int) 794 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 795 */ 796 int amdgpu_no_queue_eviction_on_vm_fault; 797 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 798 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 799 #endif 800 801 /** 802 * DOC: mtype_local (int) 803 */ 804 int amdgpu_mtype_local; 805 MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (0 = MTYPE_RW (default), 1 = MTYPE_NC, 2 = MTYPE_CC)"); 806 module_param_named(mtype_local, amdgpu_mtype_local, int, 0444); 807 808 /** 809 * DOC: pcie_p2p (bool) 810 * Enable PCIe P2P (requires large-BAR). Default value: true (on) 811 */ 812 #ifdef CONFIG_HSA_AMD_P2P 813 bool pcie_p2p = true; 814 module_param(pcie_p2p, bool, 0444); 815 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); 816 #endif 817 818 /** 819 * DOC: dcfeaturemask (uint) 820 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 821 * The default is the current set of stable display features. 822 */ 823 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 824 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 825 826 /** 827 * DOC: dcdebugmask (uint) 828 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 829 */ 830 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 831 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 832 833 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)"); 834 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444); 835 836 /** 837 * DOC: abmlevel (uint) 838 * Override the default ABM (Adaptive Backlight Management) level used for DC 839 * enabled hardware. Requires DMCU to be supported and loaded. 840 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 841 * default. Values 1-4 control the maximum allowable brightness reduction via 842 * the ABM algorithm, with 1 being the least reduction and 4 being the most 843 * reduction. 844 * 845 * Defaults to 0, or disabled. Userspace can still override this level later 846 * after boot. 847 */ 848 uint amdgpu_dm_abm_level; 849 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 850 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 851 852 int amdgpu_backlight = -1; 853 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 854 module_param_named(backlight, amdgpu_backlight, bint, 0444); 855 856 /** 857 * DOC: tmz (int) 858 * Trusted Memory Zone (TMZ) is a method to protect data being written 859 * to or read from memory. 860 * 861 * The default value: 0 (off). TODO: change to auto till it is completed. 862 */ 863 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 864 module_param_named(tmz, amdgpu_tmz, int, 0444); 865 866 /** 867 * DOC: reset_method (int) 868 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 869 */ 870 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 871 module_param_named(reset_method, amdgpu_reset_method, int, 0444); 872 873 /** 874 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 875 * threshold value of faulty pages detected by RAS ECC, which may 876 * result in the GPU entering bad status when the number of total 877 * faulty pages by ECC exceeds the threshold value. 878 */ 879 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = driver sets threshold)"); 880 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 881 882 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 883 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 884 885 /** 886 * DOC: vcnfw_log (int) 887 * Enable vcnfw log output for debugging, the default is disabled. 888 */ 889 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 890 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 891 892 /** 893 * DOC: sg_display (int) 894 * Disable S/G (scatter/gather) display (i.e., display from system memory). 895 * This option is only relevant on APUs. Set this option to 0 to disable 896 * S/G display if you experience flickering or other issues under memory 897 * pressure and report the issue. 898 */ 899 MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)"); 900 module_param_named(sg_display, amdgpu_sg_display, int, 0444); 901 902 /** 903 * DOC: umsch_mm (int) 904 * Enable Multi Media User Mode Scheduler. This is a HW scheduling engine for VCN and VPE. 905 * (0 = disabled (default), 1 = enabled) 906 */ 907 MODULE_PARM_DESC(umsch_mm, 908 "Enable Multi Media User Mode Scheduler (0 = disabled (default), 1 = enabled)"); 909 module_param_named(umsch_mm, amdgpu_umsch_mm, int, 0444); 910 911 /** 912 * DOC: smu_pptable_id (int) 913 * Used to override pptable id. id = 0 use VBIOS pptable. 914 * id > 0 use the soft pptable with specicfied id. 915 */ 916 MODULE_PARM_DESC(smu_pptable_id, 917 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 918 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 919 920 /** 921 * DOC: partition_mode (int) 922 * Used to override the default SPX mode. 923 */ 924 MODULE_PARM_DESC( 925 user_partt_mode, 926 "specify partition mode to be used (-2 = AMDGPU_AUTO_COMPUTE_PARTITION_MODE(default value) \ 927 0 = AMDGPU_SPX_PARTITION_MODE, \ 928 1 = AMDGPU_DPX_PARTITION_MODE, \ 929 2 = AMDGPU_TPX_PARTITION_MODE, \ 930 3 = AMDGPU_QPX_PARTITION_MODE, \ 931 4 = AMDGPU_CPX_PARTITION_MODE)"); 932 module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint, 0444); 933 934 935 /** 936 * DOC: enforce_isolation (bool) 937 * enforce process isolation between graphics and compute via using the same reserved vmid. 938 */ 939 module_param(enforce_isolation, bool, 0444); 940 MODULE_PARM_DESC(enforce_isolation, "enforce process isolation between graphics and compute . enforce_isolation = on"); 941 942 /** 943 * DOC: seamless (int) 944 * Seamless boot will keep the image on the screen during the boot process. 945 */ 946 MODULE_PARM_DESC(seamless, "Seamless boot (-1 = auto (default), 0 = disable, 1 = enable)"); 947 module_param_named(seamless, amdgpu_seamless, int, 0444); 948 949 /** 950 * DOC: debug_mask (uint) 951 * Debug options for amdgpu, work as a binary mask with the following options: 952 * 953 * - 0x1: Debug VM handling 954 * - 0x2: Enable simulating large-bar capability on non-large bar system. This 955 * limits the VRAM size reported to ROCm applications to the visible 956 * size, usually 256MB. 957 * - 0x4: Disable GPU soft recovery, always do a full reset 958 */ 959 MODULE_PARM_DESC(debug_mask, "debug options for amdgpu, disabled by default"); 960 module_param_named(debug_mask, amdgpu_debug_mask, uint, 0444); 961 962 /* These devices are not supported by amdgpu. 963 * They are supported by the mach64, r128, radeon drivers 964 */ 965 static const u16 amdgpu_unsupported_pciidlist[] = { 966 /* mach64 */ 967 0x4354, 968 0x4358, 969 0x4554, 970 0x4742, 971 0x4744, 972 0x4749, 973 0x474C, 974 0x474D, 975 0x474E, 976 0x474F, 977 0x4750, 978 0x4751, 979 0x4752, 980 0x4753, 981 0x4754, 982 0x4755, 983 0x4756, 984 0x4757, 985 0x4758, 986 0x4759, 987 0x475A, 988 0x4C42, 989 0x4C44, 990 0x4C47, 991 0x4C49, 992 0x4C4D, 993 0x4C4E, 994 0x4C50, 995 0x4C51, 996 0x4C52, 997 0x4C53, 998 0x5654, 999 0x5655, 1000 0x5656, 1001 /* r128 */ 1002 0x4c45, 1003 0x4c46, 1004 0x4d46, 1005 0x4d4c, 1006 0x5041, 1007 0x5042, 1008 0x5043, 1009 0x5044, 1010 0x5045, 1011 0x5046, 1012 0x5047, 1013 0x5048, 1014 0x5049, 1015 0x504A, 1016 0x504B, 1017 0x504C, 1018 0x504D, 1019 0x504E, 1020 0x504F, 1021 0x5050, 1022 0x5051, 1023 0x5052, 1024 0x5053, 1025 0x5054, 1026 0x5055, 1027 0x5056, 1028 0x5057, 1029 0x5058, 1030 0x5245, 1031 0x5246, 1032 0x5247, 1033 0x524b, 1034 0x524c, 1035 0x534d, 1036 0x5446, 1037 0x544C, 1038 0x5452, 1039 /* radeon */ 1040 0x3150, 1041 0x3151, 1042 0x3152, 1043 0x3154, 1044 0x3155, 1045 0x3E50, 1046 0x3E54, 1047 0x4136, 1048 0x4137, 1049 0x4144, 1050 0x4145, 1051 0x4146, 1052 0x4147, 1053 0x4148, 1054 0x4149, 1055 0x414A, 1056 0x414B, 1057 0x4150, 1058 0x4151, 1059 0x4152, 1060 0x4153, 1061 0x4154, 1062 0x4155, 1063 0x4156, 1064 0x4237, 1065 0x4242, 1066 0x4336, 1067 0x4337, 1068 0x4437, 1069 0x4966, 1070 0x4967, 1071 0x4A48, 1072 0x4A49, 1073 0x4A4A, 1074 0x4A4B, 1075 0x4A4C, 1076 0x4A4D, 1077 0x4A4E, 1078 0x4A4F, 1079 0x4A50, 1080 0x4A54, 1081 0x4B48, 1082 0x4B49, 1083 0x4B4A, 1084 0x4B4B, 1085 0x4B4C, 1086 0x4C57, 1087 0x4C58, 1088 0x4C59, 1089 0x4C5A, 1090 0x4C64, 1091 0x4C66, 1092 0x4C67, 1093 0x4E44, 1094 0x4E45, 1095 0x4E46, 1096 0x4E47, 1097 0x4E48, 1098 0x4E49, 1099 0x4E4A, 1100 0x4E4B, 1101 0x4E50, 1102 0x4E51, 1103 0x4E52, 1104 0x4E53, 1105 0x4E54, 1106 0x4E56, 1107 0x5144, 1108 0x5145, 1109 0x5146, 1110 0x5147, 1111 0x5148, 1112 0x514C, 1113 0x514D, 1114 0x5157, 1115 0x5158, 1116 0x5159, 1117 0x515A, 1118 0x515E, 1119 0x5460, 1120 0x5462, 1121 0x5464, 1122 0x5548, 1123 0x5549, 1124 0x554A, 1125 0x554B, 1126 0x554C, 1127 0x554D, 1128 0x554E, 1129 0x554F, 1130 0x5550, 1131 0x5551, 1132 0x5552, 1133 0x5554, 1134 0x564A, 1135 0x564B, 1136 0x564F, 1137 0x5652, 1138 0x5653, 1139 0x5657, 1140 0x5834, 1141 0x5835, 1142 0x5954, 1143 0x5955, 1144 0x5974, 1145 0x5975, 1146 0x5960, 1147 0x5961, 1148 0x5962, 1149 0x5964, 1150 0x5965, 1151 0x5969, 1152 0x5a41, 1153 0x5a42, 1154 0x5a61, 1155 0x5a62, 1156 0x5b60, 1157 0x5b62, 1158 0x5b63, 1159 0x5b64, 1160 0x5b65, 1161 0x5c61, 1162 0x5c63, 1163 0x5d48, 1164 0x5d49, 1165 0x5d4a, 1166 0x5d4c, 1167 0x5d4d, 1168 0x5d4e, 1169 0x5d4f, 1170 0x5d50, 1171 0x5d52, 1172 0x5d57, 1173 0x5e48, 1174 0x5e4a, 1175 0x5e4b, 1176 0x5e4c, 1177 0x5e4d, 1178 0x5e4f, 1179 0x6700, 1180 0x6701, 1181 0x6702, 1182 0x6703, 1183 0x6704, 1184 0x6705, 1185 0x6706, 1186 0x6707, 1187 0x6708, 1188 0x6709, 1189 0x6718, 1190 0x6719, 1191 0x671c, 1192 0x671d, 1193 0x671f, 1194 0x6720, 1195 0x6721, 1196 0x6722, 1197 0x6723, 1198 0x6724, 1199 0x6725, 1200 0x6726, 1201 0x6727, 1202 0x6728, 1203 0x6729, 1204 0x6738, 1205 0x6739, 1206 0x673e, 1207 0x6740, 1208 0x6741, 1209 0x6742, 1210 0x6743, 1211 0x6744, 1212 0x6745, 1213 0x6746, 1214 0x6747, 1215 0x6748, 1216 0x6749, 1217 0x674A, 1218 0x6750, 1219 0x6751, 1220 0x6758, 1221 0x6759, 1222 0x675B, 1223 0x675D, 1224 0x675F, 1225 0x6760, 1226 0x6761, 1227 0x6762, 1228 0x6763, 1229 0x6764, 1230 0x6765, 1231 0x6766, 1232 0x6767, 1233 0x6768, 1234 0x6770, 1235 0x6771, 1236 0x6772, 1237 0x6778, 1238 0x6779, 1239 0x677B, 1240 0x6840, 1241 0x6841, 1242 0x6842, 1243 0x6843, 1244 0x6849, 1245 0x684C, 1246 0x6850, 1247 0x6858, 1248 0x6859, 1249 0x6880, 1250 0x6888, 1251 0x6889, 1252 0x688A, 1253 0x688C, 1254 0x688D, 1255 0x6898, 1256 0x6899, 1257 0x689b, 1258 0x689c, 1259 0x689d, 1260 0x689e, 1261 0x68a0, 1262 0x68a1, 1263 0x68a8, 1264 0x68a9, 1265 0x68b0, 1266 0x68b8, 1267 0x68b9, 1268 0x68ba, 1269 0x68be, 1270 0x68bf, 1271 0x68c0, 1272 0x68c1, 1273 0x68c7, 1274 0x68c8, 1275 0x68c9, 1276 0x68d8, 1277 0x68d9, 1278 0x68da, 1279 0x68de, 1280 0x68e0, 1281 0x68e1, 1282 0x68e4, 1283 0x68e5, 1284 0x68e8, 1285 0x68e9, 1286 0x68f1, 1287 0x68f2, 1288 0x68f8, 1289 0x68f9, 1290 0x68fa, 1291 0x68fe, 1292 0x7100, 1293 0x7101, 1294 0x7102, 1295 0x7103, 1296 0x7104, 1297 0x7105, 1298 0x7106, 1299 0x7108, 1300 0x7109, 1301 0x710A, 1302 0x710B, 1303 0x710C, 1304 0x710E, 1305 0x710F, 1306 0x7140, 1307 0x7141, 1308 0x7142, 1309 0x7143, 1310 0x7144, 1311 0x7145, 1312 0x7146, 1313 0x7147, 1314 0x7149, 1315 0x714A, 1316 0x714B, 1317 0x714C, 1318 0x714D, 1319 0x714E, 1320 0x714F, 1321 0x7151, 1322 0x7152, 1323 0x7153, 1324 0x715E, 1325 0x715F, 1326 0x7180, 1327 0x7181, 1328 0x7183, 1329 0x7186, 1330 0x7187, 1331 0x7188, 1332 0x718A, 1333 0x718B, 1334 0x718C, 1335 0x718D, 1336 0x718F, 1337 0x7193, 1338 0x7196, 1339 0x719B, 1340 0x719F, 1341 0x71C0, 1342 0x71C1, 1343 0x71C2, 1344 0x71C3, 1345 0x71C4, 1346 0x71C5, 1347 0x71C6, 1348 0x71C7, 1349 0x71CD, 1350 0x71CE, 1351 0x71D2, 1352 0x71D4, 1353 0x71D5, 1354 0x71D6, 1355 0x71DA, 1356 0x71DE, 1357 0x7200, 1358 0x7210, 1359 0x7211, 1360 0x7240, 1361 0x7243, 1362 0x7244, 1363 0x7245, 1364 0x7246, 1365 0x7247, 1366 0x7248, 1367 0x7249, 1368 0x724A, 1369 0x724B, 1370 0x724C, 1371 0x724D, 1372 0x724E, 1373 0x724F, 1374 0x7280, 1375 0x7281, 1376 0x7283, 1377 0x7284, 1378 0x7287, 1379 0x7288, 1380 0x7289, 1381 0x728B, 1382 0x728C, 1383 0x7290, 1384 0x7291, 1385 0x7293, 1386 0x7297, 1387 0x7834, 1388 0x7835, 1389 0x791e, 1390 0x791f, 1391 0x793f, 1392 0x7941, 1393 0x7942, 1394 0x796c, 1395 0x796d, 1396 0x796e, 1397 0x796f, 1398 0x9400, 1399 0x9401, 1400 0x9402, 1401 0x9403, 1402 0x9405, 1403 0x940A, 1404 0x940B, 1405 0x940F, 1406 0x94A0, 1407 0x94A1, 1408 0x94A3, 1409 0x94B1, 1410 0x94B3, 1411 0x94B4, 1412 0x94B5, 1413 0x94B9, 1414 0x9440, 1415 0x9441, 1416 0x9442, 1417 0x9443, 1418 0x9444, 1419 0x9446, 1420 0x944A, 1421 0x944B, 1422 0x944C, 1423 0x944E, 1424 0x9450, 1425 0x9452, 1426 0x9456, 1427 0x945A, 1428 0x945B, 1429 0x945E, 1430 0x9460, 1431 0x9462, 1432 0x946A, 1433 0x946B, 1434 0x947A, 1435 0x947B, 1436 0x9480, 1437 0x9487, 1438 0x9488, 1439 0x9489, 1440 0x948A, 1441 0x948F, 1442 0x9490, 1443 0x9491, 1444 0x9495, 1445 0x9498, 1446 0x949C, 1447 0x949E, 1448 0x949F, 1449 0x94C0, 1450 0x94C1, 1451 0x94C3, 1452 0x94C4, 1453 0x94C5, 1454 0x94C6, 1455 0x94C7, 1456 0x94C8, 1457 0x94C9, 1458 0x94CB, 1459 0x94CC, 1460 0x94CD, 1461 0x9500, 1462 0x9501, 1463 0x9504, 1464 0x9505, 1465 0x9506, 1466 0x9507, 1467 0x9508, 1468 0x9509, 1469 0x950F, 1470 0x9511, 1471 0x9515, 1472 0x9517, 1473 0x9519, 1474 0x9540, 1475 0x9541, 1476 0x9542, 1477 0x954E, 1478 0x954F, 1479 0x9552, 1480 0x9553, 1481 0x9555, 1482 0x9557, 1483 0x955f, 1484 0x9580, 1485 0x9581, 1486 0x9583, 1487 0x9586, 1488 0x9587, 1489 0x9588, 1490 0x9589, 1491 0x958A, 1492 0x958B, 1493 0x958C, 1494 0x958D, 1495 0x958E, 1496 0x958F, 1497 0x9590, 1498 0x9591, 1499 0x9593, 1500 0x9595, 1501 0x9596, 1502 0x9597, 1503 0x9598, 1504 0x9599, 1505 0x959B, 1506 0x95C0, 1507 0x95C2, 1508 0x95C4, 1509 0x95C5, 1510 0x95C6, 1511 0x95C7, 1512 0x95C9, 1513 0x95CC, 1514 0x95CD, 1515 0x95CE, 1516 0x95CF, 1517 0x9610, 1518 0x9611, 1519 0x9612, 1520 0x9613, 1521 0x9614, 1522 0x9615, 1523 0x9616, 1524 0x9640, 1525 0x9641, 1526 0x9642, 1527 0x9643, 1528 0x9644, 1529 0x9645, 1530 0x9647, 1531 0x9648, 1532 0x9649, 1533 0x964a, 1534 0x964b, 1535 0x964c, 1536 0x964e, 1537 0x964f, 1538 0x9710, 1539 0x9711, 1540 0x9712, 1541 0x9713, 1542 0x9714, 1543 0x9715, 1544 0x9802, 1545 0x9803, 1546 0x9804, 1547 0x9805, 1548 0x9806, 1549 0x9807, 1550 0x9808, 1551 0x9809, 1552 0x980A, 1553 0x9900, 1554 0x9901, 1555 0x9903, 1556 0x9904, 1557 0x9905, 1558 0x9906, 1559 0x9907, 1560 0x9908, 1561 0x9909, 1562 0x990A, 1563 0x990B, 1564 0x990C, 1565 0x990D, 1566 0x990E, 1567 0x990F, 1568 0x9910, 1569 0x9913, 1570 0x9917, 1571 0x9918, 1572 0x9919, 1573 0x9990, 1574 0x9991, 1575 0x9992, 1576 0x9993, 1577 0x9994, 1578 0x9995, 1579 0x9996, 1580 0x9997, 1581 0x9998, 1582 0x9999, 1583 0x999A, 1584 0x999B, 1585 0x999C, 1586 0x999D, 1587 0x99A0, 1588 0x99A2, 1589 0x99A4, 1590 /* radeon secondary ids */ 1591 0x3171, 1592 0x3e70, 1593 0x4164, 1594 0x4165, 1595 0x4166, 1596 0x4168, 1597 0x4170, 1598 0x4171, 1599 0x4172, 1600 0x4173, 1601 0x496e, 1602 0x4a69, 1603 0x4a6a, 1604 0x4a6b, 1605 0x4a70, 1606 0x4a74, 1607 0x4b69, 1608 0x4b6b, 1609 0x4b6c, 1610 0x4c6e, 1611 0x4e64, 1612 0x4e65, 1613 0x4e66, 1614 0x4e67, 1615 0x4e68, 1616 0x4e69, 1617 0x4e6a, 1618 0x4e71, 1619 0x4f73, 1620 0x5569, 1621 0x556b, 1622 0x556d, 1623 0x556f, 1624 0x5571, 1625 0x5854, 1626 0x5874, 1627 0x5940, 1628 0x5941, 1629 0x5b70, 1630 0x5b72, 1631 0x5b73, 1632 0x5b74, 1633 0x5b75, 1634 0x5d44, 1635 0x5d45, 1636 0x5d6d, 1637 0x5d6f, 1638 0x5d72, 1639 0x5d77, 1640 0x5e6b, 1641 0x5e6d, 1642 0x7120, 1643 0x7124, 1644 0x7129, 1645 0x712e, 1646 0x712f, 1647 0x7162, 1648 0x7163, 1649 0x7166, 1650 0x7167, 1651 0x7172, 1652 0x7173, 1653 0x71a0, 1654 0x71a1, 1655 0x71a3, 1656 0x71a7, 1657 0x71bb, 1658 0x71e0, 1659 0x71e1, 1660 0x71e2, 1661 0x71e6, 1662 0x71e7, 1663 0x71f2, 1664 0x7269, 1665 0x726b, 1666 0x726e, 1667 0x72a0, 1668 0x72a8, 1669 0x72b1, 1670 0x72b3, 1671 0x793f, 1672 }; 1673 1674 static const struct pci_device_id pciidlist[] = { 1675 #ifdef CONFIG_DRM_AMDGPU_SI 1676 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1677 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1678 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1679 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1680 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1681 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1682 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1683 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1684 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1685 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1686 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1687 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1688 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1689 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1690 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1691 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1692 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1693 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1694 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1695 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1696 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1697 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1698 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1699 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1700 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1701 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1702 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1703 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1704 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1705 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1706 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1707 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1708 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1709 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1710 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1711 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1712 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1713 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1714 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1715 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1716 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1717 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1718 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1719 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1720 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1721 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1722 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1723 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1724 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1725 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1726 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1727 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1728 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1729 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1730 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1731 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1732 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1733 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1734 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1735 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1736 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1737 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1738 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1739 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1740 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1741 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1742 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1743 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1744 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1745 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1746 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1747 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1748 #endif 1749 #ifdef CONFIG_DRM_AMDGPU_CIK 1750 /* Kaveri */ 1751 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1752 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1753 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1754 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1755 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1756 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1757 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1758 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1759 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1760 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1761 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1762 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1763 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1764 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1765 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1766 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1767 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1768 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1769 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1770 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1771 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1772 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1773 /* Bonaire */ 1774 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1775 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1776 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1777 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1778 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1779 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1780 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1781 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1782 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1783 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1784 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1785 /* Hawaii */ 1786 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1787 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1788 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1789 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1790 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1791 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1792 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1793 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1794 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1795 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1796 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1797 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1798 /* Kabini */ 1799 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1800 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1801 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1802 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1803 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1804 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1805 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1806 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1807 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1808 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1809 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1810 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1811 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1812 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1813 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1814 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1815 /* mullins */ 1816 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1817 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1818 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1819 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1820 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1821 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1822 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1823 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1824 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1825 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1826 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1827 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1828 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1829 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1830 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1831 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1832 #endif 1833 /* topaz */ 1834 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1835 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1836 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1837 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1838 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1839 /* tonga */ 1840 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1841 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1842 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1843 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1844 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1845 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1846 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1847 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1848 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1849 /* fiji */ 1850 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1851 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1852 /* carrizo */ 1853 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1854 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1855 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1856 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1857 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1858 /* stoney */ 1859 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1860 /* Polaris11 */ 1861 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1862 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1863 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1864 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1865 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1866 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1867 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1868 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1869 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1870 /* Polaris10 */ 1871 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1872 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1873 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1874 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1875 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1876 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1877 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1878 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1879 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1880 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1881 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1882 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1883 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1884 /* Polaris12 */ 1885 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1886 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1887 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1888 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1889 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1890 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1891 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1892 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1893 /* VEGAM */ 1894 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1895 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1896 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1897 /* Vega 10 */ 1898 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1899 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1900 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1901 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1902 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1903 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1904 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1905 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1906 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1907 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1908 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1909 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1910 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1911 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1912 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1913 /* Vega 12 */ 1914 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1915 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1916 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1917 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1918 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1919 /* Vega 20 */ 1920 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1921 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1922 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1923 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1924 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1925 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1926 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1927 /* Raven */ 1928 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1929 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1930 /* Arcturus */ 1931 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1932 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1933 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1934 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1935 /* Navi10 */ 1936 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1937 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1938 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1939 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1940 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1941 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1942 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1943 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1944 /* Navi14 */ 1945 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1946 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1947 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1948 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1949 1950 /* Renoir */ 1951 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1952 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1953 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1954 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1955 1956 /* Navi12 */ 1957 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1958 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1959 1960 /* Sienna_Cichlid */ 1961 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1962 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1963 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1964 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1965 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1966 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1967 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1968 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1969 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1970 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1971 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1972 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1973 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1974 1975 /* Yellow Carp */ 1976 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1977 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1978 1979 /* Navy_Flounder */ 1980 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1981 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1982 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1983 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1984 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1985 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1986 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1987 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1988 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1989 1990 /* DIMGREY_CAVEFISH */ 1991 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1992 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1993 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1994 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1995 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1996 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1997 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1998 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1999 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2000 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2001 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2002 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2003 2004 /* Aldebaran */ 2005 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2006 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2007 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2008 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2009 2010 /* CYAN_SKILLFISH */ 2011 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2012 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2013 2014 /* BEIGE_GOBY */ 2015 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2016 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2017 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2018 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2019 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2020 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2021 2022 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2023 .class = PCI_CLASS_DISPLAY_VGA << 8, 2024 .class_mask = 0xffffff, 2025 .driver_data = CHIP_IP_DISCOVERY }, 2026 2027 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2028 .class = PCI_CLASS_DISPLAY_OTHER << 8, 2029 .class_mask = 0xffffff, 2030 .driver_data = CHIP_IP_DISCOVERY }, 2031 2032 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2033 .class = PCI_CLASS_ACCELERATOR_PROCESSING << 8, 2034 .class_mask = 0xffffff, 2035 .driver_data = CHIP_IP_DISCOVERY }, 2036 2037 {0, 0, 0} 2038 }; 2039 2040 MODULE_DEVICE_TABLE(pci, pciidlist); 2041 2042 static const struct drm_driver amdgpu_kms_driver; 2043 2044 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 2045 { 2046 struct pci_dev *p = NULL; 2047 int i; 2048 2049 /* 0 - GPU 2050 * 1 - audio 2051 * 2 - USB 2052 * 3 - UCSI 2053 */ 2054 for (i = 1; i < 4; i++) { 2055 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 2056 adev->pdev->bus->number, i); 2057 if (p) { 2058 pm_runtime_get_sync(&p->dev); 2059 pm_runtime_mark_last_busy(&p->dev); 2060 pm_runtime_put_autosuspend(&p->dev); 2061 pci_dev_put(p); 2062 } 2063 } 2064 } 2065 2066 static void amdgpu_init_debug_options(struct amdgpu_device *adev) 2067 { 2068 if (amdgpu_debug_mask & AMDGPU_DEBUG_VM) { 2069 pr_info("debug: VM handling debug enabled\n"); 2070 adev->debug_vm = true; 2071 } 2072 2073 if (amdgpu_debug_mask & AMDGPU_DEBUG_LARGEBAR) { 2074 pr_info("debug: enabled simulating large-bar capability on non-large bar system\n"); 2075 adev->debug_largebar = true; 2076 } 2077 2078 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY) { 2079 pr_info("debug: soft reset for GPU recovery disabled\n"); 2080 adev->debug_disable_soft_recovery = true; 2081 } 2082 } 2083 2084 static int amdgpu_pci_probe(struct pci_dev *pdev, 2085 const struct pci_device_id *ent) 2086 { 2087 struct drm_device *ddev; 2088 struct amdgpu_device *adev; 2089 unsigned long flags = ent->driver_data; 2090 int ret, retry = 0, i; 2091 bool supports_atomic = false; 2092 2093 /* skip devices which are owned by radeon */ 2094 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2095 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2096 return -ENODEV; 2097 } 2098 2099 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) 2100 amdgpu_aspm = 0; 2101 2102 if (amdgpu_virtual_display || 2103 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 2104 supports_atomic = true; 2105 2106 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2107 DRM_INFO("This hardware requires experimental hardware support.\n" 2108 "See modparam exp_hw_support\n"); 2109 return -ENODEV; 2110 } 2111 /* differentiate between P10 and P11 asics with the same DID */ 2112 if (pdev->device == 0x67FF && 2113 (pdev->revision == 0xE3 || 2114 pdev->revision == 0xE7 || 2115 pdev->revision == 0xF3 || 2116 pdev->revision == 0xF7)) { 2117 flags &= ~AMD_ASIC_MASK; 2118 flags |= CHIP_POLARIS10; 2119 } 2120 2121 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2122 * however, SME requires an indirect IOMMU mapping because the encryption 2123 * bit is beyond the DMA mask of the chip. 2124 */ 2125 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2126 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2127 dev_info(&pdev->dev, 2128 "SME is not compatible with RAVEN\n"); 2129 return -ENOTSUPP; 2130 } 2131 2132 #ifdef CONFIG_DRM_AMDGPU_SI 2133 if (!amdgpu_si_support) { 2134 switch (flags & AMD_ASIC_MASK) { 2135 case CHIP_TAHITI: 2136 case CHIP_PITCAIRN: 2137 case CHIP_VERDE: 2138 case CHIP_OLAND: 2139 case CHIP_HAINAN: 2140 dev_info(&pdev->dev, 2141 "SI support provided by radeon.\n"); 2142 dev_info(&pdev->dev, 2143 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 2144 ); 2145 return -ENODEV; 2146 } 2147 } 2148 #endif 2149 #ifdef CONFIG_DRM_AMDGPU_CIK 2150 if (!amdgpu_cik_support) { 2151 switch (flags & AMD_ASIC_MASK) { 2152 case CHIP_KAVERI: 2153 case CHIP_BONAIRE: 2154 case CHIP_HAWAII: 2155 case CHIP_KABINI: 2156 case CHIP_MULLINS: 2157 dev_info(&pdev->dev, 2158 "CIK support provided by radeon.\n"); 2159 dev_info(&pdev->dev, 2160 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 2161 ); 2162 return -ENODEV; 2163 } 2164 } 2165 #endif 2166 2167 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2168 if (IS_ERR(adev)) 2169 return PTR_ERR(adev); 2170 2171 adev->dev = &pdev->dev; 2172 adev->pdev = pdev; 2173 ddev = adev_to_drm(adev); 2174 2175 if (!supports_atomic) 2176 ddev->driver_features &= ~DRIVER_ATOMIC; 2177 2178 ret = pci_enable_device(pdev); 2179 if (ret) 2180 return ret; 2181 2182 pci_set_drvdata(pdev, ddev); 2183 2184 ret = amdgpu_driver_load_kms(adev, flags); 2185 if (ret) 2186 goto err_pci; 2187 2188 retry_init: 2189 ret = drm_dev_register(ddev, flags); 2190 if (ret == -EAGAIN && ++retry <= 3) { 2191 DRM_INFO("retry init %d\n", retry); 2192 /* Don't request EX mode too frequently which is attacking */ 2193 msleep(5000); 2194 goto retry_init; 2195 } else if (ret) { 2196 goto err_pci; 2197 } 2198 2199 ret = amdgpu_xcp_dev_register(adev, ent); 2200 if (ret) 2201 goto err_pci; 2202 2203 /* 2204 * 1. don't init fbdev on hw without DCE 2205 * 2. don't init fbdev if there are no connectors 2206 */ 2207 if (adev->mode_info.mode_config_initialized && 2208 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2209 /* select 8 bpp console on low vram cards */ 2210 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2211 drm_fbdev_generic_setup(adev_to_drm(adev), 8); 2212 else 2213 drm_fbdev_generic_setup(adev_to_drm(adev), 32); 2214 } 2215 2216 ret = amdgpu_debugfs_init(adev); 2217 if (ret) 2218 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2219 2220 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2221 /* only need to skip on ATPX */ 2222 if (amdgpu_device_supports_px(ddev)) 2223 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2224 /* we want direct complete for BOCO */ 2225 if (amdgpu_device_supports_boco(ddev)) 2226 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2227 DPM_FLAG_SMART_SUSPEND | 2228 DPM_FLAG_MAY_SKIP_RESUME); 2229 pm_runtime_use_autosuspend(ddev->dev); 2230 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2231 2232 pm_runtime_allow(ddev->dev); 2233 2234 pm_runtime_mark_last_busy(ddev->dev); 2235 pm_runtime_put_autosuspend(ddev->dev); 2236 2237 /* 2238 * For runpm implemented via BACO, PMFW will handle the 2239 * timing for BACO in and out: 2240 * - put ASIC into BACO state only when both video and 2241 * audio functions are in D3 state. 2242 * - pull ASIC out of BACO state when either video or 2243 * audio function is in D0 state. 2244 * Also, at startup, PMFW assumes both functions are in 2245 * D0 state. 2246 * 2247 * So if snd driver was loaded prior to amdgpu driver 2248 * and audio function was put into D3 state, there will 2249 * be no PMFW-aware D-state transition(D0->D3) on runpm 2250 * suspend. Thus the BACO will be not correctly kicked in. 2251 * 2252 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2253 * into D0 state. Then there will be a PMFW-aware D-state 2254 * transition(D0->D3) on runpm suspend. 2255 */ 2256 if (amdgpu_device_supports_baco(ddev) && 2257 !(adev->flags & AMD_IS_APU) && 2258 (adev->asic_type >= CHIP_NAVI10)) 2259 amdgpu_get_secondary_funcs(adev); 2260 } 2261 2262 amdgpu_init_debug_options(adev); 2263 2264 return 0; 2265 2266 err_pci: 2267 pci_disable_device(pdev); 2268 return ret; 2269 } 2270 2271 static void 2272 amdgpu_pci_remove(struct pci_dev *pdev) 2273 { 2274 struct drm_device *dev = pci_get_drvdata(pdev); 2275 struct amdgpu_device *adev = drm_to_adev(dev); 2276 2277 amdgpu_xcp_dev_unplug(adev); 2278 drm_dev_unplug(dev); 2279 2280 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2281 pm_runtime_get_sync(dev->dev); 2282 pm_runtime_forbid(dev->dev); 2283 } 2284 2285 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 2) && 2286 !amdgpu_sriov_vf(adev)) { 2287 bool need_to_reset_gpu = false; 2288 2289 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2290 struct amdgpu_hive_info *hive; 2291 2292 hive = amdgpu_get_xgmi_hive(adev); 2293 if (hive->device_remove_count == 0) 2294 need_to_reset_gpu = true; 2295 hive->device_remove_count++; 2296 amdgpu_put_xgmi_hive(hive); 2297 } else { 2298 need_to_reset_gpu = true; 2299 } 2300 2301 /* Workaround for ASICs need to reset SMU. 2302 * Called only when the first device is removed. 2303 */ 2304 if (need_to_reset_gpu) { 2305 struct amdgpu_reset_context reset_context; 2306 2307 adev->shutdown = true; 2308 memset(&reset_context, 0, sizeof(reset_context)); 2309 reset_context.method = AMD_RESET_METHOD_NONE; 2310 reset_context.reset_req_dev = adev; 2311 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2312 set_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context.flags); 2313 amdgpu_device_gpu_recover(adev, NULL, &reset_context); 2314 } 2315 } 2316 2317 amdgpu_driver_unload_kms(dev); 2318 2319 /* 2320 * Flush any in flight DMA operations from device. 2321 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2322 * StatusTransactions Pending bit. 2323 */ 2324 pci_disable_device(pdev); 2325 pci_wait_for_pending_transaction(pdev); 2326 } 2327 2328 static void 2329 amdgpu_pci_shutdown(struct pci_dev *pdev) 2330 { 2331 struct drm_device *dev = pci_get_drvdata(pdev); 2332 struct amdgpu_device *adev = drm_to_adev(dev); 2333 2334 if (amdgpu_ras_intr_triggered()) 2335 return; 2336 2337 /* if we are running in a VM, make sure the device 2338 * torn down properly on reboot/shutdown. 2339 * unfortunately we can't detect certain 2340 * hypervisors so just do this all the time. 2341 */ 2342 if (!amdgpu_passthrough(adev)) 2343 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2344 amdgpu_device_ip_suspend(adev); 2345 adev->mp1_state = PP_MP1_STATE_NONE; 2346 } 2347 2348 /** 2349 * amdgpu_drv_delayed_reset_work_handler - work handler for reset 2350 * 2351 * @work: work_struct. 2352 */ 2353 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) 2354 { 2355 struct list_head device_list; 2356 struct amdgpu_device *adev; 2357 int i, r; 2358 struct amdgpu_reset_context reset_context; 2359 2360 memset(&reset_context, 0, sizeof(reset_context)); 2361 2362 mutex_lock(&mgpu_info.mutex); 2363 if (mgpu_info.pending_reset == true) { 2364 mutex_unlock(&mgpu_info.mutex); 2365 return; 2366 } 2367 mgpu_info.pending_reset = true; 2368 mutex_unlock(&mgpu_info.mutex); 2369 2370 /* Use a common context, just need to make sure full reset is done */ 2371 reset_context.method = AMD_RESET_METHOD_NONE; 2372 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2373 2374 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2375 adev = mgpu_info.gpu_ins[i].adev; 2376 reset_context.reset_req_dev = adev; 2377 r = amdgpu_device_pre_asic_reset(adev, &reset_context); 2378 if (r) { 2379 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", 2380 r, adev_to_drm(adev)->unique); 2381 } 2382 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) 2383 r = -EALREADY; 2384 } 2385 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2386 adev = mgpu_info.gpu_ins[i].adev; 2387 flush_work(&adev->xgmi_reset_work); 2388 adev->gmc.xgmi.pending_reset = false; 2389 } 2390 2391 /* reset function will rebuild the xgmi hive info , clear it now */ 2392 for (i = 0; i < mgpu_info.num_dgpu; i++) 2393 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); 2394 2395 INIT_LIST_HEAD(&device_list); 2396 2397 for (i = 0; i < mgpu_info.num_dgpu; i++) 2398 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); 2399 2400 /* unregister the GPU first, reset function will add them back */ 2401 list_for_each_entry(adev, &device_list, reset_list) 2402 amdgpu_unregister_gpu_instance(adev); 2403 2404 /* Use a common context, just need to make sure full reset is done */ 2405 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); 2406 r = amdgpu_do_asic_reset(&device_list, &reset_context); 2407 2408 if (r) { 2409 DRM_ERROR("reinit gpus failure"); 2410 return; 2411 } 2412 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2413 adev = mgpu_info.gpu_ins[i].adev; 2414 if (!adev->kfd.init_complete) 2415 amdgpu_amdkfd_device_init(adev); 2416 amdgpu_ttm_set_buffer_funcs_status(adev, true); 2417 } 2418 } 2419 2420 static int amdgpu_pmops_prepare(struct device *dev) 2421 { 2422 struct drm_device *drm_dev = dev_get_drvdata(dev); 2423 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2424 2425 /* Return a positive number here so 2426 * DPM_FLAG_SMART_SUSPEND works properly 2427 */ 2428 if (amdgpu_device_supports_boco(drm_dev)) 2429 return pm_runtime_suspended(dev); 2430 2431 /* if we will not support s3 or s2i for the device 2432 * then skip suspend 2433 */ 2434 if (!amdgpu_acpi_is_s0ix_active(adev) && 2435 !amdgpu_acpi_is_s3_active(adev)) 2436 return 1; 2437 2438 return 0; 2439 } 2440 2441 static void amdgpu_pmops_complete(struct device *dev) 2442 { 2443 /* nothing to do */ 2444 } 2445 2446 static int amdgpu_pmops_suspend(struct device *dev) 2447 { 2448 struct drm_device *drm_dev = dev_get_drvdata(dev); 2449 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2450 2451 if (amdgpu_acpi_is_s0ix_active(adev)) 2452 adev->in_s0ix = true; 2453 else if (amdgpu_acpi_is_s3_active(adev)) 2454 adev->in_s3 = true; 2455 if (!adev->in_s0ix && !adev->in_s3) 2456 return 0; 2457 return amdgpu_device_suspend(drm_dev, true); 2458 } 2459 2460 static int amdgpu_pmops_suspend_noirq(struct device *dev) 2461 { 2462 struct drm_device *drm_dev = dev_get_drvdata(dev); 2463 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2464 2465 if (amdgpu_acpi_should_gpu_reset(adev)) 2466 return amdgpu_asic_reset(adev); 2467 2468 return 0; 2469 } 2470 2471 static int amdgpu_pmops_resume(struct device *dev) 2472 { 2473 struct drm_device *drm_dev = dev_get_drvdata(dev); 2474 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2475 int r; 2476 2477 if (!adev->in_s0ix && !adev->in_s3) 2478 return 0; 2479 2480 /* Avoids registers access if device is physically gone */ 2481 if (!pci_device_is_present(adev->pdev)) 2482 adev->no_hw_access = true; 2483 2484 r = amdgpu_device_resume(drm_dev, true); 2485 if (amdgpu_acpi_is_s0ix_active(adev)) 2486 adev->in_s0ix = false; 2487 else 2488 adev->in_s3 = false; 2489 return r; 2490 } 2491 2492 static int amdgpu_pmops_freeze(struct device *dev) 2493 { 2494 struct drm_device *drm_dev = dev_get_drvdata(dev); 2495 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2496 int r; 2497 2498 adev->in_s4 = true; 2499 r = amdgpu_device_suspend(drm_dev, true); 2500 adev->in_s4 = false; 2501 if (r) 2502 return r; 2503 2504 if (amdgpu_acpi_should_gpu_reset(adev)) 2505 return amdgpu_asic_reset(adev); 2506 return 0; 2507 } 2508 2509 static int amdgpu_pmops_thaw(struct device *dev) 2510 { 2511 struct drm_device *drm_dev = dev_get_drvdata(dev); 2512 2513 return amdgpu_device_resume(drm_dev, true); 2514 } 2515 2516 static int amdgpu_pmops_poweroff(struct device *dev) 2517 { 2518 struct drm_device *drm_dev = dev_get_drvdata(dev); 2519 2520 return amdgpu_device_suspend(drm_dev, true); 2521 } 2522 2523 static int amdgpu_pmops_restore(struct device *dev) 2524 { 2525 struct drm_device *drm_dev = dev_get_drvdata(dev); 2526 2527 return amdgpu_device_resume(drm_dev, true); 2528 } 2529 2530 static int amdgpu_runtime_idle_check_display(struct device *dev) 2531 { 2532 struct pci_dev *pdev = to_pci_dev(dev); 2533 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2534 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2535 2536 if (adev->mode_info.num_crtc) { 2537 struct drm_connector *list_connector; 2538 struct drm_connector_list_iter iter; 2539 int ret = 0; 2540 2541 if (amdgpu_runtime_pm != -2) { 2542 /* XXX: Return busy if any displays are connected to avoid 2543 * possible display wakeups after runtime resume due to 2544 * hotplug events in case any displays were connected while 2545 * the GPU was in suspend. Remove this once that is fixed. 2546 */ 2547 mutex_lock(&drm_dev->mode_config.mutex); 2548 drm_connector_list_iter_begin(drm_dev, &iter); 2549 drm_for_each_connector_iter(list_connector, &iter) { 2550 if (list_connector->status == connector_status_connected) { 2551 ret = -EBUSY; 2552 break; 2553 } 2554 } 2555 drm_connector_list_iter_end(&iter); 2556 mutex_unlock(&drm_dev->mode_config.mutex); 2557 2558 if (ret) 2559 return ret; 2560 } 2561 2562 if (adev->dc_enabled) { 2563 struct drm_crtc *crtc; 2564 2565 drm_for_each_crtc(crtc, drm_dev) { 2566 drm_modeset_lock(&crtc->mutex, NULL); 2567 if (crtc->state->active) 2568 ret = -EBUSY; 2569 drm_modeset_unlock(&crtc->mutex); 2570 if (ret < 0) 2571 break; 2572 } 2573 } else { 2574 mutex_lock(&drm_dev->mode_config.mutex); 2575 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2576 2577 drm_connector_list_iter_begin(drm_dev, &iter); 2578 drm_for_each_connector_iter(list_connector, &iter) { 2579 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2580 ret = -EBUSY; 2581 break; 2582 } 2583 } 2584 2585 drm_connector_list_iter_end(&iter); 2586 2587 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2588 mutex_unlock(&drm_dev->mode_config.mutex); 2589 } 2590 if (ret) 2591 return ret; 2592 } 2593 2594 return 0; 2595 } 2596 2597 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2598 { 2599 struct pci_dev *pdev = to_pci_dev(dev); 2600 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2601 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2602 int ret, i; 2603 2604 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2605 pm_runtime_forbid(dev); 2606 return -EBUSY; 2607 } 2608 2609 ret = amdgpu_runtime_idle_check_display(dev); 2610 if (ret) 2611 return ret; 2612 2613 /* wait for all rings to drain before suspending */ 2614 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2615 struct amdgpu_ring *ring = adev->rings[i]; 2616 2617 if (ring && ring->sched.ready) { 2618 ret = amdgpu_fence_wait_empty(ring); 2619 if (ret) 2620 return -EBUSY; 2621 } 2622 } 2623 2624 adev->in_runpm = true; 2625 if (amdgpu_device_supports_px(drm_dev)) 2626 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2627 2628 /* 2629 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2630 * proper cleanups and put itself into a state ready for PNP. That 2631 * can address some random resuming failure observed on BOCO capable 2632 * platforms. 2633 * TODO: this may be also needed for PX capable platform. 2634 */ 2635 if (amdgpu_device_supports_boco(drm_dev)) 2636 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2637 2638 ret = amdgpu_device_suspend(drm_dev, false); 2639 if (ret) { 2640 adev->in_runpm = false; 2641 if (amdgpu_device_supports_boco(drm_dev)) 2642 adev->mp1_state = PP_MP1_STATE_NONE; 2643 return ret; 2644 } 2645 2646 if (amdgpu_device_supports_boco(drm_dev)) 2647 adev->mp1_state = PP_MP1_STATE_NONE; 2648 2649 if (amdgpu_device_supports_px(drm_dev)) { 2650 /* Only need to handle PCI state in the driver for ATPX 2651 * PCI core handles it for _PR3. 2652 */ 2653 amdgpu_device_cache_pci_state(pdev); 2654 pci_disable_device(pdev); 2655 pci_ignore_hotplug(pdev); 2656 pci_set_power_state(pdev, PCI_D3cold); 2657 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2658 } else if (amdgpu_device_supports_boco(drm_dev)) { 2659 /* nothing to do */ 2660 } else if (amdgpu_device_supports_baco(drm_dev)) { 2661 amdgpu_device_baco_enter(drm_dev); 2662 } 2663 2664 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n"); 2665 2666 return 0; 2667 } 2668 2669 static int amdgpu_pmops_runtime_resume(struct device *dev) 2670 { 2671 struct pci_dev *pdev = to_pci_dev(dev); 2672 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2673 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2674 int ret; 2675 2676 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) 2677 return -EINVAL; 2678 2679 /* Avoids registers access if device is physically gone */ 2680 if (!pci_device_is_present(adev->pdev)) 2681 adev->no_hw_access = true; 2682 2683 if (amdgpu_device_supports_px(drm_dev)) { 2684 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2685 2686 /* Only need to handle PCI state in the driver for ATPX 2687 * PCI core handles it for _PR3. 2688 */ 2689 pci_set_power_state(pdev, PCI_D0); 2690 amdgpu_device_load_pci_state(pdev); 2691 ret = pci_enable_device(pdev); 2692 if (ret) 2693 return ret; 2694 pci_set_master(pdev); 2695 } else if (amdgpu_device_supports_boco(drm_dev)) { 2696 /* Only need to handle PCI state in the driver for ATPX 2697 * PCI core handles it for _PR3. 2698 */ 2699 pci_set_master(pdev); 2700 } else if (amdgpu_device_supports_baco(drm_dev)) { 2701 amdgpu_device_baco_exit(drm_dev); 2702 } 2703 ret = amdgpu_device_resume(drm_dev, false); 2704 if (ret) { 2705 if (amdgpu_device_supports_px(drm_dev)) 2706 pci_disable_device(pdev); 2707 return ret; 2708 } 2709 2710 if (amdgpu_device_supports_px(drm_dev)) 2711 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2712 adev->in_runpm = false; 2713 return 0; 2714 } 2715 2716 static int amdgpu_pmops_runtime_idle(struct device *dev) 2717 { 2718 struct drm_device *drm_dev = dev_get_drvdata(dev); 2719 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2720 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 2721 int ret = 1; 2722 2723 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2724 pm_runtime_forbid(dev); 2725 return -EBUSY; 2726 } 2727 2728 ret = amdgpu_runtime_idle_check_display(dev); 2729 2730 pm_runtime_mark_last_busy(dev); 2731 pm_runtime_autosuspend(dev); 2732 return ret; 2733 } 2734 2735 long amdgpu_drm_ioctl(struct file *filp, 2736 unsigned int cmd, unsigned long arg) 2737 { 2738 struct drm_file *file_priv = filp->private_data; 2739 struct drm_device *dev; 2740 long ret; 2741 2742 dev = file_priv->minor->dev; 2743 ret = pm_runtime_get_sync(dev->dev); 2744 if (ret < 0) 2745 goto out; 2746 2747 ret = drm_ioctl(filp, cmd, arg); 2748 2749 pm_runtime_mark_last_busy(dev->dev); 2750 out: 2751 pm_runtime_put_autosuspend(dev->dev); 2752 return ret; 2753 } 2754 2755 static const struct dev_pm_ops amdgpu_pm_ops = { 2756 .prepare = amdgpu_pmops_prepare, 2757 .complete = amdgpu_pmops_complete, 2758 .suspend = amdgpu_pmops_suspend, 2759 .suspend_noirq = amdgpu_pmops_suspend_noirq, 2760 .resume = amdgpu_pmops_resume, 2761 .freeze = amdgpu_pmops_freeze, 2762 .thaw = amdgpu_pmops_thaw, 2763 .poweroff = amdgpu_pmops_poweroff, 2764 .restore = amdgpu_pmops_restore, 2765 .runtime_suspend = amdgpu_pmops_runtime_suspend, 2766 .runtime_resume = amdgpu_pmops_runtime_resume, 2767 .runtime_idle = amdgpu_pmops_runtime_idle, 2768 }; 2769 2770 static int amdgpu_flush(struct file *f, fl_owner_t id) 2771 { 2772 struct drm_file *file_priv = f->private_data; 2773 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2774 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2775 2776 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 2777 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 2778 2779 return timeout >= 0 ? 0 : timeout; 2780 } 2781 2782 static const struct file_operations amdgpu_driver_kms_fops = { 2783 .owner = THIS_MODULE, 2784 .open = drm_open, 2785 .flush = amdgpu_flush, 2786 .release = drm_release, 2787 .unlocked_ioctl = amdgpu_drm_ioctl, 2788 .mmap = drm_gem_mmap, 2789 .poll = drm_poll, 2790 .read = drm_read, 2791 #ifdef CONFIG_COMPAT 2792 .compat_ioctl = amdgpu_kms_compat_ioctl, 2793 #endif 2794 #ifdef CONFIG_PROC_FS 2795 .show_fdinfo = drm_show_fdinfo, 2796 #endif 2797 }; 2798 2799 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 2800 { 2801 struct drm_file *file; 2802 2803 if (!filp) 2804 return -EINVAL; 2805 2806 if (filp->f_op != &amdgpu_driver_kms_fops) 2807 return -EINVAL; 2808 2809 file = filp->private_data; 2810 *fpriv = file->driver_priv; 2811 return 0; 2812 } 2813 2814 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 2815 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2816 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2817 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2818 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 2819 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2820 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2821 /* KMS */ 2822 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2823 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2824 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2825 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2826 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2827 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2828 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2829 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2830 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2831 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2832 }; 2833 2834 static const struct drm_driver amdgpu_kms_driver = { 2835 .driver_features = 2836 DRIVER_ATOMIC | 2837 DRIVER_GEM | 2838 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 2839 DRIVER_SYNCOBJ_TIMELINE, 2840 .open = amdgpu_driver_open_kms, 2841 .postclose = amdgpu_driver_postclose_kms, 2842 .lastclose = amdgpu_driver_lastclose_kms, 2843 .ioctls = amdgpu_ioctls_kms, 2844 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2845 .dumb_create = amdgpu_mode_dumb_create, 2846 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2847 .fops = &amdgpu_driver_kms_fops, 2848 .release = &amdgpu_driver_release_kms, 2849 #ifdef CONFIG_PROC_FS 2850 .show_fdinfo = amdgpu_show_fdinfo, 2851 #endif 2852 2853 .gem_prime_import = amdgpu_gem_prime_import, 2854 2855 .name = DRIVER_NAME, 2856 .desc = DRIVER_DESC, 2857 .date = DRIVER_DATE, 2858 .major = KMS_DRIVER_MAJOR, 2859 .minor = KMS_DRIVER_MINOR, 2860 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2861 }; 2862 2863 const struct drm_driver amdgpu_partition_driver = { 2864 .driver_features = 2865 DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ | 2866 DRIVER_SYNCOBJ_TIMELINE, 2867 .open = amdgpu_driver_open_kms, 2868 .postclose = amdgpu_driver_postclose_kms, 2869 .lastclose = amdgpu_driver_lastclose_kms, 2870 .ioctls = amdgpu_ioctls_kms, 2871 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2872 .dumb_create = amdgpu_mode_dumb_create, 2873 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2874 .fops = &amdgpu_driver_kms_fops, 2875 .release = &amdgpu_driver_release_kms, 2876 2877 .gem_prime_import = amdgpu_gem_prime_import, 2878 2879 .name = DRIVER_NAME, 2880 .desc = DRIVER_DESC, 2881 .date = DRIVER_DATE, 2882 .major = KMS_DRIVER_MAJOR, 2883 .minor = KMS_DRIVER_MINOR, 2884 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2885 }; 2886 2887 static struct pci_error_handlers amdgpu_pci_err_handler = { 2888 .error_detected = amdgpu_pci_error_detected, 2889 .mmio_enabled = amdgpu_pci_mmio_enabled, 2890 .slot_reset = amdgpu_pci_slot_reset, 2891 .resume = amdgpu_pci_resume, 2892 }; 2893 2894 static const struct attribute_group *amdgpu_sysfs_groups[] = { 2895 &amdgpu_vram_mgr_attr_group, 2896 &amdgpu_gtt_mgr_attr_group, 2897 &amdgpu_flash_attr_group, 2898 NULL, 2899 }; 2900 2901 static struct pci_driver amdgpu_kms_pci_driver = { 2902 .name = DRIVER_NAME, 2903 .id_table = pciidlist, 2904 .probe = amdgpu_pci_probe, 2905 .remove = amdgpu_pci_remove, 2906 .shutdown = amdgpu_pci_shutdown, 2907 .driver.pm = &amdgpu_pm_ops, 2908 .err_handler = &amdgpu_pci_err_handler, 2909 .dev_groups = amdgpu_sysfs_groups, 2910 }; 2911 2912 static int __init amdgpu_init(void) 2913 { 2914 int r; 2915 2916 if (drm_firmware_drivers_only()) 2917 return -EINVAL; 2918 2919 r = amdgpu_sync_init(); 2920 if (r) 2921 goto error_sync; 2922 2923 r = amdgpu_fence_slab_init(); 2924 if (r) 2925 goto error_fence; 2926 2927 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 2928 amdgpu_register_atpx_handler(); 2929 amdgpu_acpi_detect(); 2930 2931 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 2932 amdgpu_amdkfd_init(); 2933 2934 /* let modprobe override vga console setting */ 2935 return pci_register_driver(&amdgpu_kms_pci_driver); 2936 2937 error_fence: 2938 amdgpu_sync_fini(); 2939 2940 error_sync: 2941 return r; 2942 } 2943 2944 static void __exit amdgpu_exit(void) 2945 { 2946 amdgpu_amdkfd_fini(); 2947 pci_unregister_driver(&amdgpu_kms_pci_driver); 2948 amdgpu_unregister_atpx_handler(); 2949 amdgpu_acpi_release(); 2950 amdgpu_sync_fini(); 2951 amdgpu_fence_slab_fini(); 2952 mmu_notifier_synchronize(); 2953 amdgpu_xcp_drv_release(); 2954 } 2955 2956 module_init(amdgpu_init); 2957 module_exit(amdgpu_exit); 2958 2959 MODULE_AUTHOR(DRIVER_AUTHOR); 2960 MODULE_DESCRIPTION(DRIVER_DESC); 2961 MODULE_LICENSE("GPL and additional rights"); 2962