1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_drv.h> 27 #include <drm/drm_fbdev_ttm.h> 28 #include <drm/drm_gem.h> 29 #include <drm/drm_managed.h> 30 #include <drm/drm_pciids.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/drm_vblank.h> 33 34 #include <linux/cc_platform.h> 35 #include <linux/dynamic_debug.h> 36 #include <linux/module.h> 37 #include <linux/mmu_notifier.h> 38 #include <linux/pm_runtime.h> 39 #include <linux/suspend.h> 40 #include <linux/vga_switcheroo.h> 41 42 #include "amdgpu.h" 43 #include "amdgpu_amdkfd.h" 44 #include "amdgpu_dma_buf.h" 45 #include "amdgpu_drv.h" 46 #include "amdgpu_fdinfo.h" 47 #include "amdgpu_irq.h" 48 #include "amdgpu_psp.h" 49 #include "amdgpu_ras.h" 50 #include "amdgpu_reset.h" 51 #include "amdgpu_sched.h" 52 #include "amdgpu_xgmi.h" 53 #include "../amdxcp/amdgpu_xcp_drv.h" 54 55 /* 56 * KMS wrapper. 57 * - 3.0.0 - initial driver 58 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 59 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 60 * at the end of IBs. 61 * - 3.3.0 - Add VM support for UVD on supported hardware. 62 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 63 * - 3.5.0 - Add support for new UVD_NO_OP register. 64 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 65 * - 3.7.0 - Add support for VCE clock list packet 66 * - 3.8.0 - Add support raster config init in the kernel 67 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 68 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 69 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 70 * - 3.12.0 - Add query for double offchip LDS buffers 71 * - 3.13.0 - Add PRT support 72 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 73 * - 3.15.0 - Export more gpu info for gfx9 74 * - 3.16.0 - Add reserved vmid support 75 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 76 * - 3.18.0 - Export gpu always on cu bitmap 77 * - 3.19.0 - Add support for UVD MJPEG decode 78 * - 3.20.0 - Add support for local BOs 79 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 80 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 81 * - 3.23.0 - Add query for VRAM lost counter 82 * - 3.24.0 - Add high priority compute support for gfx9 83 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 84 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 85 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation. 86 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 87 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 88 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 89 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 90 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 91 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 92 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 93 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 94 * - 3.36.0 - Allow reading more status registers on si/cik 95 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 96 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 97 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 98 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 99 * - 3.41.0 - Add video codec query 100 * - 3.42.0 - Add 16bpc fixed point display support 101 * - 3.43.0 - Add device hot plug/unplug support 102 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 103 * - 3.45.0 - Add context ioctl stable pstate interface 104 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm 105 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags 106 * - 3.48.0 - Add IP discovery version info to HW INFO 107 * - 3.49.0 - Add gang submit into CS IOCTL 108 * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock 109 * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock 110 * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl 111 * 3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields: 112 * tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size, 113 * gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi 114 * 3.53.0 - Support for GFX11 CP GFX shadowing 115 * 3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support 116 * - 3.55.0 - Add AMDGPU_INFO_GPUVM_FAULT query 117 * - 3.56.0 - Update IB start address and size alignment for decode and encode 118 * - 3.57.0 - Compute tunneling on GFX10+ 119 * - 3.58.0 - Add GFX12 DCC support 120 * - 3.59.0 - Cleared VRAM 121 */ 122 #define KMS_DRIVER_MAJOR 3 123 #define KMS_DRIVER_MINOR 59 124 #define KMS_DRIVER_PATCHLEVEL 0 125 126 /* 127 * amdgpu.debug module options. Are all disabled by default 128 */ 129 enum AMDGPU_DEBUG_MASK { 130 AMDGPU_DEBUG_VM = BIT(0), 131 AMDGPU_DEBUG_LARGEBAR = BIT(1), 132 AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY = BIT(2), 133 AMDGPU_DEBUG_USE_VRAM_FW_BUF = BIT(3), 134 AMDGPU_DEBUG_ENABLE_RAS_ACA = BIT(4), 135 AMDGPU_DEBUG_ENABLE_EXP_RESETS = BIT(5), 136 }; 137 138 unsigned int amdgpu_vram_limit = UINT_MAX; 139 int amdgpu_vis_vram_limit; 140 int amdgpu_gart_size = -1; /* auto */ 141 int amdgpu_gtt_size = -1; /* auto */ 142 int amdgpu_moverate = -1; /* auto */ 143 int amdgpu_audio = -1; 144 int amdgpu_disp_priority; 145 int amdgpu_hw_i2c; 146 int amdgpu_pcie_gen2 = -1; 147 int amdgpu_msi = -1; 148 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 149 int amdgpu_dpm = -1; 150 int amdgpu_fw_load_type = -1; 151 int amdgpu_aspm = -1; 152 int amdgpu_runtime_pm = -1; 153 uint amdgpu_ip_block_mask = 0xffffffff; 154 int amdgpu_bapm = -1; 155 int amdgpu_deep_color; 156 int amdgpu_vm_size = -1; 157 int amdgpu_vm_fragment_size = -1; 158 int amdgpu_vm_block_size = -1; 159 int amdgpu_vm_fault_stop; 160 int amdgpu_vm_update_mode = -1; 161 int amdgpu_exp_hw_support; 162 int amdgpu_dc = -1; 163 int amdgpu_sched_jobs = 32; 164 int amdgpu_sched_hw_submission = 2; 165 uint amdgpu_pcie_gen_cap; 166 uint amdgpu_pcie_lane_cap; 167 u64 amdgpu_cg_mask = 0xffffffffffffffff; 168 uint amdgpu_pg_mask = 0xffffffff; 169 uint amdgpu_sdma_phase_quantum = 32; 170 char *amdgpu_disable_cu; 171 char *amdgpu_virtual_display; 172 bool enforce_isolation; 173 174 /* Specifies the default granularity for SVM, used in buffer 175 * migration and restoration of backing memory when handling 176 * recoverable page faults. 177 * 178 * The value is given as log(numPages(buffer)); for a 2 MiB 179 * buffer it computes to be 9 180 */ 181 uint amdgpu_svm_default_granularity = 9; 182 183 /* 184 * OverDrive(bit 14) disabled by default 185 * GFX DCS(bit 19) disabled by default 186 */ 187 uint amdgpu_pp_feature_mask = 0xfff7bfff; 188 uint amdgpu_force_long_training; 189 int amdgpu_lbpw = -1; 190 int amdgpu_compute_multipipe = -1; 191 int amdgpu_gpu_recovery = -1; /* auto */ 192 int amdgpu_emu_mode; 193 uint amdgpu_smu_memory_pool_size; 194 int amdgpu_smu_pptable_id = -1; 195 /* 196 * FBC (bit 0) disabled by default 197 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 198 * - With this, for multiple monitors in sync(e.g. with the same model), 199 * mclk switching will be allowed. And the mclk will be not foced to the 200 * highest. That helps saving some idle power. 201 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 202 * PSR (bit 3) disabled by default 203 * EDP NO POWER SEQUENCING (bit 4) disabled by default 204 */ 205 uint amdgpu_dc_feature_mask = 2; 206 uint amdgpu_dc_debug_mask; 207 uint amdgpu_dc_visual_confirm; 208 int amdgpu_async_gfx_ring = 1; 209 int amdgpu_mcbp = -1; 210 int amdgpu_discovery = -1; 211 int amdgpu_mes; 212 int amdgpu_mes_log_enable = 0; 213 int amdgpu_mes_kiq; 214 int amdgpu_uni_mes = 1; 215 int amdgpu_noretry = -1; 216 int amdgpu_force_asic_type = -1; 217 int amdgpu_tmz = -1; /* auto */ 218 uint amdgpu_freesync_vid_mode; 219 int amdgpu_reset_method = -1; /* auto */ 220 int amdgpu_num_kcq = -1; 221 int amdgpu_smartshift_bias; 222 int amdgpu_use_xgmi_p2p = 1; 223 int amdgpu_vcnfw_log; 224 int amdgpu_sg_display = -1; /* auto */ 225 int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE; 226 int amdgpu_umsch_mm; 227 int amdgpu_seamless = -1; /* auto */ 228 uint amdgpu_debug_mask; 229 int amdgpu_agp = -1; /* auto */ 230 int amdgpu_wbrf = -1; 231 int amdgpu_damage_clips = -1; /* auto */ 232 int amdgpu_umsch_mm_fwlog; 233 234 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 235 "DRM_UT_CORE", 236 "DRM_UT_DRIVER", 237 "DRM_UT_KMS", 238 "DRM_UT_PRIME", 239 "DRM_UT_ATOMIC", 240 "DRM_UT_VBL", 241 "DRM_UT_STATE", 242 "DRM_UT_LEASE", 243 "DRM_UT_DP", 244 "DRM_UT_DRMRES"); 245 246 struct amdgpu_mgpu_info mgpu_info = { 247 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 248 }; 249 int amdgpu_ras_enable = -1; 250 uint amdgpu_ras_mask = 0xffffffff; 251 int amdgpu_bad_page_threshold = -1; 252 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 253 .timeout_fatal_disable = false, 254 .period = 0x0, /* default to 0x0 (timeout disable) */ 255 }; 256 257 /** 258 * DOC: vramlimit (int) 259 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 260 */ 261 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 262 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 263 264 /** 265 * DOC: vis_vramlimit (int) 266 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 267 */ 268 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 269 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 270 271 /** 272 * DOC: gartsize (uint) 273 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing. 274 * The default is -1 (The size depends on asic). 275 */ 276 MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)"); 277 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 278 279 /** 280 * DOC: gttsize (int) 281 * Restrict the size of GTT domain (for userspace use) in MiB for testing. 282 * The default is -1 (Use 1/2 RAM, minimum value is 3GB). 283 */ 284 MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)"); 285 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 286 287 /** 288 * DOC: moverate (int) 289 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 290 */ 291 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 292 module_param_named(moverate, amdgpu_moverate, int, 0600); 293 294 /** 295 * DOC: audio (int) 296 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 297 */ 298 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 299 module_param_named(audio, amdgpu_audio, int, 0444); 300 301 /** 302 * DOC: disp_priority (int) 303 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 304 */ 305 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 306 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 307 308 /** 309 * DOC: hw_i2c (int) 310 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 311 */ 312 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 313 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 314 315 /** 316 * DOC: pcie_gen2 (int) 317 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 318 */ 319 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 320 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 321 322 /** 323 * DOC: msi (int) 324 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 325 */ 326 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 327 module_param_named(msi, amdgpu_msi, int, 0444); 328 329 /** 330 * DOC: svm_default_granularity (uint) 331 * Used in buffer migration and handling of recoverable page faults 332 */ 333 MODULE_PARM_DESC(svm_default_granularity, "SVM's default granularity in log(2^Pages), default 9 = 2^9 = 2 MiB"); 334 module_param_named(svm_default_granularity, amdgpu_svm_default_granularity, uint, 0644); 335 336 /** 337 * DOC: lockup_timeout (string) 338 * Set GPU scheduler timeout value in ms. 339 * 340 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 341 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 342 * to the default timeout. 343 * 344 * - With one value specified, the setting will apply to all non-compute jobs. 345 * - With multiple values specified, the first one will be for GFX. 346 * The second one is for Compute. The third and fourth ones are 347 * for SDMA and Video. 348 * 349 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 350 * jobs is 10000. The timeout for compute is 60000. 351 */ 352 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 353 "for passthrough or sriov, 10000 for all jobs. 0: keep default value. negative: infinity timeout), format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 354 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 355 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 356 357 /** 358 * DOC: dpm (int) 359 * Override for dynamic power management setting 360 * (0 = disable, 1 = enable) 361 * The default is -1 (auto). 362 */ 363 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 364 module_param_named(dpm, amdgpu_dpm, int, 0444); 365 366 /** 367 * DOC: fw_load_type (int) 368 * Set different firmware loading type for debugging, if supported. 369 * Set to 0 to force direct loading if supported by the ASIC. Set 370 * to -1 to select the default loading mode for the ASIC, as defined 371 * by the driver. The default is -1 (auto). 372 */ 373 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); 374 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 375 376 /** 377 * DOC: aspm (int) 378 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 379 */ 380 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 381 module_param_named(aspm, amdgpu_aspm, int, 0444); 382 383 /** 384 * DOC: runpm (int) 385 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 386 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 387 * Setting the value to 0 disables this functionality. 388 * Setting the value to -2 is auto enabled with power down when displays are attached. 389 */ 390 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto, -2 = auto with displays)"); 391 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 392 393 /** 394 * DOC: ip_block_mask (uint) 395 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 396 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 397 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 398 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 399 */ 400 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 401 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 402 403 /** 404 * DOC: bapm (int) 405 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 406 * The default -1 (auto, enabled) 407 */ 408 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 409 module_param_named(bapm, amdgpu_bapm, int, 0444); 410 411 /** 412 * DOC: deep_color (int) 413 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 414 */ 415 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 416 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 417 418 /** 419 * DOC: vm_size (int) 420 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 421 */ 422 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 423 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 424 425 /** 426 * DOC: vm_fragment_size (int) 427 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 428 */ 429 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 430 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 431 432 /** 433 * DOC: vm_block_size (int) 434 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 435 */ 436 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 437 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 438 439 /** 440 * DOC: vm_fault_stop (int) 441 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 442 */ 443 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 444 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 445 446 /** 447 * DOC: vm_update_mode (int) 448 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 449 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 450 */ 451 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 452 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 453 454 /** 455 * DOC: exp_hw_support (int) 456 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 457 */ 458 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 459 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 460 461 /** 462 * DOC: dc (int) 463 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 464 */ 465 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 466 module_param_named(dc, amdgpu_dc, int, 0444); 467 468 /** 469 * DOC: sched_jobs (int) 470 * Override the max number of jobs supported in the sw queue. The default is 32. 471 */ 472 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 473 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 474 475 /** 476 * DOC: sched_hw_submission (int) 477 * Override the max number of HW submissions. The default is 2. 478 */ 479 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 480 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 481 482 /** 483 * DOC: ppfeaturemask (hexint) 484 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 485 * The default is the current set of stable power features. 486 */ 487 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 488 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 489 490 /** 491 * DOC: forcelongtraining (uint) 492 * Force long memory training in resume. 493 * The default is zero, indicates short training in resume. 494 */ 495 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 496 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 497 498 /** 499 * DOC: pcie_gen_cap (uint) 500 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 501 * The default is 0 (automatic for each asic). 502 */ 503 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 504 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 505 506 /** 507 * DOC: pcie_lane_cap (uint) 508 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 509 * The default is 0 (automatic for each asic). 510 */ 511 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 512 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 513 514 /** 515 * DOC: cg_mask (ullong) 516 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 517 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 518 */ 519 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 520 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 521 522 /** 523 * DOC: pg_mask (uint) 524 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 525 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 526 */ 527 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 528 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 529 530 /** 531 * DOC: sdma_phase_quantum (uint) 532 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 533 */ 534 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 535 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 536 537 /** 538 * DOC: disable_cu (charp) 539 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 540 */ 541 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 542 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 543 544 /** 545 * DOC: virtual_display (charp) 546 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 547 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 548 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 549 * device at 26:00.0. The default is NULL. 550 */ 551 MODULE_PARM_DESC(virtual_display, 552 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 553 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 554 555 /** 556 * DOC: lbpw (int) 557 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 558 */ 559 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 560 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 561 562 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 563 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 564 565 /** 566 * DOC: gpu_recovery (int) 567 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 568 */ 569 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 570 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 571 572 /** 573 * DOC: emu_mode (int) 574 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 575 */ 576 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 577 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 578 579 /** 580 * DOC: ras_enable (int) 581 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 582 */ 583 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 584 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 585 586 /** 587 * DOC: ras_mask (uint) 588 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 589 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 590 */ 591 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 592 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 593 594 /** 595 * DOC: timeout_fatal_disable (bool) 596 * Disable Watchdog timeout fatal error event 597 */ 598 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 599 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 600 601 /** 602 * DOC: timeout_period (uint) 603 * Modify the watchdog timeout max_cycles as (1 << period) 604 */ 605 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 606 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 607 608 /** 609 * DOC: si_support (int) 610 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 611 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 612 * otherwise using amdgpu driver. 613 */ 614 #ifdef CONFIG_DRM_AMDGPU_SI 615 616 #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) 617 int amdgpu_si_support; 618 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 619 #else 620 int amdgpu_si_support = 1; 621 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 622 #endif 623 624 module_param_named(si_support, amdgpu_si_support, int, 0444); 625 #endif 626 627 /** 628 * DOC: cik_support (int) 629 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 630 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 631 * otherwise using amdgpu driver. 632 */ 633 #ifdef CONFIG_DRM_AMDGPU_CIK 634 635 #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) 636 int amdgpu_cik_support; 637 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 638 #else 639 int amdgpu_cik_support = 1; 640 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 641 #endif 642 643 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 644 #endif 645 646 /** 647 * DOC: smu_memory_pool_size (uint) 648 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 649 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 650 */ 651 MODULE_PARM_DESC(smu_memory_pool_size, 652 "reserve gtt for smu debug usage, 0 = disable,0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 653 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 654 655 /** 656 * DOC: async_gfx_ring (int) 657 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 658 */ 659 MODULE_PARM_DESC(async_gfx_ring, 660 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 661 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 662 663 /** 664 * DOC: mcbp (int) 665 * It is used to enable mid command buffer preemption. (0 = disabled, 1 = enabled, -1 auto (default)) 666 */ 667 MODULE_PARM_DESC(mcbp, 668 "Enable Mid-command buffer preemption (0 = disabled, 1 = enabled), -1 = auto (default)"); 669 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 670 671 /** 672 * DOC: discovery (int) 673 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 674 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 675 */ 676 MODULE_PARM_DESC(discovery, 677 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 678 module_param_named(discovery, amdgpu_discovery, int, 0444); 679 680 /** 681 * DOC: mes (int) 682 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 683 * (0 = disabled (default), 1 = enabled) 684 */ 685 MODULE_PARM_DESC(mes, 686 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 687 module_param_named(mes, amdgpu_mes, int, 0444); 688 689 /** 690 * DOC: mes_log_enable (int) 691 * Enable Micro Engine Scheduler log. This is used to enable/disable MES internal log. 692 * (0 = disabled (default), 1 = enabled) 693 */ 694 MODULE_PARM_DESC(mes_log_enable, 695 "Enable Micro Engine Scheduler log (0 = disabled (default), 1 = enabled)"); 696 module_param_named(mes_log_enable, amdgpu_mes_log_enable, int, 0444); 697 698 /** 699 * DOC: mes_kiq (int) 700 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq. 701 * (0 = disabled (default), 1 = enabled) 702 */ 703 MODULE_PARM_DESC(mes_kiq, 704 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)"); 705 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444); 706 707 /** 708 * DOC: uni_mes (int) 709 * Enable Unified Micro Engine Scheduler. This is a new engine pipe for unified scheduler. 710 * (0 = disabled (default), 1 = enabled) 711 */ 712 MODULE_PARM_DESC(uni_mes, 713 "Enable Unified Micro Engine Scheduler (0 = disabled, 1 = enabled(default)"); 714 module_param_named(uni_mes, amdgpu_uni_mes, int, 0444); 715 716 /** 717 * DOC: noretry (int) 718 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 719 * do not support per-process XNACK this also disables retry page faults. 720 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 721 */ 722 MODULE_PARM_DESC(noretry, 723 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 724 module_param_named(noretry, amdgpu_noretry, int, 0644); 725 726 /** 727 * DOC: force_asic_type (int) 728 * A non negative value used to specify the asic type for all supported GPUs. 729 */ 730 MODULE_PARM_DESC(force_asic_type, 731 "A non negative value used to specify the asic type for all supported GPUs"); 732 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 733 734 /** 735 * DOC: use_xgmi_p2p (int) 736 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 737 */ 738 MODULE_PARM_DESC(use_xgmi_p2p, 739 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 740 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 741 742 743 #ifdef CONFIG_HSA_AMD 744 /** 745 * DOC: sched_policy (int) 746 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 747 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 748 * assigns queues to HQDs. 749 */ 750 int sched_policy = KFD_SCHED_POLICY_HWS; 751 module_param(sched_policy, int, 0444); 752 MODULE_PARM_DESC(sched_policy, 753 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 754 755 /** 756 * DOC: hws_max_conc_proc (int) 757 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 758 * number of VMIDs assigned to the HWS, which is also the default. 759 */ 760 int hws_max_conc_proc = -1; 761 module_param(hws_max_conc_proc, int, 0444); 762 MODULE_PARM_DESC(hws_max_conc_proc, 763 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 764 765 /** 766 * DOC: cwsr_enable (int) 767 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 768 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 769 * disables it. 770 */ 771 int cwsr_enable = 1; 772 module_param(cwsr_enable, int, 0444); 773 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 774 775 /** 776 * DOC: max_num_of_queues_per_device (int) 777 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 778 * is 4096. 779 */ 780 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 781 module_param(max_num_of_queues_per_device, int, 0444); 782 MODULE_PARM_DESC(max_num_of_queues_per_device, 783 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 784 785 /** 786 * DOC: send_sigterm (int) 787 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 788 * but just print errors on dmesg. Setting 1 enables sending sigterm. 789 */ 790 int send_sigterm; 791 module_param(send_sigterm, int, 0444); 792 MODULE_PARM_DESC(send_sigterm, 793 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 794 795 /** 796 * DOC: halt_if_hws_hang (int) 797 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 798 * Setting 1 enables halt on hang. 799 */ 800 int halt_if_hws_hang; 801 module_param(halt_if_hws_hang, int, 0644); 802 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 803 804 /** 805 * DOC: hws_gws_support(bool) 806 * Assume that HWS supports GWS barriers regardless of what firmware version 807 * check says. Default value: false (rely on MEC2 firmware version check). 808 */ 809 bool hws_gws_support; 810 module_param(hws_gws_support, bool, 0444); 811 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 812 813 /** 814 * DOC: queue_preemption_timeout_ms (int) 815 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 816 */ 817 int queue_preemption_timeout_ms = 9000; 818 module_param(queue_preemption_timeout_ms, int, 0644); 819 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 820 821 /** 822 * DOC: debug_evictions(bool) 823 * Enable extra debug messages to help determine the cause of evictions 824 */ 825 bool debug_evictions; 826 module_param(debug_evictions, bool, 0644); 827 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 828 829 /** 830 * DOC: no_system_mem_limit(bool) 831 * Disable system memory limit, to support multiple process shared memory 832 */ 833 bool no_system_mem_limit; 834 module_param(no_system_mem_limit, bool, 0644); 835 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 836 837 /** 838 * DOC: no_queue_eviction_on_vm_fault (int) 839 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 840 */ 841 int amdgpu_no_queue_eviction_on_vm_fault; 842 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 843 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 844 #endif 845 846 /** 847 * DOC: mtype_local (int) 848 */ 849 int amdgpu_mtype_local; 850 MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (0 = MTYPE_RW (default), 1 = MTYPE_NC, 2 = MTYPE_CC)"); 851 module_param_named(mtype_local, amdgpu_mtype_local, int, 0444); 852 853 /** 854 * DOC: pcie_p2p (bool) 855 * Enable PCIe P2P (requires large-BAR). Default value: true (on) 856 */ 857 #ifdef CONFIG_HSA_AMD_P2P 858 bool pcie_p2p = true; 859 module_param(pcie_p2p, bool, 0444); 860 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); 861 #endif 862 863 /** 864 * DOC: dcfeaturemask (uint) 865 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 866 * The default is the current set of stable display features. 867 */ 868 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 869 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 870 871 /** 872 * DOC: dcdebugmask (uint) 873 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 874 */ 875 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 876 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 877 878 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)"); 879 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444); 880 881 /** 882 * DOC: abmlevel (uint) 883 * Override the default ABM (Adaptive Backlight Management) level used for DC 884 * enabled hardware. Requires DMCU to be supported and loaded. 885 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 886 * default. Values 1-4 control the maximum allowable brightness reduction via 887 * the ABM algorithm, with 1 being the least reduction and 4 being the most 888 * reduction. 889 * 890 * Defaults to -1, or disabled. Userspace can only override this level after 891 * boot if it's set to auto. 892 */ 893 int amdgpu_dm_abm_level = -1; 894 MODULE_PARM_DESC(abmlevel, 895 "ABM level (0 = off, 1-4 = backlight reduction level, -1 auto (default))"); 896 module_param_named(abmlevel, amdgpu_dm_abm_level, int, 0444); 897 898 int amdgpu_backlight = -1; 899 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 900 module_param_named(backlight, amdgpu_backlight, bint, 0444); 901 902 /** 903 * DOC: damageclips (int) 904 * Enable or disable damage clips support. If damage clips support is disabled, 905 * we will force full frame updates, irrespective of what user space sends to 906 * us. 907 * 908 * Defaults to -1 (where it is enabled unless a PSR-SU display is detected). 909 */ 910 MODULE_PARM_DESC(damageclips, 911 "Damage clips support (0 = disable, 1 = enable, -1 auto (default))"); 912 module_param_named(damageclips, amdgpu_damage_clips, int, 0444); 913 914 /** 915 * DOC: tmz (int) 916 * Trusted Memory Zone (TMZ) is a method to protect data being written 917 * to or read from memory. 918 * 919 * The default value: 0 (off). TODO: change to auto till it is completed. 920 */ 921 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 922 module_param_named(tmz, amdgpu_tmz, int, 0444); 923 924 /** 925 * DOC: freesync_video (uint) 926 * Enable the optimization to adjust front porch timing to achieve seamless 927 * mode change experience when setting a freesync supported mode for which full 928 * modeset is not needed. 929 * 930 * The Display Core will add a set of modes derived from the base FreeSync 931 * video mode into the corresponding connector's mode list based on commonly 932 * used refresh rates and VRR range of the connected display, when users enable 933 * this feature. From the userspace perspective, they can see a seamless mode 934 * change experience when the change between different refresh rates under the 935 * same resolution. Additionally, userspace applications such as Video playback 936 * can read this modeset list and change the refresh rate based on the video 937 * frame rate. Finally, the userspace can also derive an appropriate mode for a 938 * particular refresh rate based on the FreeSync Mode and add it to the 939 * connector's mode list. 940 * 941 * Note: This is an experimental feature. 942 * 943 * The default value: 0 (off). 944 */ 945 MODULE_PARM_DESC( 946 freesync_video, 947 "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)"); 948 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); 949 950 /** 951 * DOC: reset_method (int) 952 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 953 */ 954 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 955 module_param_named(reset_method, amdgpu_reset_method, int, 0644); 956 957 /** 958 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 959 * threshold value of faulty pages detected by RAS ECC, which may 960 * result in the GPU entering bad status when the number of total 961 * faulty pages by ECC exceeds the threshold value. 962 */ 963 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = driver sets threshold)"); 964 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 965 966 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 967 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 968 969 /** 970 * DOC: vcnfw_log (int) 971 * Enable vcnfw log output for debugging, the default is disabled. 972 */ 973 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 974 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 975 976 /** 977 * DOC: sg_display (int) 978 * Disable S/G (scatter/gather) display (i.e., display from system memory). 979 * This option is only relevant on APUs. Set this option to 0 to disable 980 * S/G display if you experience flickering or other issues under memory 981 * pressure and report the issue. 982 */ 983 MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)"); 984 module_param_named(sg_display, amdgpu_sg_display, int, 0444); 985 986 /** 987 * DOC: umsch_mm (int) 988 * Enable Multi Media User Mode Scheduler. This is a HW scheduling engine for VCN and VPE. 989 * (0 = disabled (default), 1 = enabled) 990 */ 991 MODULE_PARM_DESC(umsch_mm, 992 "Enable Multi Media User Mode Scheduler (0 = disabled (default), 1 = enabled)"); 993 module_param_named(umsch_mm, amdgpu_umsch_mm, int, 0444); 994 995 /** 996 * DOC: umsch_mm_fwlog (int) 997 * Enable umschfw log output for debugging, the default is disabled. 998 */ 999 MODULE_PARM_DESC(umsch_mm_fwlog, "Enable umschfw log(0 = disable (default value), 1 = enable)"); 1000 module_param_named(umsch_mm_fwlog, amdgpu_umsch_mm_fwlog, int, 0444); 1001 1002 /** 1003 * DOC: smu_pptable_id (int) 1004 * Used to override pptable id. id = 0 use VBIOS pptable. 1005 * id > 0 use the soft pptable with specicfied id. 1006 */ 1007 MODULE_PARM_DESC(smu_pptable_id, 1008 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 1009 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 1010 1011 /** 1012 * DOC: partition_mode (int) 1013 * Used to override the default SPX mode. 1014 */ 1015 MODULE_PARM_DESC( 1016 user_partt_mode, 1017 "specify partition mode to be used (-2 = AMDGPU_AUTO_COMPUTE_PARTITION_MODE(default value) \ 1018 0 = AMDGPU_SPX_PARTITION_MODE, \ 1019 1 = AMDGPU_DPX_PARTITION_MODE, \ 1020 2 = AMDGPU_TPX_PARTITION_MODE, \ 1021 3 = AMDGPU_QPX_PARTITION_MODE, \ 1022 4 = AMDGPU_CPX_PARTITION_MODE)"); 1023 module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint, 0444); 1024 1025 1026 /** 1027 * DOC: enforce_isolation (bool) 1028 * enforce process isolation between graphics and compute via using the same reserved vmid. 1029 */ 1030 module_param(enforce_isolation, bool, 0444); 1031 MODULE_PARM_DESC(enforce_isolation, "enforce process isolation between graphics and compute . enforce_isolation = on"); 1032 1033 /** 1034 * DOC: seamless (int) 1035 * Seamless boot will keep the image on the screen during the boot process. 1036 */ 1037 MODULE_PARM_DESC(seamless, "Seamless boot (-1 = auto (default), 0 = disable, 1 = enable)"); 1038 module_param_named(seamless, amdgpu_seamless, int, 0444); 1039 1040 /** 1041 * DOC: debug_mask (uint) 1042 * Debug options for amdgpu, work as a binary mask with the following options: 1043 * 1044 * - 0x1: Debug VM handling 1045 * - 0x2: Enable simulating large-bar capability on non-large bar system. This 1046 * limits the VRAM size reported to ROCm applications to the visible 1047 * size, usually 256MB. 1048 * - 0x4: Disable GPU soft recovery, always do a full reset 1049 */ 1050 MODULE_PARM_DESC(debug_mask, "debug options for amdgpu, disabled by default"); 1051 module_param_named(debug_mask, amdgpu_debug_mask, uint, 0444); 1052 1053 /** 1054 * DOC: agp (int) 1055 * Enable the AGP aperture. This provides an aperture in the GPU's internal 1056 * address space for direct access to system memory. Note that these accesses 1057 * are non-snooped, so they are only used for access to uncached memory. 1058 */ 1059 MODULE_PARM_DESC(agp, "AGP (-1 = auto (default), 0 = disable, 1 = enable)"); 1060 module_param_named(agp, amdgpu_agp, int, 0444); 1061 1062 /** 1063 * DOC: wbrf (int) 1064 * Enable Wifi RFI interference mitigation feature. 1065 * Due to electrical and mechanical constraints there may be likely interference of 1066 * relatively high-powered harmonics of the (G-)DDR memory clocks with local radio 1067 * module frequency bands used by Wifi 6/6e/7. To mitigate the possible RFI interference, 1068 * with this feature enabled, PMFW will use either “shadowed P-State” or “P-State” based 1069 * on active list of frequencies in-use (to be avoided) as part of initial setting or 1070 * P-state transition. However, there may be potential performance impact with this 1071 * feature enabled. 1072 * (0 = disabled, 1 = enabled, -1 = auto (default setting, will be enabled if supported)) 1073 */ 1074 MODULE_PARM_DESC(wbrf, 1075 "Enable Wifi RFI interference mitigation (0 = disabled, 1 = enabled, -1 = auto(default)"); 1076 module_param_named(wbrf, amdgpu_wbrf, int, 0444); 1077 1078 /* These devices are not supported by amdgpu. 1079 * They are supported by the mach64, r128, radeon drivers 1080 */ 1081 static const u16 amdgpu_unsupported_pciidlist[] = { 1082 /* mach64 */ 1083 0x4354, 1084 0x4358, 1085 0x4554, 1086 0x4742, 1087 0x4744, 1088 0x4749, 1089 0x474C, 1090 0x474D, 1091 0x474E, 1092 0x474F, 1093 0x4750, 1094 0x4751, 1095 0x4752, 1096 0x4753, 1097 0x4754, 1098 0x4755, 1099 0x4756, 1100 0x4757, 1101 0x4758, 1102 0x4759, 1103 0x475A, 1104 0x4C42, 1105 0x4C44, 1106 0x4C47, 1107 0x4C49, 1108 0x4C4D, 1109 0x4C4E, 1110 0x4C50, 1111 0x4C51, 1112 0x4C52, 1113 0x4C53, 1114 0x5654, 1115 0x5655, 1116 0x5656, 1117 /* r128 */ 1118 0x4c45, 1119 0x4c46, 1120 0x4d46, 1121 0x4d4c, 1122 0x5041, 1123 0x5042, 1124 0x5043, 1125 0x5044, 1126 0x5045, 1127 0x5046, 1128 0x5047, 1129 0x5048, 1130 0x5049, 1131 0x504A, 1132 0x504B, 1133 0x504C, 1134 0x504D, 1135 0x504E, 1136 0x504F, 1137 0x5050, 1138 0x5051, 1139 0x5052, 1140 0x5053, 1141 0x5054, 1142 0x5055, 1143 0x5056, 1144 0x5057, 1145 0x5058, 1146 0x5245, 1147 0x5246, 1148 0x5247, 1149 0x524b, 1150 0x524c, 1151 0x534d, 1152 0x5446, 1153 0x544C, 1154 0x5452, 1155 /* radeon */ 1156 0x3150, 1157 0x3151, 1158 0x3152, 1159 0x3154, 1160 0x3155, 1161 0x3E50, 1162 0x3E54, 1163 0x4136, 1164 0x4137, 1165 0x4144, 1166 0x4145, 1167 0x4146, 1168 0x4147, 1169 0x4148, 1170 0x4149, 1171 0x414A, 1172 0x414B, 1173 0x4150, 1174 0x4151, 1175 0x4152, 1176 0x4153, 1177 0x4154, 1178 0x4155, 1179 0x4156, 1180 0x4237, 1181 0x4242, 1182 0x4336, 1183 0x4337, 1184 0x4437, 1185 0x4966, 1186 0x4967, 1187 0x4A48, 1188 0x4A49, 1189 0x4A4A, 1190 0x4A4B, 1191 0x4A4C, 1192 0x4A4D, 1193 0x4A4E, 1194 0x4A4F, 1195 0x4A50, 1196 0x4A54, 1197 0x4B48, 1198 0x4B49, 1199 0x4B4A, 1200 0x4B4B, 1201 0x4B4C, 1202 0x4C57, 1203 0x4C58, 1204 0x4C59, 1205 0x4C5A, 1206 0x4C64, 1207 0x4C66, 1208 0x4C67, 1209 0x4E44, 1210 0x4E45, 1211 0x4E46, 1212 0x4E47, 1213 0x4E48, 1214 0x4E49, 1215 0x4E4A, 1216 0x4E4B, 1217 0x4E50, 1218 0x4E51, 1219 0x4E52, 1220 0x4E53, 1221 0x4E54, 1222 0x4E56, 1223 0x5144, 1224 0x5145, 1225 0x5146, 1226 0x5147, 1227 0x5148, 1228 0x514C, 1229 0x514D, 1230 0x5157, 1231 0x5158, 1232 0x5159, 1233 0x515A, 1234 0x515E, 1235 0x5460, 1236 0x5462, 1237 0x5464, 1238 0x5548, 1239 0x5549, 1240 0x554A, 1241 0x554B, 1242 0x554C, 1243 0x554D, 1244 0x554E, 1245 0x554F, 1246 0x5550, 1247 0x5551, 1248 0x5552, 1249 0x5554, 1250 0x564A, 1251 0x564B, 1252 0x564F, 1253 0x5652, 1254 0x5653, 1255 0x5657, 1256 0x5834, 1257 0x5835, 1258 0x5954, 1259 0x5955, 1260 0x5974, 1261 0x5975, 1262 0x5960, 1263 0x5961, 1264 0x5962, 1265 0x5964, 1266 0x5965, 1267 0x5969, 1268 0x5a41, 1269 0x5a42, 1270 0x5a61, 1271 0x5a62, 1272 0x5b60, 1273 0x5b62, 1274 0x5b63, 1275 0x5b64, 1276 0x5b65, 1277 0x5c61, 1278 0x5c63, 1279 0x5d48, 1280 0x5d49, 1281 0x5d4a, 1282 0x5d4c, 1283 0x5d4d, 1284 0x5d4e, 1285 0x5d4f, 1286 0x5d50, 1287 0x5d52, 1288 0x5d57, 1289 0x5e48, 1290 0x5e4a, 1291 0x5e4b, 1292 0x5e4c, 1293 0x5e4d, 1294 0x5e4f, 1295 0x6700, 1296 0x6701, 1297 0x6702, 1298 0x6703, 1299 0x6704, 1300 0x6705, 1301 0x6706, 1302 0x6707, 1303 0x6708, 1304 0x6709, 1305 0x6718, 1306 0x6719, 1307 0x671c, 1308 0x671d, 1309 0x671f, 1310 0x6720, 1311 0x6721, 1312 0x6722, 1313 0x6723, 1314 0x6724, 1315 0x6725, 1316 0x6726, 1317 0x6727, 1318 0x6728, 1319 0x6729, 1320 0x6738, 1321 0x6739, 1322 0x673e, 1323 0x6740, 1324 0x6741, 1325 0x6742, 1326 0x6743, 1327 0x6744, 1328 0x6745, 1329 0x6746, 1330 0x6747, 1331 0x6748, 1332 0x6749, 1333 0x674A, 1334 0x6750, 1335 0x6751, 1336 0x6758, 1337 0x6759, 1338 0x675B, 1339 0x675D, 1340 0x675F, 1341 0x6760, 1342 0x6761, 1343 0x6762, 1344 0x6763, 1345 0x6764, 1346 0x6765, 1347 0x6766, 1348 0x6767, 1349 0x6768, 1350 0x6770, 1351 0x6771, 1352 0x6772, 1353 0x6778, 1354 0x6779, 1355 0x677B, 1356 0x6840, 1357 0x6841, 1358 0x6842, 1359 0x6843, 1360 0x6849, 1361 0x684C, 1362 0x6850, 1363 0x6858, 1364 0x6859, 1365 0x6880, 1366 0x6888, 1367 0x6889, 1368 0x688A, 1369 0x688C, 1370 0x688D, 1371 0x6898, 1372 0x6899, 1373 0x689b, 1374 0x689c, 1375 0x689d, 1376 0x689e, 1377 0x68a0, 1378 0x68a1, 1379 0x68a8, 1380 0x68a9, 1381 0x68b0, 1382 0x68b8, 1383 0x68b9, 1384 0x68ba, 1385 0x68be, 1386 0x68bf, 1387 0x68c0, 1388 0x68c1, 1389 0x68c7, 1390 0x68c8, 1391 0x68c9, 1392 0x68d8, 1393 0x68d9, 1394 0x68da, 1395 0x68de, 1396 0x68e0, 1397 0x68e1, 1398 0x68e4, 1399 0x68e5, 1400 0x68e8, 1401 0x68e9, 1402 0x68f1, 1403 0x68f2, 1404 0x68f8, 1405 0x68f9, 1406 0x68fa, 1407 0x68fe, 1408 0x7100, 1409 0x7101, 1410 0x7102, 1411 0x7103, 1412 0x7104, 1413 0x7105, 1414 0x7106, 1415 0x7108, 1416 0x7109, 1417 0x710A, 1418 0x710B, 1419 0x710C, 1420 0x710E, 1421 0x710F, 1422 0x7140, 1423 0x7141, 1424 0x7142, 1425 0x7143, 1426 0x7144, 1427 0x7145, 1428 0x7146, 1429 0x7147, 1430 0x7149, 1431 0x714A, 1432 0x714B, 1433 0x714C, 1434 0x714D, 1435 0x714E, 1436 0x714F, 1437 0x7151, 1438 0x7152, 1439 0x7153, 1440 0x715E, 1441 0x715F, 1442 0x7180, 1443 0x7181, 1444 0x7183, 1445 0x7186, 1446 0x7187, 1447 0x7188, 1448 0x718A, 1449 0x718B, 1450 0x718C, 1451 0x718D, 1452 0x718F, 1453 0x7193, 1454 0x7196, 1455 0x719B, 1456 0x719F, 1457 0x71C0, 1458 0x71C1, 1459 0x71C2, 1460 0x71C3, 1461 0x71C4, 1462 0x71C5, 1463 0x71C6, 1464 0x71C7, 1465 0x71CD, 1466 0x71CE, 1467 0x71D2, 1468 0x71D4, 1469 0x71D5, 1470 0x71D6, 1471 0x71DA, 1472 0x71DE, 1473 0x7200, 1474 0x7210, 1475 0x7211, 1476 0x7240, 1477 0x7243, 1478 0x7244, 1479 0x7245, 1480 0x7246, 1481 0x7247, 1482 0x7248, 1483 0x7249, 1484 0x724A, 1485 0x724B, 1486 0x724C, 1487 0x724D, 1488 0x724E, 1489 0x724F, 1490 0x7280, 1491 0x7281, 1492 0x7283, 1493 0x7284, 1494 0x7287, 1495 0x7288, 1496 0x7289, 1497 0x728B, 1498 0x728C, 1499 0x7290, 1500 0x7291, 1501 0x7293, 1502 0x7297, 1503 0x7834, 1504 0x7835, 1505 0x791e, 1506 0x791f, 1507 0x793f, 1508 0x7941, 1509 0x7942, 1510 0x796c, 1511 0x796d, 1512 0x796e, 1513 0x796f, 1514 0x9400, 1515 0x9401, 1516 0x9402, 1517 0x9403, 1518 0x9405, 1519 0x940A, 1520 0x940B, 1521 0x940F, 1522 0x94A0, 1523 0x94A1, 1524 0x94A3, 1525 0x94B1, 1526 0x94B3, 1527 0x94B4, 1528 0x94B5, 1529 0x94B9, 1530 0x9440, 1531 0x9441, 1532 0x9442, 1533 0x9443, 1534 0x9444, 1535 0x9446, 1536 0x944A, 1537 0x944B, 1538 0x944C, 1539 0x944E, 1540 0x9450, 1541 0x9452, 1542 0x9456, 1543 0x945A, 1544 0x945B, 1545 0x945E, 1546 0x9460, 1547 0x9462, 1548 0x946A, 1549 0x946B, 1550 0x947A, 1551 0x947B, 1552 0x9480, 1553 0x9487, 1554 0x9488, 1555 0x9489, 1556 0x948A, 1557 0x948F, 1558 0x9490, 1559 0x9491, 1560 0x9495, 1561 0x9498, 1562 0x949C, 1563 0x949E, 1564 0x949F, 1565 0x94C0, 1566 0x94C1, 1567 0x94C3, 1568 0x94C4, 1569 0x94C5, 1570 0x94C6, 1571 0x94C7, 1572 0x94C8, 1573 0x94C9, 1574 0x94CB, 1575 0x94CC, 1576 0x94CD, 1577 0x9500, 1578 0x9501, 1579 0x9504, 1580 0x9505, 1581 0x9506, 1582 0x9507, 1583 0x9508, 1584 0x9509, 1585 0x950F, 1586 0x9511, 1587 0x9515, 1588 0x9517, 1589 0x9519, 1590 0x9540, 1591 0x9541, 1592 0x9542, 1593 0x954E, 1594 0x954F, 1595 0x9552, 1596 0x9553, 1597 0x9555, 1598 0x9557, 1599 0x955f, 1600 0x9580, 1601 0x9581, 1602 0x9583, 1603 0x9586, 1604 0x9587, 1605 0x9588, 1606 0x9589, 1607 0x958A, 1608 0x958B, 1609 0x958C, 1610 0x958D, 1611 0x958E, 1612 0x958F, 1613 0x9590, 1614 0x9591, 1615 0x9593, 1616 0x9595, 1617 0x9596, 1618 0x9597, 1619 0x9598, 1620 0x9599, 1621 0x959B, 1622 0x95C0, 1623 0x95C2, 1624 0x95C4, 1625 0x95C5, 1626 0x95C6, 1627 0x95C7, 1628 0x95C9, 1629 0x95CC, 1630 0x95CD, 1631 0x95CE, 1632 0x95CF, 1633 0x9610, 1634 0x9611, 1635 0x9612, 1636 0x9613, 1637 0x9614, 1638 0x9615, 1639 0x9616, 1640 0x9640, 1641 0x9641, 1642 0x9642, 1643 0x9643, 1644 0x9644, 1645 0x9645, 1646 0x9647, 1647 0x9648, 1648 0x9649, 1649 0x964a, 1650 0x964b, 1651 0x964c, 1652 0x964e, 1653 0x964f, 1654 0x9710, 1655 0x9711, 1656 0x9712, 1657 0x9713, 1658 0x9714, 1659 0x9715, 1660 0x9802, 1661 0x9803, 1662 0x9804, 1663 0x9805, 1664 0x9806, 1665 0x9807, 1666 0x9808, 1667 0x9809, 1668 0x980A, 1669 0x9900, 1670 0x9901, 1671 0x9903, 1672 0x9904, 1673 0x9905, 1674 0x9906, 1675 0x9907, 1676 0x9908, 1677 0x9909, 1678 0x990A, 1679 0x990B, 1680 0x990C, 1681 0x990D, 1682 0x990E, 1683 0x990F, 1684 0x9910, 1685 0x9913, 1686 0x9917, 1687 0x9918, 1688 0x9919, 1689 0x9990, 1690 0x9991, 1691 0x9992, 1692 0x9993, 1693 0x9994, 1694 0x9995, 1695 0x9996, 1696 0x9997, 1697 0x9998, 1698 0x9999, 1699 0x999A, 1700 0x999B, 1701 0x999C, 1702 0x999D, 1703 0x99A0, 1704 0x99A2, 1705 0x99A4, 1706 /* radeon secondary ids */ 1707 0x3171, 1708 0x3e70, 1709 0x4164, 1710 0x4165, 1711 0x4166, 1712 0x4168, 1713 0x4170, 1714 0x4171, 1715 0x4172, 1716 0x4173, 1717 0x496e, 1718 0x4a69, 1719 0x4a6a, 1720 0x4a6b, 1721 0x4a70, 1722 0x4a74, 1723 0x4b69, 1724 0x4b6b, 1725 0x4b6c, 1726 0x4c6e, 1727 0x4e64, 1728 0x4e65, 1729 0x4e66, 1730 0x4e67, 1731 0x4e68, 1732 0x4e69, 1733 0x4e6a, 1734 0x4e71, 1735 0x4f73, 1736 0x5569, 1737 0x556b, 1738 0x556d, 1739 0x556f, 1740 0x5571, 1741 0x5854, 1742 0x5874, 1743 0x5940, 1744 0x5941, 1745 0x5b70, 1746 0x5b72, 1747 0x5b73, 1748 0x5b74, 1749 0x5b75, 1750 0x5d44, 1751 0x5d45, 1752 0x5d6d, 1753 0x5d6f, 1754 0x5d72, 1755 0x5d77, 1756 0x5e6b, 1757 0x5e6d, 1758 0x7120, 1759 0x7124, 1760 0x7129, 1761 0x712e, 1762 0x712f, 1763 0x7162, 1764 0x7163, 1765 0x7166, 1766 0x7167, 1767 0x7172, 1768 0x7173, 1769 0x71a0, 1770 0x71a1, 1771 0x71a3, 1772 0x71a7, 1773 0x71bb, 1774 0x71e0, 1775 0x71e1, 1776 0x71e2, 1777 0x71e6, 1778 0x71e7, 1779 0x71f2, 1780 0x7269, 1781 0x726b, 1782 0x726e, 1783 0x72a0, 1784 0x72a8, 1785 0x72b1, 1786 0x72b3, 1787 0x793f, 1788 }; 1789 1790 static const struct pci_device_id pciidlist[] = { 1791 #ifdef CONFIG_DRM_AMDGPU_SI 1792 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1793 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1794 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1795 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1796 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1797 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1798 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1799 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1800 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1801 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1802 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1803 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1804 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1805 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1806 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1807 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1808 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1809 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1810 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1811 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1812 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1813 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1814 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1815 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1816 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1817 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1818 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1819 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1820 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1821 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1822 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1823 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1824 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1825 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1826 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1827 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1828 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1829 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1830 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1831 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1832 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1833 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1834 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1835 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1836 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1837 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1838 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1839 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1840 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1841 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1842 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1843 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1844 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1845 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1846 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1847 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1848 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1849 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1850 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1851 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1852 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1853 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1854 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1855 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1856 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1857 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1858 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1859 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1860 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1861 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1862 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1863 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1864 #endif 1865 #ifdef CONFIG_DRM_AMDGPU_CIK 1866 /* Kaveri */ 1867 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1868 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1869 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1870 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1871 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1872 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1873 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1874 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1875 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1876 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1877 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1878 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1879 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1880 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1881 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1882 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1883 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1884 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1885 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1886 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1887 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1888 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1889 /* Bonaire */ 1890 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1891 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1892 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1893 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1894 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1895 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1896 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1897 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1898 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1899 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1900 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1901 /* Hawaii */ 1902 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1903 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1904 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1905 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1906 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1907 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1908 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1909 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1910 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1911 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1912 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1913 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1914 /* Kabini */ 1915 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1916 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1917 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1918 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1919 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1920 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1921 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1922 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1923 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1924 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1925 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1926 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1927 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1928 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1929 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1930 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1931 /* mullins */ 1932 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1933 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1934 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1935 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1936 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1937 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1938 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1939 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1940 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1941 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1942 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1943 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1944 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1945 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1946 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1947 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1948 #endif 1949 /* topaz */ 1950 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1951 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1952 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1953 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1954 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1955 /* tonga */ 1956 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1957 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1958 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1959 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1960 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1961 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1962 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1963 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1964 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1965 /* fiji */ 1966 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1967 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1968 /* carrizo */ 1969 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1970 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1971 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1972 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1973 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1974 /* stoney */ 1975 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1976 /* Polaris11 */ 1977 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1978 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1979 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1980 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1981 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1982 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1983 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1984 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1985 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1986 /* Polaris10 */ 1987 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1988 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1989 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1990 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1991 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1992 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1993 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1994 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1995 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1996 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1997 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1998 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1999 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2000 /* Polaris12 */ 2001 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2002 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2003 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2004 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2005 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2006 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2007 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2008 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2009 /* VEGAM */ 2010 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 2011 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 2012 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 2013 /* Vega 10 */ 2014 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2015 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2016 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2017 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2018 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2019 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2020 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2021 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2022 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2023 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2024 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2025 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2026 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2027 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2028 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2029 /* Vega 12 */ 2030 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2031 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2032 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2033 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2034 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2035 /* Vega 20 */ 2036 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2037 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2038 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2039 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2040 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2041 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2042 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2043 /* Raven */ 2044 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 2045 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 2046 /* Arcturus */ 2047 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2048 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2049 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2050 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2051 /* Navi10 */ 2052 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2053 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2054 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2055 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2056 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2057 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2058 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2059 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2060 /* Navi14 */ 2061 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2062 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2063 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2064 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2065 2066 /* Renoir */ 2067 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2068 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2069 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2070 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2071 2072 /* Navi12 */ 2073 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 2074 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 2075 2076 /* Sienna_Cichlid */ 2077 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2078 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2079 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2080 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2081 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2082 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2083 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2084 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2085 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2086 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2087 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2088 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2089 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2090 2091 /* Yellow Carp */ 2092 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 2093 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 2094 2095 /* Navy_Flounder */ 2096 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2097 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2098 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2099 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2100 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2101 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2102 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2103 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2104 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2105 2106 /* DIMGREY_CAVEFISH */ 2107 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2108 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2109 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2110 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2111 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2112 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2113 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2114 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2115 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2116 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2117 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2118 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2119 2120 /* Aldebaran */ 2121 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2122 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2123 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2124 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2125 2126 /* CYAN_SKILLFISH */ 2127 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2128 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2129 2130 /* BEIGE_GOBY */ 2131 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2132 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2133 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2134 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2135 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2136 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2137 2138 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2139 .class = PCI_CLASS_DISPLAY_VGA << 8, 2140 .class_mask = 0xffffff, 2141 .driver_data = CHIP_IP_DISCOVERY }, 2142 2143 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2144 .class = PCI_CLASS_DISPLAY_OTHER << 8, 2145 .class_mask = 0xffffff, 2146 .driver_data = CHIP_IP_DISCOVERY }, 2147 2148 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2149 .class = PCI_CLASS_ACCELERATOR_PROCESSING << 8, 2150 .class_mask = 0xffffff, 2151 .driver_data = CHIP_IP_DISCOVERY }, 2152 2153 {0, 0, 0} 2154 }; 2155 2156 MODULE_DEVICE_TABLE(pci, pciidlist); 2157 2158 static const struct amdgpu_asic_type_quirk asic_type_quirks[] = { 2159 /* differentiate between P10 and P11 asics with the same DID */ 2160 {0x67FF, 0xE3, CHIP_POLARIS10}, 2161 {0x67FF, 0xE7, CHIP_POLARIS10}, 2162 {0x67FF, 0xF3, CHIP_POLARIS10}, 2163 {0x67FF, 0xF7, CHIP_POLARIS10}, 2164 }; 2165 2166 static const struct drm_driver amdgpu_kms_driver; 2167 2168 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 2169 { 2170 struct pci_dev *p = NULL; 2171 int i; 2172 2173 /* 0 - GPU 2174 * 1 - audio 2175 * 2 - USB 2176 * 3 - UCSI 2177 */ 2178 for (i = 1; i < 4; i++) { 2179 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 2180 adev->pdev->bus->number, i); 2181 if (p) { 2182 pm_runtime_get_sync(&p->dev); 2183 pm_runtime_mark_last_busy(&p->dev); 2184 pm_runtime_put_autosuspend(&p->dev); 2185 pci_dev_put(p); 2186 } 2187 } 2188 } 2189 2190 static void amdgpu_init_debug_options(struct amdgpu_device *adev) 2191 { 2192 if (amdgpu_debug_mask & AMDGPU_DEBUG_VM) { 2193 pr_info("debug: VM handling debug enabled\n"); 2194 adev->debug_vm = true; 2195 } 2196 2197 if (amdgpu_debug_mask & AMDGPU_DEBUG_LARGEBAR) { 2198 pr_info("debug: enabled simulating large-bar capability on non-large bar system\n"); 2199 adev->debug_largebar = true; 2200 } 2201 2202 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY) { 2203 pr_info("debug: soft reset for GPU recovery disabled\n"); 2204 adev->debug_disable_soft_recovery = true; 2205 } 2206 2207 if (amdgpu_debug_mask & AMDGPU_DEBUG_USE_VRAM_FW_BUF) { 2208 pr_info("debug: place fw in vram for frontdoor loading\n"); 2209 adev->debug_use_vram_fw_buf = true; 2210 } 2211 2212 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_RAS_ACA) { 2213 pr_info("debug: enable RAS ACA\n"); 2214 adev->debug_enable_ras_aca = true; 2215 } 2216 2217 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_EXP_RESETS) { 2218 pr_info("debug: enable experimental reset features\n"); 2219 adev->debug_exp_resets = true; 2220 } 2221 } 2222 2223 static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long flags) 2224 { 2225 int i; 2226 2227 for (i = 0; i < ARRAY_SIZE(asic_type_quirks); i++) { 2228 if (pdev->device == asic_type_quirks[i].device && 2229 pdev->revision == asic_type_quirks[i].revision) { 2230 flags &= ~AMD_ASIC_MASK; 2231 flags |= asic_type_quirks[i].type; 2232 break; 2233 } 2234 } 2235 2236 return flags; 2237 } 2238 2239 static int amdgpu_pci_probe(struct pci_dev *pdev, 2240 const struct pci_device_id *ent) 2241 { 2242 struct drm_device *ddev; 2243 struct amdgpu_device *adev; 2244 unsigned long flags = ent->driver_data; 2245 int ret, retry = 0, i; 2246 bool supports_atomic = false; 2247 2248 /* skip devices which are owned by radeon */ 2249 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2250 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2251 return -ENODEV; 2252 } 2253 2254 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) 2255 amdgpu_aspm = 0; 2256 2257 if (amdgpu_virtual_display || 2258 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 2259 supports_atomic = true; 2260 2261 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2262 DRM_INFO("This hardware requires experimental hardware support.\n" 2263 "See modparam exp_hw_support\n"); 2264 return -ENODEV; 2265 } 2266 2267 flags = amdgpu_fix_asic_type(pdev, flags); 2268 2269 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2270 * however, SME requires an indirect IOMMU mapping because the encryption 2271 * bit is beyond the DMA mask of the chip. 2272 */ 2273 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2274 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2275 dev_info(&pdev->dev, 2276 "SME is not compatible with RAVEN\n"); 2277 return -ENOTSUPP; 2278 } 2279 2280 #ifdef CONFIG_DRM_AMDGPU_SI 2281 if (!amdgpu_si_support) { 2282 switch (flags & AMD_ASIC_MASK) { 2283 case CHIP_TAHITI: 2284 case CHIP_PITCAIRN: 2285 case CHIP_VERDE: 2286 case CHIP_OLAND: 2287 case CHIP_HAINAN: 2288 dev_info(&pdev->dev, 2289 "SI support provided by radeon.\n"); 2290 dev_info(&pdev->dev, 2291 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 2292 ); 2293 return -ENODEV; 2294 } 2295 } 2296 #endif 2297 #ifdef CONFIG_DRM_AMDGPU_CIK 2298 if (!amdgpu_cik_support) { 2299 switch (flags & AMD_ASIC_MASK) { 2300 case CHIP_KAVERI: 2301 case CHIP_BONAIRE: 2302 case CHIP_HAWAII: 2303 case CHIP_KABINI: 2304 case CHIP_MULLINS: 2305 dev_info(&pdev->dev, 2306 "CIK support provided by radeon.\n"); 2307 dev_info(&pdev->dev, 2308 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 2309 ); 2310 return -ENODEV; 2311 } 2312 } 2313 #endif 2314 2315 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2316 if (IS_ERR(adev)) 2317 return PTR_ERR(adev); 2318 2319 adev->dev = &pdev->dev; 2320 adev->pdev = pdev; 2321 ddev = adev_to_drm(adev); 2322 2323 if (!supports_atomic) 2324 ddev->driver_features &= ~DRIVER_ATOMIC; 2325 2326 ret = pci_enable_device(pdev); 2327 if (ret) 2328 return ret; 2329 2330 pci_set_drvdata(pdev, ddev); 2331 2332 amdgpu_init_debug_options(adev); 2333 2334 ret = amdgpu_driver_load_kms(adev, flags); 2335 if (ret) 2336 goto err_pci; 2337 2338 retry_init: 2339 ret = drm_dev_register(ddev, flags); 2340 if (ret == -EAGAIN && ++retry <= 3) { 2341 DRM_INFO("retry init %d\n", retry); 2342 /* Don't request EX mode too frequently which is attacking */ 2343 msleep(5000); 2344 goto retry_init; 2345 } else if (ret) { 2346 goto err_pci; 2347 } 2348 2349 ret = amdgpu_xcp_dev_register(adev, ent); 2350 if (ret) 2351 goto err_pci; 2352 2353 ret = amdgpu_amdkfd_drm_client_create(adev); 2354 if (ret) 2355 goto err_pci; 2356 2357 /* 2358 * 1. don't init fbdev on hw without DCE 2359 * 2. don't init fbdev if there are no connectors 2360 */ 2361 if (adev->mode_info.mode_config_initialized && 2362 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2363 /* select 8 bpp console on low vram cards */ 2364 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2365 drm_fbdev_ttm_setup(adev_to_drm(adev), 8); 2366 else 2367 drm_fbdev_ttm_setup(adev_to_drm(adev), 32); 2368 } 2369 2370 ret = amdgpu_debugfs_init(adev); 2371 if (ret) 2372 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2373 2374 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2375 /* only need to skip on ATPX */ 2376 if (amdgpu_device_supports_px(ddev)) 2377 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2378 /* we want direct complete for BOCO */ 2379 if (amdgpu_device_supports_boco(ddev)) 2380 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2381 DPM_FLAG_SMART_SUSPEND | 2382 DPM_FLAG_MAY_SKIP_RESUME); 2383 pm_runtime_use_autosuspend(ddev->dev); 2384 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2385 2386 pm_runtime_allow(ddev->dev); 2387 2388 pm_runtime_mark_last_busy(ddev->dev); 2389 pm_runtime_put_autosuspend(ddev->dev); 2390 2391 pci_wake_from_d3(pdev, TRUE); 2392 2393 /* 2394 * For runpm implemented via BACO, PMFW will handle the 2395 * timing for BACO in and out: 2396 * - put ASIC into BACO state only when both video and 2397 * audio functions are in D3 state. 2398 * - pull ASIC out of BACO state when either video or 2399 * audio function is in D0 state. 2400 * Also, at startup, PMFW assumes both functions are in 2401 * D0 state. 2402 * 2403 * So if snd driver was loaded prior to amdgpu driver 2404 * and audio function was put into D3 state, there will 2405 * be no PMFW-aware D-state transition(D0->D3) on runpm 2406 * suspend. Thus the BACO will be not correctly kicked in. 2407 * 2408 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2409 * into D0 state. Then there will be a PMFW-aware D-state 2410 * transition(D0->D3) on runpm suspend. 2411 */ 2412 if (amdgpu_device_supports_baco(ddev) && 2413 !(adev->flags & AMD_IS_APU) && 2414 (adev->asic_type >= CHIP_NAVI10)) 2415 amdgpu_get_secondary_funcs(adev); 2416 } 2417 2418 return 0; 2419 2420 err_pci: 2421 pci_disable_device(pdev); 2422 return ret; 2423 } 2424 2425 static void 2426 amdgpu_pci_remove(struct pci_dev *pdev) 2427 { 2428 struct drm_device *dev = pci_get_drvdata(pdev); 2429 struct amdgpu_device *adev = drm_to_adev(dev); 2430 2431 amdgpu_xcp_dev_unplug(adev); 2432 amdgpu_gmc_prepare_nps_mode_change(adev); 2433 drm_dev_unplug(dev); 2434 2435 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2436 pm_runtime_get_sync(dev->dev); 2437 pm_runtime_forbid(dev->dev); 2438 } 2439 2440 amdgpu_driver_unload_kms(dev); 2441 2442 /* 2443 * Flush any in flight DMA operations from device. 2444 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2445 * StatusTransactions Pending bit. 2446 */ 2447 pci_disable_device(pdev); 2448 pci_wait_for_pending_transaction(pdev); 2449 } 2450 2451 static void 2452 amdgpu_pci_shutdown(struct pci_dev *pdev) 2453 { 2454 struct drm_device *dev = pci_get_drvdata(pdev); 2455 struct amdgpu_device *adev = drm_to_adev(dev); 2456 2457 if (amdgpu_ras_intr_triggered()) 2458 return; 2459 2460 /* if we are running in a VM, make sure the device 2461 * torn down properly on reboot/shutdown. 2462 * unfortunately we can't detect certain 2463 * hypervisors so just do this all the time. 2464 */ 2465 if (!amdgpu_passthrough(adev)) 2466 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2467 amdgpu_device_ip_suspend(adev); 2468 adev->mp1_state = PP_MP1_STATE_NONE; 2469 } 2470 2471 static int amdgpu_pmops_prepare(struct device *dev) 2472 { 2473 struct drm_device *drm_dev = dev_get_drvdata(dev); 2474 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2475 2476 /* Return a positive number here so 2477 * DPM_FLAG_SMART_SUSPEND works properly 2478 */ 2479 if (amdgpu_device_supports_boco(drm_dev) && 2480 pm_runtime_suspended(dev)) 2481 return 1; 2482 2483 /* if we will not support s3 or s2i for the device 2484 * then skip suspend 2485 */ 2486 if (!amdgpu_acpi_is_s0ix_active(adev) && 2487 !amdgpu_acpi_is_s3_active(adev)) 2488 return 1; 2489 2490 return amdgpu_device_prepare(drm_dev); 2491 } 2492 2493 static void amdgpu_pmops_complete(struct device *dev) 2494 { 2495 /* nothing to do */ 2496 } 2497 2498 static int amdgpu_pmops_suspend(struct device *dev) 2499 { 2500 struct drm_device *drm_dev = dev_get_drvdata(dev); 2501 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2502 2503 adev->suspend_complete = false; 2504 if (amdgpu_acpi_is_s0ix_active(adev)) 2505 adev->in_s0ix = true; 2506 else if (amdgpu_acpi_is_s3_active(adev)) 2507 adev->in_s3 = true; 2508 if (!adev->in_s0ix && !adev->in_s3) 2509 return 0; 2510 return amdgpu_device_suspend(drm_dev, true); 2511 } 2512 2513 static int amdgpu_pmops_suspend_noirq(struct device *dev) 2514 { 2515 struct drm_device *drm_dev = dev_get_drvdata(dev); 2516 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2517 2518 adev->suspend_complete = true; 2519 if (amdgpu_acpi_should_gpu_reset(adev)) 2520 return amdgpu_asic_reset(adev); 2521 2522 return 0; 2523 } 2524 2525 static int amdgpu_pmops_resume(struct device *dev) 2526 { 2527 struct drm_device *drm_dev = dev_get_drvdata(dev); 2528 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2529 int r; 2530 2531 if (!adev->in_s0ix && !adev->in_s3) 2532 return 0; 2533 2534 /* Avoids registers access if device is physically gone */ 2535 if (!pci_device_is_present(adev->pdev)) 2536 adev->no_hw_access = true; 2537 2538 r = amdgpu_device_resume(drm_dev, true); 2539 if (amdgpu_acpi_is_s0ix_active(adev)) 2540 adev->in_s0ix = false; 2541 else 2542 adev->in_s3 = false; 2543 return r; 2544 } 2545 2546 static int amdgpu_pmops_freeze(struct device *dev) 2547 { 2548 struct drm_device *drm_dev = dev_get_drvdata(dev); 2549 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2550 int r; 2551 2552 adev->in_s4 = true; 2553 r = amdgpu_device_suspend(drm_dev, true); 2554 adev->in_s4 = false; 2555 if (r) 2556 return r; 2557 2558 if (amdgpu_acpi_should_gpu_reset(adev)) 2559 return amdgpu_asic_reset(adev); 2560 return 0; 2561 } 2562 2563 static int amdgpu_pmops_thaw(struct device *dev) 2564 { 2565 struct drm_device *drm_dev = dev_get_drvdata(dev); 2566 2567 return amdgpu_device_resume(drm_dev, true); 2568 } 2569 2570 static int amdgpu_pmops_poweroff(struct device *dev) 2571 { 2572 struct drm_device *drm_dev = dev_get_drvdata(dev); 2573 2574 return amdgpu_device_suspend(drm_dev, true); 2575 } 2576 2577 static int amdgpu_pmops_restore(struct device *dev) 2578 { 2579 struct drm_device *drm_dev = dev_get_drvdata(dev); 2580 2581 return amdgpu_device_resume(drm_dev, true); 2582 } 2583 2584 static int amdgpu_runtime_idle_check_display(struct device *dev) 2585 { 2586 struct pci_dev *pdev = to_pci_dev(dev); 2587 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2588 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2589 2590 if (adev->mode_info.num_crtc) { 2591 struct drm_connector *list_connector; 2592 struct drm_connector_list_iter iter; 2593 int ret = 0; 2594 2595 if (amdgpu_runtime_pm != -2) { 2596 /* XXX: Return busy if any displays are connected to avoid 2597 * possible display wakeups after runtime resume due to 2598 * hotplug events in case any displays were connected while 2599 * the GPU was in suspend. Remove this once that is fixed. 2600 */ 2601 mutex_lock(&drm_dev->mode_config.mutex); 2602 drm_connector_list_iter_begin(drm_dev, &iter); 2603 drm_for_each_connector_iter(list_connector, &iter) { 2604 if (list_connector->status == connector_status_connected) { 2605 ret = -EBUSY; 2606 break; 2607 } 2608 } 2609 drm_connector_list_iter_end(&iter); 2610 mutex_unlock(&drm_dev->mode_config.mutex); 2611 2612 if (ret) 2613 return ret; 2614 } 2615 2616 if (adev->dc_enabled) { 2617 struct drm_crtc *crtc; 2618 2619 drm_for_each_crtc(crtc, drm_dev) { 2620 drm_modeset_lock(&crtc->mutex, NULL); 2621 if (crtc->state->active) 2622 ret = -EBUSY; 2623 drm_modeset_unlock(&crtc->mutex); 2624 if (ret < 0) 2625 break; 2626 } 2627 } else { 2628 mutex_lock(&drm_dev->mode_config.mutex); 2629 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2630 2631 drm_connector_list_iter_begin(drm_dev, &iter); 2632 drm_for_each_connector_iter(list_connector, &iter) { 2633 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2634 ret = -EBUSY; 2635 break; 2636 } 2637 } 2638 2639 drm_connector_list_iter_end(&iter); 2640 2641 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2642 mutex_unlock(&drm_dev->mode_config.mutex); 2643 } 2644 if (ret) 2645 return ret; 2646 } 2647 2648 return 0; 2649 } 2650 2651 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2652 { 2653 struct pci_dev *pdev = to_pci_dev(dev); 2654 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2655 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2656 int ret, i; 2657 2658 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2659 pm_runtime_forbid(dev); 2660 return -EBUSY; 2661 } 2662 2663 ret = amdgpu_runtime_idle_check_display(dev); 2664 if (ret) 2665 return ret; 2666 2667 /* wait for all rings to drain before suspending */ 2668 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2669 struct amdgpu_ring *ring = adev->rings[i]; 2670 2671 if (ring && ring->sched.ready) { 2672 ret = amdgpu_fence_wait_empty(ring); 2673 if (ret) 2674 return -EBUSY; 2675 } 2676 } 2677 2678 adev->in_runpm = true; 2679 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2680 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2681 2682 /* 2683 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2684 * proper cleanups and put itself into a state ready for PNP. That 2685 * can address some random resuming failure observed on BOCO capable 2686 * platforms. 2687 * TODO: this may be also needed for PX capable platform. 2688 */ 2689 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2690 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2691 2692 ret = amdgpu_device_prepare(drm_dev); 2693 if (ret) 2694 return ret; 2695 ret = amdgpu_device_suspend(drm_dev, false); 2696 if (ret) { 2697 adev->in_runpm = false; 2698 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2699 adev->mp1_state = PP_MP1_STATE_NONE; 2700 return ret; 2701 } 2702 2703 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2704 adev->mp1_state = PP_MP1_STATE_NONE; 2705 2706 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) { 2707 /* Only need to handle PCI state in the driver for ATPX 2708 * PCI core handles it for _PR3. 2709 */ 2710 amdgpu_device_cache_pci_state(pdev); 2711 pci_disable_device(pdev); 2712 pci_ignore_hotplug(pdev); 2713 pci_set_power_state(pdev, PCI_D3cold); 2714 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2715 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) { 2716 /* nothing to do */ 2717 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2718 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) { 2719 amdgpu_device_baco_enter(drm_dev); 2720 } 2721 2722 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n"); 2723 2724 return 0; 2725 } 2726 2727 static int amdgpu_pmops_runtime_resume(struct device *dev) 2728 { 2729 struct pci_dev *pdev = to_pci_dev(dev); 2730 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2731 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2732 int ret; 2733 2734 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) 2735 return -EINVAL; 2736 2737 /* Avoids registers access if device is physically gone */ 2738 if (!pci_device_is_present(adev->pdev)) 2739 adev->no_hw_access = true; 2740 2741 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) { 2742 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2743 2744 /* Only need to handle PCI state in the driver for ATPX 2745 * PCI core handles it for _PR3. 2746 */ 2747 pci_set_power_state(pdev, PCI_D0); 2748 amdgpu_device_load_pci_state(pdev); 2749 ret = pci_enable_device(pdev); 2750 if (ret) 2751 return ret; 2752 pci_set_master(pdev); 2753 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) { 2754 /* Only need to handle PCI state in the driver for ATPX 2755 * PCI core handles it for _PR3. 2756 */ 2757 pci_set_master(pdev); 2758 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2759 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) { 2760 amdgpu_device_baco_exit(drm_dev); 2761 } 2762 ret = amdgpu_device_resume(drm_dev, false); 2763 if (ret) { 2764 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2765 pci_disable_device(pdev); 2766 return ret; 2767 } 2768 2769 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2770 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2771 adev->in_runpm = false; 2772 return 0; 2773 } 2774 2775 static int amdgpu_pmops_runtime_idle(struct device *dev) 2776 { 2777 struct drm_device *drm_dev = dev_get_drvdata(dev); 2778 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2779 int ret; 2780 2781 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2782 pm_runtime_forbid(dev); 2783 return -EBUSY; 2784 } 2785 2786 ret = amdgpu_runtime_idle_check_display(dev); 2787 2788 pm_runtime_mark_last_busy(dev); 2789 pm_runtime_autosuspend(dev); 2790 return ret; 2791 } 2792 2793 long amdgpu_drm_ioctl(struct file *filp, 2794 unsigned int cmd, unsigned long arg) 2795 { 2796 struct drm_file *file_priv = filp->private_data; 2797 struct drm_device *dev; 2798 long ret; 2799 2800 dev = file_priv->minor->dev; 2801 ret = pm_runtime_get_sync(dev->dev); 2802 if (ret < 0) 2803 goto out; 2804 2805 ret = drm_ioctl(filp, cmd, arg); 2806 2807 pm_runtime_mark_last_busy(dev->dev); 2808 out: 2809 pm_runtime_put_autosuspend(dev->dev); 2810 return ret; 2811 } 2812 2813 static const struct dev_pm_ops amdgpu_pm_ops = { 2814 .prepare = amdgpu_pmops_prepare, 2815 .complete = amdgpu_pmops_complete, 2816 .suspend = amdgpu_pmops_suspend, 2817 .suspend_noirq = amdgpu_pmops_suspend_noirq, 2818 .resume = amdgpu_pmops_resume, 2819 .freeze = amdgpu_pmops_freeze, 2820 .thaw = amdgpu_pmops_thaw, 2821 .poweroff = amdgpu_pmops_poweroff, 2822 .restore = amdgpu_pmops_restore, 2823 .runtime_suspend = amdgpu_pmops_runtime_suspend, 2824 .runtime_resume = amdgpu_pmops_runtime_resume, 2825 .runtime_idle = amdgpu_pmops_runtime_idle, 2826 }; 2827 2828 static int amdgpu_flush(struct file *f, fl_owner_t id) 2829 { 2830 struct drm_file *file_priv = f->private_data; 2831 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2832 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2833 2834 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 2835 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 2836 2837 return timeout >= 0 ? 0 : timeout; 2838 } 2839 2840 static const struct file_operations amdgpu_driver_kms_fops = { 2841 .owner = THIS_MODULE, 2842 .open = drm_open, 2843 .flush = amdgpu_flush, 2844 .release = drm_release, 2845 .unlocked_ioctl = amdgpu_drm_ioctl, 2846 .mmap = drm_gem_mmap, 2847 .poll = drm_poll, 2848 .read = drm_read, 2849 #ifdef CONFIG_COMPAT 2850 .compat_ioctl = amdgpu_kms_compat_ioctl, 2851 #endif 2852 #ifdef CONFIG_PROC_FS 2853 .show_fdinfo = drm_show_fdinfo, 2854 #endif 2855 }; 2856 2857 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 2858 { 2859 struct drm_file *file; 2860 2861 if (!filp) 2862 return -EINVAL; 2863 2864 if (filp->f_op != &amdgpu_driver_kms_fops) 2865 return -EINVAL; 2866 2867 file = filp->private_data; 2868 *fpriv = file->driver_priv; 2869 return 0; 2870 } 2871 2872 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 2873 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2874 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2875 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2876 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 2877 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2878 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2879 /* KMS */ 2880 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2881 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2882 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2883 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2884 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2885 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2886 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2887 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2888 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2889 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2890 }; 2891 2892 static const struct drm_driver amdgpu_kms_driver = { 2893 .driver_features = 2894 DRIVER_ATOMIC | 2895 DRIVER_GEM | 2896 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 2897 DRIVER_SYNCOBJ_TIMELINE, 2898 .open = amdgpu_driver_open_kms, 2899 .postclose = amdgpu_driver_postclose_kms, 2900 .ioctls = amdgpu_ioctls_kms, 2901 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2902 .dumb_create = amdgpu_mode_dumb_create, 2903 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2904 .fops = &amdgpu_driver_kms_fops, 2905 .release = &amdgpu_driver_release_kms, 2906 #ifdef CONFIG_PROC_FS 2907 .show_fdinfo = amdgpu_show_fdinfo, 2908 #endif 2909 2910 .gem_prime_import = amdgpu_gem_prime_import, 2911 2912 .name = DRIVER_NAME, 2913 .desc = DRIVER_DESC, 2914 .date = DRIVER_DATE, 2915 .major = KMS_DRIVER_MAJOR, 2916 .minor = KMS_DRIVER_MINOR, 2917 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2918 }; 2919 2920 const struct drm_driver amdgpu_partition_driver = { 2921 .driver_features = 2922 DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ | 2923 DRIVER_SYNCOBJ_TIMELINE, 2924 .open = amdgpu_driver_open_kms, 2925 .postclose = amdgpu_driver_postclose_kms, 2926 .ioctls = amdgpu_ioctls_kms, 2927 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2928 .dumb_create = amdgpu_mode_dumb_create, 2929 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2930 .fops = &amdgpu_driver_kms_fops, 2931 .release = &amdgpu_driver_release_kms, 2932 2933 .gem_prime_import = amdgpu_gem_prime_import, 2934 2935 .name = DRIVER_NAME, 2936 .desc = DRIVER_DESC, 2937 .date = DRIVER_DATE, 2938 .major = KMS_DRIVER_MAJOR, 2939 .minor = KMS_DRIVER_MINOR, 2940 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2941 }; 2942 2943 static struct pci_error_handlers amdgpu_pci_err_handler = { 2944 .error_detected = amdgpu_pci_error_detected, 2945 .mmio_enabled = amdgpu_pci_mmio_enabled, 2946 .slot_reset = amdgpu_pci_slot_reset, 2947 .resume = amdgpu_pci_resume, 2948 }; 2949 2950 static const struct attribute_group *amdgpu_sysfs_groups[] = { 2951 &amdgpu_vram_mgr_attr_group, 2952 &amdgpu_gtt_mgr_attr_group, 2953 &amdgpu_flash_attr_group, 2954 NULL, 2955 }; 2956 2957 static struct pci_driver amdgpu_kms_pci_driver = { 2958 .name = DRIVER_NAME, 2959 .id_table = pciidlist, 2960 .probe = amdgpu_pci_probe, 2961 .remove = amdgpu_pci_remove, 2962 .shutdown = amdgpu_pci_shutdown, 2963 .driver.pm = &amdgpu_pm_ops, 2964 .err_handler = &amdgpu_pci_err_handler, 2965 .dev_groups = amdgpu_sysfs_groups, 2966 }; 2967 2968 static int __init amdgpu_init(void) 2969 { 2970 int r; 2971 2972 if (drm_firmware_drivers_only()) 2973 return -EINVAL; 2974 2975 r = amdgpu_sync_init(); 2976 if (r) 2977 goto error_sync; 2978 2979 r = amdgpu_fence_slab_init(); 2980 if (r) 2981 goto error_fence; 2982 2983 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 2984 amdgpu_register_atpx_handler(); 2985 amdgpu_acpi_detect(); 2986 2987 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 2988 amdgpu_amdkfd_init(); 2989 2990 if (amdgpu_pp_feature_mask & PP_OVERDRIVE_MASK) { 2991 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 2992 pr_crit("Overdrive is enabled, please disable it before " 2993 "reporting any bugs unrelated to overdrive.\n"); 2994 } 2995 2996 /* let modprobe override vga console setting */ 2997 return pci_register_driver(&amdgpu_kms_pci_driver); 2998 2999 error_fence: 3000 amdgpu_sync_fini(); 3001 3002 error_sync: 3003 return r; 3004 } 3005 3006 static void __exit amdgpu_exit(void) 3007 { 3008 amdgpu_amdkfd_fini(); 3009 pci_unregister_driver(&amdgpu_kms_pci_driver); 3010 amdgpu_unregister_atpx_handler(); 3011 amdgpu_acpi_release(); 3012 amdgpu_sync_fini(); 3013 amdgpu_fence_slab_fini(); 3014 mmu_notifier_synchronize(); 3015 amdgpu_xcp_drv_release(); 3016 } 3017 3018 module_init(amdgpu_init); 3019 module_exit(amdgpu_exit); 3020 3021 MODULE_AUTHOR(DRIVER_AUTHOR); 3022 MODULE_DESCRIPTION(DRIVER_DESC); 3023 MODULE_LICENSE("GPL and additional rights"); 3024