1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_aperture.h> 27 #include <drm/drm_drv.h> 28 #include <drm/drm_gem.h> 29 #include <drm/drm_vblank.h> 30 #include <drm/drm_managed.h> 31 #include "amdgpu_drv.h" 32 33 #include <drm/drm_pciids.h> 34 #include <linux/module.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/vga_switcheroo.h> 37 #include <drm/drm_probe_helper.h> 38 #include <linux/mmu_notifier.h> 39 #include <linux/suspend.h> 40 #include <linux/cc_platform.h> 41 #include <linux/fb.h> 42 43 #include "amdgpu.h" 44 #include "amdgpu_irq.h" 45 #include "amdgpu_dma_buf.h" 46 #include "amdgpu_sched.h" 47 #include "amdgpu_fdinfo.h" 48 #include "amdgpu_amdkfd.h" 49 50 #include "amdgpu_ras.h" 51 #include "amdgpu_xgmi.h" 52 #include "amdgpu_reset.h" 53 54 /* 55 * KMS wrapper. 56 * - 3.0.0 - initial driver 57 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 58 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 59 * at the end of IBs. 60 * - 3.3.0 - Add VM support for UVD on supported hardware. 61 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 62 * - 3.5.0 - Add support for new UVD_NO_OP register. 63 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 64 * - 3.7.0 - Add support for VCE clock list packet 65 * - 3.8.0 - Add support raster config init in the kernel 66 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 67 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 68 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 69 * - 3.12.0 - Add query for double offchip LDS buffers 70 * - 3.13.0 - Add PRT support 71 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 72 * - 3.15.0 - Export more gpu info for gfx9 73 * - 3.16.0 - Add reserved vmid support 74 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 75 * - 3.18.0 - Export gpu always on cu bitmap 76 * - 3.19.0 - Add support for UVD MJPEG decode 77 * - 3.20.0 - Add support for local BOs 78 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 79 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 80 * - 3.23.0 - Add query for VRAM lost counter 81 * - 3.24.0 - Add high priority compute support for gfx9 82 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 83 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 84 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation. 85 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 86 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 87 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 88 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 89 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 90 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 91 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 92 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 93 * - 3.36.0 - Allow reading more status registers on si/cik 94 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 95 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 96 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 97 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 98 * - 3.41.0 - Add video codec query 99 * - 3.42.0 - Add 16bpc fixed point display support 100 * - 3.43.0 - Add device hot plug/unplug support 101 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 102 * - 3.45.0 - Add context ioctl stable pstate interface 103 */ 104 #define KMS_DRIVER_MAJOR 3 105 #define KMS_DRIVER_MINOR 45 106 #define KMS_DRIVER_PATCHLEVEL 0 107 108 int amdgpu_vram_limit; 109 int amdgpu_vis_vram_limit; 110 int amdgpu_gart_size = -1; /* auto */ 111 int amdgpu_gtt_size = -1; /* auto */ 112 int amdgpu_moverate = -1; /* auto */ 113 int amdgpu_benchmarking; 114 int amdgpu_testing; 115 int amdgpu_audio = -1; 116 int amdgpu_disp_priority; 117 int amdgpu_hw_i2c; 118 int amdgpu_pcie_gen2 = -1; 119 int amdgpu_msi = -1; 120 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 121 int amdgpu_dpm = -1; 122 int amdgpu_fw_load_type = -1; 123 int amdgpu_aspm = -1; 124 int amdgpu_runtime_pm = -1; 125 uint amdgpu_ip_block_mask = 0xffffffff; 126 int amdgpu_bapm = -1; 127 int amdgpu_deep_color; 128 int amdgpu_vm_size = -1; 129 int amdgpu_vm_fragment_size = -1; 130 int amdgpu_vm_block_size = -1; 131 int amdgpu_vm_fault_stop; 132 int amdgpu_vm_debug; 133 int amdgpu_vm_update_mode = -1; 134 int amdgpu_exp_hw_support; 135 int amdgpu_dc = -1; 136 int amdgpu_sched_jobs = 32; 137 int amdgpu_sched_hw_submission = 2; 138 uint amdgpu_pcie_gen_cap; 139 uint amdgpu_pcie_lane_cap; 140 uint amdgpu_cg_mask = 0xffffffff; 141 uint amdgpu_pg_mask = 0xffffffff; 142 uint amdgpu_sdma_phase_quantum = 32; 143 char *amdgpu_disable_cu = NULL; 144 char *amdgpu_virtual_display = NULL; 145 146 /* 147 * OverDrive(bit 14) disabled by default 148 * GFX DCS(bit 19) disabled by default 149 */ 150 uint amdgpu_pp_feature_mask = 0xfff7bfff; 151 uint amdgpu_force_long_training; 152 int amdgpu_job_hang_limit; 153 int amdgpu_lbpw = -1; 154 int amdgpu_compute_multipipe = -1; 155 int amdgpu_gpu_recovery = -1; /* auto */ 156 int amdgpu_emu_mode; 157 uint amdgpu_smu_memory_pool_size; 158 int amdgpu_smu_pptable_id = -1; 159 /* 160 * FBC (bit 0) disabled by default 161 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 162 * - With this, for multiple monitors in sync(e.g. with the same model), 163 * mclk switching will be allowed. And the mclk will be not foced to the 164 * highest. That helps saving some idle power. 165 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 166 * PSR (bit 3) disabled by default 167 * EDP NO POWER SEQUENCING (bit 4) disabled by default 168 */ 169 uint amdgpu_dc_feature_mask = 2; 170 uint amdgpu_dc_debug_mask; 171 int amdgpu_async_gfx_ring = 1; 172 int amdgpu_mcbp; 173 int amdgpu_discovery = -1; 174 int amdgpu_mes; 175 int amdgpu_noretry = -1; 176 int amdgpu_force_asic_type = -1; 177 int amdgpu_tmz = -1; /* auto */ 178 int amdgpu_reset_method = -1; /* auto */ 179 int amdgpu_num_kcq = -1; 180 int amdgpu_smartshift_bias; 181 182 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 183 184 struct amdgpu_mgpu_info mgpu_info = { 185 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 186 .delayed_reset_work = __DELAYED_WORK_INITIALIZER( 187 mgpu_info.delayed_reset_work, 188 amdgpu_drv_delayed_reset_work_handler, 0), 189 }; 190 int amdgpu_ras_enable = -1; 191 uint amdgpu_ras_mask = 0xffffffff; 192 int amdgpu_bad_page_threshold = -1; 193 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 194 .timeout_fatal_disable = false, 195 .period = 0x0, /* default to 0x0 (timeout disable) */ 196 }; 197 198 /** 199 * DOC: vramlimit (int) 200 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 201 */ 202 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 203 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 204 205 /** 206 * DOC: vis_vramlimit (int) 207 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 208 */ 209 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 210 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 211 212 /** 213 * DOC: gartsize (uint) 214 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic). 215 */ 216 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); 217 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 218 219 /** 220 * DOC: gttsize (int) 221 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM, 222 * otherwise 3/4 RAM size). 223 */ 224 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); 225 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 226 227 /** 228 * DOC: moverate (int) 229 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 230 */ 231 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 232 module_param_named(moverate, amdgpu_moverate, int, 0600); 233 234 /** 235 * DOC: benchmark (int) 236 * Run benchmarks. The default is 0 (Skip benchmarks). 237 */ 238 MODULE_PARM_DESC(benchmark, "Run benchmark"); 239 module_param_named(benchmark, amdgpu_benchmarking, int, 0444); 240 241 /** 242 * DOC: test (int) 243 * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test). 244 */ 245 MODULE_PARM_DESC(test, "Run tests"); 246 module_param_named(test, amdgpu_testing, int, 0444); 247 248 /** 249 * DOC: audio (int) 250 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 251 */ 252 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 253 module_param_named(audio, amdgpu_audio, int, 0444); 254 255 /** 256 * DOC: disp_priority (int) 257 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 258 */ 259 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 260 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 261 262 /** 263 * DOC: hw_i2c (int) 264 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 265 */ 266 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 267 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 268 269 /** 270 * DOC: pcie_gen2 (int) 271 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 272 */ 273 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 274 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 275 276 /** 277 * DOC: msi (int) 278 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 279 */ 280 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 281 module_param_named(msi, amdgpu_msi, int, 0444); 282 283 /** 284 * DOC: lockup_timeout (string) 285 * Set GPU scheduler timeout value in ms. 286 * 287 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 288 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 289 * to the default timeout. 290 * 291 * - With one value specified, the setting will apply to all non-compute jobs. 292 * - With multiple values specified, the first one will be for GFX. 293 * The second one is for Compute. The third and fourth ones are 294 * for SDMA and Video. 295 * 296 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 297 * jobs is 10000. The timeout for compute is 60000. 298 */ 299 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 300 "for passthrough or sriov, 10000 for all jobs." 301 " 0: keep default value. negative: infinity timeout), " 302 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 303 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 304 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 305 306 /** 307 * DOC: dpm (int) 308 * Override for dynamic power management setting 309 * (0 = disable, 1 = enable) 310 * The default is -1 (auto). 311 */ 312 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 313 module_param_named(dpm, amdgpu_dpm, int, 0444); 314 315 /** 316 * DOC: fw_load_type (int) 317 * Set different firmware loading type for debugging, if supported. 318 * Set to 0 to force direct loading if supported by the ASIC. Set 319 * to -1 to select the default loading mode for the ASIC, as defined 320 * by the driver. The default is -1 (auto). 321 */ 322 MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = force direct if supported, -1 = auto)"); 323 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 324 325 /** 326 * DOC: aspm (int) 327 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 328 */ 329 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 330 module_param_named(aspm, amdgpu_aspm, int, 0444); 331 332 /** 333 * DOC: runpm (int) 334 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 335 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 336 * Setting the value to 0 disables this functionality. 337 */ 338 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto)"); 339 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 340 341 /** 342 * DOC: ip_block_mask (uint) 343 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 344 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 345 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 346 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 347 */ 348 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 349 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 350 351 /** 352 * DOC: bapm (int) 353 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 354 * The default -1 (auto, enabled) 355 */ 356 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 357 module_param_named(bapm, amdgpu_bapm, int, 0444); 358 359 /** 360 * DOC: deep_color (int) 361 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 362 */ 363 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 364 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 365 366 /** 367 * DOC: vm_size (int) 368 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 369 */ 370 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 371 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 372 373 /** 374 * DOC: vm_fragment_size (int) 375 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 376 */ 377 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 378 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 379 380 /** 381 * DOC: vm_block_size (int) 382 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 383 */ 384 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 385 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 386 387 /** 388 * DOC: vm_fault_stop (int) 389 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 390 */ 391 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 392 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 393 394 /** 395 * DOC: vm_debug (int) 396 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 397 */ 398 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 399 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 400 401 /** 402 * DOC: vm_update_mode (int) 403 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 404 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 405 */ 406 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 407 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 408 409 /** 410 * DOC: exp_hw_support (int) 411 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 412 */ 413 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 414 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 415 416 /** 417 * DOC: dc (int) 418 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 419 */ 420 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 421 module_param_named(dc, amdgpu_dc, int, 0444); 422 423 /** 424 * DOC: sched_jobs (int) 425 * Override the max number of jobs supported in the sw queue. The default is 32. 426 */ 427 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 428 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 429 430 /** 431 * DOC: sched_hw_submission (int) 432 * Override the max number of HW submissions. The default is 2. 433 */ 434 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 435 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 436 437 /** 438 * DOC: ppfeaturemask (hexint) 439 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 440 * The default is the current set of stable power features. 441 */ 442 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 443 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 444 445 /** 446 * DOC: forcelongtraining (uint) 447 * Force long memory training in resume. 448 * The default is zero, indicates short training in resume. 449 */ 450 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 451 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 452 453 /** 454 * DOC: pcie_gen_cap (uint) 455 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 456 * The default is 0 (automatic for each asic). 457 */ 458 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 459 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 460 461 /** 462 * DOC: pcie_lane_cap (uint) 463 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 464 * The default is 0 (automatic for each asic). 465 */ 466 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 467 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 468 469 /** 470 * DOC: cg_mask (uint) 471 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 472 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 473 */ 474 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 475 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); 476 477 /** 478 * DOC: pg_mask (uint) 479 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 480 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 481 */ 482 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 483 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 484 485 /** 486 * DOC: sdma_phase_quantum (uint) 487 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 488 */ 489 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 490 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 491 492 /** 493 * DOC: disable_cu (charp) 494 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 495 */ 496 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 497 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 498 499 /** 500 * DOC: virtual_display (charp) 501 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 502 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 503 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 504 * device at 26:00.0. The default is NULL. 505 */ 506 MODULE_PARM_DESC(virtual_display, 507 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 508 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 509 510 /** 511 * DOC: job_hang_limit (int) 512 * Set how much time allow a job hang and not drop it. The default is 0. 513 */ 514 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 515 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 516 517 /** 518 * DOC: lbpw (int) 519 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 520 */ 521 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 522 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 523 524 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 525 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 526 527 /** 528 * DOC: gpu_recovery (int) 529 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 530 */ 531 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (2 = advanced tdr mode, 1 = enable, 0 = disable, -1 = auto)"); 532 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 533 534 /** 535 * DOC: emu_mode (int) 536 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 537 */ 538 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 539 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 540 541 /** 542 * DOC: ras_enable (int) 543 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 544 */ 545 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 546 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 547 548 /** 549 * DOC: ras_mask (uint) 550 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 551 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 552 */ 553 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 554 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 555 556 /** 557 * DOC: timeout_fatal_disable (bool) 558 * Disable Watchdog timeout fatal error event 559 */ 560 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 561 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 562 563 /** 564 * DOC: timeout_period (uint) 565 * Modify the watchdog timeout max_cycles as (1 << period) 566 */ 567 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 568 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 569 570 /** 571 * DOC: si_support (int) 572 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 573 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 574 * otherwise using amdgpu driver. 575 */ 576 #ifdef CONFIG_DRM_AMDGPU_SI 577 578 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 579 int amdgpu_si_support = 0; 580 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 581 #else 582 int amdgpu_si_support = 1; 583 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 584 #endif 585 586 module_param_named(si_support, amdgpu_si_support, int, 0444); 587 #endif 588 589 /** 590 * DOC: cik_support (int) 591 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 592 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 593 * otherwise using amdgpu driver. 594 */ 595 #ifdef CONFIG_DRM_AMDGPU_CIK 596 597 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 598 int amdgpu_cik_support = 0; 599 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 600 #else 601 int amdgpu_cik_support = 1; 602 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 603 #endif 604 605 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 606 #endif 607 608 /** 609 * DOC: smu_memory_pool_size (uint) 610 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 611 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 612 */ 613 MODULE_PARM_DESC(smu_memory_pool_size, 614 "reserve gtt for smu debug usage, 0 = disable," 615 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 616 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 617 618 /** 619 * DOC: async_gfx_ring (int) 620 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 621 */ 622 MODULE_PARM_DESC(async_gfx_ring, 623 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 624 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 625 626 /** 627 * DOC: mcbp (int) 628 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled) 629 */ 630 MODULE_PARM_DESC(mcbp, 631 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); 632 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 633 634 /** 635 * DOC: discovery (int) 636 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 637 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 638 */ 639 MODULE_PARM_DESC(discovery, 640 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 641 module_param_named(discovery, amdgpu_discovery, int, 0444); 642 643 /** 644 * DOC: mes (int) 645 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 646 * (0 = disabled (default), 1 = enabled) 647 */ 648 MODULE_PARM_DESC(mes, 649 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 650 module_param_named(mes, amdgpu_mes, int, 0444); 651 652 /** 653 * DOC: noretry (int) 654 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 655 * do not support per-process XNACK this also disables retry page faults. 656 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 657 */ 658 MODULE_PARM_DESC(noretry, 659 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 660 module_param_named(noretry, amdgpu_noretry, int, 0644); 661 662 /** 663 * DOC: force_asic_type (int) 664 * A non negative value used to specify the asic type for all supported GPUs. 665 */ 666 MODULE_PARM_DESC(force_asic_type, 667 "A non negative value used to specify the asic type for all supported GPUs"); 668 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 669 670 671 672 #ifdef CONFIG_HSA_AMD 673 /** 674 * DOC: sched_policy (int) 675 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 676 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 677 * assigns queues to HQDs. 678 */ 679 int sched_policy = KFD_SCHED_POLICY_HWS; 680 module_param(sched_policy, int, 0444); 681 MODULE_PARM_DESC(sched_policy, 682 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 683 684 /** 685 * DOC: hws_max_conc_proc (int) 686 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 687 * number of VMIDs assigned to the HWS, which is also the default. 688 */ 689 int hws_max_conc_proc = 8; 690 module_param(hws_max_conc_proc, int, 0444); 691 MODULE_PARM_DESC(hws_max_conc_proc, 692 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 693 694 /** 695 * DOC: cwsr_enable (int) 696 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 697 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 698 * disables it. 699 */ 700 int cwsr_enable = 1; 701 module_param(cwsr_enable, int, 0444); 702 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 703 704 /** 705 * DOC: max_num_of_queues_per_device (int) 706 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 707 * is 4096. 708 */ 709 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 710 module_param(max_num_of_queues_per_device, int, 0444); 711 MODULE_PARM_DESC(max_num_of_queues_per_device, 712 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 713 714 /** 715 * DOC: send_sigterm (int) 716 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 717 * but just print errors on dmesg. Setting 1 enables sending sigterm. 718 */ 719 int send_sigterm; 720 module_param(send_sigterm, int, 0444); 721 MODULE_PARM_DESC(send_sigterm, 722 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 723 724 /** 725 * DOC: debug_largebar (int) 726 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 727 * system. This limits the VRAM size reported to ROCm applications to the visible 728 * size, usually 256MB. 729 * Default value is 0, diabled. 730 */ 731 int debug_largebar; 732 module_param(debug_largebar, int, 0444); 733 MODULE_PARM_DESC(debug_largebar, 734 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 735 736 /** 737 * DOC: ignore_crat (int) 738 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 739 * table to get information about AMD APUs. This option can serve as a workaround on 740 * systems with a broken CRAT table. 741 * 742 * Default is auto (according to asic type, iommu_v2, and crat table, to decide 743 * whehter use CRAT) 744 */ 745 int ignore_crat; 746 module_param(ignore_crat, int, 0444); 747 MODULE_PARM_DESC(ignore_crat, 748 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)"); 749 750 /** 751 * DOC: halt_if_hws_hang (int) 752 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 753 * Setting 1 enables halt on hang. 754 */ 755 int halt_if_hws_hang; 756 module_param(halt_if_hws_hang, int, 0644); 757 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 758 759 /** 760 * DOC: hws_gws_support(bool) 761 * Assume that HWS supports GWS barriers regardless of what firmware version 762 * check says. Default value: false (rely on MEC2 firmware version check). 763 */ 764 bool hws_gws_support; 765 module_param(hws_gws_support, bool, 0444); 766 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 767 768 /** 769 * DOC: queue_preemption_timeout_ms (int) 770 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 771 */ 772 int queue_preemption_timeout_ms = 9000; 773 module_param(queue_preemption_timeout_ms, int, 0644); 774 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 775 776 /** 777 * DOC: debug_evictions(bool) 778 * Enable extra debug messages to help determine the cause of evictions 779 */ 780 bool debug_evictions; 781 module_param(debug_evictions, bool, 0644); 782 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 783 784 /** 785 * DOC: no_system_mem_limit(bool) 786 * Disable system memory limit, to support multiple process shared memory 787 */ 788 bool no_system_mem_limit; 789 module_param(no_system_mem_limit, bool, 0644); 790 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 791 792 /** 793 * DOC: no_queue_eviction_on_vm_fault (int) 794 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 795 */ 796 int amdgpu_no_queue_eviction_on_vm_fault = 0; 797 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 798 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 799 #endif 800 801 /** 802 * DOC: dcfeaturemask (uint) 803 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 804 * The default is the current set of stable display features. 805 */ 806 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 807 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 808 809 /** 810 * DOC: dcdebugmask (uint) 811 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 812 */ 813 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 814 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 815 816 /** 817 * DOC: abmlevel (uint) 818 * Override the default ABM (Adaptive Backlight Management) level used for DC 819 * enabled hardware. Requires DMCU to be supported and loaded. 820 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 821 * default. Values 1-4 control the maximum allowable brightness reduction via 822 * the ABM algorithm, with 1 being the least reduction and 4 being the most 823 * reduction. 824 * 825 * Defaults to 0, or disabled. Userspace can still override this level later 826 * after boot. 827 */ 828 uint amdgpu_dm_abm_level; 829 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 830 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 831 832 int amdgpu_backlight = -1; 833 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 834 module_param_named(backlight, amdgpu_backlight, bint, 0444); 835 836 /** 837 * DOC: tmz (int) 838 * Trusted Memory Zone (TMZ) is a method to protect data being written 839 * to or read from memory. 840 * 841 * The default value: 0 (off). TODO: change to auto till it is completed. 842 */ 843 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 844 module_param_named(tmz, amdgpu_tmz, int, 0444); 845 846 /** 847 * DOC: reset_method (int) 848 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco, 5 = pci) 849 */ 850 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco, 5 = pci)"); 851 module_param_named(reset_method, amdgpu_reset_method, int, 0444); 852 853 /** 854 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 855 * threshold value of faulty pages detected by RAS ECC, which may 856 * result in the GPU entering bad status when the number of total 857 * faulty pages by ECC exceeds the threshold value. 858 */ 859 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement, -2 = ignore bad page threshold)"); 860 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 861 862 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 863 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 864 865 /** 866 * DOC: smu_pptable_id (int) 867 * Used to override pptable id. id = 0 use VBIOS pptable. 868 * id > 0 use the soft pptable with specicfied id. 869 */ 870 MODULE_PARM_DESC(smu_pptable_id, 871 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 872 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 873 874 /* These devices are not supported by amdgpu. 875 * They are supported by the mach64, r128, radeon drivers 876 */ 877 static const u16 amdgpu_unsupported_pciidlist[] = { 878 /* mach64 */ 879 0x4354, 880 0x4358, 881 0x4554, 882 0x4742, 883 0x4744, 884 0x4749, 885 0x474C, 886 0x474D, 887 0x474E, 888 0x474F, 889 0x4750, 890 0x4751, 891 0x4752, 892 0x4753, 893 0x4754, 894 0x4755, 895 0x4756, 896 0x4757, 897 0x4758, 898 0x4759, 899 0x475A, 900 0x4C42, 901 0x4C44, 902 0x4C47, 903 0x4C49, 904 0x4C4D, 905 0x4C4E, 906 0x4C50, 907 0x4C51, 908 0x4C52, 909 0x4C53, 910 0x5654, 911 0x5655, 912 0x5656, 913 /* r128 */ 914 0x4c45, 915 0x4c46, 916 0x4d46, 917 0x4d4c, 918 0x5041, 919 0x5042, 920 0x5043, 921 0x5044, 922 0x5045, 923 0x5046, 924 0x5047, 925 0x5048, 926 0x5049, 927 0x504A, 928 0x504B, 929 0x504C, 930 0x504D, 931 0x504E, 932 0x504F, 933 0x5050, 934 0x5051, 935 0x5052, 936 0x5053, 937 0x5054, 938 0x5055, 939 0x5056, 940 0x5057, 941 0x5058, 942 0x5245, 943 0x5246, 944 0x5247, 945 0x524b, 946 0x524c, 947 0x534d, 948 0x5446, 949 0x544C, 950 0x5452, 951 /* radeon */ 952 0x3150, 953 0x3151, 954 0x3152, 955 0x3154, 956 0x3155, 957 0x3E50, 958 0x3E54, 959 0x4136, 960 0x4137, 961 0x4144, 962 0x4145, 963 0x4146, 964 0x4147, 965 0x4148, 966 0x4149, 967 0x414A, 968 0x414B, 969 0x4150, 970 0x4151, 971 0x4152, 972 0x4153, 973 0x4154, 974 0x4155, 975 0x4156, 976 0x4237, 977 0x4242, 978 0x4336, 979 0x4337, 980 0x4437, 981 0x4966, 982 0x4967, 983 0x4A48, 984 0x4A49, 985 0x4A4A, 986 0x4A4B, 987 0x4A4C, 988 0x4A4D, 989 0x4A4E, 990 0x4A4F, 991 0x4A50, 992 0x4A54, 993 0x4B48, 994 0x4B49, 995 0x4B4A, 996 0x4B4B, 997 0x4B4C, 998 0x4C57, 999 0x4C58, 1000 0x4C59, 1001 0x4C5A, 1002 0x4C64, 1003 0x4C66, 1004 0x4C67, 1005 0x4E44, 1006 0x4E45, 1007 0x4E46, 1008 0x4E47, 1009 0x4E48, 1010 0x4E49, 1011 0x4E4A, 1012 0x4E4B, 1013 0x4E50, 1014 0x4E51, 1015 0x4E52, 1016 0x4E53, 1017 0x4E54, 1018 0x4E56, 1019 0x5144, 1020 0x5145, 1021 0x5146, 1022 0x5147, 1023 0x5148, 1024 0x514C, 1025 0x514D, 1026 0x5157, 1027 0x5158, 1028 0x5159, 1029 0x515A, 1030 0x515E, 1031 0x5460, 1032 0x5462, 1033 0x5464, 1034 0x5548, 1035 0x5549, 1036 0x554A, 1037 0x554B, 1038 0x554C, 1039 0x554D, 1040 0x554E, 1041 0x554F, 1042 0x5550, 1043 0x5551, 1044 0x5552, 1045 0x5554, 1046 0x564A, 1047 0x564B, 1048 0x564F, 1049 0x5652, 1050 0x5653, 1051 0x5657, 1052 0x5834, 1053 0x5835, 1054 0x5954, 1055 0x5955, 1056 0x5974, 1057 0x5975, 1058 0x5960, 1059 0x5961, 1060 0x5962, 1061 0x5964, 1062 0x5965, 1063 0x5969, 1064 0x5a41, 1065 0x5a42, 1066 0x5a61, 1067 0x5a62, 1068 0x5b60, 1069 0x5b62, 1070 0x5b63, 1071 0x5b64, 1072 0x5b65, 1073 0x5c61, 1074 0x5c63, 1075 0x5d48, 1076 0x5d49, 1077 0x5d4a, 1078 0x5d4c, 1079 0x5d4d, 1080 0x5d4e, 1081 0x5d4f, 1082 0x5d50, 1083 0x5d52, 1084 0x5d57, 1085 0x5e48, 1086 0x5e4a, 1087 0x5e4b, 1088 0x5e4c, 1089 0x5e4d, 1090 0x5e4f, 1091 0x6700, 1092 0x6701, 1093 0x6702, 1094 0x6703, 1095 0x6704, 1096 0x6705, 1097 0x6706, 1098 0x6707, 1099 0x6708, 1100 0x6709, 1101 0x6718, 1102 0x6719, 1103 0x671c, 1104 0x671d, 1105 0x671f, 1106 0x6720, 1107 0x6721, 1108 0x6722, 1109 0x6723, 1110 0x6724, 1111 0x6725, 1112 0x6726, 1113 0x6727, 1114 0x6728, 1115 0x6729, 1116 0x6738, 1117 0x6739, 1118 0x673e, 1119 0x6740, 1120 0x6741, 1121 0x6742, 1122 0x6743, 1123 0x6744, 1124 0x6745, 1125 0x6746, 1126 0x6747, 1127 0x6748, 1128 0x6749, 1129 0x674A, 1130 0x6750, 1131 0x6751, 1132 0x6758, 1133 0x6759, 1134 0x675B, 1135 0x675D, 1136 0x675F, 1137 0x6760, 1138 0x6761, 1139 0x6762, 1140 0x6763, 1141 0x6764, 1142 0x6765, 1143 0x6766, 1144 0x6767, 1145 0x6768, 1146 0x6770, 1147 0x6771, 1148 0x6772, 1149 0x6778, 1150 0x6779, 1151 0x677B, 1152 0x6840, 1153 0x6841, 1154 0x6842, 1155 0x6843, 1156 0x6849, 1157 0x684C, 1158 0x6850, 1159 0x6858, 1160 0x6859, 1161 0x6880, 1162 0x6888, 1163 0x6889, 1164 0x688A, 1165 0x688C, 1166 0x688D, 1167 0x6898, 1168 0x6899, 1169 0x689b, 1170 0x689c, 1171 0x689d, 1172 0x689e, 1173 0x68a0, 1174 0x68a1, 1175 0x68a8, 1176 0x68a9, 1177 0x68b0, 1178 0x68b8, 1179 0x68b9, 1180 0x68ba, 1181 0x68be, 1182 0x68bf, 1183 0x68c0, 1184 0x68c1, 1185 0x68c7, 1186 0x68c8, 1187 0x68c9, 1188 0x68d8, 1189 0x68d9, 1190 0x68da, 1191 0x68de, 1192 0x68e0, 1193 0x68e1, 1194 0x68e4, 1195 0x68e5, 1196 0x68e8, 1197 0x68e9, 1198 0x68f1, 1199 0x68f2, 1200 0x68f8, 1201 0x68f9, 1202 0x68fa, 1203 0x68fe, 1204 0x7100, 1205 0x7101, 1206 0x7102, 1207 0x7103, 1208 0x7104, 1209 0x7105, 1210 0x7106, 1211 0x7108, 1212 0x7109, 1213 0x710A, 1214 0x710B, 1215 0x710C, 1216 0x710E, 1217 0x710F, 1218 0x7140, 1219 0x7141, 1220 0x7142, 1221 0x7143, 1222 0x7144, 1223 0x7145, 1224 0x7146, 1225 0x7147, 1226 0x7149, 1227 0x714A, 1228 0x714B, 1229 0x714C, 1230 0x714D, 1231 0x714E, 1232 0x714F, 1233 0x7151, 1234 0x7152, 1235 0x7153, 1236 0x715E, 1237 0x715F, 1238 0x7180, 1239 0x7181, 1240 0x7183, 1241 0x7186, 1242 0x7187, 1243 0x7188, 1244 0x718A, 1245 0x718B, 1246 0x718C, 1247 0x718D, 1248 0x718F, 1249 0x7193, 1250 0x7196, 1251 0x719B, 1252 0x719F, 1253 0x71C0, 1254 0x71C1, 1255 0x71C2, 1256 0x71C3, 1257 0x71C4, 1258 0x71C5, 1259 0x71C6, 1260 0x71C7, 1261 0x71CD, 1262 0x71CE, 1263 0x71D2, 1264 0x71D4, 1265 0x71D5, 1266 0x71D6, 1267 0x71DA, 1268 0x71DE, 1269 0x7200, 1270 0x7210, 1271 0x7211, 1272 0x7240, 1273 0x7243, 1274 0x7244, 1275 0x7245, 1276 0x7246, 1277 0x7247, 1278 0x7248, 1279 0x7249, 1280 0x724A, 1281 0x724B, 1282 0x724C, 1283 0x724D, 1284 0x724E, 1285 0x724F, 1286 0x7280, 1287 0x7281, 1288 0x7283, 1289 0x7284, 1290 0x7287, 1291 0x7288, 1292 0x7289, 1293 0x728B, 1294 0x728C, 1295 0x7290, 1296 0x7291, 1297 0x7293, 1298 0x7297, 1299 0x7834, 1300 0x7835, 1301 0x791e, 1302 0x791f, 1303 0x793f, 1304 0x7941, 1305 0x7942, 1306 0x796c, 1307 0x796d, 1308 0x796e, 1309 0x796f, 1310 0x9400, 1311 0x9401, 1312 0x9402, 1313 0x9403, 1314 0x9405, 1315 0x940A, 1316 0x940B, 1317 0x940F, 1318 0x94A0, 1319 0x94A1, 1320 0x94A3, 1321 0x94B1, 1322 0x94B3, 1323 0x94B4, 1324 0x94B5, 1325 0x94B9, 1326 0x9440, 1327 0x9441, 1328 0x9442, 1329 0x9443, 1330 0x9444, 1331 0x9446, 1332 0x944A, 1333 0x944B, 1334 0x944C, 1335 0x944E, 1336 0x9450, 1337 0x9452, 1338 0x9456, 1339 0x945A, 1340 0x945B, 1341 0x945E, 1342 0x9460, 1343 0x9462, 1344 0x946A, 1345 0x946B, 1346 0x947A, 1347 0x947B, 1348 0x9480, 1349 0x9487, 1350 0x9488, 1351 0x9489, 1352 0x948A, 1353 0x948F, 1354 0x9490, 1355 0x9491, 1356 0x9495, 1357 0x9498, 1358 0x949C, 1359 0x949E, 1360 0x949F, 1361 0x94C0, 1362 0x94C1, 1363 0x94C3, 1364 0x94C4, 1365 0x94C5, 1366 0x94C6, 1367 0x94C7, 1368 0x94C8, 1369 0x94C9, 1370 0x94CB, 1371 0x94CC, 1372 0x94CD, 1373 0x9500, 1374 0x9501, 1375 0x9504, 1376 0x9505, 1377 0x9506, 1378 0x9507, 1379 0x9508, 1380 0x9509, 1381 0x950F, 1382 0x9511, 1383 0x9515, 1384 0x9517, 1385 0x9519, 1386 0x9540, 1387 0x9541, 1388 0x9542, 1389 0x954E, 1390 0x954F, 1391 0x9552, 1392 0x9553, 1393 0x9555, 1394 0x9557, 1395 0x955f, 1396 0x9580, 1397 0x9581, 1398 0x9583, 1399 0x9586, 1400 0x9587, 1401 0x9588, 1402 0x9589, 1403 0x958A, 1404 0x958B, 1405 0x958C, 1406 0x958D, 1407 0x958E, 1408 0x958F, 1409 0x9590, 1410 0x9591, 1411 0x9593, 1412 0x9595, 1413 0x9596, 1414 0x9597, 1415 0x9598, 1416 0x9599, 1417 0x959B, 1418 0x95C0, 1419 0x95C2, 1420 0x95C4, 1421 0x95C5, 1422 0x95C6, 1423 0x95C7, 1424 0x95C9, 1425 0x95CC, 1426 0x95CD, 1427 0x95CE, 1428 0x95CF, 1429 0x9610, 1430 0x9611, 1431 0x9612, 1432 0x9613, 1433 0x9614, 1434 0x9615, 1435 0x9616, 1436 0x9640, 1437 0x9641, 1438 0x9642, 1439 0x9643, 1440 0x9644, 1441 0x9645, 1442 0x9647, 1443 0x9648, 1444 0x9649, 1445 0x964a, 1446 0x964b, 1447 0x964c, 1448 0x964e, 1449 0x964f, 1450 0x9710, 1451 0x9711, 1452 0x9712, 1453 0x9713, 1454 0x9714, 1455 0x9715, 1456 0x9802, 1457 0x9803, 1458 0x9804, 1459 0x9805, 1460 0x9806, 1461 0x9807, 1462 0x9808, 1463 0x9809, 1464 0x980A, 1465 0x9900, 1466 0x9901, 1467 0x9903, 1468 0x9904, 1469 0x9905, 1470 0x9906, 1471 0x9907, 1472 0x9908, 1473 0x9909, 1474 0x990A, 1475 0x990B, 1476 0x990C, 1477 0x990D, 1478 0x990E, 1479 0x990F, 1480 0x9910, 1481 0x9913, 1482 0x9917, 1483 0x9918, 1484 0x9919, 1485 0x9990, 1486 0x9991, 1487 0x9992, 1488 0x9993, 1489 0x9994, 1490 0x9995, 1491 0x9996, 1492 0x9997, 1493 0x9998, 1494 0x9999, 1495 0x999A, 1496 0x999B, 1497 0x999C, 1498 0x999D, 1499 0x99A0, 1500 0x99A2, 1501 0x99A4, 1502 /* radeon secondary ids */ 1503 0x3171, 1504 0x3e70, 1505 0x4164, 1506 0x4165, 1507 0x4166, 1508 0x4168, 1509 0x4170, 1510 0x4171, 1511 0x4172, 1512 0x4173, 1513 0x496e, 1514 0x4a69, 1515 0x4a6a, 1516 0x4a6b, 1517 0x4a70, 1518 0x4a74, 1519 0x4b69, 1520 0x4b6b, 1521 0x4b6c, 1522 0x4c6e, 1523 0x4e64, 1524 0x4e65, 1525 0x4e66, 1526 0x4e67, 1527 0x4e68, 1528 0x4e69, 1529 0x4e6a, 1530 0x4e71, 1531 0x4f73, 1532 0x5569, 1533 0x556b, 1534 0x556d, 1535 0x556f, 1536 0x5571, 1537 0x5854, 1538 0x5874, 1539 0x5940, 1540 0x5941, 1541 0x5b72, 1542 0x5b73, 1543 0x5b74, 1544 0x5b75, 1545 0x5d44, 1546 0x5d45, 1547 0x5d6d, 1548 0x5d6f, 1549 0x5d72, 1550 0x5d77, 1551 0x5e6b, 1552 0x5e6d, 1553 0x7120, 1554 0x7124, 1555 0x7129, 1556 0x712e, 1557 0x712f, 1558 0x7162, 1559 0x7163, 1560 0x7166, 1561 0x7167, 1562 0x7172, 1563 0x7173, 1564 0x71a0, 1565 0x71a1, 1566 0x71a3, 1567 0x71a7, 1568 0x71bb, 1569 0x71e0, 1570 0x71e1, 1571 0x71e2, 1572 0x71e6, 1573 0x71e7, 1574 0x71f2, 1575 0x7269, 1576 0x726b, 1577 0x726e, 1578 0x72a0, 1579 0x72a8, 1580 0x72b1, 1581 0x72b3, 1582 0x793f, 1583 }; 1584 1585 static const struct pci_device_id pciidlist[] = { 1586 #ifdef CONFIG_DRM_AMDGPU_SI 1587 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1588 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1589 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1590 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1591 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1592 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1593 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1594 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1595 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1596 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1597 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1598 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1599 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1600 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1601 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1602 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1603 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1604 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1605 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1606 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1607 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1608 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1609 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1610 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1611 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1612 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1613 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1614 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1615 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1616 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1617 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1618 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1619 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1620 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1621 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1622 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1623 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1624 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1625 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1626 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1627 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1628 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1629 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1630 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1631 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1632 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1633 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1634 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1635 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1636 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1637 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1638 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1639 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1640 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1641 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1642 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1643 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1644 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1645 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1646 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1647 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1648 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1649 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1650 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1651 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1652 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1653 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1654 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1655 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1656 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1657 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1658 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1659 #endif 1660 #ifdef CONFIG_DRM_AMDGPU_CIK 1661 /* Kaveri */ 1662 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1663 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1664 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1665 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1666 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1667 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1668 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1669 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1670 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1671 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1672 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1673 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1674 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1675 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1676 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1677 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1678 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1679 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1680 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1681 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1682 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1683 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1684 /* Bonaire */ 1685 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1686 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1687 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1688 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1689 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1690 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1691 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1692 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1693 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1694 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1695 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1696 /* Hawaii */ 1697 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1698 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1699 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1700 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1701 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1702 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1703 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1704 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1705 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1706 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1707 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1708 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1709 /* Kabini */ 1710 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1711 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1712 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1713 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1714 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1715 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1716 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1717 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1718 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1719 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1720 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1721 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1722 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1723 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1724 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1725 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1726 /* mullins */ 1727 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1728 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1729 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1730 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1731 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1732 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1733 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1734 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1735 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1736 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1737 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1738 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1739 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1740 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1741 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1742 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1743 #endif 1744 /* topaz */ 1745 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1746 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1747 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1748 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1749 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1750 /* tonga */ 1751 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1752 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1753 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1754 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1755 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1756 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1757 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1758 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1759 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1760 /* fiji */ 1761 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1762 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1763 /* carrizo */ 1764 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1765 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1766 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1767 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1768 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1769 /* stoney */ 1770 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1771 /* Polaris11 */ 1772 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1773 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1774 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1775 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1776 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1777 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1778 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1779 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1780 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1781 /* Polaris10 */ 1782 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1783 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1784 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1785 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1786 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1787 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1788 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1789 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1790 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1791 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1792 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1793 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1794 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1795 /* Polaris12 */ 1796 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1797 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1798 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1799 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1800 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1801 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1802 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1803 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1804 /* VEGAM */ 1805 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1806 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1807 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1808 /* Vega 10 */ 1809 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1810 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1811 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1812 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1813 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1814 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1815 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1816 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1817 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1818 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1819 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1820 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1821 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1822 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1823 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1824 /* Vega 12 */ 1825 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1826 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1827 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1828 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1829 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1830 /* Vega 20 */ 1831 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1832 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1833 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1834 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1835 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1836 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1837 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1838 /* Raven */ 1839 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1840 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1841 /* Arcturus */ 1842 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1843 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1844 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1845 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1846 /* Navi10 */ 1847 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1848 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1849 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1850 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1851 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1852 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1853 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1854 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1855 /* Navi14 */ 1856 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1857 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1858 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1859 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1860 1861 /* Renoir */ 1862 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1863 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1864 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1865 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1866 1867 /* Navi12 */ 1868 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1869 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1870 1871 /* Sienna_Cichlid */ 1872 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1873 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1874 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1875 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1876 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1877 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1878 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1879 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1880 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1881 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1882 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1883 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1884 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1885 1886 /* Van Gogh */ 1887 {0x1002, 0x163F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VANGOGH|AMD_IS_APU}, 1888 1889 /* Yellow Carp */ 1890 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1891 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1892 1893 /* Navy_Flounder */ 1894 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1895 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1896 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1897 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1898 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1899 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1900 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1901 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1902 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1903 1904 /* DIMGREY_CAVEFISH */ 1905 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1906 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1907 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1908 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1909 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1910 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1911 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1912 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1913 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1914 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1915 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1916 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1917 1918 /* Aldebaran */ 1919 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1920 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1921 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1922 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1923 1924 /* CYAN_SKILLFISH */ 1925 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 1926 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 1927 1928 /* BEIGE_GOBY */ 1929 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1930 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1931 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1932 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1933 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1934 1935 { PCI_DEVICE(0x1002, PCI_ANY_ID), 1936 .class = PCI_CLASS_DISPLAY_VGA << 8, 1937 .class_mask = 0xffffff, 1938 .driver_data = CHIP_IP_DISCOVERY }, 1939 1940 { PCI_DEVICE(0x1002, PCI_ANY_ID), 1941 .class = PCI_CLASS_DISPLAY_OTHER << 8, 1942 .class_mask = 0xffffff, 1943 .driver_data = CHIP_IP_DISCOVERY }, 1944 1945 {0, 0, 0} 1946 }; 1947 1948 MODULE_DEVICE_TABLE(pci, pciidlist); 1949 1950 static const struct drm_driver amdgpu_kms_driver; 1951 1952 static bool amdgpu_is_fw_framebuffer(resource_size_t base, 1953 resource_size_t size) 1954 { 1955 bool found = false; 1956 #if IS_REACHABLE(CONFIG_FB) 1957 struct apertures_struct *a; 1958 1959 a = alloc_apertures(1); 1960 if (!a) 1961 return false; 1962 1963 a->ranges[0].base = base; 1964 a->ranges[0].size = size; 1965 1966 found = is_firmware_framebuffer(a); 1967 kfree(a); 1968 #endif 1969 return found; 1970 } 1971 1972 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 1973 { 1974 struct pci_dev *p = NULL; 1975 int i; 1976 1977 /* 0 - GPU 1978 * 1 - audio 1979 * 2 - USB 1980 * 3 - UCSI 1981 */ 1982 for (i = 1; i < 4; i++) { 1983 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 1984 adev->pdev->bus->number, i); 1985 if (p) { 1986 pm_runtime_get_sync(&p->dev); 1987 pm_runtime_mark_last_busy(&p->dev); 1988 pm_runtime_put_autosuspend(&p->dev); 1989 pci_dev_put(p); 1990 } 1991 } 1992 } 1993 1994 static int amdgpu_pci_probe(struct pci_dev *pdev, 1995 const struct pci_device_id *ent) 1996 { 1997 struct drm_device *ddev; 1998 struct amdgpu_device *adev; 1999 unsigned long flags = ent->driver_data; 2000 int ret, retry = 0, i; 2001 bool supports_atomic = false; 2002 bool is_fw_fb; 2003 resource_size_t base, size; 2004 2005 /* skip devices which are owned by radeon */ 2006 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2007 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2008 return -ENODEV; 2009 } 2010 2011 if (amdgpu_virtual_display || 2012 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 2013 supports_atomic = true; 2014 2015 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2016 DRM_INFO("This hardware requires experimental hardware support.\n" 2017 "See modparam exp_hw_support\n"); 2018 return -ENODEV; 2019 } 2020 2021 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2022 * however, SME requires an indirect IOMMU mapping because the encryption 2023 * bit is beyond the DMA mask of the chip. 2024 */ 2025 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2026 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2027 dev_info(&pdev->dev, 2028 "SME is not compatible with RAVEN\n"); 2029 return -ENOTSUPP; 2030 } 2031 2032 #ifdef CONFIG_DRM_AMDGPU_SI 2033 if (!amdgpu_si_support) { 2034 switch (flags & AMD_ASIC_MASK) { 2035 case CHIP_TAHITI: 2036 case CHIP_PITCAIRN: 2037 case CHIP_VERDE: 2038 case CHIP_OLAND: 2039 case CHIP_HAINAN: 2040 dev_info(&pdev->dev, 2041 "SI support provided by radeon.\n"); 2042 dev_info(&pdev->dev, 2043 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 2044 ); 2045 return -ENODEV; 2046 } 2047 } 2048 #endif 2049 #ifdef CONFIG_DRM_AMDGPU_CIK 2050 if (!amdgpu_cik_support) { 2051 switch (flags & AMD_ASIC_MASK) { 2052 case CHIP_KAVERI: 2053 case CHIP_BONAIRE: 2054 case CHIP_HAWAII: 2055 case CHIP_KABINI: 2056 case CHIP_MULLINS: 2057 dev_info(&pdev->dev, 2058 "CIK support provided by radeon.\n"); 2059 dev_info(&pdev->dev, 2060 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 2061 ); 2062 return -ENODEV; 2063 } 2064 } 2065 #endif 2066 2067 base = pci_resource_start(pdev, 0); 2068 size = pci_resource_len(pdev, 0); 2069 is_fw_fb = amdgpu_is_fw_framebuffer(base, size); 2070 2071 /* Get rid of things like offb */ 2072 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &amdgpu_kms_driver); 2073 if (ret) 2074 return ret; 2075 2076 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2077 if (IS_ERR(adev)) 2078 return PTR_ERR(adev); 2079 2080 adev->dev = &pdev->dev; 2081 adev->pdev = pdev; 2082 ddev = adev_to_drm(adev); 2083 adev->is_fw_fb = is_fw_fb; 2084 2085 if (!supports_atomic) 2086 ddev->driver_features &= ~DRIVER_ATOMIC; 2087 2088 ret = pci_enable_device(pdev); 2089 if (ret) 2090 return ret; 2091 2092 pci_set_drvdata(pdev, ddev); 2093 2094 ret = amdgpu_driver_load_kms(adev, ent->driver_data); 2095 if (ret) 2096 goto err_pci; 2097 2098 retry_init: 2099 ret = drm_dev_register(ddev, ent->driver_data); 2100 if (ret == -EAGAIN && ++retry <= 3) { 2101 DRM_INFO("retry init %d\n", retry); 2102 /* Don't request EX mode too frequently which is attacking */ 2103 msleep(5000); 2104 goto retry_init; 2105 } else if (ret) { 2106 goto err_pci; 2107 } 2108 2109 /* 2110 * 1. don't init fbdev on hw without DCE 2111 * 2. don't init fbdev if there are no connectors 2112 */ 2113 if (adev->mode_info.mode_config_initialized && 2114 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2115 /* select 8 bpp console on low vram cards */ 2116 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2117 drm_fbdev_generic_setup(adev_to_drm(adev), 8); 2118 else 2119 drm_fbdev_generic_setup(adev_to_drm(adev), 32); 2120 } 2121 2122 ret = amdgpu_debugfs_init(adev); 2123 if (ret) 2124 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2125 2126 if (adev->runpm) { 2127 /* only need to skip on ATPX */ 2128 if (amdgpu_device_supports_px(ddev)) 2129 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2130 /* we want direct complete for BOCO */ 2131 if (amdgpu_device_supports_boco(ddev)) 2132 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2133 DPM_FLAG_SMART_SUSPEND | 2134 DPM_FLAG_MAY_SKIP_RESUME); 2135 pm_runtime_use_autosuspend(ddev->dev); 2136 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2137 2138 pm_runtime_allow(ddev->dev); 2139 2140 pm_runtime_mark_last_busy(ddev->dev); 2141 pm_runtime_put_autosuspend(ddev->dev); 2142 2143 /* 2144 * For runpm implemented via BACO, PMFW will handle the 2145 * timing for BACO in and out: 2146 * - put ASIC into BACO state only when both video and 2147 * audio functions are in D3 state. 2148 * - pull ASIC out of BACO state when either video or 2149 * audio function is in D0 state. 2150 * Also, at startup, PMFW assumes both functions are in 2151 * D0 state. 2152 * 2153 * So if snd driver was loaded prior to amdgpu driver 2154 * and audio function was put into D3 state, there will 2155 * be no PMFW-aware D-state transition(D0->D3) on runpm 2156 * suspend. Thus the BACO will be not correctly kicked in. 2157 * 2158 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2159 * into D0 state. Then there will be a PMFW-aware D-state 2160 * transition(D0->D3) on runpm suspend. 2161 */ 2162 if (amdgpu_device_supports_baco(ddev) && 2163 !(adev->flags & AMD_IS_APU) && 2164 (adev->asic_type >= CHIP_NAVI10)) 2165 amdgpu_get_secondary_funcs(adev); 2166 } 2167 2168 return 0; 2169 2170 err_pci: 2171 pci_disable_device(pdev); 2172 return ret; 2173 } 2174 2175 static void 2176 amdgpu_pci_remove(struct pci_dev *pdev) 2177 { 2178 struct drm_device *dev = pci_get_drvdata(pdev); 2179 struct amdgpu_device *adev = drm_to_adev(dev); 2180 2181 drm_dev_unplug(dev); 2182 2183 if (adev->runpm) { 2184 pm_runtime_get_sync(dev->dev); 2185 pm_runtime_forbid(dev->dev); 2186 } 2187 2188 amdgpu_driver_unload_kms(dev); 2189 2190 /* 2191 * Flush any in flight DMA operations from device. 2192 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2193 * StatusTransactions Pending bit. 2194 */ 2195 pci_disable_device(pdev); 2196 pci_wait_for_pending_transaction(pdev); 2197 } 2198 2199 static void 2200 amdgpu_pci_shutdown(struct pci_dev *pdev) 2201 { 2202 struct drm_device *dev = pci_get_drvdata(pdev); 2203 struct amdgpu_device *adev = drm_to_adev(dev); 2204 2205 if (amdgpu_ras_intr_triggered()) 2206 return; 2207 2208 /* if we are running in a VM, make sure the device 2209 * torn down properly on reboot/shutdown. 2210 * unfortunately we can't detect certain 2211 * hypervisors so just do this all the time. 2212 */ 2213 if (!amdgpu_passthrough(adev)) 2214 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2215 amdgpu_device_ip_suspend(adev); 2216 adev->mp1_state = PP_MP1_STATE_NONE; 2217 } 2218 2219 /** 2220 * amdgpu_drv_delayed_reset_work_handler - work handler for reset 2221 * 2222 * @work: work_struct. 2223 */ 2224 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) 2225 { 2226 struct list_head device_list; 2227 struct amdgpu_device *adev; 2228 int i, r; 2229 struct amdgpu_reset_context reset_context; 2230 2231 memset(&reset_context, 0, sizeof(reset_context)); 2232 2233 mutex_lock(&mgpu_info.mutex); 2234 if (mgpu_info.pending_reset == true) { 2235 mutex_unlock(&mgpu_info.mutex); 2236 return; 2237 } 2238 mgpu_info.pending_reset = true; 2239 mutex_unlock(&mgpu_info.mutex); 2240 2241 /* Use a common context, just need to make sure full reset is done */ 2242 reset_context.method = AMD_RESET_METHOD_NONE; 2243 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2244 2245 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2246 adev = mgpu_info.gpu_ins[i].adev; 2247 reset_context.reset_req_dev = adev; 2248 r = amdgpu_device_pre_asic_reset(adev, &reset_context); 2249 if (r) { 2250 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", 2251 r, adev_to_drm(adev)->unique); 2252 } 2253 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) 2254 r = -EALREADY; 2255 } 2256 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2257 adev = mgpu_info.gpu_ins[i].adev; 2258 flush_work(&adev->xgmi_reset_work); 2259 adev->gmc.xgmi.pending_reset = false; 2260 } 2261 2262 /* reset function will rebuild the xgmi hive info , clear it now */ 2263 for (i = 0; i < mgpu_info.num_dgpu; i++) 2264 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); 2265 2266 INIT_LIST_HEAD(&device_list); 2267 2268 for (i = 0; i < mgpu_info.num_dgpu; i++) 2269 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); 2270 2271 /* unregister the GPU first, reset function will add them back */ 2272 list_for_each_entry(adev, &device_list, reset_list) 2273 amdgpu_unregister_gpu_instance(adev); 2274 2275 /* Use a common context, just need to make sure full reset is done */ 2276 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); 2277 r = amdgpu_do_asic_reset(&device_list, &reset_context); 2278 2279 if (r) { 2280 DRM_ERROR("reinit gpus failure"); 2281 return; 2282 } 2283 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2284 adev = mgpu_info.gpu_ins[i].adev; 2285 if (!adev->kfd.init_complete) 2286 amdgpu_amdkfd_device_init(adev); 2287 amdgpu_ttm_set_buffer_funcs_status(adev, true); 2288 } 2289 return; 2290 } 2291 2292 static int amdgpu_pmops_prepare(struct device *dev) 2293 { 2294 struct drm_device *drm_dev = dev_get_drvdata(dev); 2295 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2296 2297 /* Return a positive number here so 2298 * DPM_FLAG_SMART_SUSPEND works properly 2299 */ 2300 if (amdgpu_device_supports_boco(drm_dev)) 2301 return pm_runtime_suspended(dev); 2302 2303 /* if we will not support s3 or s2i for the device 2304 * then skip suspend 2305 */ 2306 if (!amdgpu_acpi_is_s0ix_active(adev) && 2307 !amdgpu_acpi_is_s3_active(adev)) 2308 return 1; 2309 2310 return 0; 2311 } 2312 2313 static void amdgpu_pmops_complete(struct device *dev) 2314 { 2315 /* nothing to do */ 2316 } 2317 2318 static int amdgpu_pmops_suspend(struct device *dev) 2319 { 2320 struct drm_device *drm_dev = dev_get_drvdata(dev); 2321 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2322 int r; 2323 2324 if (amdgpu_acpi_is_s0ix_active(adev)) 2325 adev->in_s0ix = true; 2326 else 2327 adev->in_s3 = true; 2328 r = amdgpu_device_suspend(drm_dev, true); 2329 if (r) 2330 return r; 2331 if (!adev->in_s0ix) 2332 r = amdgpu_asic_reset(adev); 2333 return r; 2334 } 2335 2336 static int amdgpu_pmops_resume(struct device *dev) 2337 { 2338 struct drm_device *drm_dev = dev_get_drvdata(dev); 2339 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2340 int r; 2341 2342 /* Avoids registers access if device is physically gone */ 2343 if (!pci_device_is_present(adev->pdev)) 2344 adev->no_hw_access = true; 2345 2346 r = amdgpu_device_resume(drm_dev, true); 2347 if (amdgpu_acpi_is_s0ix_active(adev)) 2348 adev->in_s0ix = false; 2349 else 2350 adev->in_s3 = false; 2351 return r; 2352 } 2353 2354 static int amdgpu_pmops_freeze(struct device *dev) 2355 { 2356 struct drm_device *drm_dev = dev_get_drvdata(dev); 2357 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2358 int r; 2359 2360 adev->in_s4 = true; 2361 r = amdgpu_device_suspend(drm_dev, true); 2362 adev->in_s4 = false; 2363 if (r) 2364 return r; 2365 return amdgpu_asic_reset(adev); 2366 } 2367 2368 static int amdgpu_pmops_thaw(struct device *dev) 2369 { 2370 struct drm_device *drm_dev = dev_get_drvdata(dev); 2371 2372 return amdgpu_device_resume(drm_dev, true); 2373 } 2374 2375 static int amdgpu_pmops_poweroff(struct device *dev) 2376 { 2377 struct drm_device *drm_dev = dev_get_drvdata(dev); 2378 2379 return amdgpu_device_suspend(drm_dev, true); 2380 } 2381 2382 static int amdgpu_pmops_restore(struct device *dev) 2383 { 2384 struct drm_device *drm_dev = dev_get_drvdata(dev); 2385 2386 return amdgpu_device_resume(drm_dev, true); 2387 } 2388 2389 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2390 { 2391 struct pci_dev *pdev = to_pci_dev(dev); 2392 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2393 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2394 int ret, i; 2395 2396 if (!adev->runpm) { 2397 pm_runtime_forbid(dev); 2398 return -EBUSY; 2399 } 2400 2401 /* wait for all rings to drain before suspending */ 2402 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2403 struct amdgpu_ring *ring = adev->rings[i]; 2404 if (ring && ring->sched.ready) { 2405 ret = amdgpu_fence_wait_empty(ring); 2406 if (ret) 2407 return -EBUSY; 2408 } 2409 } 2410 2411 adev->in_runpm = true; 2412 if (amdgpu_device_supports_px(drm_dev)) 2413 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2414 2415 /* 2416 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2417 * proper cleanups and put itself into a state ready for PNP. That 2418 * can address some random resuming failure observed on BOCO capable 2419 * platforms. 2420 * TODO: this may be also needed for PX capable platform. 2421 */ 2422 if (amdgpu_device_supports_boco(drm_dev)) 2423 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2424 2425 ret = amdgpu_device_suspend(drm_dev, false); 2426 if (ret) { 2427 adev->in_runpm = false; 2428 if (amdgpu_device_supports_boco(drm_dev)) 2429 adev->mp1_state = PP_MP1_STATE_NONE; 2430 return ret; 2431 } 2432 2433 if (amdgpu_device_supports_boco(drm_dev)) 2434 adev->mp1_state = PP_MP1_STATE_NONE; 2435 2436 if (amdgpu_device_supports_px(drm_dev)) { 2437 /* Only need to handle PCI state in the driver for ATPX 2438 * PCI core handles it for _PR3. 2439 */ 2440 amdgpu_device_cache_pci_state(pdev); 2441 pci_disable_device(pdev); 2442 pci_ignore_hotplug(pdev); 2443 pci_set_power_state(pdev, PCI_D3cold); 2444 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2445 } else if (amdgpu_device_supports_boco(drm_dev)) { 2446 /* nothing to do */ 2447 } else if (amdgpu_device_supports_baco(drm_dev)) { 2448 amdgpu_device_baco_enter(drm_dev); 2449 } 2450 2451 return 0; 2452 } 2453 2454 static int amdgpu_pmops_runtime_resume(struct device *dev) 2455 { 2456 struct pci_dev *pdev = to_pci_dev(dev); 2457 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2458 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2459 int ret; 2460 2461 if (!adev->runpm) 2462 return -EINVAL; 2463 2464 /* Avoids registers access if device is physically gone */ 2465 if (!pci_device_is_present(adev->pdev)) 2466 adev->no_hw_access = true; 2467 2468 if (amdgpu_device_supports_px(drm_dev)) { 2469 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2470 2471 /* Only need to handle PCI state in the driver for ATPX 2472 * PCI core handles it for _PR3. 2473 */ 2474 pci_set_power_state(pdev, PCI_D0); 2475 amdgpu_device_load_pci_state(pdev); 2476 ret = pci_enable_device(pdev); 2477 if (ret) 2478 return ret; 2479 pci_set_master(pdev); 2480 } else if (amdgpu_device_supports_boco(drm_dev)) { 2481 /* Only need to handle PCI state in the driver for ATPX 2482 * PCI core handles it for _PR3. 2483 */ 2484 pci_set_master(pdev); 2485 } else if (amdgpu_device_supports_baco(drm_dev)) { 2486 amdgpu_device_baco_exit(drm_dev); 2487 } 2488 ret = amdgpu_device_resume(drm_dev, false); 2489 if (ret) 2490 return ret; 2491 2492 if (amdgpu_device_supports_px(drm_dev)) 2493 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2494 adev->in_runpm = false; 2495 return 0; 2496 } 2497 2498 static int amdgpu_pmops_runtime_idle(struct device *dev) 2499 { 2500 struct drm_device *drm_dev = dev_get_drvdata(dev); 2501 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2502 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 2503 int ret = 1; 2504 2505 if (!adev->runpm) { 2506 pm_runtime_forbid(dev); 2507 return -EBUSY; 2508 } 2509 2510 if (amdgpu_device_has_dc_support(adev)) { 2511 struct drm_crtc *crtc; 2512 2513 drm_for_each_crtc(crtc, drm_dev) { 2514 drm_modeset_lock(&crtc->mutex, NULL); 2515 if (crtc->state->active) 2516 ret = -EBUSY; 2517 drm_modeset_unlock(&crtc->mutex); 2518 if (ret < 0) 2519 break; 2520 } 2521 2522 } else { 2523 struct drm_connector *list_connector; 2524 struct drm_connector_list_iter iter; 2525 2526 mutex_lock(&drm_dev->mode_config.mutex); 2527 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2528 2529 drm_connector_list_iter_begin(drm_dev, &iter); 2530 drm_for_each_connector_iter(list_connector, &iter) { 2531 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2532 ret = -EBUSY; 2533 break; 2534 } 2535 } 2536 2537 drm_connector_list_iter_end(&iter); 2538 2539 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2540 mutex_unlock(&drm_dev->mode_config.mutex); 2541 } 2542 2543 if (ret == -EBUSY) 2544 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 2545 2546 pm_runtime_mark_last_busy(dev); 2547 pm_runtime_autosuspend(dev); 2548 return ret; 2549 } 2550 2551 long amdgpu_drm_ioctl(struct file *filp, 2552 unsigned int cmd, unsigned long arg) 2553 { 2554 struct drm_file *file_priv = filp->private_data; 2555 struct drm_device *dev; 2556 long ret; 2557 dev = file_priv->minor->dev; 2558 ret = pm_runtime_get_sync(dev->dev); 2559 if (ret < 0) 2560 goto out; 2561 2562 ret = drm_ioctl(filp, cmd, arg); 2563 2564 pm_runtime_mark_last_busy(dev->dev); 2565 out: 2566 pm_runtime_put_autosuspend(dev->dev); 2567 return ret; 2568 } 2569 2570 static const struct dev_pm_ops amdgpu_pm_ops = { 2571 .prepare = amdgpu_pmops_prepare, 2572 .complete = amdgpu_pmops_complete, 2573 .suspend = amdgpu_pmops_suspend, 2574 .resume = amdgpu_pmops_resume, 2575 .freeze = amdgpu_pmops_freeze, 2576 .thaw = amdgpu_pmops_thaw, 2577 .poweroff = amdgpu_pmops_poweroff, 2578 .restore = amdgpu_pmops_restore, 2579 .runtime_suspend = amdgpu_pmops_runtime_suspend, 2580 .runtime_resume = amdgpu_pmops_runtime_resume, 2581 .runtime_idle = amdgpu_pmops_runtime_idle, 2582 }; 2583 2584 static int amdgpu_flush(struct file *f, fl_owner_t id) 2585 { 2586 struct drm_file *file_priv = f->private_data; 2587 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2588 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2589 2590 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 2591 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 2592 2593 return timeout >= 0 ? 0 : timeout; 2594 } 2595 2596 static const struct file_operations amdgpu_driver_kms_fops = { 2597 .owner = THIS_MODULE, 2598 .open = drm_open, 2599 .flush = amdgpu_flush, 2600 .release = drm_release, 2601 .unlocked_ioctl = amdgpu_drm_ioctl, 2602 .mmap = drm_gem_mmap, 2603 .poll = drm_poll, 2604 .read = drm_read, 2605 #ifdef CONFIG_COMPAT 2606 .compat_ioctl = amdgpu_kms_compat_ioctl, 2607 #endif 2608 #ifdef CONFIG_PROC_FS 2609 .show_fdinfo = amdgpu_show_fdinfo 2610 #endif 2611 }; 2612 2613 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 2614 { 2615 struct drm_file *file; 2616 2617 if (!filp) 2618 return -EINVAL; 2619 2620 if (filp->f_op != &amdgpu_driver_kms_fops) { 2621 return -EINVAL; 2622 } 2623 2624 file = filp->private_data; 2625 *fpriv = file->driver_priv; 2626 return 0; 2627 } 2628 2629 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 2630 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2631 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2632 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2633 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 2634 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2635 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2636 /* KMS */ 2637 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2638 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2639 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2640 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2641 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2642 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2643 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2644 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2645 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2646 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2647 }; 2648 2649 static const struct drm_driver amdgpu_kms_driver = { 2650 .driver_features = 2651 DRIVER_ATOMIC | 2652 DRIVER_GEM | 2653 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 2654 DRIVER_SYNCOBJ_TIMELINE, 2655 .open = amdgpu_driver_open_kms, 2656 .postclose = amdgpu_driver_postclose_kms, 2657 .lastclose = amdgpu_driver_lastclose_kms, 2658 .ioctls = amdgpu_ioctls_kms, 2659 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2660 .dumb_create = amdgpu_mode_dumb_create, 2661 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2662 .fops = &amdgpu_driver_kms_fops, 2663 .release = &amdgpu_driver_release_kms, 2664 2665 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 2666 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 2667 .gem_prime_import = amdgpu_gem_prime_import, 2668 .gem_prime_mmap = drm_gem_prime_mmap, 2669 2670 .name = DRIVER_NAME, 2671 .desc = DRIVER_DESC, 2672 .date = DRIVER_DATE, 2673 .major = KMS_DRIVER_MAJOR, 2674 .minor = KMS_DRIVER_MINOR, 2675 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2676 }; 2677 2678 static struct pci_error_handlers amdgpu_pci_err_handler = { 2679 .error_detected = amdgpu_pci_error_detected, 2680 .mmio_enabled = amdgpu_pci_mmio_enabled, 2681 .slot_reset = amdgpu_pci_slot_reset, 2682 .resume = amdgpu_pci_resume, 2683 }; 2684 2685 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 2686 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 2687 extern const struct attribute_group amdgpu_vbios_version_attr_group; 2688 2689 static const struct attribute_group *amdgpu_sysfs_groups[] = { 2690 &amdgpu_vram_mgr_attr_group, 2691 &amdgpu_gtt_mgr_attr_group, 2692 &amdgpu_vbios_version_attr_group, 2693 NULL, 2694 }; 2695 2696 2697 static struct pci_driver amdgpu_kms_pci_driver = { 2698 .name = DRIVER_NAME, 2699 .id_table = pciidlist, 2700 .probe = amdgpu_pci_probe, 2701 .remove = amdgpu_pci_remove, 2702 .shutdown = amdgpu_pci_shutdown, 2703 .driver.pm = &amdgpu_pm_ops, 2704 .err_handler = &amdgpu_pci_err_handler, 2705 .dev_groups = amdgpu_sysfs_groups, 2706 }; 2707 2708 static int __init amdgpu_init(void) 2709 { 2710 int r; 2711 2712 if (drm_firmware_drivers_only()) 2713 return -EINVAL; 2714 2715 r = amdgpu_sync_init(); 2716 if (r) 2717 goto error_sync; 2718 2719 r = amdgpu_fence_slab_init(); 2720 if (r) 2721 goto error_fence; 2722 2723 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 2724 amdgpu_register_atpx_handler(); 2725 amdgpu_acpi_detect(); 2726 2727 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 2728 amdgpu_amdkfd_init(); 2729 2730 /* let modprobe override vga console setting */ 2731 return pci_register_driver(&amdgpu_kms_pci_driver); 2732 2733 error_fence: 2734 amdgpu_sync_fini(); 2735 2736 error_sync: 2737 return r; 2738 } 2739 2740 static void __exit amdgpu_exit(void) 2741 { 2742 amdgpu_amdkfd_fini(); 2743 pci_unregister_driver(&amdgpu_kms_pci_driver); 2744 amdgpu_unregister_atpx_handler(); 2745 amdgpu_sync_fini(); 2746 amdgpu_fence_slab_fini(); 2747 mmu_notifier_synchronize(); 2748 } 2749 2750 module_init(amdgpu_init); 2751 module_exit(amdgpu_exit); 2752 2753 MODULE_AUTHOR(DRIVER_AUTHOR); 2754 MODULE_DESCRIPTION(DRIVER_DESC); 2755 MODULE_LICENSE("GPL and additional rights"); 2756