1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_drv.h> 27 #include <drm/drm_gem.h> 28 #include <drm/drm_vblank.h> 29 #include "amdgpu_drv.h" 30 31 #include <drm/drm_pciids.h> 32 #include <linux/console.h> 33 #include <linux/module.h> 34 #include <linux/pci.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/vga_switcheroo.h> 37 #include <drm/drm_probe_helper.h> 38 39 #include "amdgpu.h" 40 #include "amdgpu_irq.h" 41 #include "amdgpu_dma_buf.h" 42 43 #include "amdgpu_amdkfd.h" 44 45 #include "amdgpu_ras.h" 46 47 /* 48 * KMS wrapper. 49 * - 3.0.0 - initial driver 50 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 51 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 52 * at the end of IBs. 53 * - 3.3.0 - Add VM support for UVD on supported hardware. 54 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 55 * - 3.5.0 - Add support for new UVD_NO_OP register. 56 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 57 * - 3.7.0 - Add support for VCE clock list packet 58 * - 3.8.0 - Add support raster config init in the kernel 59 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 60 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 61 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 62 * - 3.12.0 - Add query for double offchip LDS buffers 63 * - 3.13.0 - Add PRT support 64 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 65 * - 3.15.0 - Export more gpu info for gfx9 66 * - 3.16.0 - Add reserved vmid support 67 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 68 * - 3.18.0 - Export gpu always on cu bitmap 69 * - 3.19.0 - Add support for UVD MJPEG decode 70 * - 3.20.0 - Add support for local BOs 71 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 72 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 73 * - 3.23.0 - Add query for VRAM lost counter 74 * - 3.24.0 - Add high priority compute support for gfx9 75 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 76 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 77 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation. 78 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 79 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 80 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 81 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 82 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 83 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 84 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 85 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 86 * - 3.36.0 - Allow reading more status registers on si/cik 87 */ 88 #define KMS_DRIVER_MAJOR 3 89 #define KMS_DRIVER_MINOR 36 90 #define KMS_DRIVER_PATCHLEVEL 0 91 92 int amdgpu_vram_limit = 0; 93 int amdgpu_vis_vram_limit = 0; 94 int amdgpu_gart_size = -1; /* auto */ 95 int amdgpu_gtt_size = -1; /* auto */ 96 int amdgpu_moverate = -1; /* auto */ 97 int amdgpu_benchmarking = 0; 98 int amdgpu_testing = 0; 99 int amdgpu_audio = -1; 100 int amdgpu_disp_priority = 0; 101 int amdgpu_hw_i2c = 0; 102 int amdgpu_pcie_gen2 = -1; 103 int amdgpu_msi = -1; 104 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 105 int amdgpu_dpm = -1; 106 int amdgpu_fw_load_type = -1; 107 int amdgpu_aspm = -1; 108 int amdgpu_runtime_pm = -1; 109 uint amdgpu_ip_block_mask = 0xffffffff; 110 int amdgpu_bapm = -1; 111 int amdgpu_deep_color = 0; 112 int amdgpu_vm_size = -1; 113 int amdgpu_vm_fragment_size = -1; 114 int amdgpu_vm_block_size = -1; 115 int amdgpu_vm_fault_stop = 0; 116 int amdgpu_vm_debug = 0; 117 int amdgpu_vm_update_mode = -1; 118 int amdgpu_exp_hw_support = 0; 119 int amdgpu_dc = -1; 120 int amdgpu_sched_jobs = 32; 121 int amdgpu_sched_hw_submission = 2; 122 uint amdgpu_pcie_gen_cap = 0; 123 uint amdgpu_pcie_lane_cap = 0; 124 uint amdgpu_cg_mask = 0xffffffff; 125 uint amdgpu_pg_mask = 0xffffffff; 126 uint amdgpu_sdma_phase_quantum = 32; 127 char *amdgpu_disable_cu = NULL; 128 char *amdgpu_virtual_display = NULL; 129 /* OverDrive(bit 14) disabled by default*/ 130 uint amdgpu_pp_feature_mask = 0xffffbfff; 131 uint amdgpu_force_long_training = 0; 132 int amdgpu_job_hang_limit = 0; 133 int amdgpu_lbpw = -1; 134 int amdgpu_compute_multipipe = -1; 135 int amdgpu_gpu_recovery = -1; /* auto */ 136 int amdgpu_emu_mode = 0; 137 uint amdgpu_smu_memory_pool_size = 0; 138 /* FBC (bit 0) disabled by default*/ 139 uint amdgpu_dc_feature_mask = 0; 140 int amdgpu_async_gfx_ring = 1; 141 int amdgpu_mcbp = 0; 142 int amdgpu_discovery = -1; 143 int amdgpu_mes = 0; 144 int amdgpu_noretry = 1; 145 int amdgpu_force_asic_type = -1; 146 147 struct amdgpu_mgpu_info mgpu_info = { 148 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 149 }; 150 int amdgpu_ras_enable = -1; 151 uint amdgpu_ras_mask = 0xffffffff; 152 153 /** 154 * DOC: vramlimit (int) 155 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 156 */ 157 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 158 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 159 160 /** 161 * DOC: vis_vramlimit (int) 162 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 163 */ 164 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 165 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 166 167 /** 168 * DOC: gartsize (uint) 169 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic). 170 */ 171 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); 172 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 173 174 /** 175 * DOC: gttsize (int) 176 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM, 177 * otherwise 3/4 RAM size). 178 */ 179 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); 180 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 181 182 /** 183 * DOC: moverate (int) 184 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 185 */ 186 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 187 module_param_named(moverate, amdgpu_moverate, int, 0600); 188 189 /** 190 * DOC: benchmark (int) 191 * Run benchmarks. The default is 0 (Skip benchmarks). 192 */ 193 MODULE_PARM_DESC(benchmark, "Run benchmark"); 194 module_param_named(benchmark, amdgpu_benchmarking, int, 0444); 195 196 /** 197 * DOC: test (int) 198 * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test). 199 */ 200 MODULE_PARM_DESC(test, "Run tests"); 201 module_param_named(test, amdgpu_testing, int, 0444); 202 203 /** 204 * DOC: audio (int) 205 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 206 */ 207 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 208 module_param_named(audio, amdgpu_audio, int, 0444); 209 210 /** 211 * DOC: disp_priority (int) 212 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 213 */ 214 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 215 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 216 217 /** 218 * DOC: hw_i2c (int) 219 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 220 */ 221 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 222 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 223 224 /** 225 * DOC: pcie_gen2 (int) 226 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 227 */ 228 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 229 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 230 231 /** 232 * DOC: msi (int) 233 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 234 */ 235 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 236 module_param_named(msi, amdgpu_msi, int, 0444); 237 238 /** 239 * DOC: lockup_timeout (string) 240 * Set GPU scheduler timeout value in ms. 241 * 242 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 243 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 244 * to the default timeout. 245 * 246 * - With one value specified, the setting will apply to all non-compute jobs. 247 * - With multiple values specified, the first one will be for GFX. 248 * The second one is for Compute. The third and fourth ones are 249 * for SDMA and Video. 250 * 251 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 252 * jobs is 10000. And there is no timeout enforced on compute jobs. 253 */ 254 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and infinity timeout for compute jobs; " 255 "for passthrough or sriov, 10000 for all jobs." 256 " 0: keep default value. negative: infinity timeout), " 257 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 258 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 259 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 260 261 /** 262 * DOC: dpm (int) 263 * Override for dynamic power management setting 264 * (0 = disable, 1 = enable, 2 = enable sw smu driver for vega20) 265 * The default is -1 (auto). 266 */ 267 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 268 module_param_named(dpm, amdgpu_dpm, int, 0444); 269 270 /** 271 * DOC: fw_load_type (int) 272 * Set different firmware loading type for debugging (0 = direct, 1 = SMU, 2 = PSP). The default is -1 (auto). 273 */ 274 MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)"); 275 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 276 277 /** 278 * DOC: aspm (int) 279 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 280 */ 281 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 282 module_param_named(aspm, amdgpu_aspm, int, 0444); 283 284 /** 285 * DOC: runpm (int) 286 * Override for runtime power management control for dGPUs in PX/HG laptops. The amdgpu driver can dynamically power down 287 * the dGPU on PX/HG laptops when it is idle. The default is -1 (auto enable). Setting the value to 0 disables this functionality. 288 */ 289 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 290 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 291 292 /** 293 * DOC: ip_block_mask (uint) 294 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 295 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 296 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 297 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 298 */ 299 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 300 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 301 302 /** 303 * DOC: bapm (int) 304 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 305 * The default -1 (auto, enabled) 306 */ 307 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 308 module_param_named(bapm, amdgpu_bapm, int, 0444); 309 310 /** 311 * DOC: deep_color (int) 312 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 313 */ 314 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 315 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 316 317 /** 318 * DOC: vm_size (int) 319 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 320 */ 321 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 322 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 323 324 /** 325 * DOC: vm_fragment_size (int) 326 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 327 */ 328 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 329 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 330 331 /** 332 * DOC: vm_block_size (int) 333 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 334 */ 335 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 336 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 337 338 /** 339 * DOC: vm_fault_stop (int) 340 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 341 */ 342 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 343 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 344 345 /** 346 * DOC: vm_debug (int) 347 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 348 */ 349 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 350 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 351 352 /** 353 * DOC: vm_update_mode (int) 354 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 355 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 356 */ 357 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 358 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 359 360 /** 361 * DOC: exp_hw_support (int) 362 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 363 */ 364 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 365 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 366 367 /** 368 * DOC: dc (int) 369 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 370 */ 371 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 372 module_param_named(dc, amdgpu_dc, int, 0444); 373 374 /** 375 * DOC: sched_jobs (int) 376 * Override the max number of jobs supported in the sw queue. The default is 32. 377 */ 378 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 379 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 380 381 /** 382 * DOC: sched_hw_submission (int) 383 * Override the max number of HW submissions. The default is 2. 384 */ 385 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 386 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 387 388 /** 389 * DOC: ppfeaturemask (uint) 390 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 391 * The default is the current set of stable power features. 392 */ 393 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 394 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, uint, 0444); 395 396 /** 397 * DOC: forcelongtraining (uint) 398 * Force long memory training in resume. 399 * The default is zero, indicates short training in resume. 400 */ 401 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 402 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 403 404 /** 405 * DOC: pcie_gen_cap (uint) 406 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 407 * The default is 0 (automatic for each asic). 408 */ 409 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 410 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 411 412 /** 413 * DOC: pcie_lane_cap (uint) 414 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 415 * The default is 0 (automatic for each asic). 416 */ 417 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 418 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 419 420 /** 421 * DOC: cg_mask (uint) 422 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 423 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 424 */ 425 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 426 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); 427 428 /** 429 * DOC: pg_mask (uint) 430 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 431 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 432 */ 433 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 434 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 435 436 /** 437 * DOC: sdma_phase_quantum (uint) 438 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 439 */ 440 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 441 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 442 443 /** 444 * DOC: disable_cu (charp) 445 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 446 */ 447 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 448 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 449 450 /** 451 * DOC: virtual_display (charp) 452 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 453 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 454 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 455 * device at 26:00.0. The default is NULL. 456 */ 457 MODULE_PARM_DESC(virtual_display, 458 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 459 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 460 461 /** 462 * DOC: job_hang_limit (int) 463 * Set how much time allow a job hang and not drop it. The default is 0. 464 */ 465 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 466 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 467 468 /** 469 * DOC: lbpw (int) 470 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 471 */ 472 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 473 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 474 475 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 476 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 477 478 /** 479 * DOC: gpu_recovery (int) 480 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 481 */ 482 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 483 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 484 485 /** 486 * DOC: emu_mode (int) 487 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 488 */ 489 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 490 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 491 492 /** 493 * DOC: ras_enable (int) 494 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 495 */ 496 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 497 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 498 499 /** 500 * DOC: ras_mask (uint) 501 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 502 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 503 */ 504 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 505 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 506 507 /** 508 * DOC: si_support (int) 509 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 510 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 511 * otherwise using amdgpu driver. 512 */ 513 #ifdef CONFIG_DRM_AMDGPU_SI 514 515 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 516 int amdgpu_si_support = 0; 517 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 518 #else 519 int amdgpu_si_support = 1; 520 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 521 #endif 522 523 module_param_named(si_support, amdgpu_si_support, int, 0444); 524 #endif 525 526 /** 527 * DOC: cik_support (int) 528 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 529 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 530 * otherwise using amdgpu driver. 531 */ 532 #ifdef CONFIG_DRM_AMDGPU_CIK 533 534 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 535 int amdgpu_cik_support = 0; 536 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 537 #else 538 int amdgpu_cik_support = 1; 539 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 540 #endif 541 542 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 543 #endif 544 545 /** 546 * DOC: smu_memory_pool_size (uint) 547 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 548 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 549 */ 550 MODULE_PARM_DESC(smu_memory_pool_size, 551 "reserve gtt for smu debug usage, 0 = disable," 552 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 553 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 554 555 /** 556 * DOC: async_gfx_ring (int) 557 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 558 */ 559 MODULE_PARM_DESC(async_gfx_ring, 560 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 561 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 562 563 /** 564 * DOC: mcbp (int) 565 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled) 566 */ 567 MODULE_PARM_DESC(mcbp, 568 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); 569 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 570 571 /** 572 * DOC: discovery (int) 573 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 574 * (-1 = auto (default), 0 = disabled, 1 = enabled) 575 */ 576 MODULE_PARM_DESC(discovery, 577 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 578 module_param_named(discovery, amdgpu_discovery, int, 0444); 579 580 /** 581 * DOC: mes (int) 582 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 583 * (0 = disabled (default), 1 = enabled) 584 */ 585 MODULE_PARM_DESC(mes, 586 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 587 module_param_named(mes, amdgpu_mes, int, 0444); 588 589 MODULE_PARM_DESC(noretry, 590 "Disable retry faults (0 = retry enabled, 1 = retry disabled (default))"); 591 module_param_named(noretry, amdgpu_noretry, int, 0644); 592 593 /** 594 * DOC: force_asic_type (int) 595 * A non negative value used to specify the asic type for all supported GPUs. 596 */ 597 MODULE_PARM_DESC(force_asic_type, 598 "A non negative value used to specify the asic type for all supported GPUs"); 599 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 600 601 602 603 #ifdef CONFIG_HSA_AMD 604 /** 605 * DOC: sched_policy (int) 606 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 607 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 608 * assigns queues to HQDs. 609 */ 610 int sched_policy = KFD_SCHED_POLICY_HWS; 611 module_param(sched_policy, int, 0444); 612 MODULE_PARM_DESC(sched_policy, 613 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 614 615 /** 616 * DOC: hws_max_conc_proc (int) 617 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 618 * number of VMIDs assigned to the HWS, which is also the default. 619 */ 620 int hws_max_conc_proc = 8; 621 module_param(hws_max_conc_proc, int, 0444); 622 MODULE_PARM_DESC(hws_max_conc_proc, 623 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 624 625 /** 626 * DOC: cwsr_enable (int) 627 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 628 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 629 * disables it. 630 */ 631 int cwsr_enable = 1; 632 module_param(cwsr_enable, int, 0444); 633 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 634 635 /** 636 * DOC: max_num_of_queues_per_device (int) 637 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 638 * is 4096. 639 */ 640 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 641 module_param(max_num_of_queues_per_device, int, 0444); 642 MODULE_PARM_DESC(max_num_of_queues_per_device, 643 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 644 645 /** 646 * DOC: send_sigterm (int) 647 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 648 * but just print errors on dmesg. Setting 1 enables sending sigterm. 649 */ 650 int send_sigterm; 651 module_param(send_sigterm, int, 0444); 652 MODULE_PARM_DESC(send_sigterm, 653 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 654 655 /** 656 * DOC: debug_largebar (int) 657 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 658 * system. This limits the VRAM size reported to ROCm applications to the visible 659 * size, usually 256MB. 660 * Default value is 0, diabled. 661 */ 662 int debug_largebar; 663 module_param(debug_largebar, int, 0444); 664 MODULE_PARM_DESC(debug_largebar, 665 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 666 667 /** 668 * DOC: ignore_crat (int) 669 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 670 * table to get information about AMD APUs. This option can serve as a workaround on 671 * systems with a broken CRAT table. 672 */ 673 int ignore_crat; 674 module_param(ignore_crat, int, 0444); 675 MODULE_PARM_DESC(ignore_crat, 676 "Ignore CRAT table during KFD initialization (0 = use CRAT (default), 1 = ignore CRAT)"); 677 678 /** 679 * DOC: halt_if_hws_hang (int) 680 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 681 * Setting 1 enables halt on hang. 682 */ 683 int halt_if_hws_hang; 684 module_param(halt_if_hws_hang, int, 0644); 685 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 686 687 /** 688 * DOC: hws_gws_support(bool) 689 * Whether HWS support gws barriers. Default value: false (not supported) 690 * This will be replaced with a MEC firmware version check once firmware 691 * is ready 692 */ 693 bool hws_gws_support; 694 module_param(hws_gws_support, bool, 0444); 695 MODULE_PARM_DESC(hws_gws_support, "MEC FW support gws barriers (false = not supported (Default), true = supported)"); 696 697 /** 698 * DOC: queue_preemption_timeout_ms (int) 699 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 700 */ 701 int queue_preemption_timeout_ms = 9000; 702 module_param(queue_preemption_timeout_ms, int, 0644); 703 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 704 #endif 705 706 /** 707 * DOC: dcfeaturemask (uint) 708 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 709 * The default is the current set of stable display features. 710 */ 711 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 712 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 713 714 /** 715 * DOC: abmlevel (uint) 716 * Override the default ABM (Adaptive Backlight Management) level used for DC 717 * enabled hardware. Requires DMCU to be supported and loaded. 718 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 719 * default. Values 1-4 control the maximum allowable brightness reduction via 720 * the ABM algorithm, with 1 being the least reduction and 4 being the most 721 * reduction. 722 * 723 * Defaults to 0, or disabled. Userspace can still override this level later 724 * after boot. 725 */ 726 uint amdgpu_dm_abm_level = 0; 727 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 728 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 729 730 static const struct pci_device_id pciidlist[] = { 731 #ifdef CONFIG_DRM_AMDGPU_SI 732 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 733 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 734 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 735 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 736 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 737 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 738 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 739 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 740 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 741 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 742 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 743 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 744 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 745 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 746 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 747 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 748 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 749 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 750 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 751 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 752 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 753 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 754 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 755 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 756 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 757 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 758 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 759 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 760 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 761 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 762 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 763 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 764 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 765 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 766 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 767 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 768 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 769 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 770 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 771 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 772 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 773 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 774 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 775 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 776 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 777 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 778 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 779 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 780 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 781 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 782 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 783 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 784 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 785 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 786 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 787 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 788 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 789 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 790 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 791 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 792 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 793 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 794 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 795 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 796 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 797 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 798 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 799 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 800 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 801 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 802 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 803 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 804 #endif 805 #ifdef CONFIG_DRM_AMDGPU_CIK 806 /* Kaveri */ 807 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 808 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 809 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 810 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 811 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 812 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 813 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 814 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 815 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 816 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 817 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 818 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 819 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 820 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 821 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 822 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 823 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 824 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 825 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 826 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 827 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 828 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 829 /* Bonaire */ 830 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 831 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 832 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 833 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 834 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 835 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 836 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 837 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 838 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 839 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 840 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 841 /* Hawaii */ 842 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 843 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 844 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 845 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 846 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 847 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 848 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 849 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 850 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 851 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 852 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 853 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 854 /* Kabini */ 855 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 856 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 857 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 858 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 859 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 860 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 861 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 862 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 863 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 864 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 865 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 866 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 867 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 868 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 869 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 870 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 871 /* mullins */ 872 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 873 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 874 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 875 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 876 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 877 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 878 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 879 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 880 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 881 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 882 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 883 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 884 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 885 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 886 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 887 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 888 #endif 889 /* topaz */ 890 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 891 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 892 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 893 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 894 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 895 /* tonga */ 896 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 897 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 898 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 899 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 900 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 901 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 902 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 903 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 904 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 905 /* fiji */ 906 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 907 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 908 /* carrizo */ 909 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 910 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 911 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 912 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 913 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 914 /* stoney */ 915 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 916 /* Polaris11 */ 917 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 918 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 919 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 920 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 921 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 922 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 923 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 924 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 925 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 926 /* Polaris10 */ 927 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 928 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 929 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 930 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 931 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 932 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 933 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 934 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 935 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 936 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 937 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 938 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 939 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 940 /* Polaris12 */ 941 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 942 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 943 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 944 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 945 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 946 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 947 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 948 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 949 /* VEGAM */ 950 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 951 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 952 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 953 /* Vega 10 */ 954 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 955 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 956 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 957 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 958 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 959 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 960 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 961 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 962 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 963 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 964 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 965 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 966 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 967 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 968 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 969 /* Vega 12 */ 970 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 971 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 972 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 973 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 974 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 975 /* Vega 20 */ 976 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 977 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 978 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 979 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 980 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 981 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 982 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 983 /* Raven */ 984 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 985 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 986 /* Arcturus */ 987 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT}, 988 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT}, 989 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT}, 990 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT}, 991 /* Navi10 */ 992 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 993 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 994 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 995 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 996 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 997 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 998 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 999 /* Navi14 */ 1000 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14|AMD_EXP_HW_SUPPORT}, 1001 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14|AMD_EXP_HW_SUPPORT}, 1002 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14|AMD_EXP_HW_SUPPORT}, 1003 1004 /* Renoir */ 1005 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU|AMD_EXP_HW_SUPPORT}, 1006 1007 /* Navi12 */ 1008 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12|AMD_EXP_HW_SUPPORT}, 1009 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12|AMD_EXP_HW_SUPPORT}, 1010 1011 {0, 0, 0} 1012 }; 1013 1014 MODULE_DEVICE_TABLE(pci, pciidlist); 1015 1016 static struct drm_driver kms_driver; 1017 1018 static int amdgpu_pci_probe(struct pci_dev *pdev, 1019 const struct pci_device_id *ent) 1020 { 1021 struct drm_device *dev; 1022 unsigned long flags = ent->driver_data; 1023 int ret, retry = 0; 1024 bool supports_atomic = false; 1025 1026 if (!amdgpu_virtual_display && 1027 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 1028 supports_atomic = true; 1029 1030 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 1031 DRM_INFO("This hardware requires experimental hardware support.\n" 1032 "See modparam exp_hw_support\n"); 1033 return -ENODEV; 1034 } 1035 1036 #ifdef CONFIG_DRM_AMDGPU_SI 1037 if (!amdgpu_si_support) { 1038 switch (flags & AMD_ASIC_MASK) { 1039 case CHIP_TAHITI: 1040 case CHIP_PITCAIRN: 1041 case CHIP_VERDE: 1042 case CHIP_OLAND: 1043 case CHIP_HAINAN: 1044 dev_info(&pdev->dev, 1045 "SI support provided by radeon.\n"); 1046 dev_info(&pdev->dev, 1047 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 1048 ); 1049 return -ENODEV; 1050 } 1051 } 1052 #endif 1053 #ifdef CONFIG_DRM_AMDGPU_CIK 1054 if (!amdgpu_cik_support) { 1055 switch (flags & AMD_ASIC_MASK) { 1056 case CHIP_KAVERI: 1057 case CHIP_BONAIRE: 1058 case CHIP_HAWAII: 1059 case CHIP_KABINI: 1060 case CHIP_MULLINS: 1061 dev_info(&pdev->dev, 1062 "CIK support provided by radeon.\n"); 1063 dev_info(&pdev->dev, 1064 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 1065 ); 1066 return -ENODEV; 1067 } 1068 } 1069 #endif 1070 1071 /* Get rid of things like offb */ 1072 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, 0, "amdgpudrmfb"); 1073 if (ret) 1074 return ret; 1075 1076 dev = drm_dev_alloc(&kms_driver, &pdev->dev); 1077 if (IS_ERR(dev)) 1078 return PTR_ERR(dev); 1079 1080 if (!supports_atomic) 1081 dev->driver_features &= ~DRIVER_ATOMIC; 1082 1083 ret = pci_enable_device(pdev); 1084 if (ret) 1085 goto err_free; 1086 1087 dev->pdev = pdev; 1088 1089 pci_set_drvdata(pdev, dev); 1090 1091 retry_init: 1092 ret = drm_dev_register(dev, ent->driver_data); 1093 if (ret == -EAGAIN && ++retry <= 3) { 1094 DRM_INFO("retry init %d\n", retry); 1095 /* Don't request EX mode too frequently which is attacking */ 1096 msleep(5000); 1097 goto retry_init; 1098 } else if (ret) 1099 goto err_pci; 1100 1101 return 0; 1102 1103 err_pci: 1104 pci_disable_device(pdev); 1105 err_free: 1106 drm_dev_put(dev); 1107 return ret; 1108 } 1109 1110 static void 1111 amdgpu_pci_remove(struct pci_dev *pdev) 1112 { 1113 struct drm_device *dev = pci_get_drvdata(pdev); 1114 1115 #ifdef MODULE 1116 if (THIS_MODULE->state != MODULE_STATE_GOING) 1117 #endif 1118 DRM_ERROR("Hotplug removal is not supported\n"); 1119 drm_dev_unplug(dev); 1120 drm_dev_put(dev); 1121 pci_disable_device(pdev); 1122 pci_set_drvdata(pdev, NULL); 1123 } 1124 1125 static void 1126 amdgpu_pci_shutdown(struct pci_dev *pdev) 1127 { 1128 struct drm_device *dev = pci_get_drvdata(pdev); 1129 struct amdgpu_device *adev = dev->dev_private; 1130 1131 if (amdgpu_ras_intr_triggered()) 1132 return; 1133 1134 /* if we are running in a VM, make sure the device 1135 * torn down properly on reboot/shutdown. 1136 * unfortunately we can't detect certain 1137 * hypervisors so just do this all the time. 1138 */ 1139 adev->mp1_state = PP_MP1_STATE_UNLOAD; 1140 amdgpu_device_ip_suspend(adev); 1141 adev->mp1_state = PP_MP1_STATE_NONE; 1142 } 1143 1144 static int amdgpu_pmops_suspend(struct device *dev) 1145 { 1146 struct drm_device *drm_dev = dev_get_drvdata(dev); 1147 1148 return amdgpu_device_suspend(drm_dev, true, true); 1149 } 1150 1151 static int amdgpu_pmops_resume(struct device *dev) 1152 { 1153 struct drm_device *drm_dev = dev_get_drvdata(dev); 1154 1155 /* GPU comes up enabled by the bios on resume */ 1156 if (amdgpu_device_is_px(drm_dev)) { 1157 pm_runtime_disable(dev); 1158 pm_runtime_set_active(dev); 1159 pm_runtime_enable(dev); 1160 } 1161 1162 return amdgpu_device_resume(drm_dev, true, true); 1163 } 1164 1165 static int amdgpu_pmops_freeze(struct device *dev) 1166 { 1167 struct drm_device *drm_dev = dev_get_drvdata(dev); 1168 struct amdgpu_device *adev = drm_dev->dev_private; 1169 int r; 1170 1171 r = amdgpu_device_suspend(drm_dev, false, true); 1172 if (r) 1173 return r; 1174 return amdgpu_asic_reset(adev); 1175 } 1176 1177 static int amdgpu_pmops_thaw(struct device *dev) 1178 { 1179 struct drm_device *drm_dev = dev_get_drvdata(dev); 1180 1181 return amdgpu_device_resume(drm_dev, false, true); 1182 } 1183 1184 static int amdgpu_pmops_poweroff(struct device *dev) 1185 { 1186 struct drm_device *drm_dev = dev_get_drvdata(dev); 1187 1188 return amdgpu_device_suspend(drm_dev, true, true); 1189 } 1190 1191 static int amdgpu_pmops_restore(struct device *dev) 1192 { 1193 struct drm_device *drm_dev = dev_get_drvdata(dev); 1194 1195 return amdgpu_device_resume(drm_dev, false, true); 1196 } 1197 1198 static int amdgpu_pmops_runtime_suspend(struct device *dev) 1199 { 1200 struct pci_dev *pdev = to_pci_dev(dev); 1201 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1202 int ret; 1203 1204 if (!amdgpu_device_is_px(drm_dev)) { 1205 pm_runtime_forbid(dev); 1206 return -EBUSY; 1207 } 1208 1209 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1210 drm_kms_helper_poll_disable(drm_dev); 1211 1212 ret = amdgpu_device_suspend(drm_dev, false, false); 1213 pci_save_state(pdev); 1214 pci_disable_device(pdev); 1215 pci_ignore_hotplug(pdev); 1216 if (amdgpu_is_atpx_hybrid()) 1217 pci_set_power_state(pdev, PCI_D3cold); 1218 else if (!amdgpu_has_atpx_dgpu_power_cntl()) 1219 pci_set_power_state(pdev, PCI_D3hot); 1220 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 1221 1222 return 0; 1223 } 1224 1225 static int amdgpu_pmops_runtime_resume(struct device *dev) 1226 { 1227 struct pci_dev *pdev = to_pci_dev(dev); 1228 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1229 int ret; 1230 1231 if (!amdgpu_device_is_px(drm_dev)) 1232 return -EINVAL; 1233 1234 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1235 1236 if (amdgpu_is_atpx_hybrid() || 1237 !amdgpu_has_atpx_dgpu_power_cntl()) 1238 pci_set_power_state(pdev, PCI_D0); 1239 pci_restore_state(pdev); 1240 ret = pci_enable_device(pdev); 1241 if (ret) 1242 return ret; 1243 pci_set_master(pdev); 1244 1245 ret = amdgpu_device_resume(drm_dev, false, false); 1246 drm_kms_helper_poll_enable(drm_dev); 1247 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 1248 return 0; 1249 } 1250 1251 static int amdgpu_pmops_runtime_idle(struct device *dev) 1252 { 1253 struct drm_device *drm_dev = dev_get_drvdata(dev); 1254 struct drm_crtc *crtc; 1255 1256 if (!amdgpu_device_is_px(drm_dev)) { 1257 pm_runtime_forbid(dev); 1258 return -EBUSY; 1259 } 1260 1261 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 1262 if (crtc->enabled) { 1263 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 1264 return -EBUSY; 1265 } 1266 } 1267 1268 pm_runtime_mark_last_busy(dev); 1269 pm_runtime_autosuspend(dev); 1270 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 1271 return 1; 1272 } 1273 1274 long amdgpu_drm_ioctl(struct file *filp, 1275 unsigned int cmd, unsigned long arg) 1276 { 1277 struct drm_file *file_priv = filp->private_data; 1278 struct drm_device *dev; 1279 long ret; 1280 dev = file_priv->minor->dev; 1281 ret = pm_runtime_get_sync(dev->dev); 1282 if (ret < 0) 1283 return ret; 1284 1285 ret = drm_ioctl(filp, cmd, arg); 1286 1287 pm_runtime_mark_last_busy(dev->dev); 1288 pm_runtime_put_autosuspend(dev->dev); 1289 return ret; 1290 } 1291 1292 static const struct dev_pm_ops amdgpu_pm_ops = { 1293 .suspend = amdgpu_pmops_suspend, 1294 .resume = amdgpu_pmops_resume, 1295 .freeze = amdgpu_pmops_freeze, 1296 .thaw = amdgpu_pmops_thaw, 1297 .poweroff = amdgpu_pmops_poweroff, 1298 .restore = amdgpu_pmops_restore, 1299 .runtime_suspend = amdgpu_pmops_runtime_suspend, 1300 .runtime_resume = amdgpu_pmops_runtime_resume, 1301 .runtime_idle = amdgpu_pmops_runtime_idle, 1302 }; 1303 1304 static int amdgpu_flush(struct file *f, fl_owner_t id) 1305 { 1306 struct drm_file *file_priv = f->private_data; 1307 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1308 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 1309 1310 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 1311 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 1312 1313 return timeout >= 0 ? 0 : timeout; 1314 } 1315 1316 static const struct file_operations amdgpu_driver_kms_fops = { 1317 .owner = THIS_MODULE, 1318 .open = drm_open, 1319 .flush = amdgpu_flush, 1320 .release = drm_release, 1321 .unlocked_ioctl = amdgpu_drm_ioctl, 1322 .mmap = amdgpu_mmap, 1323 .poll = drm_poll, 1324 .read = drm_read, 1325 #ifdef CONFIG_COMPAT 1326 .compat_ioctl = amdgpu_kms_compat_ioctl, 1327 #endif 1328 }; 1329 1330 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 1331 { 1332 struct drm_file *file; 1333 1334 if (!filp) 1335 return -EINVAL; 1336 1337 if (filp->f_op != &amdgpu_driver_kms_fops) { 1338 return -EINVAL; 1339 } 1340 1341 file = filp->private_data; 1342 *fpriv = file->driver_priv; 1343 return 0; 1344 } 1345 1346 static bool 1347 amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe, 1348 bool in_vblank_irq, int *vpos, int *hpos, 1349 ktime_t *stime, ktime_t *etime, 1350 const struct drm_display_mode *mode) 1351 { 1352 return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos, 1353 stime, etime, mode); 1354 } 1355 1356 static struct drm_driver kms_driver = { 1357 .driver_features = 1358 DRIVER_USE_AGP | DRIVER_ATOMIC | 1359 DRIVER_GEM | 1360 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ, 1361 .load = amdgpu_driver_load_kms, 1362 .open = amdgpu_driver_open_kms, 1363 .postclose = amdgpu_driver_postclose_kms, 1364 .lastclose = amdgpu_driver_lastclose_kms, 1365 .unload = amdgpu_driver_unload_kms, 1366 .get_vblank_counter = amdgpu_get_vblank_counter_kms, 1367 .enable_vblank = amdgpu_enable_vblank_kms, 1368 .disable_vblank = amdgpu_disable_vblank_kms, 1369 .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos, 1370 .get_scanout_position = amdgpu_get_crtc_scanout_position, 1371 .irq_handler = amdgpu_irq_handler, 1372 .ioctls = amdgpu_ioctls_kms, 1373 .gem_free_object_unlocked = amdgpu_gem_object_free, 1374 .gem_open_object = amdgpu_gem_object_open, 1375 .gem_close_object = amdgpu_gem_object_close, 1376 .dumb_create = amdgpu_mode_dumb_create, 1377 .dumb_map_offset = amdgpu_mode_dumb_mmap, 1378 .fops = &amdgpu_driver_kms_fops, 1379 1380 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 1381 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 1382 .gem_prime_export = amdgpu_gem_prime_export, 1383 .gem_prime_import = amdgpu_gem_prime_import, 1384 .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table, 1385 .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table, 1386 .gem_prime_vmap = amdgpu_gem_prime_vmap, 1387 .gem_prime_vunmap = amdgpu_gem_prime_vunmap, 1388 .gem_prime_mmap = amdgpu_gem_prime_mmap, 1389 1390 .name = DRIVER_NAME, 1391 .desc = DRIVER_DESC, 1392 .date = DRIVER_DATE, 1393 .major = KMS_DRIVER_MAJOR, 1394 .minor = KMS_DRIVER_MINOR, 1395 .patchlevel = KMS_DRIVER_PATCHLEVEL, 1396 }; 1397 1398 static struct pci_driver amdgpu_kms_pci_driver = { 1399 .name = DRIVER_NAME, 1400 .id_table = pciidlist, 1401 .probe = amdgpu_pci_probe, 1402 .remove = amdgpu_pci_remove, 1403 .shutdown = amdgpu_pci_shutdown, 1404 .driver.pm = &amdgpu_pm_ops, 1405 }; 1406 1407 1408 1409 static int __init amdgpu_init(void) 1410 { 1411 int r; 1412 1413 if (vgacon_text_force()) { 1414 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); 1415 return -EINVAL; 1416 } 1417 1418 r = amdgpu_sync_init(); 1419 if (r) 1420 goto error_sync; 1421 1422 r = amdgpu_fence_slab_init(); 1423 if (r) 1424 goto error_fence; 1425 1426 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 1427 kms_driver.num_ioctls = amdgpu_max_kms_ioctl; 1428 amdgpu_register_atpx_handler(); 1429 1430 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 1431 amdgpu_amdkfd_init(); 1432 1433 /* let modprobe override vga console setting */ 1434 return pci_register_driver(&amdgpu_kms_pci_driver); 1435 1436 error_fence: 1437 amdgpu_sync_fini(); 1438 1439 error_sync: 1440 return r; 1441 } 1442 1443 static void __exit amdgpu_exit(void) 1444 { 1445 amdgpu_amdkfd_fini(); 1446 pci_unregister_driver(&amdgpu_kms_pci_driver); 1447 amdgpu_unregister_atpx_handler(); 1448 amdgpu_sync_fini(); 1449 amdgpu_fence_slab_fini(); 1450 } 1451 1452 module_init(amdgpu_init); 1453 module_exit(amdgpu_exit); 1454 1455 MODULE_AUTHOR(DRIVER_AUTHOR); 1456 MODULE_DESCRIPTION(DRIVER_DESC); 1457 MODULE_LICENSE("GPL and additional rights"); 1458