1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_aperture.h> 27 #include <drm/drm_drv.h> 28 #include <drm/drm_gem.h> 29 #include <drm/drm_vblank.h> 30 #include <drm/drm_managed.h> 31 #include "amdgpu_drv.h" 32 33 #include <drm/drm_pciids.h> 34 #include <linux/module.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/vga_switcheroo.h> 37 #include <drm/drm_probe_helper.h> 38 #include <linux/mmu_notifier.h> 39 #include <linux/suspend.h> 40 #include <linux/cc_platform.h> 41 42 #include "amdgpu.h" 43 #include "amdgpu_irq.h" 44 #include "amdgpu_dma_buf.h" 45 #include "amdgpu_sched.h" 46 #include "amdgpu_fdinfo.h" 47 #include "amdgpu_amdkfd.h" 48 49 #include "amdgpu_ras.h" 50 #include "amdgpu_xgmi.h" 51 #include "amdgpu_reset.h" 52 53 /* 54 * KMS wrapper. 55 * - 3.0.0 - initial driver 56 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 57 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 58 * at the end of IBs. 59 * - 3.3.0 - Add VM support for UVD on supported hardware. 60 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 61 * - 3.5.0 - Add support for new UVD_NO_OP register. 62 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 63 * - 3.7.0 - Add support for VCE clock list packet 64 * - 3.8.0 - Add support raster config init in the kernel 65 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 66 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 67 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 68 * - 3.12.0 - Add query for double offchip LDS buffers 69 * - 3.13.0 - Add PRT support 70 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 71 * - 3.15.0 - Export more gpu info for gfx9 72 * - 3.16.0 - Add reserved vmid support 73 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 74 * - 3.18.0 - Export gpu always on cu bitmap 75 * - 3.19.0 - Add support for UVD MJPEG decode 76 * - 3.20.0 - Add support for local BOs 77 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 78 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 79 * - 3.23.0 - Add query for VRAM lost counter 80 * - 3.24.0 - Add high priority compute support for gfx9 81 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 82 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 83 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation. 84 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 85 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 86 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 87 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 88 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 89 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 90 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 91 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 92 * - 3.36.0 - Allow reading more status registers on si/cik 93 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 94 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 95 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 96 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 97 * - 3.41.0 - Add video codec query 98 * - 3.42.0 - Add 16bpc fixed point display support 99 * - 3.43.0 - Add device hot plug/unplug support 100 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 101 */ 102 #define KMS_DRIVER_MAJOR 3 103 #define KMS_DRIVER_MINOR 44 104 #define KMS_DRIVER_PATCHLEVEL 0 105 106 int amdgpu_vram_limit; 107 int amdgpu_vis_vram_limit; 108 int amdgpu_gart_size = -1; /* auto */ 109 int amdgpu_gtt_size = -1; /* auto */ 110 int amdgpu_moverate = -1; /* auto */ 111 int amdgpu_benchmarking; 112 int amdgpu_testing; 113 int amdgpu_audio = -1; 114 int amdgpu_disp_priority; 115 int amdgpu_hw_i2c; 116 int amdgpu_pcie_gen2 = -1; 117 int amdgpu_msi = -1; 118 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 119 int amdgpu_dpm = -1; 120 int amdgpu_fw_load_type = -1; 121 int amdgpu_aspm = -1; 122 int amdgpu_runtime_pm = -1; 123 uint amdgpu_ip_block_mask = 0xffffffff; 124 int amdgpu_bapm = -1; 125 int amdgpu_deep_color; 126 int amdgpu_vm_size = -1; 127 int amdgpu_vm_fragment_size = -1; 128 int amdgpu_vm_block_size = -1; 129 int amdgpu_vm_fault_stop; 130 int amdgpu_vm_debug; 131 int amdgpu_vm_update_mode = -1; 132 int amdgpu_exp_hw_support; 133 int amdgpu_dc = -1; 134 int amdgpu_sched_jobs = 32; 135 int amdgpu_sched_hw_submission = 2; 136 uint amdgpu_pcie_gen_cap; 137 uint amdgpu_pcie_lane_cap; 138 uint amdgpu_cg_mask = 0xffffffff; 139 uint amdgpu_pg_mask = 0xffffffff; 140 uint amdgpu_sdma_phase_quantum = 32; 141 char *amdgpu_disable_cu = NULL; 142 char *amdgpu_virtual_display = NULL; 143 144 /* 145 * OverDrive(bit 14) disabled by default 146 * GFX DCS(bit 19) disabled by default 147 */ 148 uint amdgpu_pp_feature_mask = 0xfff7bfff; 149 uint amdgpu_force_long_training; 150 int amdgpu_job_hang_limit; 151 int amdgpu_lbpw = -1; 152 int amdgpu_compute_multipipe = -1; 153 int amdgpu_gpu_recovery = -1; /* auto */ 154 int amdgpu_emu_mode; 155 uint amdgpu_smu_memory_pool_size; 156 int amdgpu_smu_pptable_id = -1; 157 /* 158 * FBC (bit 0) disabled by default 159 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 160 * - With this, for multiple monitors in sync(e.g. with the same model), 161 * mclk switching will be allowed. And the mclk will be not foced to the 162 * highest. That helps saving some idle power. 163 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 164 * PSR (bit 3) disabled by default 165 * EDP NO POWER SEQUENCING (bit 4) disabled by default 166 */ 167 uint amdgpu_dc_feature_mask = 2; 168 uint amdgpu_dc_debug_mask; 169 int amdgpu_async_gfx_ring = 1; 170 int amdgpu_mcbp; 171 int amdgpu_discovery = -1; 172 int amdgpu_mes; 173 int amdgpu_noretry = -1; 174 int amdgpu_force_asic_type = -1; 175 int amdgpu_tmz = -1; /* auto */ 176 uint amdgpu_freesync_vid_mode; 177 int amdgpu_reset_method = -1; /* auto */ 178 int amdgpu_num_kcq = -1; 179 int amdgpu_smartshift_bias; 180 181 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 182 183 struct amdgpu_mgpu_info mgpu_info = { 184 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 185 .delayed_reset_work = __DELAYED_WORK_INITIALIZER( 186 mgpu_info.delayed_reset_work, 187 amdgpu_drv_delayed_reset_work_handler, 0), 188 }; 189 int amdgpu_ras_enable = -1; 190 uint amdgpu_ras_mask = 0xffffffff; 191 int amdgpu_bad_page_threshold = -1; 192 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 193 .timeout_fatal_disable = false, 194 .period = 0x0, /* default to 0x0 (timeout disable) */ 195 }; 196 197 /** 198 * DOC: vramlimit (int) 199 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 200 */ 201 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 202 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 203 204 /** 205 * DOC: vis_vramlimit (int) 206 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 207 */ 208 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 209 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 210 211 /** 212 * DOC: gartsize (uint) 213 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic). 214 */ 215 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); 216 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 217 218 /** 219 * DOC: gttsize (int) 220 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM, 221 * otherwise 3/4 RAM size). 222 */ 223 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); 224 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 225 226 /** 227 * DOC: moverate (int) 228 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 229 */ 230 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 231 module_param_named(moverate, amdgpu_moverate, int, 0600); 232 233 /** 234 * DOC: benchmark (int) 235 * Run benchmarks. The default is 0 (Skip benchmarks). 236 */ 237 MODULE_PARM_DESC(benchmark, "Run benchmark"); 238 module_param_named(benchmark, amdgpu_benchmarking, int, 0444); 239 240 /** 241 * DOC: test (int) 242 * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test). 243 */ 244 MODULE_PARM_DESC(test, "Run tests"); 245 module_param_named(test, amdgpu_testing, int, 0444); 246 247 /** 248 * DOC: audio (int) 249 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 250 */ 251 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 252 module_param_named(audio, amdgpu_audio, int, 0444); 253 254 /** 255 * DOC: disp_priority (int) 256 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 257 */ 258 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 259 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 260 261 /** 262 * DOC: hw_i2c (int) 263 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 264 */ 265 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 266 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 267 268 /** 269 * DOC: pcie_gen2 (int) 270 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 271 */ 272 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 273 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 274 275 /** 276 * DOC: msi (int) 277 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 278 */ 279 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 280 module_param_named(msi, amdgpu_msi, int, 0444); 281 282 /** 283 * DOC: lockup_timeout (string) 284 * Set GPU scheduler timeout value in ms. 285 * 286 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 287 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 288 * to the default timeout. 289 * 290 * - With one value specified, the setting will apply to all non-compute jobs. 291 * - With multiple values specified, the first one will be for GFX. 292 * The second one is for Compute. The third and fourth ones are 293 * for SDMA and Video. 294 * 295 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 296 * jobs is 10000. The timeout for compute is 60000. 297 */ 298 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 299 "for passthrough or sriov, 10000 for all jobs." 300 " 0: keep default value. negative: infinity timeout), " 301 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 302 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 303 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 304 305 /** 306 * DOC: dpm (int) 307 * Override for dynamic power management setting 308 * (0 = disable, 1 = enable) 309 * The default is -1 (auto). 310 */ 311 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 312 module_param_named(dpm, amdgpu_dpm, int, 0444); 313 314 /** 315 * DOC: fw_load_type (int) 316 * Set different firmware loading type for debugging (0 = direct, 1 = SMU, 2 = PSP). The default is -1 (auto). 317 */ 318 MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)"); 319 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 320 321 /** 322 * DOC: aspm (int) 323 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 324 */ 325 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 326 module_param_named(aspm, amdgpu_aspm, int, 0444); 327 328 /** 329 * DOC: runpm (int) 330 * Override for runtime power management control for dGPUs in PX/HG laptops. The amdgpu driver can dynamically power down 331 * the dGPU on PX/HG laptops when it is idle. The default is -1 (auto enable). Setting the value to 0 disables this functionality. 332 */ 333 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = PX only default)"); 334 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 335 336 /** 337 * DOC: ip_block_mask (uint) 338 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 339 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 340 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 341 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 342 */ 343 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 344 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 345 346 /** 347 * DOC: bapm (int) 348 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 349 * The default -1 (auto, enabled) 350 */ 351 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 352 module_param_named(bapm, amdgpu_bapm, int, 0444); 353 354 /** 355 * DOC: deep_color (int) 356 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 357 */ 358 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 359 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 360 361 /** 362 * DOC: vm_size (int) 363 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 364 */ 365 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 366 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 367 368 /** 369 * DOC: vm_fragment_size (int) 370 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 371 */ 372 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 373 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 374 375 /** 376 * DOC: vm_block_size (int) 377 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 378 */ 379 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 380 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 381 382 /** 383 * DOC: vm_fault_stop (int) 384 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 385 */ 386 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 387 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 388 389 /** 390 * DOC: vm_debug (int) 391 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 392 */ 393 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 394 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 395 396 /** 397 * DOC: vm_update_mode (int) 398 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 399 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 400 */ 401 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 402 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 403 404 /** 405 * DOC: exp_hw_support (int) 406 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 407 */ 408 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 409 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 410 411 /** 412 * DOC: dc (int) 413 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 414 */ 415 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 416 module_param_named(dc, amdgpu_dc, int, 0444); 417 418 /** 419 * DOC: sched_jobs (int) 420 * Override the max number of jobs supported in the sw queue. The default is 32. 421 */ 422 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 423 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 424 425 /** 426 * DOC: sched_hw_submission (int) 427 * Override the max number of HW submissions. The default is 2. 428 */ 429 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 430 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 431 432 /** 433 * DOC: ppfeaturemask (hexint) 434 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 435 * The default is the current set of stable power features. 436 */ 437 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 438 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 439 440 /** 441 * DOC: forcelongtraining (uint) 442 * Force long memory training in resume. 443 * The default is zero, indicates short training in resume. 444 */ 445 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 446 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 447 448 /** 449 * DOC: pcie_gen_cap (uint) 450 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 451 * The default is 0 (automatic for each asic). 452 */ 453 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 454 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 455 456 /** 457 * DOC: pcie_lane_cap (uint) 458 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 459 * The default is 0 (automatic for each asic). 460 */ 461 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 462 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 463 464 /** 465 * DOC: cg_mask (uint) 466 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 467 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 468 */ 469 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 470 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); 471 472 /** 473 * DOC: pg_mask (uint) 474 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 475 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 476 */ 477 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 478 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 479 480 /** 481 * DOC: sdma_phase_quantum (uint) 482 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 483 */ 484 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 485 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 486 487 /** 488 * DOC: disable_cu (charp) 489 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 490 */ 491 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 492 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 493 494 /** 495 * DOC: virtual_display (charp) 496 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 497 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 498 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 499 * device at 26:00.0. The default is NULL. 500 */ 501 MODULE_PARM_DESC(virtual_display, 502 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 503 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 504 505 /** 506 * DOC: job_hang_limit (int) 507 * Set how much time allow a job hang and not drop it. The default is 0. 508 */ 509 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 510 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 511 512 /** 513 * DOC: lbpw (int) 514 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 515 */ 516 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 517 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 518 519 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 520 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 521 522 /** 523 * DOC: gpu_recovery (int) 524 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 525 */ 526 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (2 = advanced tdr mode, 1 = enable, 0 = disable, -1 = auto)"); 527 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 528 529 /** 530 * DOC: emu_mode (int) 531 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 532 */ 533 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 534 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 535 536 /** 537 * DOC: ras_enable (int) 538 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 539 */ 540 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 541 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 542 543 /** 544 * DOC: ras_mask (uint) 545 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 546 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 547 */ 548 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 549 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 550 551 /** 552 * DOC: timeout_fatal_disable (bool) 553 * Disable Watchdog timeout fatal error event 554 */ 555 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 556 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 557 558 /** 559 * DOC: timeout_period (uint) 560 * Modify the watchdog timeout max_cycles as (1 << period) 561 */ 562 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 563 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 564 565 /** 566 * DOC: si_support (int) 567 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 568 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 569 * otherwise using amdgpu driver. 570 */ 571 #ifdef CONFIG_DRM_AMDGPU_SI 572 573 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 574 int amdgpu_si_support = 0; 575 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 576 #else 577 int amdgpu_si_support = 1; 578 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 579 #endif 580 581 module_param_named(si_support, amdgpu_si_support, int, 0444); 582 #endif 583 584 /** 585 * DOC: cik_support (int) 586 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 587 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 588 * otherwise using amdgpu driver. 589 */ 590 #ifdef CONFIG_DRM_AMDGPU_CIK 591 592 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 593 int amdgpu_cik_support = 0; 594 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 595 #else 596 int amdgpu_cik_support = 1; 597 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 598 #endif 599 600 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 601 #endif 602 603 /** 604 * DOC: smu_memory_pool_size (uint) 605 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 606 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 607 */ 608 MODULE_PARM_DESC(smu_memory_pool_size, 609 "reserve gtt for smu debug usage, 0 = disable," 610 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 611 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 612 613 /** 614 * DOC: async_gfx_ring (int) 615 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 616 */ 617 MODULE_PARM_DESC(async_gfx_ring, 618 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 619 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 620 621 /** 622 * DOC: mcbp (int) 623 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled) 624 */ 625 MODULE_PARM_DESC(mcbp, 626 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); 627 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 628 629 /** 630 * DOC: discovery (int) 631 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 632 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 633 */ 634 MODULE_PARM_DESC(discovery, 635 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 636 module_param_named(discovery, amdgpu_discovery, int, 0444); 637 638 /** 639 * DOC: mes (int) 640 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 641 * (0 = disabled (default), 1 = enabled) 642 */ 643 MODULE_PARM_DESC(mes, 644 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 645 module_param_named(mes, amdgpu_mes, int, 0444); 646 647 /** 648 * DOC: noretry (int) 649 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 650 * do not support per-process XNACK this also disables retry page faults. 651 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 652 */ 653 MODULE_PARM_DESC(noretry, 654 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 655 module_param_named(noretry, amdgpu_noretry, int, 0644); 656 657 /** 658 * DOC: force_asic_type (int) 659 * A non negative value used to specify the asic type for all supported GPUs. 660 */ 661 MODULE_PARM_DESC(force_asic_type, 662 "A non negative value used to specify the asic type for all supported GPUs"); 663 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 664 665 666 667 #ifdef CONFIG_HSA_AMD 668 /** 669 * DOC: sched_policy (int) 670 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 671 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 672 * assigns queues to HQDs. 673 */ 674 int sched_policy = KFD_SCHED_POLICY_HWS; 675 module_param(sched_policy, int, 0444); 676 MODULE_PARM_DESC(sched_policy, 677 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 678 679 /** 680 * DOC: hws_max_conc_proc (int) 681 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 682 * number of VMIDs assigned to the HWS, which is also the default. 683 */ 684 int hws_max_conc_proc = 8; 685 module_param(hws_max_conc_proc, int, 0444); 686 MODULE_PARM_DESC(hws_max_conc_proc, 687 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 688 689 /** 690 * DOC: cwsr_enable (int) 691 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 692 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 693 * disables it. 694 */ 695 int cwsr_enable = 1; 696 module_param(cwsr_enable, int, 0444); 697 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 698 699 /** 700 * DOC: max_num_of_queues_per_device (int) 701 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 702 * is 4096. 703 */ 704 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 705 module_param(max_num_of_queues_per_device, int, 0444); 706 MODULE_PARM_DESC(max_num_of_queues_per_device, 707 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 708 709 /** 710 * DOC: send_sigterm (int) 711 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 712 * but just print errors on dmesg. Setting 1 enables sending sigterm. 713 */ 714 int send_sigterm; 715 module_param(send_sigterm, int, 0444); 716 MODULE_PARM_DESC(send_sigterm, 717 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 718 719 /** 720 * DOC: debug_largebar (int) 721 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 722 * system. This limits the VRAM size reported to ROCm applications to the visible 723 * size, usually 256MB. 724 * Default value is 0, diabled. 725 */ 726 int debug_largebar; 727 module_param(debug_largebar, int, 0444); 728 MODULE_PARM_DESC(debug_largebar, 729 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 730 731 /** 732 * DOC: ignore_crat (int) 733 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 734 * table to get information about AMD APUs. This option can serve as a workaround on 735 * systems with a broken CRAT table. 736 * 737 * Default is auto (according to asic type, iommu_v2, and crat table, to decide 738 * whehter use CRAT) 739 */ 740 int ignore_crat; 741 module_param(ignore_crat, int, 0444); 742 MODULE_PARM_DESC(ignore_crat, 743 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)"); 744 745 /** 746 * DOC: halt_if_hws_hang (int) 747 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 748 * Setting 1 enables halt on hang. 749 */ 750 int halt_if_hws_hang; 751 module_param(halt_if_hws_hang, int, 0644); 752 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 753 754 /** 755 * DOC: hws_gws_support(bool) 756 * Assume that HWS supports GWS barriers regardless of what firmware version 757 * check says. Default value: false (rely on MEC2 firmware version check). 758 */ 759 bool hws_gws_support; 760 module_param(hws_gws_support, bool, 0444); 761 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 762 763 /** 764 * DOC: queue_preemption_timeout_ms (int) 765 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 766 */ 767 int queue_preemption_timeout_ms = 9000; 768 module_param(queue_preemption_timeout_ms, int, 0644); 769 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 770 771 /** 772 * DOC: debug_evictions(bool) 773 * Enable extra debug messages to help determine the cause of evictions 774 */ 775 bool debug_evictions; 776 module_param(debug_evictions, bool, 0644); 777 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 778 779 /** 780 * DOC: no_system_mem_limit(bool) 781 * Disable system memory limit, to support multiple process shared memory 782 */ 783 bool no_system_mem_limit; 784 module_param(no_system_mem_limit, bool, 0644); 785 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 786 787 /** 788 * DOC: no_queue_eviction_on_vm_fault (int) 789 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 790 */ 791 int amdgpu_no_queue_eviction_on_vm_fault = 0; 792 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 793 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 794 #endif 795 796 /** 797 * DOC: dcfeaturemask (uint) 798 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 799 * The default is the current set of stable display features. 800 */ 801 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 802 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 803 804 /** 805 * DOC: dcdebugmask (uint) 806 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 807 */ 808 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 809 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 810 811 /** 812 * DOC: abmlevel (uint) 813 * Override the default ABM (Adaptive Backlight Management) level used for DC 814 * enabled hardware. Requires DMCU to be supported and loaded. 815 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 816 * default. Values 1-4 control the maximum allowable brightness reduction via 817 * the ABM algorithm, with 1 being the least reduction and 4 being the most 818 * reduction. 819 * 820 * Defaults to 0, or disabled. Userspace can still override this level later 821 * after boot. 822 */ 823 uint amdgpu_dm_abm_level; 824 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 825 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 826 827 int amdgpu_backlight = -1; 828 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 829 module_param_named(backlight, amdgpu_backlight, bint, 0444); 830 831 /** 832 * DOC: tmz (int) 833 * Trusted Memory Zone (TMZ) is a method to protect data being written 834 * to or read from memory. 835 * 836 * The default value: 0 (off). TODO: change to auto till it is completed. 837 */ 838 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 839 module_param_named(tmz, amdgpu_tmz, int, 0444); 840 841 /** 842 * DOC: freesync_video (uint) 843 * Enable the optimization to adjust front porch timing to achieve seamless 844 * mode change experience when setting a freesync supported mode for which full 845 * modeset is not needed. 846 * 847 * The Display Core will add a set of modes derived from the base FreeSync 848 * video mode into the corresponding connector's mode list based on commonly 849 * used refresh rates and VRR range of the connected display, when users enable 850 * this feature. From the userspace perspective, they can see a seamless mode 851 * change experience when the change between different refresh rates under the 852 * same resolution. Additionally, userspace applications such as Video playback 853 * can read this modeset list and change the refresh rate based on the video 854 * frame rate. Finally, the userspace can also derive an appropriate mode for a 855 * particular refresh rate based on the FreeSync Mode and add it to the 856 * connector's mode list. 857 * 858 * Note: This is an experimental feature. 859 * 860 * The default value: 0 (off). 861 */ 862 MODULE_PARM_DESC( 863 freesync_video, 864 "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)"); 865 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); 866 867 /** 868 * DOC: reset_method (int) 869 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco, 5 = pci) 870 */ 871 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco, 5 = pci)"); 872 module_param_named(reset_method, amdgpu_reset_method, int, 0444); 873 874 /** 875 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 876 * threshold value of faulty pages detected by RAS ECC, which may 877 * result in the GPU entering bad status when the number of total 878 * faulty pages by ECC exceeds the threshold value. 879 */ 880 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement, -2 = ignore bad page threshold)"); 881 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 882 883 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 884 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 885 886 /** 887 * DOC: smu_pptable_id (int) 888 * Used to override pptable id. id = 0 use VBIOS pptable. 889 * id > 0 use the soft pptable with specicfied id. 890 */ 891 MODULE_PARM_DESC(smu_pptable_id, 892 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 893 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 894 895 /* These devices are not supported by amdgpu. 896 * They are supported by the mach64, r128, radeon drivers 897 */ 898 static const u16 amdgpu_unsupported_pciidlist[] = { 899 /* mach64 */ 900 0x4354, 901 0x4358, 902 0x4554, 903 0x4742, 904 0x4744, 905 0x4749, 906 0x474C, 907 0x474D, 908 0x474E, 909 0x474F, 910 0x4750, 911 0x4751, 912 0x4752, 913 0x4753, 914 0x4754, 915 0x4755, 916 0x4756, 917 0x4757, 918 0x4758, 919 0x4759, 920 0x475A, 921 0x4C42, 922 0x4C44, 923 0x4C47, 924 0x4C49, 925 0x4C4D, 926 0x4C4E, 927 0x4C50, 928 0x4C51, 929 0x4C52, 930 0x4C53, 931 0x5654, 932 0x5655, 933 0x5656, 934 /* r128 */ 935 0x4c45, 936 0x4c46, 937 0x4d46, 938 0x4d4c, 939 0x5041, 940 0x5042, 941 0x5043, 942 0x5044, 943 0x5045, 944 0x5046, 945 0x5047, 946 0x5048, 947 0x5049, 948 0x504A, 949 0x504B, 950 0x504C, 951 0x504D, 952 0x504E, 953 0x504F, 954 0x5050, 955 0x5051, 956 0x5052, 957 0x5053, 958 0x5054, 959 0x5055, 960 0x5056, 961 0x5057, 962 0x5058, 963 0x5245, 964 0x5246, 965 0x5247, 966 0x524b, 967 0x524c, 968 0x534d, 969 0x5446, 970 0x544C, 971 0x5452, 972 /* radeon */ 973 0x3150, 974 0x3151, 975 0x3152, 976 0x3154, 977 0x3155, 978 0x3E50, 979 0x3E54, 980 0x4136, 981 0x4137, 982 0x4144, 983 0x4145, 984 0x4146, 985 0x4147, 986 0x4148, 987 0x4149, 988 0x414A, 989 0x414B, 990 0x4150, 991 0x4151, 992 0x4152, 993 0x4153, 994 0x4154, 995 0x4155, 996 0x4156, 997 0x4237, 998 0x4242, 999 0x4336, 1000 0x4337, 1001 0x4437, 1002 0x4966, 1003 0x4967, 1004 0x4A48, 1005 0x4A49, 1006 0x4A4A, 1007 0x4A4B, 1008 0x4A4C, 1009 0x4A4D, 1010 0x4A4E, 1011 0x4A4F, 1012 0x4A50, 1013 0x4A54, 1014 0x4B48, 1015 0x4B49, 1016 0x4B4A, 1017 0x4B4B, 1018 0x4B4C, 1019 0x4C57, 1020 0x4C58, 1021 0x4C59, 1022 0x4C5A, 1023 0x4C64, 1024 0x4C66, 1025 0x4C67, 1026 0x4E44, 1027 0x4E45, 1028 0x4E46, 1029 0x4E47, 1030 0x4E48, 1031 0x4E49, 1032 0x4E4A, 1033 0x4E4B, 1034 0x4E50, 1035 0x4E51, 1036 0x4E52, 1037 0x4E53, 1038 0x4E54, 1039 0x4E56, 1040 0x5144, 1041 0x5145, 1042 0x5146, 1043 0x5147, 1044 0x5148, 1045 0x514C, 1046 0x514D, 1047 0x5157, 1048 0x5158, 1049 0x5159, 1050 0x515A, 1051 0x515E, 1052 0x5460, 1053 0x5462, 1054 0x5464, 1055 0x5548, 1056 0x5549, 1057 0x554A, 1058 0x554B, 1059 0x554C, 1060 0x554D, 1061 0x554E, 1062 0x554F, 1063 0x5550, 1064 0x5551, 1065 0x5552, 1066 0x5554, 1067 0x564A, 1068 0x564B, 1069 0x564F, 1070 0x5652, 1071 0x5653, 1072 0x5657, 1073 0x5834, 1074 0x5835, 1075 0x5954, 1076 0x5955, 1077 0x5974, 1078 0x5975, 1079 0x5960, 1080 0x5961, 1081 0x5962, 1082 0x5964, 1083 0x5965, 1084 0x5969, 1085 0x5a41, 1086 0x5a42, 1087 0x5a61, 1088 0x5a62, 1089 0x5b60, 1090 0x5b62, 1091 0x5b63, 1092 0x5b64, 1093 0x5b65, 1094 0x5c61, 1095 0x5c63, 1096 0x5d48, 1097 0x5d49, 1098 0x5d4a, 1099 0x5d4c, 1100 0x5d4d, 1101 0x5d4e, 1102 0x5d4f, 1103 0x5d50, 1104 0x5d52, 1105 0x5d57, 1106 0x5e48, 1107 0x5e4a, 1108 0x5e4b, 1109 0x5e4c, 1110 0x5e4d, 1111 0x5e4f, 1112 0x6700, 1113 0x6701, 1114 0x6702, 1115 0x6703, 1116 0x6704, 1117 0x6705, 1118 0x6706, 1119 0x6707, 1120 0x6708, 1121 0x6709, 1122 0x6718, 1123 0x6719, 1124 0x671c, 1125 0x671d, 1126 0x671f, 1127 0x6720, 1128 0x6721, 1129 0x6722, 1130 0x6723, 1131 0x6724, 1132 0x6725, 1133 0x6726, 1134 0x6727, 1135 0x6728, 1136 0x6729, 1137 0x6738, 1138 0x6739, 1139 0x673e, 1140 0x6740, 1141 0x6741, 1142 0x6742, 1143 0x6743, 1144 0x6744, 1145 0x6745, 1146 0x6746, 1147 0x6747, 1148 0x6748, 1149 0x6749, 1150 0x674A, 1151 0x6750, 1152 0x6751, 1153 0x6758, 1154 0x6759, 1155 0x675B, 1156 0x675D, 1157 0x675F, 1158 0x6760, 1159 0x6761, 1160 0x6762, 1161 0x6763, 1162 0x6764, 1163 0x6765, 1164 0x6766, 1165 0x6767, 1166 0x6768, 1167 0x6770, 1168 0x6771, 1169 0x6772, 1170 0x6778, 1171 0x6779, 1172 0x677B, 1173 0x6840, 1174 0x6841, 1175 0x6842, 1176 0x6843, 1177 0x6849, 1178 0x684C, 1179 0x6850, 1180 0x6858, 1181 0x6859, 1182 0x6880, 1183 0x6888, 1184 0x6889, 1185 0x688A, 1186 0x688C, 1187 0x688D, 1188 0x6898, 1189 0x6899, 1190 0x689b, 1191 0x689c, 1192 0x689d, 1193 0x689e, 1194 0x68a0, 1195 0x68a1, 1196 0x68a8, 1197 0x68a9, 1198 0x68b0, 1199 0x68b8, 1200 0x68b9, 1201 0x68ba, 1202 0x68be, 1203 0x68bf, 1204 0x68c0, 1205 0x68c1, 1206 0x68c7, 1207 0x68c8, 1208 0x68c9, 1209 0x68d8, 1210 0x68d9, 1211 0x68da, 1212 0x68de, 1213 0x68e0, 1214 0x68e1, 1215 0x68e4, 1216 0x68e5, 1217 0x68e8, 1218 0x68e9, 1219 0x68f1, 1220 0x68f2, 1221 0x68f8, 1222 0x68f9, 1223 0x68fa, 1224 0x68fe, 1225 0x7100, 1226 0x7101, 1227 0x7102, 1228 0x7103, 1229 0x7104, 1230 0x7105, 1231 0x7106, 1232 0x7108, 1233 0x7109, 1234 0x710A, 1235 0x710B, 1236 0x710C, 1237 0x710E, 1238 0x710F, 1239 0x7140, 1240 0x7141, 1241 0x7142, 1242 0x7143, 1243 0x7144, 1244 0x7145, 1245 0x7146, 1246 0x7147, 1247 0x7149, 1248 0x714A, 1249 0x714B, 1250 0x714C, 1251 0x714D, 1252 0x714E, 1253 0x714F, 1254 0x7151, 1255 0x7152, 1256 0x7153, 1257 0x715E, 1258 0x715F, 1259 0x7180, 1260 0x7181, 1261 0x7183, 1262 0x7186, 1263 0x7187, 1264 0x7188, 1265 0x718A, 1266 0x718B, 1267 0x718C, 1268 0x718D, 1269 0x718F, 1270 0x7193, 1271 0x7196, 1272 0x719B, 1273 0x719F, 1274 0x71C0, 1275 0x71C1, 1276 0x71C2, 1277 0x71C3, 1278 0x71C4, 1279 0x71C5, 1280 0x71C6, 1281 0x71C7, 1282 0x71CD, 1283 0x71CE, 1284 0x71D2, 1285 0x71D4, 1286 0x71D5, 1287 0x71D6, 1288 0x71DA, 1289 0x71DE, 1290 0x7200, 1291 0x7210, 1292 0x7211, 1293 0x7240, 1294 0x7243, 1295 0x7244, 1296 0x7245, 1297 0x7246, 1298 0x7247, 1299 0x7248, 1300 0x7249, 1301 0x724A, 1302 0x724B, 1303 0x724C, 1304 0x724D, 1305 0x724E, 1306 0x724F, 1307 0x7280, 1308 0x7281, 1309 0x7283, 1310 0x7284, 1311 0x7287, 1312 0x7288, 1313 0x7289, 1314 0x728B, 1315 0x728C, 1316 0x7290, 1317 0x7291, 1318 0x7293, 1319 0x7297, 1320 0x7834, 1321 0x7835, 1322 0x791e, 1323 0x791f, 1324 0x793f, 1325 0x7941, 1326 0x7942, 1327 0x796c, 1328 0x796d, 1329 0x796e, 1330 0x796f, 1331 0x9400, 1332 0x9401, 1333 0x9402, 1334 0x9403, 1335 0x9405, 1336 0x940A, 1337 0x940B, 1338 0x940F, 1339 0x94A0, 1340 0x94A1, 1341 0x94A3, 1342 0x94B1, 1343 0x94B3, 1344 0x94B4, 1345 0x94B5, 1346 0x94B9, 1347 0x9440, 1348 0x9441, 1349 0x9442, 1350 0x9443, 1351 0x9444, 1352 0x9446, 1353 0x944A, 1354 0x944B, 1355 0x944C, 1356 0x944E, 1357 0x9450, 1358 0x9452, 1359 0x9456, 1360 0x945A, 1361 0x945B, 1362 0x945E, 1363 0x9460, 1364 0x9462, 1365 0x946A, 1366 0x946B, 1367 0x947A, 1368 0x947B, 1369 0x9480, 1370 0x9487, 1371 0x9488, 1372 0x9489, 1373 0x948A, 1374 0x948F, 1375 0x9490, 1376 0x9491, 1377 0x9495, 1378 0x9498, 1379 0x949C, 1380 0x949E, 1381 0x949F, 1382 0x94C0, 1383 0x94C1, 1384 0x94C3, 1385 0x94C4, 1386 0x94C5, 1387 0x94C6, 1388 0x94C7, 1389 0x94C8, 1390 0x94C9, 1391 0x94CB, 1392 0x94CC, 1393 0x94CD, 1394 0x9500, 1395 0x9501, 1396 0x9504, 1397 0x9505, 1398 0x9506, 1399 0x9507, 1400 0x9508, 1401 0x9509, 1402 0x950F, 1403 0x9511, 1404 0x9515, 1405 0x9517, 1406 0x9519, 1407 0x9540, 1408 0x9541, 1409 0x9542, 1410 0x954E, 1411 0x954F, 1412 0x9552, 1413 0x9553, 1414 0x9555, 1415 0x9557, 1416 0x955f, 1417 0x9580, 1418 0x9581, 1419 0x9583, 1420 0x9586, 1421 0x9587, 1422 0x9588, 1423 0x9589, 1424 0x958A, 1425 0x958B, 1426 0x958C, 1427 0x958D, 1428 0x958E, 1429 0x958F, 1430 0x9590, 1431 0x9591, 1432 0x9593, 1433 0x9595, 1434 0x9596, 1435 0x9597, 1436 0x9598, 1437 0x9599, 1438 0x959B, 1439 0x95C0, 1440 0x95C2, 1441 0x95C4, 1442 0x95C5, 1443 0x95C6, 1444 0x95C7, 1445 0x95C9, 1446 0x95CC, 1447 0x95CD, 1448 0x95CE, 1449 0x95CF, 1450 0x9610, 1451 0x9611, 1452 0x9612, 1453 0x9613, 1454 0x9614, 1455 0x9615, 1456 0x9616, 1457 0x9640, 1458 0x9641, 1459 0x9642, 1460 0x9643, 1461 0x9644, 1462 0x9645, 1463 0x9647, 1464 0x9648, 1465 0x9649, 1466 0x964a, 1467 0x964b, 1468 0x964c, 1469 0x964e, 1470 0x964f, 1471 0x9710, 1472 0x9711, 1473 0x9712, 1474 0x9713, 1475 0x9714, 1476 0x9715, 1477 0x9802, 1478 0x9803, 1479 0x9804, 1480 0x9805, 1481 0x9806, 1482 0x9807, 1483 0x9808, 1484 0x9809, 1485 0x980A, 1486 0x9900, 1487 0x9901, 1488 0x9903, 1489 0x9904, 1490 0x9905, 1491 0x9906, 1492 0x9907, 1493 0x9908, 1494 0x9909, 1495 0x990A, 1496 0x990B, 1497 0x990C, 1498 0x990D, 1499 0x990E, 1500 0x990F, 1501 0x9910, 1502 0x9913, 1503 0x9917, 1504 0x9918, 1505 0x9919, 1506 0x9990, 1507 0x9991, 1508 0x9992, 1509 0x9993, 1510 0x9994, 1511 0x9995, 1512 0x9996, 1513 0x9997, 1514 0x9998, 1515 0x9999, 1516 0x999A, 1517 0x999B, 1518 0x999C, 1519 0x999D, 1520 0x99A0, 1521 0x99A2, 1522 0x99A4, 1523 }; 1524 1525 static const struct pci_device_id pciidlist[] = { 1526 #ifdef CONFIG_DRM_AMDGPU_SI 1527 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1528 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1529 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1530 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1531 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1532 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1533 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1534 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1535 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1536 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1537 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1538 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1539 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1540 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1541 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1542 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1543 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1544 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1545 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1546 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1547 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1548 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1549 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1550 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1551 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1552 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1553 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1554 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1555 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1556 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1557 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1558 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1559 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1560 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1561 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1562 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1563 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1564 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1565 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1566 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1567 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1568 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1569 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1570 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1571 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1572 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1573 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1574 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1575 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1576 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1577 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1578 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1579 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1580 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1581 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1582 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1583 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1584 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1585 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1586 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1587 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1588 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1589 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1590 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1591 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1592 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1593 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1594 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1595 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1596 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1597 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1598 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1599 #endif 1600 #ifdef CONFIG_DRM_AMDGPU_CIK 1601 /* Kaveri */ 1602 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1603 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1604 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1605 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1606 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1607 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1608 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1609 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1610 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1611 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1612 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1613 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1614 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1615 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1616 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1617 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1618 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1619 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1620 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1621 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1622 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1623 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1624 /* Bonaire */ 1625 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1626 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1627 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1628 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1629 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1630 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1631 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1632 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1633 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1634 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1635 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1636 /* Hawaii */ 1637 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1638 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1639 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1640 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1641 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1642 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1643 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1644 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1645 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1646 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1647 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1648 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1649 /* Kabini */ 1650 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1651 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1652 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1653 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1654 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1655 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1656 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1657 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1658 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1659 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1660 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1661 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1662 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1663 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1664 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1665 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1666 /* mullins */ 1667 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1668 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1669 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1670 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1671 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1672 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1673 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1674 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1675 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1676 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1677 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1678 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1679 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1680 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1681 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1682 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1683 #endif 1684 /* topaz */ 1685 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1686 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1687 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1688 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1689 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1690 /* tonga */ 1691 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1692 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1693 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1694 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1695 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1696 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1697 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1698 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1699 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1700 /* fiji */ 1701 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1702 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1703 /* carrizo */ 1704 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1705 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1706 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1707 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1708 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1709 /* stoney */ 1710 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1711 /* Polaris11 */ 1712 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1713 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1714 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1715 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1716 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1717 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1718 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1719 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1720 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1721 /* Polaris10 */ 1722 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1723 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1724 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1725 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1726 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1727 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1728 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1729 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1730 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1731 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1732 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1733 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1734 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1735 /* Polaris12 */ 1736 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1737 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1738 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1739 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1740 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1741 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1742 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1743 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1744 /* VEGAM */ 1745 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1746 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1747 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1748 /* Vega 10 */ 1749 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1750 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1751 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1752 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1753 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1754 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1755 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1756 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1757 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1758 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1759 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1760 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1761 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1762 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1763 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1764 /* Vega 12 */ 1765 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1766 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1767 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1768 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1769 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1770 /* Vega 20 */ 1771 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1772 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1773 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1774 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1775 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1776 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1777 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1778 /* Raven */ 1779 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1780 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1781 /* Arcturus */ 1782 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1783 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1784 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1785 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1786 /* Navi10 */ 1787 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1788 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1789 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1790 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1791 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1792 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1793 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1794 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1795 /* Navi14 */ 1796 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1797 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1798 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1799 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1800 1801 /* Renoir */ 1802 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1803 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1804 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1805 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1806 1807 /* Navi12 */ 1808 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1809 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1810 1811 /* Sienna_Cichlid */ 1812 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1813 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1814 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1815 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1816 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1817 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1818 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1819 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1820 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1821 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1822 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1823 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1824 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1825 1826 /* Van Gogh */ 1827 {0x1002, 0x163F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VANGOGH|AMD_IS_APU}, 1828 1829 /* Yellow Carp */ 1830 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1831 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1832 1833 /* Navy_Flounder */ 1834 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1835 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1836 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1837 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1838 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1839 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1840 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1841 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1842 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1843 1844 /* DIMGREY_CAVEFISH */ 1845 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1846 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1847 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1848 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1849 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1850 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1851 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1852 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1853 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1854 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1855 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1856 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1857 1858 /* Aldebaran */ 1859 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT}, 1860 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT}, 1861 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT}, 1862 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT}, 1863 1864 /* CYAN_SKILLFISH */ 1865 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 1866 1867 /* BEIGE_GOBY */ 1868 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1869 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1870 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1871 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1872 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1873 1874 { PCI_DEVICE(0x1002, PCI_ANY_ID), 1875 .class = PCI_CLASS_DISPLAY_VGA << 8, 1876 .class_mask = 0xffffff, 1877 .driver_data = CHIP_IP_DISCOVERY }, 1878 1879 { PCI_DEVICE(0x1002, PCI_ANY_ID), 1880 .class = PCI_CLASS_DISPLAY_OTHER << 8, 1881 .class_mask = 0xffffff, 1882 .driver_data = CHIP_IP_DISCOVERY }, 1883 1884 {0, 0, 0} 1885 }; 1886 1887 MODULE_DEVICE_TABLE(pci, pciidlist); 1888 1889 static const struct drm_driver amdgpu_kms_driver; 1890 1891 static int amdgpu_pci_probe(struct pci_dev *pdev, 1892 const struct pci_device_id *ent) 1893 { 1894 struct drm_device *ddev; 1895 struct amdgpu_device *adev; 1896 unsigned long flags = ent->driver_data; 1897 int ret, retry = 0, i; 1898 bool supports_atomic = false; 1899 1900 /* skip devices which are owned by radeon */ 1901 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 1902 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 1903 return -ENODEV; 1904 } 1905 1906 if (flags == 0) { 1907 DRM_INFO("Unsupported asic. Remove me when IP discovery init is in place.\n"); 1908 return -ENODEV; 1909 } 1910 1911 if (amdgpu_virtual_display || 1912 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 1913 supports_atomic = true; 1914 1915 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 1916 DRM_INFO("This hardware requires experimental hardware support.\n" 1917 "See modparam exp_hw_support\n"); 1918 return -ENODEV; 1919 } 1920 1921 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 1922 * however, SME requires an indirect IOMMU mapping because the encryption 1923 * bit is beyond the DMA mask of the chip. 1924 */ 1925 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 1926 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 1927 dev_info(&pdev->dev, 1928 "SME is not compatible with RAVEN\n"); 1929 return -ENOTSUPP; 1930 } 1931 1932 #ifdef CONFIG_DRM_AMDGPU_SI 1933 if (!amdgpu_si_support) { 1934 switch (flags & AMD_ASIC_MASK) { 1935 case CHIP_TAHITI: 1936 case CHIP_PITCAIRN: 1937 case CHIP_VERDE: 1938 case CHIP_OLAND: 1939 case CHIP_HAINAN: 1940 dev_info(&pdev->dev, 1941 "SI support provided by radeon.\n"); 1942 dev_info(&pdev->dev, 1943 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 1944 ); 1945 return -ENODEV; 1946 } 1947 } 1948 #endif 1949 #ifdef CONFIG_DRM_AMDGPU_CIK 1950 if (!amdgpu_cik_support) { 1951 switch (flags & AMD_ASIC_MASK) { 1952 case CHIP_KAVERI: 1953 case CHIP_BONAIRE: 1954 case CHIP_HAWAII: 1955 case CHIP_KABINI: 1956 case CHIP_MULLINS: 1957 dev_info(&pdev->dev, 1958 "CIK support provided by radeon.\n"); 1959 dev_info(&pdev->dev, 1960 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 1961 ); 1962 return -ENODEV; 1963 } 1964 } 1965 #endif 1966 1967 /* Get rid of things like offb */ 1968 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &amdgpu_kms_driver); 1969 if (ret) 1970 return ret; 1971 1972 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 1973 if (IS_ERR(adev)) 1974 return PTR_ERR(adev); 1975 1976 adev->dev = &pdev->dev; 1977 adev->pdev = pdev; 1978 ddev = adev_to_drm(adev); 1979 1980 if (!supports_atomic) 1981 ddev->driver_features &= ~DRIVER_ATOMIC; 1982 1983 ret = pci_enable_device(pdev); 1984 if (ret) 1985 return ret; 1986 1987 pci_set_drvdata(pdev, ddev); 1988 1989 ret = amdgpu_driver_load_kms(adev, ent->driver_data); 1990 if (ret) 1991 goto err_pci; 1992 1993 retry_init: 1994 ret = drm_dev_register(ddev, ent->driver_data); 1995 if (ret == -EAGAIN && ++retry <= 3) { 1996 DRM_INFO("retry init %d\n", retry); 1997 /* Don't request EX mode too frequently which is attacking */ 1998 msleep(5000); 1999 goto retry_init; 2000 } else if (ret) { 2001 goto err_pci; 2002 } 2003 2004 /* 2005 * 1. don't init fbdev on hw without DCE 2006 * 2. don't init fbdev if there are no connectors 2007 */ 2008 if (adev->mode_info.mode_config_initialized && 2009 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2010 /* select 8 bpp console on low vram cards */ 2011 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2012 drm_fbdev_generic_setup(adev_to_drm(adev), 8); 2013 else 2014 drm_fbdev_generic_setup(adev_to_drm(adev), 32); 2015 } 2016 2017 ret = amdgpu_debugfs_init(adev); 2018 if (ret) 2019 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2020 2021 return 0; 2022 2023 err_pci: 2024 pci_disable_device(pdev); 2025 return ret; 2026 } 2027 2028 static void 2029 amdgpu_pci_remove(struct pci_dev *pdev) 2030 { 2031 struct drm_device *dev = pci_get_drvdata(pdev); 2032 2033 drm_dev_unplug(dev); 2034 amdgpu_driver_unload_kms(dev); 2035 2036 /* 2037 * Flush any in flight DMA operations from device. 2038 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2039 * StatusTransactions Pending bit. 2040 */ 2041 pci_disable_device(pdev); 2042 pci_wait_for_pending_transaction(pdev); 2043 } 2044 2045 static void 2046 amdgpu_pci_shutdown(struct pci_dev *pdev) 2047 { 2048 struct drm_device *dev = pci_get_drvdata(pdev); 2049 struct amdgpu_device *adev = drm_to_adev(dev); 2050 2051 if (amdgpu_ras_intr_triggered()) 2052 return; 2053 2054 /* if we are running in a VM, make sure the device 2055 * torn down properly on reboot/shutdown. 2056 * unfortunately we can't detect certain 2057 * hypervisors so just do this all the time. 2058 */ 2059 if (!amdgpu_passthrough(adev)) 2060 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2061 amdgpu_device_ip_suspend(adev); 2062 adev->mp1_state = PP_MP1_STATE_NONE; 2063 } 2064 2065 /** 2066 * amdgpu_drv_delayed_reset_work_handler - work handler for reset 2067 * 2068 * @work: work_struct. 2069 */ 2070 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) 2071 { 2072 struct list_head device_list; 2073 struct amdgpu_device *adev; 2074 int i, r; 2075 struct amdgpu_reset_context reset_context; 2076 2077 memset(&reset_context, 0, sizeof(reset_context)); 2078 2079 mutex_lock(&mgpu_info.mutex); 2080 if (mgpu_info.pending_reset == true) { 2081 mutex_unlock(&mgpu_info.mutex); 2082 return; 2083 } 2084 mgpu_info.pending_reset = true; 2085 mutex_unlock(&mgpu_info.mutex); 2086 2087 /* Use a common context, just need to make sure full reset is done */ 2088 reset_context.method = AMD_RESET_METHOD_NONE; 2089 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2090 2091 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2092 adev = mgpu_info.gpu_ins[i].adev; 2093 reset_context.reset_req_dev = adev; 2094 r = amdgpu_device_pre_asic_reset(adev, &reset_context); 2095 if (r) { 2096 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", 2097 r, adev_to_drm(adev)->unique); 2098 } 2099 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) 2100 r = -EALREADY; 2101 } 2102 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2103 adev = mgpu_info.gpu_ins[i].adev; 2104 flush_work(&adev->xgmi_reset_work); 2105 adev->gmc.xgmi.pending_reset = false; 2106 } 2107 2108 /* reset function will rebuild the xgmi hive info , clear it now */ 2109 for (i = 0; i < mgpu_info.num_dgpu; i++) 2110 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); 2111 2112 INIT_LIST_HEAD(&device_list); 2113 2114 for (i = 0; i < mgpu_info.num_dgpu; i++) 2115 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); 2116 2117 /* unregister the GPU first, reset function will add them back */ 2118 list_for_each_entry(adev, &device_list, reset_list) 2119 amdgpu_unregister_gpu_instance(adev); 2120 2121 /* Use a common context, just need to make sure full reset is done */ 2122 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); 2123 r = amdgpu_do_asic_reset(&device_list, &reset_context); 2124 2125 if (r) { 2126 DRM_ERROR("reinit gpus failure"); 2127 return; 2128 } 2129 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2130 adev = mgpu_info.gpu_ins[i].adev; 2131 if (!adev->kfd.init_complete) 2132 amdgpu_amdkfd_device_init(adev); 2133 amdgpu_ttm_set_buffer_funcs_status(adev, true); 2134 } 2135 return; 2136 } 2137 2138 static int amdgpu_pmops_prepare(struct device *dev) 2139 { 2140 struct drm_device *drm_dev = dev_get_drvdata(dev); 2141 2142 /* Return a positive number here so 2143 * DPM_FLAG_SMART_SUSPEND works properly 2144 */ 2145 if (amdgpu_device_supports_boco(drm_dev)) 2146 return pm_runtime_suspended(dev) && 2147 pm_suspend_via_firmware(); 2148 2149 return 0; 2150 } 2151 2152 static void amdgpu_pmops_complete(struct device *dev) 2153 { 2154 /* nothing to do */ 2155 } 2156 2157 static int amdgpu_pmops_suspend(struct device *dev) 2158 { 2159 struct drm_device *drm_dev = dev_get_drvdata(dev); 2160 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2161 int r; 2162 2163 if (amdgpu_acpi_is_s0ix_active(adev)) 2164 adev->in_s0ix = true; 2165 adev->in_s3 = true; 2166 r = amdgpu_device_suspend(drm_dev, true); 2167 adev->in_s3 = false; 2168 2169 return r; 2170 } 2171 2172 static int amdgpu_pmops_resume(struct device *dev) 2173 { 2174 struct drm_device *drm_dev = dev_get_drvdata(dev); 2175 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2176 int r; 2177 2178 /* Avoids registers access if device is physically gone */ 2179 if (!pci_device_is_present(adev->pdev)) 2180 adev->no_hw_access = true; 2181 2182 r = amdgpu_device_resume(drm_dev, true); 2183 if (amdgpu_acpi_is_s0ix_active(adev)) 2184 adev->in_s0ix = false; 2185 return r; 2186 } 2187 2188 static int amdgpu_pmops_freeze(struct device *dev) 2189 { 2190 struct drm_device *drm_dev = dev_get_drvdata(dev); 2191 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2192 int r; 2193 2194 adev->in_s4 = true; 2195 r = amdgpu_device_suspend(drm_dev, true); 2196 adev->in_s4 = false; 2197 if (r) 2198 return r; 2199 return amdgpu_asic_reset(adev); 2200 } 2201 2202 static int amdgpu_pmops_thaw(struct device *dev) 2203 { 2204 struct drm_device *drm_dev = dev_get_drvdata(dev); 2205 2206 return amdgpu_device_resume(drm_dev, true); 2207 } 2208 2209 static int amdgpu_pmops_poweroff(struct device *dev) 2210 { 2211 struct drm_device *drm_dev = dev_get_drvdata(dev); 2212 2213 return amdgpu_device_suspend(drm_dev, true); 2214 } 2215 2216 static int amdgpu_pmops_restore(struct device *dev) 2217 { 2218 struct drm_device *drm_dev = dev_get_drvdata(dev); 2219 2220 return amdgpu_device_resume(drm_dev, true); 2221 } 2222 2223 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2224 { 2225 struct pci_dev *pdev = to_pci_dev(dev); 2226 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2227 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2228 int ret, i; 2229 2230 if (!adev->runpm) { 2231 pm_runtime_forbid(dev); 2232 return -EBUSY; 2233 } 2234 2235 /* wait for all rings to drain before suspending */ 2236 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2237 struct amdgpu_ring *ring = adev->rings[i]; 2238 if (ring && ring->sched.ready) { 2239 ret = amdgpu_fence_wait_empty(ring); 2240 if (ret) 2241 return -EBUSY; 2242 } 2243 } 2244 2245 adev->in_runpm = true; 2246 if (amdgpu_device_supports_px(drm_dev)) 2247 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2248 2249 ret = amdgpu_device_suspend(drm_dev, false); 2250 if (ret) { 2251 adev->in_runpm = false; 2252 return ret; 2253 } 2254 2255 if (amdgpu_device_supports_px(drm_dev)) { 2256 /* Only need to handle PCI state in the driver for ATPX 2257 * PCI core handles it for _PR3. 2258 */ 2259 amdgpu_device_cache_pci_state(pdev); 2260 pci_disable_device(pdev); 2261 pci_ignore_hotplug(pdev); 2262 pci_set_power_state(pdev, PCI_D3cold); 2263 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2264 } else if (amdgpu_device_supports_boco(drm_dev)) { 2265 /* nothing to do */ 2266 } else if (amdgpu_device_supports_baco(drm_dev)) { 2267 amdgpu_device_baco_enter(drm_dev); 2268 } 2269 2270 return 0; 2271 } 2272 2273 static int amdgpu_pmops_runtime_resume(struct device *dev) 2274 { 2275 struct pci_dev *pdev = to_pci_dev(dev); 2276 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2277 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2278 int ret; 2279 2280 if (!adev->runpm) 2281 return -EINVAL; 2282 2283 /* Avoids registers access if device is physically gone */ 2284 if (!pci_device_is_present(adev->pdev)) 2285 adev->no_hw_access = true; 2286 2287 if (amdgpu_device_supports_px(drm_dev)) { 2288 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2289 2290 /* Only need to handle PCI state in the driver for ATPX 2291 * PCI core handles it for _PR3. 2292 */ 2293 pci_set_power_state(pdev, PCI_D0); 2294 amdgpu_device_load_pci_state(pdev); 2295 ret = pci_enable_device(pdev); 2296 if (ret) 2297 return ret; 2298 pci_set_master(pdev); 2299 } else if (amdgpu_device_supports_boco(drm_dev)) { 2300 /* Only need to handle PCI state in the driver for ATPX 2301 * PCI core handles it for _PR3. 2302 */ 2303 pci_set_master(pdev); 2304 } else if (amdgpu_device_supports_baco(drm_dev)) { 2305 amdgpu_device_baco_exit(drm_dev); 2306 } 2307 ret = amdgpu_device_resume(drm_dev, false); 2308 if (ret) 2309 return ret; 2310 2311 if (amdgpu_device_supports_px(drm_dev)) 2312 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2313 adev->in_runpm = false; 2314 return 0; 2315 } 2316 2317 static int amdgpu_pmops_runtime_idle(struct device *dev) 2318 { 2319 struct drm_device *drm_dev = dev_get_drvdata(dev); 2320 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2321 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 2322 int ret = 1; 2323 2324 if (!adev->runpm) { 2325 pm_runtime_forbid(dev); 2326 return -EBUSY; 2327 } 2328 2329 if (amdgpu_device_has_dc_support(adev)) { 2330 struct drm_crtc *crtc; 2331 2332 drm_for_each_crtc(crtc, drm_dev) { 2333 drm_modeset_lock(&crtc->mutex, NULL); 2334 if (crtc->state->active) 2335 ret = -EBUSY; 2336 drm_modeset_unlock(&crtc->mutex); 2337 if (ret < 0) 2338 break; 2339 } 2340 2341 } else { 2342 struct drm_connector *list_connector; 2343 struct drm_connector_list_iter iter; 2344 2345 mutex_lock(&drm_dev->mode_config.mutex); 2346 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2347 2348 drm_connector_list_iter_begin(drm_dev, &iter); 2349 drm_for_each_connector_iter(list_connector, &iter) { 2350 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2351 ret = -EBUSY; 2352 break; 2353 } 2354 } 2355 2356 drm_connector_list_iter_end(&iter); 2357 2358 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2359 mutex_unlock(&drm_dev->mode_config.mutex); 2360 } 2361 2362 if (ret == -EBUSY) 2363 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 2364 2365 pm_runtime_mark_last_busy(dev); 2366 pm_runtime_autosuspend(dev); 2367 return ret; 2368 } 2369 2370 long amdgpu_drm_ioctl(struct file *filp, 2371 unsigned int cmd, unsigned long arg) 2372 { 2373 struct drm_file *file_priv = filp->private_data; 2374 struct drm_device *dev; 2375 long ret; 2376 dev = file_priv->minor->dev; 2377 ret = pm_runtime_get_sync(dev->dev); 2378 if (ret < 0) 2379 goto out; 2380 2381 ret = drm_ioctl(filp, cmd, arg); 2382 2383 pm_runtime_mark_last_busy(dev->dev); 2384 out: 2385 pm_runtime_put_autosuspend(dev->dev); 2386 return ret; 2387 } 2388 2389 static const struct dev_pm_ops amdgpu_pm_ops = { 2390 .prepare = amdgpu_pmops_prepare, 2391 .complete = amdgpu_pmops_complete, 2392 .suspend = amdgpu_pmops_suspend, 2393 .resume = amdgpu_pmops_resume, 2394 .freeze = amdgpu_pmops_freeze, 2395 .thaw = amdgpu_pmops_thaw, 2396 .poweroff = amdgpu_pmops_poweroff, 2397 .restore = amdgpu_pmops_restore, 2398 .runtime_suspend = amdgpu_pmops_runtime_suspend, 2399 .runtime_resume = amdgpu_pmops_runtime_resume, 2400 .runtime_idle = amdgpu_pmops_runtime_idle, 2401 }; 2402 2403 static int amdgpu_flush(struct file *f, fl_owner_t id) 2404 { 2405 struct drm_file *file_priv = f->private_data; 2406 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2407 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2408 2409 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 2410 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 2411 2412 return timeout >= 0 ? 0 : timeout; 2413 } 2414 2415 static const struct file_operations amdgpu_driver_kms_fops = { 2416 .owner = THIS_MODULE, 2417 .open = drm_open, 2418 .flush = amdgpu_flush, 2419 .release = drm_release, 2420 .unlocked_ioctl = amdgpu_drm_ioctl, 2421 .mmap = drm_gem_mmap, 2422 .poll = drm_poll, 2423 .read = drm_read, 2424 #ifdef CONFIG_COMPAT 2425 .compat_ioctl = amdgpu_kms_compat_ioctl, 2426 #endif 2427 #ifdef CONFIG_PROC_FS 2428 .show_fdinfo = amdgpu_show_fdinfo 2429 #endif 2430 }; 2431 2432 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 2433 { 2434 struct drm_file *file; 2435 2436 if (!filp) 2437 return -EINVAL; 2438 2439 if (filp->f_op != &amdgpu_driver_kms_fops) { 2440 return -EINVAL; 2441 } 2442 2443 file = filp->private_data; 2444 *fpriv = file->driver_priv; 2445 return 0; 2446 } 2447 2448 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 2449 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2450 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2451 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2452 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 2453 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2454 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2455 /* KMS */ 2456 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2457 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2458 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2459 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2460 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2461 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2462 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2463 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2464 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2465 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2466 }; 2467 2468 static const struct drm_driver amdgpu_kms_driver = { 2469 .driver_features = 2470 DRIVER_ATOMIC | 2471 DRIVER_GEM | 2472 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 2473 DRIVER_SYNCOBJ_TIMELINE, 2474 .open = amdgpu_driver_open_kms, 2475 .postclose = amdgpu_driver_postclose_kms, 2476 .lastclose = amdgpu_driver_lastclose_kms, 2477 .ioctls = amdgpu_ioctls_kms, 2478 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2479 .dumb_create = amdgpu_mode_dumb_create, 2480 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2481 .fops = &amdgpu_driver_kms_fops, 2482 .release = &amdgpu_driver_release_kms, 2483 2484 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 2485 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 2486 .gem_prime_import = amdgpu_gem_prime_import, 2487 .gem_prime_mmap = drm_gem_prime_mmap, 2488 2489 .name = DRIVER_NAME, 2490 .desc = DRIVER_DESC, 2491 .date = DRIVER_DATE, 2492 .major = KMS_DRIVER_MAJOR, 2493 .minor = KMS_DRIVER_MINOR, 2494 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2495 }; 2496 2497 static struct pci_error_handlers amdgpu_pci_err_handler = { 2498 .error_detected = amdgpu_pci_error_detected, 2499 .mmio_enabled = amdgpu_pci_mmio_enabled, 2500 .slot_reset = amdgpu_pci_slot_reset, 2501 .resume = amdgpu_pci_resume, 2502 }; 2503 2504 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 2505 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 2506 extern const struct attribute_group amdgpu_vbios_version_attr_group; 2507 2508 static const struct attribute_group *amdgpu_sysfs_groups[] = { 2509 &amdgpu_vram_mgr_attr_group, 2510 &amdgpu_gtt_mgr_attr_group, 2511 &amdgpu_vbios_version_attr_group, 2512 NULL, 2513 }; 2514 2515 2516 static struct pci_driver amdgpu_kms_pci_driver = { 2517 .name = DRIVER_NAME, 2518 .id_table = pciidlist, 2519 .probe = amdgpu_pci_probe, 2520 .remove = amdgpu_pci_remove, 2521 .shutdown = amdgpu_pci_shutdown, 2522 .driver.pm = &amdgpu_pm_ops, 2523 .err_handler = &amdgpu_pci_err_handler, 2524 .dev_groups = amdgpu_sysfs_groups, 2525 }; 2526 2527 static int __init amdgpu_init(void) 2528 { 2529 int r; 2530 2531 if (drm_firmware_drivers_only()) 2532 return -EINVAL; 2533 2534 r = amdgpu_sync_init(); 2535 if (r) 2536 goto error_sync; 2537 2538 r = amdgpu_fence_slab_init(); 2539 if (r) 2540 goto error_fence; 2541 2542 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 2543 amdgpu_register_atpx_handler(); 2544 amdgpu_acpi_detect(); 2545 2546 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 2547 amdgpu_amdkfd_init(); 2548 2549 /* let modprobe override vga console setting */ 2550 return pci_register_driver(&amdgpu_kms_pci_driver); 2551 2552 error_fence: 2553 amdgpu_sync_fini(); 2554 2555 error_sync: 2556 return r; 2557 } 2558 2559 static void __exit amdgpu_exit(void) 2560 { 2561 amdgpu_amdkfd_fini(); 2562 pci_unregister_driver(&amdgpu_kms_pci_driver); 2563 amdgpu_unregister_atpx_handler(); 2564 amdgpu_sync_fini(); 2565 amdgpu_fence_slab_fini(); 2566 mmu_notifier_synchronize(); 2567 } 2568 2569 module_init(amdgpu_init); 2570 module_exit(amdgpu_exit); 2571 2572 MODULE_AUTHOR(DRIVER_AUTHOR); 2573 MODULE_DESCRIPTION(DRIVER_DESC); 2574 MODULE_LICENSE("GPL and additional rights"); 2575