1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/clients/drm_client_setup.h> 27 #include <drm/drm_drv.h> 28 #include <drm/drm_fbdev_ttm.h> 29 #include <drm/drm_gem.h> 30 #include <drm/drm_managed.h> 31 #include <drm/drm_pciids.h> 32 #include <drm/drm_probe_helper.h> 33 #include <drm/drm_vblank.h> 34 35 #include <linux/cc_platform.h> 36 #include <linux/dynamic_debug.h> 37 #include <linux/module.h> 38 #include <linux/mmu_notifier.h> 39 #include <linux/pm_runtime.h> 40 #include <linux/suspend.h> 41 #include <linux/vga_switcheroo.h> 42 43 #include "amdgpu.h" 44 #include "amdgpu_amdkfd.h" 45 #include "amdgpu_dma_buf.h" 46 #include "amdgpu_drv.h" 47 #include "amdgpu_fdinfo.h" 48 #include "amdgpu_irq.h" 49 #include "amdgpu_psp.h" 50 #include "amdgpu_ras.h" 51 #include "amdgpu_reset.h" 52 #include "amdgpu_sched.h" 53 #include "amdgpu_xgmi.h" 54 #include "amdgpu_userq.h" 55 #include "amdgpu_userq_fence.h" 56 #include "../amdxcp/amdgpu_xcp_drv.h" 57 58 /* 59 * KMS wrapper. 60 * - 3.0.0 - initial driver 61 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 62 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 63 * at the end of IBs. 64 * - 3.3.0 - Add VM support for UVD on supported hardware. 65 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 66 * - 3.5.0 - Add support for new UVD_NO_OP register. 67 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 68 * - 3.7.0 - Add support for VCE clock list packet 69 * - 3.8.0 - Add support raster config init in the kernel 70 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 71 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 72 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 73 * - 3.12.0 - Add query for double offchip LDS buffers 74 * - 3.13.0 - Add PRT support 75 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 76 * - 3.15.0 - Export more gpu info for gfx9 77 * - 3.16.0 - Add reserved vmid support 78 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 79 * - 3.18.0 - Export gpu always on cu bitmap 80 * - 3.19.0 - Add support for UVD MJPEG decode 81 * - 3.20.0 - Add support for local BOs 82 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 83 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 84 * - 3.23.0 - Add query for VRAM lost counter 85 * - 3.24.0 - Add high priority compute support for gfx9 86 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 87 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 88 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation. 89 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 90 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 91 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 92 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 93 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 94 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 95 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 96 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 97 * - 3.36.0 - Allow reading more status registers on si/cik 98 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 99 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 100 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 101 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 102 * - 3.41.0 - Add video codec query 103 * - 3.42.0 - Add 16bpc fixed point display support 104 * - 3.43.0 - Add device hot plug/unplug support 105 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 106 * - 3.45.0 - Add context ioctl stable pstate interface 107 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm 108 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags 109 * - 3.48.0 - Add IP discovery version info to HW INFO 110 * - 3.49.0 - Add gang submit into CS IOCTL 111 * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock 112 * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock 113 * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl 114 * 3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields: 115 * tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size, 116 * gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi 117 * 3.53.0 - Support for GFX11 CP GFX shadowing 118 * 3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support 119 * - 3.55.0 - Add AMDGPU_INFO_GPUVM_FAULT query 120 * - 3.56.0 - Update IB start address and size alignment for decode and encode 121 * - 3.57.0 - Compute tunneling on GFX10+ 122 * - 3.58.0 - Add GFX12 DCC support 123 * - 3.59.0 - Cleared VRAM 124 * - 3.60.0 - Add AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE (Vulkan requirement) 125 * - 3.61.0 - Contains fix for RV/PCO compute queues 126 * - 3.62.0 - Add AMDGPU_IDS_FLAGS_MODE_PF, AMDGPU_IDS_FLAGS_MODE_VF & AMDGPU_IDS_FLAGS_MODE_PT 127 * - 3.63.0 - GFX12 display DCC supports 256B max compressed block size 128 * - 3.64.0 - Userq IP support query 129 */ 130 #define KMS_DRIVER_MAJOR 3 131 #define KMS_DRIVER_MINOR 64 132 #define KMS_DRIVER_PATCHLEVEL 0 133 134 /* 135 * amdgpu.debug module options. Are all disabled by default 136 */ 137 enum AMDGPU_DEBUG_MASK { 138 AMDGPU_DEBUG_VM = BIT(0), 139 AMDGPU_DEBUG_LARGEBAR = BIT(1), 140 AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY = BIT(2), 141 AMDGPU_DEBUG_USE_VRAM_FW_BUF = BIT(3), 142 AMDGPU_DEBUG_ENABLE_EXP_RESETS = BIT(5), 143 AMDGPU_DEBUG_DISABLE_GPU_RING_RESET = BIT(6), 144 AMDGPU_DEBUG_SMU_POOL = BIT(7), 145 AMDGPU_DEBUG_VM_USERPTR = BIT(8), 146 AMDGPU_DEBUG_DISABLE_RAS_CE_LOG = BIT(9), 147 AMDGPU_DEBUG_ENABLE_CE_CS = BIT(10), 148 AMDGPU_DEBUG_HIBERNATION_THAW_RESUME_GPU = BIT(11), 149 AMDGPU_DEBUG_DISABLE_IP_BLOCK_SOFT_RESET = BIT(12), 150 }; 151 152 unsigned int amdgpu_vram_limit = UINT_MAX; 153 int amdgpu_vis_vram_limit; 154 int amdgpu_gart_size = -1; /* auto */ 155 int amdgpu_gtt_size = -1; /* auto */ 156 int amdgpu_moverate = -1; /* auto */ 157 int amdgpu_audio = -1; 158 int amdgpu_disp_priority; 159 int amdgpu_hw_i2c; 160 int amdgpu_pcie_gen2 = -1; 161 int amdgpu_msi = -1; 162 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 163 int amdgpu_dpm = -1; 164 int amdgpu_fw_load_type = -1; 165 int amdgpu_aspm = -1; 166 int amdgpu_runtime_pm = -1; 167 uint amdgpu_ip_block_mask = 0xffffffff; 168 int amdgpu_bapm = -1; 169 int amdgpu_deep_color; 170 int amdgpu_vm_size = -1; 171 int amdgpu_vm_fragment_size = -1; 172 int amdgpu_vm_block_size = -1; 173 int amdgpu_vm_fault_stop; 174 int amdgpu_vm_update_mode = -1; 175 int amdgpu_exp_hw_support; 176 int amdgpu_dc = -1; 177 int amdgpu_sched_jobs = 32; 178 int amdgpu_sched_hw_submission = 2; 179 uint amdgpu_pcie_gen_cap; 180 uint amdgpu_pcie_lane_cap; 181 u64 amdgpu_cg_mask = 0xffffffffffffffff; 182 uint amdgpu_pg_mask = 0xffffffff; 183 uint amdgpu_sdma_phase_quantum = 32; 184 char *amdgpu_disable_cu; 185 char *amdgpu_virtual_display; 186 int amdgpu_enforce_isolation = -1; 187 int amdgpu_modeset = -1; 188 189 /* Specifies the default granularity for SVM, used in buffer 190 * migration and restoration of backing memory when handling 191 * recoverable page faults. 192 * 193 * The value is given as log(numPages(buffer)); for a 2 MiB 194 * buffer it computes to be 9 195 */ 196 uint amdgpu_svm_default_granularity = 9; 197 198 /* 199 * OverDrive(bit 14) disabled by default 200 * GFX DCS(bit 19) disabled by default 201 */ 202 uint amdgpu_pp_feature_mask = 0xfff7bfff; 203 uint amdgpu_force_long_training; 204 int amdgpu_lbpw = -1; 205 int amdgpu_compute_multipipe = -1; 206 int amdgpu_gpu_recovery = -1; /* auto */ 207 int amdgpu_emu_mode; 208 uint amdgpu_smu_memory_pool_size; 209 int amdgpu_smu_pptable_id = -1; 210 /* 211 * FBC (bit 0) disabled by default 212 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 213 * - With this, for multiple monitors in sync(e.g. with the same model), 214 * mclk switching will be allowed. And the mclk will be not foced to the 215 * highest. That helps saving some idle power. 216 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 217 * PSR (bit 3) disabled by default 218 * EDP NO POWER SEQUENCING (bit 4) disabled by default 219 */ 220 uint amdgpu_dc_feature_mask = 2; 221 uint amdgpu_dc_debug_mask; 222 uint amdgpu_dc_visual_confirm; 223 int amdgpu_async_gfx_ring = 1; 224 int amdgpu_mcbp = -1; 225 int amdgpu_discovery = -1; 226 int amdgpu_mes_log_enable = 0; 227 int amdgpu_uni_mes = 1; 228 int amdgpu_noretry = -1; 229 int amdgpu_force_asic_type = -1; 230 int amdgpu_tmz = -1; /* auto */ 231 uint amdgpu_freesync_vid_mode; 232 int amdgpu_reset_method = -1; /* auto */ 233 int amdgpu_num_kcq = -1; 234 int amdgpu_smartshift_bias; 235 int amdgpu_use_xgmi_p2p = 1; 236 int amdgpu_vcnfw_log; 237 int amdgpu_sg_display = -1; /* auto */ 238 int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE; 239 int amdgpu_umsch_mm; 240 int amdgpu_seamless = -1; /* auto */ 241 uint amdgpu_debug_mask; 242 int amdgpu_agp = -1; /* auto */ 243 int amdgpu_wbrf = -1; 244 int amdgpu_damage_clips = -1; /* auto */ 245 int amdgpu_umsch_mm_fwlog; 246 int amdgpu_rebar = -1; /* auto */ 247 int amdgpu_user_queue = -1; 248 uint amdgpu_hdmi_hpd_debounce_delay_ms; 249 int amdgpu_ptl = -1; /* auto */ 250 251 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 252 "DRM_UT_CORE", 253 "DRM_UT_DRIVER", 254 "DRM_UT_KMS", 255 "DRM_UT_PRIME", 256 "DRM_UT_ATOMIC", 257 "DRM_UT_VBL", 258 "DRM_UT_STATE", 259 "DRM_UT_LEASE", 260 "DRM_UT_DP", 261 "DRM_UT_DRMRES"); 262 263 struct amdgpu_mgpu_info mgpu_info = { 264 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 265 }; 266 int amdgpu_ras_enable = -1; 267 uint amdgpu_ras_mask = 0xffffffff; 268 int amdgpu_bad_page_threshold = -1; 269 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 270 .timeout_fatal_disable = false, 271 .period = 0x0, /* default to 0x0 (timeout disable) */ 272 }; 273 274 /** 275 * DOC: vramlimit (int) 276 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 277 */ 278 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 279 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 280 281 /** 282 * DOC: vis_vramlimit (int) 283 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 284 */ 285 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 286 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 287 288 /** 289 * DOC: gartsize (uint) 290 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing. 291 * The default is -1 (The size depends on asic). 292 */ 293 MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)"); 294 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 295 296 /** 297 * DOC: gttsize (int) 298 * Restrict the size of GTT domain (for userspace use) in MiB for testing. 299 * The default is -1 (Use value specified by TTM). 300 * This parameter is deprecated and will be removed in the future. 301 */ 302 MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)"); 303 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 304 305 /** 306 * DOC: moverate (int) 307 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 308 */ 309 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 310 module_param_named(moverate, amdgpu_moverate, int, 0600); 311 312 /** 313 * DOC: audio (int) 314 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 315 */ 316 MODULE_PARM_DESC(audio, "HDMI/DP Audio enable for non DC displays (-1 = auto, 0 = disable, 1 = enable)"); 317 module_param_named(audio, amdgpu_audio, int, 0444); 318 319 /** 320 * DOC: disp_priority (int) 321 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 322 */ 323 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 324 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 325 326 /** 327 * DOC: hw_i2c (int) 328 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 329 */ 330 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 331 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 332 333 /** 334 * DOC: pcie_gen2 (int) 335 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 336 */ 337 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 338 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 339 340 /** 341 * DOC: msi (int) 342 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 343 */ 344 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 345 module_param_named(msi, amdgpu_msi, int, 0444); 346 347 /** 348 * DOC: svm_default_granularity (uint) 349 * Used in buffer migration and handling of recoverable page faults 350 */ 351 MODULE_PARM_DESC(svm_default_granularity, "SVM's default granularity in log(2^Pages), default 9 = 2^9 = 2 MiB"); 352 module_param_named(svm_default_granularity, amdgpu_svm_default_granularity, uint, 0644); 353 354 /** 355 * DOC: lockup_timeout (string) 356 * Set GPU scheduler timeout value in ms. 357 * 358 * The format can be [single value] for setting all timeouts at once or 359 * [GFX,Compute,SDMA,Video] to set individual timeouts. 360 * Negative values mean infinity. 361 * 362 * By default(with no lockup_timeout settings), the timeout for all queues is 2000. 363 */ 364 MODULE_PARM_DESC(lockup_timeout, 365 "GPU lockup timeout in ms (default: 2000. 0: keep default value. negative: infinity timeout), format: [single value for all] or [GFX,Compute,SDMA,Video]."); 366 module_param_string(lockup_timeout, amdgpu_lockup_timeout, 367 sizeof(amdgpu_lockup_timeout), 0444); 368 369 /** 370 * DOC: dpm (int) 371 * Override for dynamic power management setting 372 * (0 = disable, 1 = enable) 373 * The default is -1 (auto). 374 */ 375 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 376 module_param_named(dpm, amdgpu_dpm, int, 0444); 377 378 /** 379 * DOC: fw_load_type (int) 380 * Set different firmware loading type for debugging, if supported. 381 * Set to 0 to force direct loading if supported by the ASIC. Set 382 * to -1 to select the default loading mode for the ASIC, as defined 383 * by the driver. The default is -1 (auto). 384 */ 385 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); 386 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 387 388 /** 389 * DOC: aspm (int) 390 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 391 */ 392 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 393 module_param_named(aspm, amdgpu_aspm, int, 0444); 394 395 /** 396 * DOC: runpm (int) 397 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 398 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 399 * Setting the value to 0 disables this functionality. 400 * Setting the value to -2 is auto enabled with power down when displays are attached. 401 */ 402 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto, -2 = auto with displays)"); 403 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 404 405 /** 406 * DOC: ip_block_mask (uint) 407 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 408 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 409 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 410 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 411 */ 412 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 413 module_param_named_unsafe(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 414 415 /** 416 * DOC: bapm (int) 417 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 418 * The default -1 (auto, enabled) 419 */ 420 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 421 module_param_named(bapm, amdgpu_bapm, int, 0444); 422 423 /** 424 * DOC: deep_color (int) 425 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 426 */ 427 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 428 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 429 430 /** 431 * DOC: vm_size (int) 432 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 433 */ 434 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 435 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 436 437 /** 438 * DOC: vm_fragment_size (int) 439 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 440 */ 441 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 442 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 443 444 /** 445 * DOC: vm_block_size (int) 446 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 447 */ 448 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 449 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 450 451 /** 452 * DOC: vm_fault_stop (int) 453 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 454 */ 455 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 456 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 457 458 /** 459 * DOC: vm_update_mode (int) 460 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 461 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 462 */ 463 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 464 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 465 466 /** 467 * DOC: exp_hw_support (int) 468 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 469 */ 470 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 471 module_param_named_unsafe(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 472 473 /** 474 * DOC: dc (int) 475 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 476 */ 477 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 478 module_param_named(dc, amdgpu_dc, int, 0444); 479 480 /** 481 * DOC: sched_jobs (int) 482 * Override the max number of jobs supported in the sw queue. The default is 32. 483 */ 484 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 485 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 486 487 /** 488 * DOC: sched_hw_submission (int) 489 * Override the max number of HW submissions. The default is 2. 490 */ 491 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 492 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 493 494 /** 495 * DOC: ppfeaturemask (hexint) 496 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 497 * The default is the current set of stable power features. 498 */ 499 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 500 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 501 502 /** 503 * DOC: forcelongtraining (uint) 504 * Force long memory training in resume. 505 * The default is zero, indicates short training in resume. 506 */ 507 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 508 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 509 510 /** 511 * DOC: pcie_gen_cap (uint) 512 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 513 * The default is 0 (automatic for each asic). 514 */ 515 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 516 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 517 518 /** 519 * DOC: pcie_lane_cap (uint) 520 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 521 * The default is 0 (automatic for each asic). 522 */ 523 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 524 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 525 526 /** 527 * DOC: cg_mask (ullong) 528 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 529 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 530 */ 531 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 532 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 533 534 /** 535 * DOC: pg_mask (uint) 536 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 537 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 538 */ 539 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 540 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 541 542 /** 543 * DOC: sdma_phase_quantum (uint) 544 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 545 */ 546 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 547 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 548 549 /** 550 * DOC: disable_cu (charp) 551 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 552 */ 553 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 554 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 555 556 /** 557 * DOC: virtual_display (charp) 558 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 559 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 560 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 561 * device at 26:00.0. The default is NULL. 562 */ 563 MODULE_PARM_DESC(virtual_display, 564 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 565 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 566 567 /** 568 * DOC: lbpw (int) 569 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 570 */ 571 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 572 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 573 574 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 575 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 576 577 /** 578 * DOC: gpu_recovery (int) 579 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 580 */ 581 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 582 module_param_named_unsafe(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 583 584 /** 585 * DOC: emu_mode (int) 586 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 587 */ 588 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 589 module_param_named_unsafe(emu_mode, amdgpu_emu_mode, int, 0444); 590 591 /** 592 * DOC: ras_enable (int) 593 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 594 */ 595 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 596 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 597 598 /** 599 * DOC: ras_mask (uint) 600 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 601 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 602 */ 603 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 604 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 605 606 /** 607 * DOC: timeout_fatal_disable (bool) 608 * Disable Watchdog timeout fatal error event 609 */ 610 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 611 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 612 613 /** 614 * DOC: timeout_period (uint) 615 * Modify the watchdog timeout max_cycles as (1 << period) 616 */ 617 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 618 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 619 620 /** 621 * DOC: si_support (int) 622 * 1 = enabled, 0 = disabled, -1 = default 623 * 624 * SI (Southern Islands) are first generation GCN GPUs, supported by both 625 * drivers: radeon (old) and amdgpu (new). This parameter controls whether 626 * amdgpu should support SI. 627 * By default, SI dedicated GPUs are supported by amdgpu. 628 * Only relevant when CONFIG_DRM_AMDGPU_SI is enabled to build SI support in amdgpu. 629 * See also radeon.si_support which should be disabled when amdgpu.si_support is 630 * enabled, and vice versa. 631 */ 632 int amdgpu_si_support = -1; 633 #ifdef CONFIG_DRM_AMDGPU_SI 634 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled, -1 = default)"); 635 module_param_named(si_support, amdgpu_si_support, int, 0444); 636 #endif 637 638 /** 639 * DOC: cik_support (int) 640 * 1 = enabled, 0 = disabled, -1 = default 641 * 642 * CIK (Sea Islands) are second generation GCN GPUs, supported by both 643 * drivers: radeon (old) and amdgpu (new). This parameter controls whether 644 * amdgpu should support CIK. 645 * By default, CIK dedicated GPUs and APUs are supported by amdgpu. 646 * Only relevant when CONFIG_DRM_AMDGPU_CIK is enabled to build CIK support in amdgpu. 647 * See also radeon.cik_support which should be disabled when amdgpu.cik_support is 648 * enabled, and vice versa. 649 */ 650 int amdgpu_cik_support = -1; 651 #ifdef CONFIG_DRM_AMDGPU_CIK 652 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled, -1 = default)"); 653 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 654 #endif 655 656 /** 657 * DOC: smu_memory_pool_size (uint) 658 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 659 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 660 */ 661 MODULE_PARM_DESC(smu_memory_pool_size, 662 "reserve gtt for smu debug usage, 0 = disable,0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 663 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 664 665 /** 666 * DOC: async_gfx_ring (int) 667 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 668 */ 669 MODULE_PARM_DESC(async_gfx_ring, 670 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 671 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 672 673 /** 674 * DOC: mcbp (int) 675 * It is used to enable mid command buffer preemption. (0 = disabled, 1 = enabled, -1 auto (default)) 676 */ 677 MODULE_PARM_DESC(mcbp, 678 "Enable Mid-command buffer preemption (0 = disabled, 1 = enabled), -1 = auto (default)"); 679 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 680 681 /** 682 * DOC: discovery (int) 683 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 684 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 685 */ 686 MODULE_PARM_DESC(discovery, 687 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 688 module_param_named(discovery, amdgpu_discovery, int, 0444); 689 690 /** 691 * DOC: mes_log_enable (int) 692 * Enable Micro Engine Scheduler log. This is used to enable/disable MES internal log. 693 * (0 = disabled (default), 1 = enabled) 694 */ 695 MODULE_PARM_DESC(mes_log_enable, 696 "Enable Micro Engine Scheduler log (0 = disabled (default), 1 = enabled)"); 697 module_param_named(mes_log_enable, amdgpu_mes_log_enable, int, 0444); 698 699 /** 700 * DOC: uni_mes (int) 701 * Enable Unified Micro Engine Scheduler. This is a new engine pipe for unified scheduler. 702 * (0 = disabled (default), 1 = enabled) 703 */ 704 MODULE_PARM_DESC(uni_mes, 705 "Enable Unified Micro Engine Scheduler (0 = disabled, 1 = enabled(default)"); 706 module_param_named(uni_mes, amdgpu_uni_mes, int, 0444); 707 708 /** 709 * DOC: noretry (int) 710 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 711 * do not support per-process XNACK this also disables retry page faults. 712 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 713 */ 714 MODULE_PARM_DESC(noretry, 715 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 716 module_param_named(noretry, amdgpu_noretry, int, 0644); 717 718 /** 719 * DOC: force_asic_type (int) 720 * A non negative value used to specify the asic type for all supported GPUs. 721 */ 722 MODULE_PARM_DESC(force_asic_type, 723 "A non negative value used to specify the asic type for all supported GPUs"); 724 module_param_named_unsafe(force_asic_type, amdgpu_force_asic_type, int, 0444); 725 726 /** 727 * DOC: use_xgmi_p2p (int) 728 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 729 */ 730 MODULE_PARM_DESC(use_xgmi_p2p, 731 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 732 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 733 734 735 #ifdef CONFIG_HSA_AMD 736 /** 737 * DOC: sched_policy (int) 738 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 739 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 740 * assigns queues to HQDs. 741 */ 742 int sched_policy = KFD_SCHED_POLICY_HWS; 743 module_param_unsafe(sched_policy, int, 0444); 744 MODULE_PARM_DESC(sched_policy, 745 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 746 747 /** 748 * DOC: hws_max_conc_proc (int) 749 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 750 * number of VMIDs assigned to the HWS, which is also the default. 751 */ 752 int hws_max_conc_proc = -1; 753 module_param(hws_max_conc_proc, int, 0444); 754 MODULE_PARM_DESC(hws_max_conc_proc, 755 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 756 757 /** 758 * DOC: cwsr_enable (int) 759 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 760 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 761 * disables it. 762 */ 763 int cwsr_enable = 1; 764 module_param(cwsr_enable, int, 0444); 765 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 766 767 /** 768 * DOC: max_num_of_queues_per_device (int) 769 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 770 * is 4096. 771 */ 772 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 773 module_param(max_num_of_queues_per_device, int, 0444); 774 MODULE_PARM_DESC(max_num_of_queues_per_device, 775 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 776 777 /** 778 * DOC: send_sigterm (int) 779 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 780 * but just print errors on dmesg. Setting 1 enables sending sigterm. 781 */ 782 int send_sigterm; 783 module_param(send_sigterm, int, 0444); 784 MODULE_PARM_DESC(send_sigterm, 785 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 786 787 /** 788 * DOC: halt_if_hws_hang (int) 789 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 790 * Setting 1 enables halt on hang. 791 */ 792 int halt_if_hws_hang; 793 module_param_unsafe(halt_if_hws_hang, int, 0644); 794 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 795 796 /** 797 * DOC: hws_gws_support(bool) 798 * Assume that HWS supports GWS barriers regardless of what firmware version 799 * check says. Default value: false (rely on MEC2 firmware version check). 800 */ 801 bool hws_gws_support; 802 module_param_unsafe(hws_gws_support, bool, 0444); 803 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 804 805 /** 806 * DOC: queue_preemption_timeout_ms (int) 807 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 808 */ 809 int queue_preemption_timeout_ms = 9000; 810 module_param(queue_preemption_timeout_ms, int, 0644); 811 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 812 813 /** 814 * DOC: debug_evictions(bool) 815 * Enable extra debug messages to help determine the cause of evictions 816 */ 817 bool debug_evictions; 818 module_param(debug_evictions, bool, 0644); 819 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 820 821 /** 822 * DOC: no_system_mem_limit(bool) 823 * Disable system memory limit, to support multiple process shared memory 824 */ 825 bool no_system_mem_limit; 826 module_param(no_system_mem_limit, bool, 0644); 827 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 828 829 /** 830 * DOC: no_queue_eviction_on_vm_fault (int) 831 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 832 */ 833 int amdgpu_no_queue_eviction_on_vm_fault; 834 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 835 module_param_named_unsafe(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 836 #endif 837 838 /** 839 * DOC: mtype_local (int) 840 */ 841 int amdgpu_mtype_local = -1; 842 MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (default: ASIC dependent, 0 = MTYPE_RW, 1 = MTYPE_NC, 2 = MTYPE_CC)"); 843 module_param_named_unsafe(mtype_local, amdgpu_mtype_local, int, 0444); 844 845 /** 846 * DOC: pcie_p2p (bool) 847 * Enable PCIe P2P (requires large-BAR). Default value: true (on) 848 */ 849 #ifdef CONFIG_HSA_AMD_P2P 850 bool pcie_p2p = true; 851 module_param(pcie_p2p, bool, 0444); 852 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); 853 #endif 854 855 /** 856 * DOC: dcfeaturemask (uint) 857 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 858 * The default is the current set of stable display features. 859 */ 860 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 861 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 862 863 /** 864 * DOC: dcdebugmask (uint) 865 * Display debug options. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 866 */ 867 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 868 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 869 870 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)"); 871 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444); 872 873 /** 874 * DOC: abmlevel (uint) 875 * Override the default ABM (Adaptive Backlight Management) level used for DC 876 * enabled hardware. Requires DMCU to be supported and loaded. 877 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 878 * default. Values 1-4 control the maximum allowable brightness reduction via 879 * the ABM algorithm, with 1 being the least reduction and 4 being the most 880 * reduction. 881 * 882 * Defaults to -1, or auto. Userspace can only override this level after 883 * boot if it's set to auto. 884 */ 885 int amdgpu_dm_abm_level = -1; 886 MODULE_PARM_DESC(abmlevel, 887 "ABM level (0 = off, 1-4 = backlight reduction level, -1 auto (default))"); 888 module_param_named(abmlevel, amdgpu_dm_abm_level, int, 0444); 889 890 int amdgpu_backlight = -1; 891 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 892 module_param_named(backlight, amdgpu_backlight, bint, 0444); 893 894 /** 895 * DOC: damageclips (int) 896 * Enable or disable damage clips support. If damage clips support is disabled, 897 * we will force full frame updates, irrespective of what user space sends to 898 * us. 899 * 900 * Defaults to -1 (where it is enabled unless a PSR-SU display is detected). 901 */ 902 MODULE_PARM_DESC(damageclips, 903 "Damage clips support (0 = disable, 1 = enable, -1 auto (default))"); 904 module_param_named(damageclips, amdgpu_damage_clips, int, 0444); 905 906 /** 907 * DOC: tmz (int) 908 * Trusted Memory Zone (TMZ) is a method to protect data being written 909 * to or read from memory. 910 * 911 * The default value: 0 (off). TODO: change to auto till it is completed. 912 */ 913 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 914 module_param_named(tmz, amdgpu_tmz, int, 0444); 915 916 /** 917 * DOC: freesync_video (uint) 918 * Enable the optimization to adjust front porch timing to achieve seamless 919 * mode change experience when setting a freesync supported mode for which full 920 * modeset is not needed. 921 * 922 * The Display Core will add a set of modes derived from the base FreeSync 923 * video mode into the corresponding connector's mode list based on commonly 924 * used refresh rates and VRR range of the connected display, when users enable 925 * this feature. From the userspace perspective, they can see a seamless mode 926 * change experience when the change between different refresh rates under the 927 * same resolution. Additionally, userspace applications such as Video playback 928 * can read this modeset list and change the refresh rate based on the video 929 * frame rate. Finally, the userspace can also derive an appropriate mode for a 930 * particular refresh rate based on the FreeSync Mode and add it to the 931 * connector's mode list. 932 * 933 * Note: This is an experimental feature. 934 * 935 * The default value: 0 (off). 936 */ 937 MODULE_PARM_DESC( 938 freesync_video, 939 "Adds additional modes via VRR for refresh changes without a full modeset (0 = off (default), 1 = on)"); 940 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); 941 942 /** 943 * DOC: reset_method (int) 944 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 945 */ 946 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 947 module_param_named_unsafe(reset_method, amdgpu_reset_method, int, 0644); 948 949 /** 950 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 951 * threshold value of faulty pages detected by RAS ECC, which may 952 * result in the GPU entering bad status when the number of total 953 * faulty pages by ECC exceeds the threshold value. 954 */ 955 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = threshold determined by a formula, 0 < threshold < max records, user-defined threshold)"); 956 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 957 958 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 959 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 960 961 /** 962 * DOC: vcnfw_log (int) 963 * Enable vcnfw log output for debugging, the default is disabled. 964 */ 965 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 966 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 967 968 /** 969 * DOC: sg_display (int) 970 * Disable S/G (scatter/gather) display (i.e., display from system memory). 971 * This option is only relevant on APUs. Set this option to 0 to disable 972 * S/G display if you experience flickering or other issues under memory 973 * pressure and report the issue. 974 */ 975 MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)"); 976 module_param_named(sg_display, amdgpu_sg_display, int, 0444); 977 978 /** 979 * DOC: umsch_mm (int) 980 * Enable Multi Media User Mode Scheduler. This is a HW scheduling engine for VCN and VPE. 981 * (0 = disabled (default), 1 = enabled) 982 */ 983 MODULE_PARM_DESC(umsch_mm, 984 "Enable Multi Media User Mode Scheduler (0 = disabled (default), 1 = enabled)"); 985 module_param_named(umsch_mm, amdgpu_umsch_mm, int, 0444); 986 987 /** 988 * DOC: umsch_mm_fwlog (int) 989 * Enable umschfw log output for debugging, the default is disabled. 990 */ 991 MODULE_PARM_DESC(umsch_mm_fwlog, "Enable umschfw log(0 = disable (default value), 1 = enable)"); 992 module_param_named(umsch_mm_fwlog, amdgpu_umsch_mm_fwlog, int, 0444); 993 994 /** 995 * DOC: smu_pptable_id (int) 996 * Used to override pptable id. id = 0 use VBIOS pptable. 997 * id > 0 use the soft pptable with specicfied id. 998 */ 999 MODULE_PARM_DESC(smu_pptable_id, 1000 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 1001 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 1002 1003 /** 1004 * DOC: partition_mode (int) 1005 * Used to override the default SPX mode. 1006 */ 1007 MODULE_PARM_DESC( 1008 user_partt_mode, 1009 "specify partition mode to be used (-2 = AMDGPU_AUTO_COMPUTE_PARTITION_MODE(default value) \ 1010 0 = AMDGPU_SPX_PARTITION_MODE, \ 1011 1 = AMDGPU_DPX_PARTITION_MODE, \ 1012 2 = AMDGPU_TPX_PARTITION_MODE, \ 1013 3 = AMDGPU_QPX_PARTITION_MODE, \ 1014 4 = AMDGPU_CPX_PARTITION_MODE)"); 1015 module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint, 0444); 1016 1017 1018 /** 1019 * DOC: enforce_isolation (int) 1020 * enforce process isolation between graphics and compute. 1021 * (-1 = auto, 0 = disable, 1 = enable, 2 = enable legacy mode, 3 = enable without cleaner shader) 1022 */ 1023 module_param_named(enforce_isolation, amdgpu_enforce_isolation, int, 0444); 1024 MODULE_PARM_DESC(enforce_isolation, 1025 "enforce process isolation between graphics and compute. (-1 = auto, 0 = disable, 1 = enable, 2 = enable legacy mode, 3 = enable without cleaner shader)"); 1026 1027 /** 1028 * DOC: modeset (int) 1029 * Override nomodeset (1 = override, -1 = auto). The default is -1 (auto). 1030 */ 1031 MODULE_PARM_DESC(modeset, "Override nomodeset (1 = enable, -1 = auto)"); 1032 module_param_named(modeset, amdgpu_modeset, int, 0444); 1033 1034 /** 1035 * DOC: seamless (int) 1036 * Seamless boot will keep the image on the screen during the boot process. 1037 */ 1038 MODULE_PARM_DESC(seamless, "Seamless boot (-1 = auto (default), 0 = disable, 1 = enable)"); 1039 module_param_named(seamless, amdgpu_seamless, int, 0444); 1040 1041 /** 1042 * DOC: debug_mask (uint) 1043 * Debug options for amdgpu, work as a binary mask with the following options: 1044 * 1045 * - 0x1: Debug VM handling 1046 * - 0x2: Enable simulating large-bar capability on non-large bar system. This 1047 * limits the VRAM size reported to ROCm applications to the visible 1048 * size, usually 256MB. 1049 * - 0x4: Disable GPU soft recovery, always do a full reset 1050 * - 0x8: Use VRAM for firmware loading 1051 * - 0x10: Enable ACA based RAS logging 1052 * - 0x20: Enable experimental resets 1053 * - 0x40: Disable ring resets 1054 * - 0x80: Use VRAM for SMU pool 1055 */ 1056 MODULE_PARM_DESC(debug_mask, "debug options for amdgpu, disabled by default"); 1057 module_param_named_unsafe(debug_mask, amdgpu_debug_mask, uint, 0444); 1058 1059 /** 1060 * DOC: agp (int) 1061 * Enable the AGP aperture. This provides an aperture in the GPU's internal 1062 * address space for direct access to system memory. Note that these accesses 1063 * are non-snooped, so they are only used for access to uncached memory. 1064 */ 1065 MODULE_PARM_DESC(agp, "AGP (-1 = auto (default), 0 = disable, 1 = enable)"); 1066 module_param_named(agp, amdgpu_agp, int, 0444); 1067 1068 /** 1069 * DOC: wbrf (int) 1070 * Enable Wifi RFI interference mitigation feature. 1071 * Due to electrical and mechanical constraints there may be likely interference of 1072 * relatively high-powered harmonics of the (G-)DDR memory clocks with local radio 1073 * module frequency bands used by Wifi 6/6e/7. To mitigate the possible RFI interference, 1074 * with this feature enabled, PMFW will use either “shadowed P-State” or “P-State” based 1075 * on active list of frequencies in-use (to be avoided) as part of initial setting or 1076 * P-state transition. However, there may be potential performance impact with this 1077 * feature enabled. 1078 * (0 = disabled, 1 = enabled, -1 = auto (default setting, will be enabled if supported)) 1079 */ 1080 MODULE_PARM_DESC(wbrf, 1081 "Enable Wifi RFI interference mitigation (0 = disabled, 1 = enabled, -1 = auto(default)"); 1082 module_param_named(wbrf, amdgpu_wbrf, int, 0444); 1083 1084 /** 1085 * DOC: rebar (int) 1086 * Allow BAR resizing. Disable this to prevent the driver from attempting 1087 * to resize the BAR if the GPU supports it and there is available MMIO space. 1088 * Note that this just prevents the driver from resizing the BAR. The BIOS 1089 * may have already resized the BAR at boot time. 1090 */ 1091 MODULE_PARM_DESC(rebar, "Resizable BAR (-1 = auto (default), 0 = disable, 1 = enable)"); 1092 module_param_named(rebar, amdgpu_rebar, int, 0444); 1093 1094 /** 1095 * DOC: user_queue (int) 1096 * Enable user queues on systems that support user queues. Possible values: 1097 * 1098 * - -1 = auto (ASIC specific default) 1099 * - 0 = user queues disabled 1100 * - 1 = user queues enabled and kernel queues enabled (if supported) 1101 * - 2 = user queues enabled and kernel queues disabled 1102 */ 1103 MODULE_PARM_DESC(user_queue, "Enable user queues (-1 = auto (default), 0 = disable, 1 = enable, 2 = enable UQs and disable KQs)"); 1104 module_param_named(user_queue, amdgpu_user_queue, int, 0444); 1105 1106 /* 1107 * DOC: hdmi_hpd_debounce_delay_ms (uint) 1108 * HDMI HPD disconnect debounce delay in milliseconds. 1109 * 1110 * Used to filter short disconnect->reconnect HPD toggles some HDMI sinks 1111 * generate while entering/leaving power save. Set to 0 to disable by default. 1112 */ 1113 MODULE_PARM_DESC(hdmi_hpd_debounce_delay_ms, "HDMI HPD disconnect debounce delay in milliseconds (0 to disable (by default), 1500 is common)"); 1114 module_param_named(hdmi_hpd_debounce_delay_ms, amdgpu_hdmi_hpd_debounce_delay_ms, uint, 0644); 1115 1116 /** 1117 * DOC: ptl (int) 1118 * Enable PTL feature at boot time. Possible values: 1119 * 1120 * - -1 = auto (ASIC specific default) 1121 * - 0 = disable PTL (default) 1122 * - 1 = enable PTL 1123 * - 2 = permanently disable PTL (cannot be re-enabled at runtime) 1124 */ 1125 MODULE_PARM_DESC(ptl, "Enable PTL (-1 = auto, 0 = disable (default), 1 = enable, 2 = permanently disable)"); 1126 module_param_named(ptl, amdgpu_ptl, int, 0444); 1127 1128 /* These devices are not supported by amdgpu. 1129 * They are supported by the mach64, r128, radeon drivers 1130 */ 1131 static const u16 amdgpu_unsupported_pciidlist[] = { 1132 /* mach64 */ 1133 0x4354, 1134 0x4358, 1135 0x4554, 1136 0x4742, 1137 0x4744, 1138 0x4749, 1139 0x474C, 1140 0x474D, 1141 0x474E, 1142 0x474F, 1143 0x4750, 1144 0x4751, 1145 0x4752, 1146 0x4753, 1147 0x4754, 1148 0x4755, 1149 0x4756, 1150 0x4757, 1151 0x4758, 1152 0x4759, 1153 0x475A, 1154 0x4C42, 1155 0x4C44, 1156 0x4C47, 1157 0x4C49, 1158 0x4C4D, 1159 0x4C4E, 1160 0x4C50, 1161 0x4C51, 1162 0x4C52, 1163 0x4C53, 1164 0x5654, 1165 0x5655, 1166 0x5656, 1167 /* r128 */ 1168 0x4c45, 1169 0x4c46, 1170 0x4d46, 1171 0x4d4c, 1172 0x5041, 1173 0x5042, 1174 0x5043, 1175 0x5044, 1176 0x5045, 1177 0x5046, 1178 0x5047, 1179 0x5048, 1180 0x5049, 1181 0x504A, 1182 0x504B, 1183 0x504C, 1184 0x504D, 1185 0x504E, 1186 0x504F, 1187 0x5050, 1188 0x5051, 1189 0x5052, 1190 0x5053, 1191 0x5054, 1192 0x5055, 1193 0x5056, 1194 0x5057, 1195 0x5058, 1196 0x5245, 1197 0x5246, 1198 0x5247, 1199 0x524b, 1200 0x524c, 1201 0x534d, 1202 0x5446, 1203 0x544C, 1204 0x5452, 1205 /* radeon */ 1206 0x3150, 1207 0x3151, 1208 0x3152, 1209 0x3154, 1210 0x3155, 1211 0x3E50, 1212 0x3E54, 1213 0x4136, 1214 0x4137, 1215 0x4144, 1216 0x4145, 1217 0x4146, 1218 0x4147, 1219 0x4148, 1220 0x4149, 1221 0x414A, 1222 0x414B, 1223 0x4150, 1224 0x4151, 1225 0x4152, 1226 0x4153, 1227 0x4154, 1228 0x4155, 1229 0x4156, 1230 0x4237, 1231 0x4242, 1232 0x4336, 1233 0x4337, 1234 0x4437, 1235 0x4966, 1236 0x4967, 1237 0x4A48, 1238 0x4A49, 1239 0x4A4A, 1240 0x4A4B, 1241 0x4A4C, 1242 0x4A4D, 1243 0x4A4E, 1244 0x4A4F, 1245 0x4A50, 1246 0x4A54, 1247 0x4B48, 1248 0x4B49, 1249 0x4B4A, 1250 0x4B4B, 1251 0x4B4C, 1252 0x4C57, 1253 0x4C58, 1254 0x4C59, 1255 0x4C5A, 1256 0x4C64, 1257 0x4C66, 1258 0x4C67, 1259 0x4E44, 1260 0x4E45, 1261 0x4E46, 1262 0x4E47, 1263 0x4E48, 1264 0x4E49, 1265 0x4E4A, 1266 0x4E4B, 1267 0x4E50, 1268 0x4E51, 1269 0x4E52, 1270 0x4E53, 1271 0x4E54, 1272 0x4E56, 1273 0x5144, 1274 0x5145, 1275 0x5146, 1276 0x5147, 1277 0x5148, 1278 0x514C, 1279 0x514D, 1280 0x5157, 1281 0x5158, 1282 0x5159, 1283 0x515A, 1284 0x515E, 1285 0x5460, 1286 0x5462, 1287 0x5464, 1288 0x5548, 1289 0x5549, 1290 0x554A, 1291 0x554B, 1292 0x554C, 1293 0x554D, 1294 0x554E, 1295 0x554F, 1296 0x5550, 1297 0x5551, 1298 0x5552, 1299 0x5554, 1300 0x564A, 1301 0x564B, 1302 0x564F, 1303 0x5652, 1304 0x5653, 1305 0x5657, 1306 0x5834, 1307 0x5835, 1308 0x5954, 1309 0x5955, 1310 0x5974, 1311 0x5975, 1312 0x5960, 1313 0x5961, 1314 0x5962, 1315 0x5964, 1316 0x5965, 1317 0x5969, 1318 0x5a41, 1319 0x5a42, 1320 0x5a61, 1321 0x5a62, 1322 0x5b60, 1323 0x5b62, 1324 0x5b63, 1325 0x5b64, 1326 0x5b65, 1327 0x5c61, 1328 0x5c63, 1329 0x5d48, 1330 0x5d49, 1331 0x5d4a, 1332 0x5d4c, 1333 0x5d4d, 1334 0x5d4e, 1335 0x5d4f, 1336 0x5d50, 1337 0x5d52, 1338 0x5d57, 1339 0x5e48, 1340 0x5e4a, 1341 0x5e4b, 1342 0x5e4c, 1343 0x5e4d, 1344 0x5e4f, 1345 0x6700, 1346 0x6701, 1347 0x6702, 1348 0x6703, 1349 0x6704, 1350 0x6705, 1351 0x6706, 1352 0x6707, 1353 0x6708, 1354 0x6709, 1355 0x6718, 1356 0x6719, 1357 0x671c, 1358 0x671d, 1359 0x671f, 1360 0x6720, 1361 0x6721, 1362 0x6722, 1363 0x6723, 1364 0x6724, 1365 0x6725, 1366 0x6726, 1367 0x6727, 1368 0x6728, 1369 0x6729, 1370 0x6738, 1371 0x6739, 1372 0x673e, 1373 0x6740, 1374 0x6741, 1375 0x6742, 1376 0x6743, 1377 0x6744, 1378 0x6745, 1379 0x6746, 1380 0x6747, 1381 0x6748, 1382 0x6749, 1383 0x674A, 1384 0x6750, 1385 0x6751, 1386 0x6758, 1387 0x6759, 1388 0x675B, 1389 0x675D, 1390 0x675F, 1391 0x6760, 1392 0x6761, 1393 0x6762, 1394 0x6763, 1395 0x6764, 1396 0x6765, 1397 0x6766, 1398 0x6767, 1399 0x6768, 1400 0x6770, 1401 0x6771, 1402 0x6772, 1403 0x6778, 1404 0x6779, 1405 0x677B, 1406 0x6840, 1407 0x6841, 1408 0x6842, 1409 0x6843, 1410 0x6849, 1411 0x684C, 1412 0x6850, 1413 0x6858, 1414 0x6859, 1415 0x6880, 1416 0x6888, 1417 0x6889, 1418 0x688A, 1419 0x688C, 1420 0x688D, 1421 0x6898, 1422 0x6899, 1423 0x689b, 1424 0x689c, 1425 0x689d, 1426 0x689e, 1427 0x68a0, 1428 0x68a1, 1429 0x68a8, 1430 0x68a9, 1431 0x68b0, 1432 0x68b8, 1433 0x68b9, 1434 0x68ba, 1435 0x68be, 1436 0x68bf, 1437 0x68c0, 1438 0x68c1, 1439 0x68c7, 1440 0x68c8, 1441 0x68c9, 1442 0x68d8, 1443 0x68d9, 1444 0x68da, 1445 0x68de, 1446 0x68e0, 1447 0x68e1, 1448 0x68e4, 1449 0x68e5, 1450 0x68e8, 1451 0x68e9, 1452 0x68f1, 1453 0x68f2, 1454 0x68f8, 1455 0x68f9, 1456 0x68fa, 1457 0x68fe, 1458 0x7100, 1459 0x7101, 1460 0x7102, 1461 0x7103, 1462 0x7104, 1463 0x7105, 1464 0x7106, 1465 0x7108, 1466 0x7109, 1467 0x710A, 1468 0x710B, 1469 0x710C, 1470 0x710E, 1471 0x710F, 1472 0x7140, 1473 0x7141, 1474 0x7142, 1475 0x7143, 1476 0x7144, 1477 0x7145, 1478 0x7146, 1479 0x7147, 1480 0x7149, 1481 0x714A, 1482 0x714B, 1483 0x714C, 1484 0x714D, 1485 0x714E, 1486 0x714F, 1487 0x7151, 1488 0x7152, 1489 0x7153, 1490 0x715E, 1491 0x715F, 1492 0x7180, 1493 0x7181, 1494 0x7183, 1495 0x7186, 1496 0x7187, 1497 0x7188, 1498 0x718A, 1499 0x718B, 1500 0x718C, 1501 0x718D, 1502 0x718F, 1503 0x7193, 1504 0x7196, 1505 0x719B, 1506 0x719F, 1507 0x71C0, 1508 0x71C1, 1509 0x71C2, 1510 0x71C3, 1511 0x71C4, 1512 0x71C5, 1513 0x71C6, 1514 0x71C7, 1515 0x71CD, 1516 0x71CE, 1517 0x71D2, 1518 0x71D4, 1519 0x71D5, 1520 0x71D6, 1521 0x71DA, 1522 0x71DE, 1523 0x7200, 1524 0x7210, 1525 0x7211, 1526 0x7240, 1527 0x7243, 1528 0x7244, 1529 0x7245, 1530 0x7246, 1531 0x7247, 1532 0x7248, 1533 0x7249, 1534 0x724A, 1535 0x724B, 1536 0x724C, 1537 0x724D, 1538 0x724E, 1539 0x724F, 1540 0x7280, 1541 0x7281, 1542 0x7283, 1543 0x7284, 1544 0x7287, 1545 0x7288, 1546 0x7289, 1547 0x728B, 1548 0x728C, 1549 0x7290, 1550 0x7291, 1551 0x7293, 1552 0x7297, 1553 0x7834, 1554 0x7835, 1555 0x791e, 1556 0x791f, 1557 0x793f, 1558 0x7941, 1559 0x7942, 1560 0x796c, 1561 0x796d, 1562 0x796e, 1563 0x796f, 1564 0x9400, 1565 0x9401, 1566 0x9402, 1567 0x9403, 1568 0x9405, 1569 0x940A, 1570 0x940B, 1571 0x940F, 1572 0x94A0, 1573 0x94A1, 1574 0x94A3, 1575 0x94B1, 1576 0x94B3, 1577 0x94B4, 1578 0x94B5, 1579 0x94B9, 1580 0x9440, 1581 0x9441, 1582 0x9442, 1583 0x9443, 1584 0x9444, 1585 0x9446, 1586 0x944A, 1587 0x944B, 1588 0x944C, 1589 0x944E, 1590 0x9450, 1591 0x9452, 1592 0x9456, 1593 0x945A, 1594 0x945B, 1595 0x945E, 1596 0x9460, 1597 0x9462, 1598 0x946A, 1599 0x946B, 1600 0x947A, 1601 0x947B, 1602 0x9480, 1603 0x9487, 1604 0x9488, 1605 0x9489, 1606 0x948A, 1607 0x948F, 1608 0x9490, 1609 0x9491, 1610 0x9495, 1611 0x9498, 1612 0x949C, 1613 0x949E, 1614 0x949F, 1615 0x94C0, 1616 0x94C1, 1617 0x94C3, 1618 0x94C4, 1619 0x94C5, 1620 0x94C6, 1621 0x94C7, 1622 0x94C8, 1623 0x94C9, 1624 0x94CB, 1625 0x94CC, 1626 0x94CD, 1627 0x9500, 1628 0x9501, 1629 0x9504, 1630 0x9505, 1631 0x9506, 1632 0x9507, 1633 0x9508, 1634 0x9509, 1635 0x950F, 1636 0x9511, 1637 0x9515, 1638 0x9517, 1639 0x9519, 1640 0x9540, 1641 0x9541, 1642 0x9542, 1643 0x954E, 1644 0x954F, 1645 0x9552, 1646 0x9553, 1647 0x9555, 1648 0x9557, 1649 0x955f, 1650 0x9580, 1651 0x9581, 1652 0x9583, 1653 0x9586, 1654 0x9587, 1655 0x9588, 1656 0x9589, 1657 0x958A, 1658 0x958B, 1659 0x958C, 1660 0x958D, 1661 0x958E, 1662 0x958F, 1663 0x9590, 1664 0x9591, 1665 0x9593, 1666 0x9595, 1667 0x9596, 1668 0x9597, 1669 0x9598, 1670 0x9599, 1671 0x959B, 1672 0x95C0, 1673 0x95C2, 1674 0x95C4, 1675 0x95C5, 1676 0x95C6, 1677 0x95C7, 1678 0x95C9, 1679 0x95CC, 1680 0x95CD, 1681 0x95CE, 1682 0x95CF, 1683 0x9610, 1684 0x9611, 1685 0x9612, 1686 0x9613, 1687 0x9614, 1688 0x9615, 1689 0x9616, 1690 0x9640, 1691 0x9641, 1692 0x9642, 1693 0x9643, 1694 0x9644, 1695 0x9645, 1696 0x9647, 1697 0x9648, 1698 0x9649, 1699 0x964a, 1700 0x964b, 1701 0x964c, 1702 0x964e, 1703 0x964f, 1704 0x9710, 1705 0x9711, 1706 0x9712, 1707 0x9713, 1708 0x9714, 1709 0x9715, 1710 0x9802, 1711 0x9803, 1712 0x9804, 1713 0x9805, 1714 0x9806, 1715 0x9807, 1716 0x9808, 1717 0x9809, 1718 0x980A, 1719 0x9900, 1720 0x9901, 1721 0x9903, 1722 0x9904, 1723 0x9905, 1724 0x9906, 1725 0x9907, 1726 0x9908, 1727 0x9909, 1728 0x990A, 1729 0x990B, 1730 0x990C, 1731 0x990D, 1732 0x990E, 1733 0x990F, 1734 0x9910, 1735 0x9913, 1736 0x9917, 1737 0x9918, 1738 0x9919, 1739 0x9990, 1740 0x9991, 1741 0x9992, 1742 0x9993, 1743 0x9994, 1744 0x9995, 1745 0x9996, 1746 0x9997, 1747 0x9998, 1748 0x9999, 1749 0x999A, 1750 0x999B, 1751 0x999C, 1752 0x999D, 1753 0x99A0, 1754 0x99A2, 1755 0x99A4, 1756 /* radeon secondary ids */ 1757 0x3171, 1758 0x3e70, 1759 0x4164, 1760 0x4165, 1761 0x4166, 1762 0x4168, 1763 0x4170, 1764 0x4171, 1765 0x4172, 1766 0x4173, 1767 0x496e, 1768 0x4a69, 1769 0x4a6a, 1770 0x4a6b, 1771 0x4a70, 1772 0x4a74, 1773 0x4b69, 1774 0x4b6b, 1775 0x4b6c, 1776 0x4c6e, 1777 0x4e64, 1778 0x4e65, 1779 0x4e66, 1780 0x4e67, 1781 0x4e68, 1782 0x4e69, 1783 0x4e6a, 1784 0x4e71, 1785 0x4f73, 1786 0x5569, 1787 0x556b, 1788 0x556d, 1789 0x556f, 1790 0x5571, 1791 0x5854, 1792 0x5874, 1793 0x5940, 1794 0x5941, 1795 0x5b70, 1796 0x5b72, 1797 0x5b73, 1798 0x5b74, 1799 0x5b75, 1800 0x5d44, 1801 0x5d45, 1802 0x5d6d, 1803 0x5d6f, 1804 0x5d72, 1805 0x5d77, 1806 0x5e6b, 1807 0x5e6d, 1808 0x7120, 1809 0x7124, 1810 0x7129, 1811 0x712e, 1812 0x712f, 1813 0x7162, 1814 0x7163, 1815 0x7166, 1816 0x7167, 1817 0x7172, 1818 0x7173, 1819 0x71a0, 1820 0x71a1, 1821 0x71a3, 1822 0x71a7, 1823 0x71bb, 1824 0x71e0, 1825 0x71e1, 1826 0x71e2, 1827 0x71e6, 1828 0x71e7, 1829 0x71f2, 1830 0x7269, 1831 0x726b, 1832 0x726e, 1833 0x72a0, 1834 0x72a8, 1835 0x72b1, 1836 0x72b3, 1837 0x793f, 1838 }; 1839 1840 static const struct pci_device_id pciidlist[] = { 1841 { PCI_DEVICE(0x1002, 0x6780), .driver_data = CHIP_TAHITI }, 1842 { PCI_DEVICE(0x1002, 0x6784), .driver_data = CHIP_TAHITI }, 1843 { PCI_DEVICE(0x1002, 0x6788), .driver_data = CHIP_TAHITI }, 1844 { PCI_DEVICE(0x1002, 0x678A), .driver_data = CHIP_TAHITI }, 1845 { PCI_DEVICE(0x1002, 0x6790), .driver_data = CHIP_TAHITI }, 1846 { PCI_DEVICE(0x1002, 0x6791), .driver_data = CHIP_TAHITI }, 1847 { PCI_DEVICE(0x1002, 0x6792), .driver_data = CHIP_TAHITI }, 1848 { PCI_DEVICE(0x1002, 0x6798), .driver_data = CHIP_TAHITI }, 1849 { PCI_DEVICE(0x1002, 0x6799), .driver_data = CHIP_TAHITI }, 1850 { PCI_DEVICE(0x1002, 0x679A), .driver_data = CHIP_TAHITI }, 1851 { PCI_DEVICE(0x1002, 0x679B), .driver_data = CHIP_TAHITI }, 1852 { PCI_DEVICE(0x1002, 0x679E), .driver_data = CHIP_TAHITI }, 1853 { PCI_DEVICE(0x1002, 0x679F), .driver_data = CHIP_TAHITI }, 1854 { PCI_DEVICE(0x1002, 0x6800), .driver_data = CHIP_PITCAIRN|AMD_IS_MOBILITY }, 1855 { PCI_DEVICE(0x1002, 0x6801), .driver_data = CHIP_PITCAIRN|AMD_IS_MOBILITY }, 1856 { PCI_DEVICE(0x1002, 0x6802), .driver_data = CHIP_PITCAIRN|AMD_IS_MOBILITY }, 1857 { PCI_DEVICE(0x1002, 0x6806), .driver_data = CHIP_PITCAIRN }, 1858 { PCI_DEVICE(0x1002, 0x6808), .driver_data = CHIP_PITCAIRN }, 1859 { PCI_DEVICE(0x1002, 0x6809), .driver_data = CHIP_PITCAIRN }, 1860 { PCI_DEVICE(0x1002, 0x6810), .driver_data = CHIP_PITCAIRN }, 1861 { PCI_DEVICE(0x1002, 0x6811), .driver_data = CHIP_PITCAIRN }, 1862 { PCI_DEVICE(0x1002, 0x6816), .driver_data = CHIP_PITCAIRN }, 1863 { PCI_DEVICE(0x1002, 0x6817), .driver_data = CHIP_PITCAIRN }, 1864 { PCI_DEVICE(0x1002, 0x6818), .driver_data = CHIP_PITCAIRN }, 1865 { PCI_DEVICE(0x1002, 0x6819), .driver_data = CHIP_PITCAIRN }, 1866 { PCI_DEVICE(0x1002, 0x6600), .driver_data = CHIP_OLAND|AMD_IS_MOBILITY }, 1867 { PCI_DEVICE(0x1002, 0x6601), .driver_data = CHIP_OLAND|AMD_IS_MOBILITY }, 1868 { PCI_DEVICE(0x1002, 0x6602), .driver_data = CHIP_OLAND|AMD_IS_MOBILITY }, 1869 { PCI_DEVICE(0x1002, 0x6603), .driver_data = CHIP_OLAND|AMD_IS_MOBILITY }, 1870 { PCI_DEVICE(0x1002, 0x6604), .driver_data = CHIP_OLAND|AMD_IS_MOBILITY }, 1871 { PCI_DEVICE(0x1002, 0x6605), .driver_data = CHIP_OLAND|AMD_IS_MOBILITY }, 1872 { PCI_DEVICE(0x1002, 0x6606), .driver_data = CHIP_OLAND|AMD_IS_MOBILITY }, 1873 { PCI_DEVICE(0x1002, 0x6607), .driver_data = CHIP_OLAND|AMD_IS_MOBILITY }, 1874 { PCI_DEVICE(0x1002, 0x6608), .driver_data = CHIP_OLAND }, 1875 { PCI_DEVICE(0x1002, 0x6610), .driver_data = CHIP_OLAND }, 1876 { PCI_DEVICE(0x1002, 0x6611), .driver_data = CHIP_OLAND }, 1877 { PCI_DEVICE(0x1002, 0x6613), .driver_data = CHIP_OLAND }, 1878 { PCI_DEVICE(0x1002, 0x6617), .driver_data = CHIP_OLAND|AMD_IS_MOBILITY }, 1879 { PCI_DEVICE(0x1002, 0x6620), .driver_data = CHIP_OLAND|AMD_IS_MOBILITY }, 1880 { PCI_DEVICE(0x1002, 0x6621), .driver_data = CHIP_OLAND|AMD_IS_MOBILITY }, 1881 { PCI_DEVICE(0x1002, 0x6623), .driver_data = CHIP_OLAND|AMD_IS_MOBILITY }, 1882 { PCI_DEVICE(0x1002, 0x6631), .driver_data = CHIP_OLAND }, 1883 { PCI_DEVICE(0x1002, 0x6820), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY }, 1884 { PCI_DEVICE(0x1002, 0x6821), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY }, 1885 { PCI_DEVICE(0x1002, 0x6822), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY }, 1886 { PCI_DEVICE(0x1002, 0x6823), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY }, 1887 { PCI_DEVICE(0x1002, 0x6824), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY }, 1888 { PCI_DEVICE(0x1002, 0x6825), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY }, 1889 { PCI_DEVICE(0x1002, 0x6826), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY }, 1890 { PCI_DEVICE(0x1002, 0x6827), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY }, 1891 { PCI_DEVICE(0x1002, 0x6828), .driver_data = CHIP_VERDE }, 1892 { PCI_DEVICE(0x1002, 0x6829), .driver_data = CHIP_VERDE }, 1893 { PCI_DEVICE(0x1002, 0x682A), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY }, 1894 { PCI_DEVICE(0x1002, 0x682B), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY }, 1895 { PCI_DEVICE(0x1002, 0x682C), .driver_data = CHIP_VERDE }, 1896 { PCI_DEVICE(0x1002, 0x682D), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY }, 1897 { PCI_DEVICE(0x1002, 0x682F), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY }, 1898 { PCI_DEVICE(0x1002, 0x6830), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY }, 1899 { PCI_DEVICE(0x1002, 0x6831), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY }, 1900 { PCI_DEVICE(0x1002, 0x6835), .driver_data = CHIP_VERDE }, 1901 { PCI_DEVICE(0x1002, 0x6837), .driver_data = CHIP_VERDE }, 1902 { PCI_DEVICE(0x1002, 0x6838), .driver_data = CHIP_VERDE }, 1903 { PCI_DEVICE(0x1002, 0x6839), .driver_data = CHIP_VERDE }, 1904 { PCI_DEVICE(0x1002, 0x683B), .driver_data = CHIP_VERDE }, 1905 { PCI_DEVICE(0x1002, 0x683D), .driver_data = CHIP_VERDE }, 1906 { PCI_DEVICE(0x1002, 0x683F), .driver_data = CHIP_VERDE }, 1907 { PCI_DEVICE(0x1002, 0x6660), .driver_data = CHIP_HAINAN|AMD_IS_MOBILITY }, 1908 { PCI_DEVICE(0x1002, 0x6663), .driver_data = CHIP_HAINAN|AMD_IS_MOBILITY }, 1909 { PCI_DEVICE(0x1002, 0x6664), .driver_data = CHIP_HAINAN|AMD_IS_MOBILITY }, 1910 { PCI_DEVICE(0x1002, 0x6665), .driver_data = CHIP_HAINAN|AMD_IS_MOBILITY }, 1911 { PCI_DEVICE(0x1002, 0x6667), .driver_data = CHIP_HAINAN|AMD_IS_MOBILITY }, 1912 { PCI_DEVICE(0x1002, 0x666F), .driver_data = CHIP_HAINAN|AMD_IS_MOBILITY }, 1913 /* Kaveri */ 1914 { PCI_DEVICE(0x1002, 0x1304), .driver_data = CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU }, 1915 { PCI_DEVICE(0x1002, 0x1305), .driver_data = CHIP_KAVERI|AMD_IS_APU }, 1916 { PCI_DEVICE(0x1002, 0x1306), .driver_data = CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU }, 1917 { PCI_DEVICE(0x1002, 0x1307), .driver_data = CHIP_KAVERI|AMD_IS_APU }, 1918 { PCI_DEVICE(0x1002, 0x1309), .driver_data = CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU }, 1919 { PCI_DEVICE(0x1002, 0x130A), .driver_data = CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU }, 1920 { PCI_DEVICE(0x1002, 0x130B), .driver_data = CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU }, 1921 { PCI_DEVICE(0x1002, 0x130C), .driver_data = CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU }, 1922 { PCI_DEVICE(0x1002, 0x130D), .driver_data = CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU }, 1923 { PCI_DEVICE(0x1002, 0x130E), .driver_data = CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU }, 1924 { PCI_DEVICE(0x1002, 0x130F), .driver_data = CHIP_KAVERI|AMD_IS_APU }, 1925 { PCI_DEVICE(0x1002, 0x1310), .driver_data = CHIP_KAVERI|AMD_IS_APU }, 1926 { PCI_DEVICE(0x1002, 0x1311), .driver_data = CHIP_KAVERI|AMD_IS_APU }, 1927 { PCI_DEVICE(0x1002, 0x1312), .driver_data = CHIP_KAVERI|AMD_IS_APU }, 1928 { PCI_DEVICE(0x1002, 0x1313), .driver_data = CHIP_KAVERI|AMD_IS_APU }, 1929 { PCI_DEVICE(0x1002, 0x1315), .driver_data = CHIP_KAVERI|AMD_IS_APU }, 1930 { PCI_DEVICE(0x1002, 0x1316), .driver_data = CHIP_KAVERI|AMD_IS_APU }, 1931 { PCI_DEVICE(0x1002, 0x1317), .driver_data = CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU }, 1932 { PCI_DEVICE(0x1002, 0x1318), .driver_data = CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU }, 1933 { PCI_DEVICE(0x1002, 0x131B), .driver_data = CHIP_KAVERI|AMD_IS_APU }, 1934 { PCI_DEVICE(0x1002, 0x131C), .driver_data = CHIP_KAVERI|AMD_IS_APU }, 1935 { PCI_DEVICE(0x1002, 0x131D), .driver_data = CHIP_KAVERI|AMD_IS_APU }, 1936 /* Bonaire */ 1937 { PCI_DEVICE(0x1002, 0x6640), .driver_data = CHIP_BONAIRE|AMD_IS_MOBILITY }, 1938 { PCI_DEVICE(0x1002, 0x6641), .driver_data = CHIP_BONAIRE|AMD_IS_MOBILITY }, 1939 { PCI_DEVICE(0x1002, 0x6646), .driver_data = CHIP_BONAIRE|AMD_IS_MOBILITY }, 1940 { PCI_DEVICE(0x1002, 0x6647), .driver_data = CHIP_BONAIRE|AMD_IS_MOBILITY }, 1941 { PCI_DEVICE(0x1002, 0x6649), .driver_data = CHIP_BONAIRE }, 1942 { PCI_DEVICE(0x1002, 0x664D), .driver_data = CHIP_BONAIRE }, 1943 { PCI_DEVICE(0x1002, 0x6650), .driver_data = CHIP_BONAIRE }, 1944 { PCI_DEVICE(0x1002, 0x6651), .driver_data = CHIP_BONAIRE }, 1945 { PCI_DEVICE(0x1002, 0x6658), .driver_data = CHIP_BONAIRE }, 1946 { PCI_DEVICE(0x1002, 0x665c), .driver_data = CHIP_BONAIRE }, 1947 { PCI_DEVICE(0x1002, 0x665d), .driver_data = CHIP_BONAIRE }, 1948 { PCI_DEVICE(0x1002, 0x665f), .driver_data = CHIP_BONAIRE }, 1949 /* Hawaii */ 1950 { PCI_DEVICE(0x1002, 0x67A0), .driver_data = CHIP_HAWAII }, 1951 { PCI_DEVICE(0x1002, 0x67A1), .driver_data = CHIP_HAWAII }, 1952 { PCI_DEVICE(0x1002, 0x67A2), .driver_data = CHIP_HAWAII }, 1953 { PCI_DEVICE(0x1002, 0x67A8), .driver_data = CHIP_HAWAII }, 1954 { PCI_DEVICE(0x1002, 0x67A9), .driver_data = CHIP_HAWAII }, 1955 { PCI_DEVICE(0x1002, 0x67AA), .driver_data = CHIP_HAWAII }, 1956 { PCI_DEVICE(0x1002, 0x67B0), .driver_data = CHIP_HAWAII }, 1957 { PCI_DEVICE(0x1002, 0x67B1), .driver_data = CHIP_HAWAII }, 1958 { PCI_DEVICE(0x1002, 0x67B8), .driver_data = CHIP_HAWAII }, 1959 { PCI_DEVICE(0x1002, 0x67B9), .driver_data = CHIP_HAWAII }, 1960 { PCI_DEVICE(0x1002, 0x67BA), .driver_data = CHIP_HAWAII }, 1961 { PCI_DEVICE(0x1002, 0x67BE), .driver_data = CHIP_HAWAII }, 1962 /* Kabini */ 1963 { PCI_DEVICE(0x1002, 0x9830), .driver_data = CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU }, 1964 { PCI_DEVICE(0x1002, 0x9831), .driver_data = CHIP_KABINI|AMD_IS_APU }, 1965 { PCI_DEVICE(0x1002, 0x9832), .driver_data = CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU }, 1966 { PCI_DEVICE(0x1002, 0x9833), .driver_data = CHIP_KABINI|AMD_IS_APU }, 1967 { PCI_DEVICE(0x1002, 0x9834), .driver_data = CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU }, 1968 { PCI_DEVICE(0x1002, 0x9835), .driver_data = CHIP_KABINI|AMD_IS_APU }, 1969 { PCI_DEVICE(0x1002, 0x9836), .driver_data = CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU }, 1970 { PCI_DEVICE(0x1002, 0x9837), .driver_data = CHIP_KABINI|AMD_IS_APU }, 1971 { PCI_DEVICE(0x1002, 0x9838), .driver_data = CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU }, 1972 { PCI_DEVICE(0x1002, 0x9839), .driver_data = CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU }, 1973 { PCI_DEVICE(0x1002, 0x983a), .driver_data = CHIP_KABINI|AMD_IS_APU }, 1974 { PCI_DEVICE(0x1002, 0x983b), .driver_data = CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU }, 1975 { PCI_DEVICE(0x1002, 0x983c), .driver_data = CHIP_KABINI|AMD_IS_APU }, 1976 { PCI_DEVICE(0x1002, 0x983d), .driver_data = CHIP_KABINI|AMD_IS_APU }, 1977 { PCI_DEVICE(0x1002, 0x983e), .driver_data = CHIP_KABINI|AMD_IS_APU }, 1978 { PCI_DEVICE(0x1002, 0x983f), .driver_data = CHIP_KABINI|AMD_IS_APU }, 1979 /* mullins */ 1980 { PCI_DEVICE(0x1002, 0x9850), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU }, 1981 { PCI_DEVICE(0x1002, 0x9851), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU }, 1982 { PCI_DEVICE(0x1002, 0x9852), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU }, 1983 { PCI_DEVICE(0x1002, 0x9853), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU }, 1984 { PCI_DEVICE(0x1002, 0x9854), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU }, 1985 { PCI_DEVICE(0x1002, 0x9855), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU }, 1986 { PCI_DEVICE(0x1002, 0x9856), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU }, 1987 { PCI_DEVICE(0x1002, 0x9857), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU }, 1988 { PCI_DEVICE(0x1002, 0x9858), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU }, 1989 { PCI_DEVICE(0x1002, 0x9859), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU }, 1990 { PCI_DEVICE(0x1002, 0x985A), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU }, 1991 { PCI_DEVICE(0x1002, 0x985B), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU }, 1992 { PCI_DEVICE(0x1002, 0x985C), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU }, 1993 { PCI_DEVICE(0x1002, 0x985D), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU }, 1994 { PCI_DEVICE(0x1002, 0x985E), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU }, 1995 { PCI_DEVICE(0x1002, 0x985F), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU }, 1996 /* topaz */ 1997 { PCI_DEVICE(0x1002, 0x6900), .driver_data = CHIP_TOPAZ }, 1998 { PCI_DEVICE(0x1002, 0x6901), .driver_data = CHIP_TOPAZ }, 1999 { PCI_DEVICE(0x1002, 0x6902), .driver_data = CHIP_TOPAZ }, 2000 { PCI_DEVICE(0x1002, 0x6903), .driver_data = CHIP_TOPAZ }, 2001 { PCI_DEVICE(0x1002, 0x6907), .driver_data = CHIP_TOPAZ }, 2002 /* tonga */ 2003 { PCI_DEVICE(0x1002, 0x6920), .driver_data = CHIP_TONGA }, 2004 { PCI_DEVICE(0x1002, 0x6921), .driver_data = CHIP_TONGA }, 2005 { PCI_DEVICE(0x1002, 0x6928), .driver_data = CHIP_TONGA }, 2006 { PCI_DEVICE(0x1002, 0x6929), .driver_data = CHIP_TONGA }, 2007 { PCI_DEVICE(0x1002, 0x692B), .driver_data = CHIP_TONGA }, 2008 { PCI_DEVICE(0x1002, 0x692F), .driver_data = CHIP_TONGA }, 2009 { PCI_DEVICE(0x1002, 0x6930), .driver_data = CHIP_TONGA }, 2010 { PCI_DEVICE(0x1002, 0x6938), .driver_data = CHIP_TONGA }, 2011 { PCI_DEVICE(0x1002, 0x6939), .driver_data = CHIP_TONGA }, 2012 { PCI_DEVICE(0x1002, 0x693B), .driver_data = CHIP_TONGA }, 2013 /* fiji */ 2014 { PCI_DEVICE(0x1002, 0x7300), .driver_data = CHIP_FIJI }, 2015 { PCI_DEVICE(0x1002, 0x730F), .driver_data = CHIP_FIJI }, 2016 /* carrizo */ 2017 { PCI_DEVICE(0x1002, 0x9870), .driver_data = CHIP_CARRIZO|AMD_IS_APU }, 2018 { PCI_DEVICE(0x1002, 0x9874), .driver_data = CHIP_CARRIZO|AMD_IS_APU }, 2019 { PCI_DEVICE(0x1002, 0x9875), .driver_data = CHIP_CARRIZO|AMD_IS_APU }, 2020 { PCI_DEVICE(0x1002, 0x9876), .driver_data = CHIP_CARRIZO|AMD_IS_APU }, 2021 { PCI_DEVICE(0x1002, 0x9877), .driver_data = CHIP_CARRIZO|AMD_IS_APU }, 2022 /* stoney */ 2023 { PCI_DEVICE(0x1002, 0x98E4), .driver_data = CHIP_STONEY|AMD_IS_APU }, 2024 /* Polaris11 */ 2025 { PCI_DEVICE(0x1002, 0x67E0), .driver_data = CHIP_POLARIS11 }, 2026 { PCI_DEVICE(0x1002, 0x67E3), .driver_data = CHIP_POLARIS11 }, 2027 { PCI_DEVICE(0x1002, 0x67E8), .driver_data = CHIP_POLARIS11 }, 2028 { PCI_DEVICE(0x1002, 0x67EB), .driver_data = CHIP_POLARIS11 }, 2029 { PCI_DEVICE(0x1002, 0x67EF), .driver_data = CHIP_POLARIS11 }, 2030 { PCI_DEVICE(0x1002, 0x67FF), .driver_data = CHIP_POLARIS11 }, 2031 { PCI_DEVICE(0x1002, 0x67E1), .driver_data = CHIP_POLARIS11 }, 2032 { PCI_DEVICE(0x1002, 0x67E7), .driver_data = CHIP_POLARIS11 }, 2033 { PCI_DEVICE(0x1002, 0x67E9), .driver_data = CHIP_POLARIS11 }, 2034 /* Polaris10 */ 2035 { PCI_DEVICE(0x1002, 0x67C0), .driver_data = CHIP_POLARIS10 }, 2036 { PCI_DEVICE(0x1002, 0x67C1), .driver_data = CHIP_POLARIS10 }, 2037 { PCI_DEVICE(0x1002, 0x67C2), .driver_data = CHIP_POLARIS10 }, 2038 { PCI_DEVICE(0x1002, 0x67C4), .driver_data = CHIP_POLARIS10 }, 2039 { PCI_DEVICE(0x1002, 0x67C7), .driver_data = CHIP_POLARIS10 }, 2040 { PCI_DEVICE(0x1002, 0x67D0), .driver_data = CHIP_POLARIS10 }, 2041 { PCI_DEVICE(0x1002, 0x67D4), .driver_data = CHIP_POLARIS10 }, 2042 { PCI_DEVICE(0x1002, 0x67DF), .driver_data = CHIP_POLARIS10 }, 2043 { PCI_DEVICE(0x1002, 0x67C8), .driver_data = CHIP_POLARIS10 }, 2044 { PCI_DEVICE(0x1002, 0x67C9), .driver_data = CHIP_POLARIS10 }, 2045 { PCI_DEVICE(0x1002, 0x67CA), .driver_data = CHIP_POLARIS10 }, 2046 { PCI_DEVICE(0x1002, 0x67CC), .driver_data = CHIP_POLARIS10 }, 2047 { PCI_DEVICE(0x1002, 0x67CF), .driver_data = CHIP_POLARIS10 }, 2048 { PCI_DEVICE(0x1002, 0x6FDF), .driver_data = CHIP_POLARIS10 }, 2049 /* Polaris12 */ 2050 { PCI_DEVICE(0x1002, 0x6980), .driver_data = CHIP_POLARIS12 }, 2051 { PCI_DEVICE(0x1002, 0x6981), .driver_data = CHIP_POLARIS12 }, 2052 { PCI_DEVICE(0x1002, 0x6985), .driver_data = CHIP_POLARIS12 }, 2053 { PCI_DEVICE(0x1002, 0x6986), .driver_data = CHIP_POLARIS12 }, 2054 { PCI_DEVICE(0x1002, 0x6987), .driver_data = CHIP_POLARIS12 }, 2055 { PCI_DEVICE(0x1002, 0x698F), .driver_data = CHIP_POLARIS12 }, 2056 { PCI_DEVICE(0x1002, 0x6995), .driver_data = CHIP_POLARIS12 }, 2057 { PCI_DEVICE(0x1002, 0x6997), .driver_data = CHIP_POLARIS12 }, 2058 { PCI_DEVICE(0x1002, 0x699F), .driver_data = CHIP_POLARIS12 }, 2059 /* VEGAM */ 2060 { PCI_DEVICE(0x1002, 0x694C), .driver_data = CHIP_VEGAM }, 2061 { PCI_DEVICE(0x1002, 0x694E), .driver_data = CHIP_VEGAM }, 2062 { PCI_DEVICE(0x1002, 0x694F), .driver_data = CHIP_VEGAM }, 2063 /* Vega 10 */ 2064 { PCI_DEVICE(0x1002, 0x6860), .driver_data = CHIP_VEGA10 }, 2065 { PCI_DEVICE(0x1002, 0x6861), .driver_data = CHIP_VEGA10 }, 2066 { PCI_DEVICE(0x1002, 0x6862), .driver_data = CHIP_VEGA10 }, 2067 { PCI_DEVICE(0x1002, 0x6863), .driver_data = CHIP_VEGA10 }, 2068 { PCI_DEVICE(0x1002, 0x6864), .driver_data = CHIP_VEGA10 }, 2069 { PCI_DEVICE(0x1002, 0x6867), .driver_data = CHIP_VEGA10 }, 2070 { PCI_DEVICE(0x1002, 0x6868), .driver_data = CHIP_VEGA10 }, 2071 { PCI_DEVICE(0x1002, 0x6869), .driver_data = CHIP_VEGA10 }, 2072 { PCI_DEVICE(0x1002, 0x686a), .driver_data = CHIP_VEGA10 }, 2073 { PCI_DEVICE(0x1002, 0x686b), .driver_data = CHIP_VEGA10 }, 2074 { PCI_DEVICE(0x1002, 0x686c), .driver_data = CHIP_VEGA10 }, 2075 { PCI_DEVICE(0x1002, 0x686d), .driver_data = CHIP_VEGA10 }, 2076 { PCI_DEVICE(0x1002, 0x686e), .driver_data = CHIP_VEGA10 }, 2077 { PCI_DEVICE(0x1002, 0x686f), .driver_data = CHIP_VEGA10 }, 2078 { PCI_DEVICE(0x1002, 0x687f), .driver_data = CHIP_VEGA10 }, 2079 /* Vega 12 */ 2080 { PCI_DEVICE(0x1002, 0x69A0), .driver_data = CHIP_VEGA12 }, 2081 { PCI_DEVICE(0x1002, 0x69A1), .driver_data = CHIP_VEGA12 }, 2082 { PCI_DEVICE(0x1002, 0x69A2), .driver_data = CHIP_VEGA12 }, 2083 { PCI_DEVICE(0x1002, 0x69A3), .driver_data = CHIP_VEGA12 }, 2084 { PCI_DEVICE(0x1002, 0x69AF), .driver_data = CHIP_VEGA12 }, 2085 /* Vega 20 */ 2086 { PCI_DEVICE(0x1002, 0x66A0), .driver_data = CHIP_VEGA20 }, 2087 { PCI_DEVICE(0x1002, 0x66A1), .driver_data = CHIP_VEGA20 }, 2088 { PCI_DEVICE(0x1002, 0x66A2), .driver_data = CHIP_VEGA20 }, 2089 { PCI_DEVICE(0x1002, 0x66A3), .driver_data = CHIP_VEGA20 }, 2090 { PCI_DEVICE(0x1002, 0x66A4), .driver_data = CHIP_VEGA20 }, 2091 { PCI_DEVICE(0x1002, 0x66A7), .driver_data = CHIP_VEGA20 }, 2092 { PCI_DEVICE(0x1002, 0x66AF), .driver_data = CHIP_VEGA20 }, 2093 /* Raven */ 2094 { PCI_DEVICE(0x1002, 0x15dd), .driver_data = CHIP_RAVEN|AMD_IS_APU }, 2095 { PCI_DEVICE(0x1002, 0x15d8), .driver_data = CHIP_RAVEN|AMD_IS_APU }, 2096 /* Arcturus */ 2097 { PCI_DEVICE(0x1002, 0x738C), .driver_data = CHIP_ARCTURUS }, 2098 { PCI_DEVICE(0x1002, 0x7388), .driver_data = CHIP_ARCTURUS }, 2099 { PCI_DEVICE(0x1002, 0x738E), .driver_data = CHIP_ARCTURUS }, 2100 { PCI_DEVICE(0x1002, 0x7390), .driver_data = CHIP_ARCTURUS }, 2101 /* Navi10 */ 2102 { PCI_DEVICE(0x1002, 0x7310), .driver_data = CHIP_NAVI10 }, 2103 { PCI_DEVICE(0x1002, 0x7312), .driver_data = CHIP_NAVI10 }, 2104 { PCI_DEVICE(0x1002, 0x7318), .driver_data = CHIP_NAVI10 }, 2105 { PCI_DEVICE(0x1002, 0x7319), .driver_data = CHIP_NAVI10 }, 2106 { PCI_DEVICE(0x1002, 0x731A), .driver_data = CHIP_NAVI10 }, 2107 { PCI_DEVICE(0x1002, 0x731B), .driver_data = CHIP_NAVI10 }, 2108 { PCI_DEVICE(0x1002, 0x731E), .driver_data = CHIP_NAVI10 }, 2109 { PCI_DEVICE(0x1002, 0x731F), .driver_data = CHIP_NAVI10 }, 2110 /* Navi14 */ 2111 { PCI_DEVICE(0x1002, 0x7340), .driver_data = CHIP_NAVI14 }, 2112 { PCI_DEVICE(0x1002, 0x7341), .driver_data = CHIP_NAVI14 }, 2113 { PCI_DEVICE(0x1002, 0x7347), .driver_data = CHIP_NAVI14 }, 2114 { PCI_DEVICE(0x1002, 0x734F), .driver_data = CHIP_NAVI14 }, 2115 2116 /* Renoir */ 2117 { PCI_DEVICE(0x1002, 0x15E7), .driver_data = CHIP_RENOIR|AMD_IS_APU }, 2118 { PCI_DEVICE(0x1002, 0x1636), .driver_data = CHIP_RENOIR|AMD_IS_APU }, 2119 { PCI_DEVICE(0x1002, 0x1638), .driver_data = CHIP_RENOIR|AMD_IS_APU }, 2120 { PCI_DEVICE(0x1002, 0x164C), .driver_data = CHIP_RENOIR|AMD_IS_APU }, 2121 2122 /* Navi12 */ 2123 { PCI_DEVICE(0x1002, 0x7360), .driver_data = CHIP_NAVI12 }, 2124 { PCI_DEVICE(0x1002, 0x7362), .driver_data = CHIP_NAVI12 }, 2125 2126 /* Sienna_Cichlid */ 2127 { PCI_DEVICE(0x1002, 0x73A0), .driver_data = CHIP_SIENNA_CICHLID }, 2128 { PCI_DEVICE(0x1002, 0x73A1), .driver_data = CHIP_SIENNA_CICHLID }, 2129 { PCI_DEVICE(0x1002, 0x73A2), .driver_data = CHIP_SIENNA_CICHLID }, 2130 { PCI_DEVICE(0x1002, 0x73A3), .driver_data = CHIP_SIENNA_CICHLID }, 2131 { PCI_DEVICE(0x1002, 0x73A5), .driver_data = CHIP_SIENNA_CICHLID }, 2132 { PCI_DEVICE(0x1002, 0x73A8), .driver_data = CHIP_SIENNA_CICHLID }, 2133 { PCI_DEVICE(0x1002, 0x73A9), .driver_data = CHIP_SIENNA_CICHLID }, 2134 { PCI_DEVICE(0x1002, 0x73AB), .driver_data = CHIP_SIENNA_CICHLID }, 2135 { PCI_DEVICE(0x1002, 0x73AC), .driver_data = CHIP_SIENNA_CICHLID }, 2136 { PCI_DEVICE(0x1002, 0x73AD), .driver_data = CHIP_SIENNA_CICHLID }, 2137 { PCI_DEVICE(0x1002, 0x73AE), .driver_data = CHIP_SIENNA_CICHLID }, 2138 { PCI_DEVICE(0x1002, 0x73AF), .driver_data = CHIP_SIENNA_CICHLID }, 2139 { PCI_DEVICE(0x1002, 0x73BF), .driver_data = CHIP_SIENNA_CICHLID }, 2140 2141 /* Yellow Carp */ 2142 { PCI_DEVICE(0x1002, 0x164D), .driver_data = CHIP_YELLOW_CARP|AMD_IS_APU }, 2143 { PCI_DEVICE(0x1002, 0x1681), .driver_data = CHIP_YELLOW_CARP|AMD_IS_APU }, 2144 2145 /* Navy_Flounder */ 2146 { PCI_DEVICE(0x1002, 0x73C0), .driver_data = CHIP_NAVY_FLOUNDER }, 2147 { PCI_DEVICE(0x1002, 0x73C1), .driver_data = CHIP_NAVY_FLOUNDER }, 2148 { PCI_DEVICE(0x1002, 0x73C3), .driver_data = CHIP_NAVY_FLOUNDER }, 2149 { PCI_DEVICE(0x1002, 0x73DA), .driver_data = CHIP_NAVY_FLOUNDER }, 2150 { PCI_DEVICE(0x1002, 0x73DB), .driver_data = CHIP_NAVY_FLOUNDER }, 2151 { PCI_DEVICE(0x1002, 0x73DC), .driver_data = CHIP_NAVY_FLOUNDER }, 2152 { PCI_DEVICE(0x1002, 0x73DD), .driver_data = CHIP_NAVY_FLOUNDER }, 2153 { PCI_DEVICE(0x1002, 0x73DE), .driver_data = CHIP_NAVY_FLOUNDER }, 2154 { PCI_DEVICE(0x1002, 0x73DF), .driver_data = CHIP_NAVY_FLOUNDER }, 2155 2156 /* DIMGREY_CAVEFISH */ 2157 { PCI_DEVICE(0x1002, 0x73E0), .driver_data = CHIP_DIMGREY_CAVEFISH }, 2158 { PCI_DEVICE(0x1002, 0x73E1), .driver_data = CHIP_DIMGREY_CAVEFISH }, 2159 { PCI_DEVICE(0x1002, 0x73E2), .driver_data = CHIP_DIMGREY_CAVEFISH }, 2160 { PCI_DEVICE(0x1002, 0x73E3), .driver_data = CHIP_DIMGREY_CAVEFISH }, 2161 { PCI_DEVICE(0x1002, 0x73E8), .driver_data = CHIP_DIMGREY_CAVEFISH }, 2162 { PCI_DEVICE(0x1002, 0x73E9), .driver_data = CHIP_DIMGREY_CAVEFISH }, 2163 { PCI_DEVICE(0x1002, 0x73EA), .driver_data = CHIP_DIMGREY_CAVEFISH }, 2164 { PCI_DEVICE(0x1002, 0x73EB), .driver_data = CHIP_DIMGREY_CAVEFISH }, 2165 { PCI_DEVICE(0x1002, 0x73EC), .driver_data = CHIP_DIMGREY_CAVEFISH }, 2166 { PCI_DEVICE(0x1002, 0x73ED), .driver_data = CHIP_DIMGREY_CAVEFISH }, 2167 { PCI_DEVICE(0x1002, 0x73EF), .driver_data = CHIP_DIMGREY_CAVEFISH }, 2168 { PCI_DEVICE(0x1002, 0x73FF), .driver_data = CHIP_DIMGREY_CAVEFISH }, 2169 2170 /* Aldebaran */ 2171 { PCI_DEVICE(0x1002, 0x7408), .driver_data = CHIP_ALDEBARAN }, 2172 { PCI_DEVICE(0x1002, 0x740C), .driver_data = CHIP_ALDEBARAN }, 2173 { PCI_DEVICE(0x1002, 0x740F), .driver_data = CHIP_ALDEBARAN }, 2174 { PCI_DEVICE(0x1002, 0x7410), .driver_data = CHIP_ALDEBARAN }, 2175 2176 /* CYAN_SKILLFISH */ 2177 { PCI_DEVICE(0x1002, 0x13DB), .driver_data = CHIP_CYAN_SKILLFISH|AMD_IS_APU }, 2178 { PCI_DEVICE(0x1002, 0x13F9), .driver_data = CHIP_CYAN_SKILLFISH|AMD_IS_APU }, 2179 { PCI_DEVICE(0x1002, 0x13FA), .driver_data = CHIP_CYAN_SKILLFISH|AMD_IS_APU }, 2180 { PCI_DEVICE(0x1002, 0x13FB), .driver_data = CHIP_CYAN_SKILLFISH|AMD_IS_APU }, 2181 { PCI_DEVICE(0x1002, 0x13FC), .driver_data = CHIP_CYAN_SKILLFISH|AMD_IS_APU }, 2182 { PCI_DEVICE(0x1002, 0x13FE), .driver_data = CHIP_CYAN_SKILLFISH|AMD_IS_APU }, 2183 { PCI_DEVICE(0x1002, 0x143F), .driver_data = CHIP_CYAN_SKILLFISH|AMD_IS_APU }, 2184 2185 /* BEIGE_GOBY */ 2186 { PCI_DEVICE(0x1002, 0x7420), .driver_data = CHIP_BEIGE_GOBY }, 2187 { PCI_DEVICE(0x1002, 0x7421), .driver_data = CHIP_BEIGE_GOBY }, 2188 { PCI_DEVICE(0x1002, 0x7422), .driver_data = CHIP_BEIGE_GOBY }, 2189 { PCI_DEVICE(0x1002, 0x7423), .driver_data = CHIP_BEIGE_GOBY }, 2190 { PCI_DEVICE(0x1002, 0x7424), .driver_data = CHIP_BEIGE_GOBY }, 2191 { PCI_DEVICE(0x1002, 0x743F), .driver_data = CHIP_BEIGE_GOBY }, 2192 2193 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2194 .class = PCI_CLASS_DISPLAY_VGA << 8, 2195 .class_mask = 0xffffff, 2196 .driver_data = CHIP_IP_DISCOVERY }, 2197 2198 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2199 .class = PCI_CLASS_DISPLAY_OTHER << 8, 2200 .class_mask = 0xffffff, 2201 .driver_data = CHIP_IP_DISCOVERY }, 2202 2203 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2204 .class = PCI_CLASS_ACCELERATOR_PROCESSING << 8, 2205 .class_mask = 0xffffff, 2206 .driver_data = CHIP_IP_DISCOVERY }, 2207 2208 { } 2209 }; 2210 2211 MODULE_DEVICE_TABLE(pci, pciidlist); 2212 2213 static const struct amdgpu_asic_type_quirk asic_type_quirks[] = { 2214 /* differentiate between P10 and P11 asics with the same DID */ 2215 {0x67FF, 0xE3, CHIP_POLARIS10}, 2216 {0x67FF, 0xE7, CHIP_POLARIS10}, 2217 {0x67FF, 0xF3, CHIP_POLARIS10}, 2218 {0x67FF, 0xF7, CHIP_POLARIS10}, 2219 }; 2220 2221 static const struct drm_driver amdgpu_kms_driver; 2222 2223 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 2224 { 2225 struct pci_dev *p = NULL; 2226 int i; 2227 2228 /* 0 - GPU 2229 * 1 - audio 2230 * 2 - USB 2231 * 3 - UCSI 2232 */ 2233 for (i = 1; i < 4; i++) { 2234 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 2235 adev->pdev->bus->number, i); 2236 if (p) { 2237 pm_runtime_get_sync(&p->dev); 2238 pm_runtime_put_autosuspend(&p->dev); 2239 pci_dev_put(p); 2240 } 2241 } 2242 } 2243 2244 static void amdgpu_init_debug_options(struct amdgpu_device *adev) 2245 { 2246 if (amdgpu_debug_mask & AMDGPU_DEBUG_VM) { 2247 pr_info("debug: VM handling debug enabled\n"); 2248 adev->debug_vm = true; 2249 } 2250 2251 if (amdgpu_debug_mask & AMDGPU_DEBUG_LARGEBAR) { 2252 pr_info("debug: enabled simulating large-bar capability on non-large bar system\n"); 2253 adev->debug_largebar = true; 2254 } 2255 2256 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY) { 2257 pr_info("debug: soft recovery disabled\n"); 2258 adev->debug_disable_soft_recovery = true; 2259 } 2260 2261 if (amdgpu_debug_mask & AMDGPU_DEBUG_USE_VRAM_FW_BUF) { 2262 pr_info("debug: place fw in vram for frontdoor loading\n"); 2263 adev->debug_use_vram_fw_buf = true; 2264 } 2265 2266 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_EXP_RESETS) { 2267 pr_info("debug: enable experimental reset features\n"); 2268 adev->debug_exp_resets = true; 2269 } 2270 2271 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_RING_RESET) { 2272 pr_info("debug: ring reset disabled\n"); 2273 adev->debug_disable_gpu_ring_reset = true; 2274 } 2275 if (amdgpu_debug_mask & AMDGPU_DEBUG_SMU_POOL) { 2276 pr_info("debug: use vram for smu pool\n"); 2277 adev->pm.smu_debug_mask |= SMU_DEBUG_POOL_USE_VRAM; 2278 } 2279 if (amdgpu_debug_mask & AMDGPU_DEBUG_VM_USERPTR) { 2280 pr_info("debug: VM mode debug for userptr is enabled\n"); 2281 adev->debug_vm_userptr = true; 2282 } 2283 2284 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_RAS_CE_LOG) { 2285 pr_info("debug: disable kernel logs of correctable errors\n"); 2286 adev->debug_disable_ce_logs = true; 2287 } 2288 2289 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_CE_CS) { 2290 pr_info("debug: allowing command submission to CE engine\n"); 2291 adev->debug_enable_ce_cs = true; 2292 } 2293 2294 if (amdgpu_debug_mask & AMDGPU_DEBUG_HIBERNATION_THAW_RESUME_GPU) { 2295 pr_info("debug: resume gpu in thaw() of hibernation\n"); 2296 adev->debug_hibernation_thaw_resume_gpu = true; 2297 } 2298 2299 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_IP_BLOCK_SOFT_RESET) { 2300 pr_info("debug: IP block soft reset disabled\n"); 2301 adev->debug_disable_ip_block_soft_reset = true; 2302 } 2303 } 2304 2305 static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long flags) 2306 { 2307 int i; 2308 2309 for (i = 0; i < ARRAY_SIZE(asic_type_quirks); i++) { 2310 if (pdev->device == asic_type_quirks[i].device && 2311 pdev->revision == asic_type_quirks[i].revision) { 2312 flags &= ~AMD_ASIC_MASK; 2313 flags |= asic_type_quirks[i].type; 2314 break; 2315 } 2316 } 2317 2318 return flags; 2319 } 2320 2321 static bool amdgpu_support_enabled(struct device *dev, 2322 const enum amd_asic_type family) 2323 { 2324 const char *gen; 2325 const char *param; 2326 int module_param = -1; 2327 bool radeon_support_built = IS_ENABLED(CONFIG_DRM_RADEON); 2328 bool amdgpu_support_built = false; 2329 bool support_by_default = false; 2330 2331 switch (family) { 2332 case CHIP_TAHITI: 2333 case CHIP_PITCAIRN: 2334 case CHIP_VERDE: 2335 case CHIP_OLAND: 2336 case CHIP_HAINAN: 2337 gen = "SI"; 2338 param = "si_support"; 2339 module_param = amdgpu_si_support; 2340 amdgpu_support_built = IS_ENABLED(CONFIG_DRM_AMDGPU_SI); 2341 support_by_default = true; 2342 break; 2343 2344 case CHIP_BONAIRE: 2345 case CHIP_HAWAII: 2346 case CHIP_KAVERI: 2347 case CHIP_KABINI: 2348 case CHIP_MULLINS: 2349 gen = "CIK"; 2350 param = "cik_support"; 2351 module_param = amdgpu_cik_support; 2352 amdgpu_support_built = IS_ENABLED(CONFIG_DRM_AMDGPU_CIK); 2353 support_by_default = true; 2354 break; 2355 2356 default: 2357 /* All other chips are supported by amdgpu only */ 2358 return true; 2359 } 2360 2361 if (!amdgpu_support_built) { 2362 dev_info(dev, "amdgpu built without %s support\n", gen); 2363 return false; 2364 } 2365 2366 if ((module_param == -1 && (support_by_default || !radeon_support_built)) || 2367 module_param == 1) { 2368 if (radeon_support_built) 2369 dev_info(dev, "%s support provided by amdgpu.\n" 2370 "Use radeon.%s=1 amdgpu.%s=0 to override.\n", 2371 gen, param, param); 2372 2373 return true; 2374 } 2375 2376 if (radeon_support_built) 2377 dev_info(dev, "%s support provided by radeon.\n" 2378 "Use radeon.%s=0 amdgpu.%s=1 to override.\n", 2379 gen, param, param); 2380 else if (module_param == 0) 2381 dev_info(dev, "%s support disabled by module param\n", gen); 2382 2383 return false; 2384 } 2385 2386 static int amdgpu_pci_probe(struct pci_dev *pdev, 2387 const struct pci_device_id *ent) 2388 { 2389 struct drm_device *ddev; 2390 struct amdgpu_device *adev; 2391 unsigned long flags = ent->driver_data; 2392 int ret, retry = 0, i; 2393 bool supports_atomic = false; 2394 2395 if ((pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA || 2396 (pdev->class >> 8) == PCI_CLASS_DISPLAY_OTHER) { 2397 if (drm_firmware_drivers_only() && amdgpu_modeset == -1) 2398 return -EINVAL; 2399 } 2400 2401 /* skip devices which are owned by radeon */ 2402 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2403 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2404 return -ENODEV; 2405 } 2406 2407 if (amdgpu_virtual_display || 2408 amdgpu_device_asic_has_dc_support(pdev, flags & AMD_ASIC_MASK)) 2409 supports_atomic = true; 2410 2411 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2412 dev_info(&pdev->dev, "This hardware requires experimental hardware support.\n" 2413 "See modparam exp_hw_support\n"); 2414 return -ENODEV; 2415 } 2416 2417 flags = amdgpu_fix_asic_type(pdev, flags); 2418 2419 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2420 * however, SME requires an indirect IOMMU mapping because the encryption 2421 * bit is beyond the DMA mask of the chip. 2422 */ 2423 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2424 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2425 dev_info(&pdev->dev, 2426 "SME is not compatible with RAVEN\n"); 2427 return -ENOTSUPP; 2428 } 2429 2430 if (!amdgpu_support_enabled(&pdev->dev, flags & AMD_ASIC_MASK)) 2431 return -ENODEV; 2432 2433 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2434 if (IS_ERR(adev)) 2435 return PTR_ERR(adev); 2436 2437 adev->dev = &pdev->dev; 2438 adev->pdev = pdev; 2439 ddev = adev_to_drm(adev); 2440 2441 if (!supports_atomic) 2442 ddev->driver_features &= ~DRIVER_ATOMIC; 2443 2444 ret = pci_enable_device(pdev); 2445 if (ret) 2446 return ret; 2447 2448 pci_set_drvdata(pdev, ddev); 2449 2450 amdgpu_init_debug_options(adev); 2451 2452 ret = amdgpu_driver_load_kms(adev, flags); 2453 if (ret) 2454 goto err_pci; 2455 2456 retry_init: 2457 ret = drm_dev_register(ddev, flags); 2458 if (ret == -EAGAIN && ++retry <= 3) { 2459 drm_info(adev_to_drm(adev), "retry init %d\n", retry); 2460 /* Don't request EX mode too frequently which is attacking */ 2461 msleep(5000); 2462 goto retry_init; 2463 } else if (ret) { 2464 goto err_pci; 2465 } 2466 2467 ret = amdgpu_xcp_dev_register(adev, ent); 2468 if (ret) 2469 goto err_pci; 2470 2471 ret = amdgpu_amdkfd_drm_client_create(adev); 2472 if (ret) 2473 goto err_pci; 2474 2475 /* 2476 * 1. don't init fbdev on hw without DCE 2477 * 2. don't init fbdev if there are no connectors 2478 */ 2479 if (adev->mode_info.mode_config_initialized && 2480 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2481 const struct drm_format_info *format; 2482 2483 /* select 8 bpp console on low vram cards */ 2484 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2485 format = drm_format_info(DRM_FORMAT_C8); 2486 else 2487 format = NULL; 2488 2489 drm_client_setup(adev_to_drm(adev), format); 2490 } 2491 2492 ret = amdgpu_debugfs_init(adev); 2493 if (ret) 2494 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2495 2496 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2497 /* only need to skip on ATPX */ 2498 if (amdgpu_device_supports_px(adev)) 2499 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2500 /* we want direct complete for BOCO */ 2501 if (amdgpu_device_supports_boco(adev)) 2502 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2503 DPM_FLAG_SMART_SUSPEND | 2504 DPM_FLAG_MAY_SKIP_RESUME); 2505 pm_runtime_use_autosuspend(ddev->dev); 2506 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2507 2508 pm_runtime_allow(ddev->dev); 2509 2510 pm_runtime_put_autosuspend(ddev->dev); 2511 2512 pci_wake_from_d3(pdev, TRUE); 2513 2514 /* 2515 * For runpm implemented via BACO, PMFW will handle the 2516 * timing for BACO in and out: 2517 * - put ASIC into BACO state only when both video and 2518 * audio functions are in D3 state. 2519 * - pull ASIC out of BACO state when either video or 2520 * audio function is in D0 state. 2521 * Also, at startup, PMFW assumes both functions are in 2522 * D0 state. 2523 * 2524 * So if snd driver was loaded prior to amdgpu driver 2525 * and audio function was put into D3 state, there will 2526 * be no PMFW-aware D-state transition(D0->D3) on runpm 2527 * suspend. Thus the BACO will be not correctly kicked in. 2528 * 2529 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2530 * into D0 state. Then there will be a PMFW-aware D-state 2531 * transition(D0->D3) on runpm suspend. 2532 */ 2533 if (amdgpu_device_supports_baco(adev) && 2534 !(adev->flags & AMD_IS_APU) && 2535 adev->asic_type >= CHIP_NAVI10) 2536 amdgpu_get_secondary_funcs(adev); 2537 } 2538 2539 return 0; 2540 2541 err_pci: 2542 pci_disable_device(pdev); 2543 return ret; 2544 } 2545 2546 static void 2547 amdgpu_pci_remove(struct pci_dev *pdev) 2548 { 2549 struct drm_device *dev = pci_get_drvdata(pdev); 2550 struct amdgpu_device *adev = drm_to_adev(dev); 2551 2552 amdgpu_ras_eeprom_check_and_recover(adev); 2553 amdgpu_xcp_dev_unplug(adev); 2554 amdgpu_gmc_prepare_nps_mode_change(adev); 2555 drm_dev_unplug(dev); 2556 2557 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2558 pm_runtime_get_sync(dev->dev); 2559 pm_runtime_forbid(dev->dev); 2560 } 2561 2562 amdgpu_driver_unload_kms(dev); 2563 2564 amdgpu_discovery_sysfs_early_fini(pdev); 2565 2566 /* 2567 * Flush any in flight DMA operations from device. 2568 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2569 * StatusTransactions Pending bit. 2570 */ 2571 pci_disable_device(pdev); 2572 pci_wait_for_pending_transaction(pdev); 2573 } 2574 2575 static void 2576 amdgpu_pci_shutdown(struct pci_dev *pdev) 2577 { 2578 struct drm_device *dev = pci_get_drvdata(pdev); 2579 struct amdgpu_device *adev = drm_to_adev(dev); 2580 2581 if (amdgpu_ras_intr_triggered()) 2582 return; 2583 2584 /* device maybe not resumed here, return immediately in this case */ 2585 if (adev->in_s4 && adev->in_suspend) 2586 return; 2587 2588 /* if we are running in a VM, make sure the device 2589 * torn down properly on reboot/shutdown. 2590 * unfortunately we can't detect certain 2591 * hypervisors so just do this all the time. 2592 */ 2593 if (!amdgpu_passthrough(adev)) 2594 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2595 amdgpu_device_prepare(dev); 2596 amdgpu_device_suspend(dev, true); 2597 adev->mp1_state = PP_MP1_STATE_NONE; 2598 } 2599 2600 static int amdgpu_pmops_prepare(struct device *dev) 2601 { 2602 struct drm_device *drm_dev = dev_get_drvdata(dev); 2603 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2604 2605 /* device maybe not resumed here, return immediately in this case */ 2606 if (adev->in_s4 && adev->in_suspend) 2607 return 0; 2608 2609 /* Return a positive number here so 2610 * DPM_FLAG_SMART_SUSPEND works properly 2611 */ 2612 if (amdgpu_device_supports_boco(adev) && pm_runtime_suspended(dev)) 2613 return 1; 2614 2615 /* if we will not support s3 or s2i for the device 2616 * then skip suspend 2617 */ 2618 if (!amdgpu_acpi_is_s0ix_active(adev) && 2619 !amdgpu_acpi_is_s3_active(adev)) 2620 return 1; 2621 2622 return amdgpu_device_prepare(drm_dev); 2623 } 2624 2625 static void amdgpu_pmops_complete(struct device *dev) 2626 { 2627 amdgpu_device_complete(dev_get_drvdata(dev)); 2628 } 2629 2630 static int amdgpu_pmops_suspend(struct device *dev) 2631 { 2632 struct drm_device *drm_dev = dev_get_drvdata(dev); 2633 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2634 2635 if (amdgpu_acpi_is_s0ix_active(adev)) 2636 adev->in_s0ix = true; 2637 else if (amdgpu_acpi_is_s3_active(adev)) 2638 adev->in_s3 = true; 2639 if (!adev->in_s0ix && !adev->in_s3) { 2640 #if IS_ENABLED(CONFIG_SUSPEND) 2641 /* don't allow going deep first time followed by s2idle the next time */ 2642 if (adev->last_suspend_state != PM_SUSPEND_ON && 2643 adev->last_suspend_state != pm_suspend_target_state) { 2644 drm_err_once(drm_dev, "Unsupported suspend state %d\n", 2645 pm_suspend_target_state); 2646 return -EINVAL; 2647 } 2648 #endif 2649 return 0; 2650 } 2651 2652 #if IS_ENABLED(CONFIG_SUSPEND) 2653 /* cache the state last used for suspend */ 2654 adev->last_suspend_state = pm_suspend_target_state; 2655 #endif 2656 2657 return amdgpu_device_suspend(drm_dev, true); 2658 } 2659 2660 static int amdgpu_pmops_suspend_noirq(struct device *dev) 2661 { 2662 struct drm_device *drm_dev = dev_get_drvdata(dev); 2663 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2664 int r; 2665 2666 if (amdgpu_acpi_should_gpu_reset(adev)) { 2667 amdgpu_device_lock_reset_domain(adev->reset_domain); 2668 r = amdgpu_asic_reset(adev); 2669 amdgpu_device_unlock_reset_domain(adev->reset_domain); 2670 return r; 2671 } 2672 2673 return 0; 2674 } 2675 2676 static int amdgpu_pmops_resume(struct device *dev) 2677 { 2678 struct drm_device *drm_dev = dev_get_drvdata(dev); 2679 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2680 int r; 2681 2682 if (!adev->in_s0ix && !adev->in_s3) 2683 return 0; 2684 2685 /* Avoids registers access if device is physically gone */ 2686 if (!pci_device_is_present(adev->pdev)) 2687 adev->no_hw_access = true; 2688 2689 r = amdgpu_device_resume(drm_dev, true); 2690 if (amdgpu_acpi_is_s0ix_active(adev)) 2691 adev->in_s0ix = false; 2692 else 2693 adev->in_s3 = false; 2694 return r; 2695 } 2696 2697 static int amdgpu_pmops_freeze(struct device *dev) 2698 { 2699 struct drm_device *drm_dev = dev_get_drvdata(dev); 2700 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2701 int r; 2702 2703 r = amdgpu_device_suspend(drm_dev, true); 2704 if (r) 2705 return r; 2706 2707 if (amdgpu_acpi_should_gpu_reset(adev)) { 2708 amdgpu_device_lock_reset_domain(adev->reset_domain); 2709 r = amdgpu_asic_reset(adev); 2710 amdgpu_device_unlock_reset_domain(adev->reset_domain); 2711 return r; 2712 } 2713 return 0; 2714 } 2715 2716 static int amdgpu_pmops_thaw(struct device *dev) 2717 { 2718 struct drm_device *drm_dev = dev_get_drvdata(dev); 2719 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2720 2721 /* do not resume device if it's normal hibernation */ 2722 if (!adev->debug_hibernation_thaw_resume_gpu && 2723 !pm_hibernate_is_recovering() && 2724 !pm_hibernation_mode_is_suspend()) 2725 return 0; 2726 2727 return amdgpu_device_resume(drm_dev, true); 2728 } 2729 2730 static int amdgpu_pmops_poweroff(struct device *dev) 2731 { 2732 struct drm_device *drm_dev = dev_get_drvdata(dev); 2733 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2734 2735 /* device maybe not resumed here, return immediately in this case */ 2736 if (adev->in_s4 && adev->in_suspend) 2737 return 0; 2738 2739 return amdgpu_device_suspend(drm_dev, true); 2740 } 2741 2742 static int amdgpu_pmops_restore(struct device *dev) 2743 { 2744 struct drm_device *drm_dev = dev_get_drvdata(dev); 2745 2746 return amdgpu_device_resume(drm_dev, true); 2747 } 2748 2749 static int amdgpu_runtime_idle_check_display(struct device *dev) 2750 { 2751 struct pci_dev *pdev = to_pci_dev(dev); 2752 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2753 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2754 2755 if (adev->mode_info.num_crtc) { 2756 struct drm_connector *list_connector; 2757 struct drm_connector_list_iter iter; 2758 int ret = 0; 2759 2760 if (amdgpu_runtime_pm != -2) { 2761 /* XXX: Return busy if any displays are connected to avoid 2762 * possible display wakeups after runtime resume due to 2763 * hotplug events in case any displays were connected while 2764 * the GPU was in suspend. Remove this once that is fixed. 2765 */ 2766 mutex_lock(&drm_dev->mode_config.mutex); 2767 drm_connector_list_iter_begin(drm_dev, &iter); 2768 drm_for_each_connector_iter(list_connector, &iter) { 2769 if (list_connector->status == connector_status_connected) { 2770 ret = -EBUSY; 2771 break; 2772 } 2773 } 2774 drm_connector_list_iter_end(&iter); 2775 mutex_unlock(&drm_dev->mode_config.mutex); 2776 2777 if (ret) 2778 return ret; 2779 } 2780 2781 if (adev->dc_enabled) { 2782 struct drm_crtc *crtc; 2783 2784 drm_for_each_crtc(crtc, drm_dev) { 2785 drm_modeset_lock(&crtc->mutex, NULL); 2786 if (crtc->state->active) 2787 ret = -EBUSY; 2788 drm_modeset_unlock(&crtc->mutex); 2789 if (ret < 0) 2790 break; 2791 } 2792 } else { 2793 mutex_lock(&drm_dev->mode_config.mutex); 2794 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2795 2796 drm_connector_list_iter_begin(drm_dev, &iter); 2797 drm_for_each_connector_iter(list_connector, &iter) { 2798 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2799 ret = -EBUSY; 2800 break; 2801 } 2802 } 2803 2804 drm_connector_list_iter_end(&iter); 2805 2806 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2807 mutex_unlock(&drm_dev->mode_config.mutex); 2808 } 2809 if (ret) 2810 return ret; 2811 } 2812 2813 return 0; 2814 } 2815 2816 static int amdgpu_runtime_idle_check_userq(struct device *dev) 2817 { 2818 struct pci_dev *pdev = to_pci_dev(dev); 2819 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2820 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2821 2822 return xa_empty(&adev->userq_doorbell_xa) ? 0 : -EBUSY; 2823 } 2824 2825 static int amdgpu_pmops_runtime_checks(struct device *dev) 2826 { 2827 struct drm_device *drm_dev = dev_get_drvdata(dev); 2828 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2829 int ret; 2830 2831 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2832 pm_runtime_forbid(dev); 2833 return -EBUSY; 2834 } 2835 2836 ret = amdgpu_runtime_idle_check_display(dev); 2837 if (ret) 2838 return ret; 2839 2840 return amdgpu_runtime_idle_check_userq(dev); 2841 } 2842 2843 static int amdgpu_pmops_runtime_idle(struct device *dev) 2844 { 2845 int ret; 2846 2847 ret = amdgpu_pmops_runtime_checks(dev); 2848 pm_runtime_autosuspend(dev); 2849 return ret; 2850 } 2851 2852 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2853 { 2854 struct pci_dev *pdev = to_pci_dev(dev); 2855 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2856 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2857 int ret, i; 2858 2859 ret = amdgpu_pmops_runtime_checks(dev); 2860 if (ret) 2861 return ret; 2862 2863 /* wait for all rings to drain before suspending */ 2864 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2865 struct amdgpu_ring *ring = adev->rings[i]; 2866 2867 if (ring && ring->sched.ready) { 2868 ret = amdgpu_fence_wait_empty(ring); 2869 if (ret) 2870 return -EBUSY; 2871 } 2872 } 2873 2874 adev->in_runpm = true; 2875 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2876 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2877 2878 /* 2879 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2880 * proper cleanups and put itself into a state ready for PNP. That 2881 * can address some random resuming failure observed on BOCO capable 2882 * platforms. 2883 * TODO: this may be also needed for PX capable platform. 2884 */ 2885 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2886 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2887 2888 ret = amdgpu_device_prepare(drm_dev); 2889 if (ret) 2890 return ret; 2891 ret = amdgpu_device_suspend(drm_dev, false); 2892 if (ret) { 2893 adev->in_runpm = false; 2894 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2895 adev->mp1_state = PP_MP1_STATE_NONE; 2896 return ret; 2897 } 2898 2899 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2900 adev->mp1_state = PP_MP1_STATE_NONE; 2901 2902 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) { 2903 /* Only need to handle PCI state in the driver for ATPX 2904 * PCI core handles it for _PR3. 2905 */ 2906 amdgpu_device_cache_pci_state(pdev); 2907 pci_disable_device(pdev); 2908 pci_ignore_hotplug(pdev); 2909 pci_set_power_state(pdev, PCI_D3cold); 2910 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2911 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) { 2912 /* nothing to do */ 2913 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2914 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) { 2915 amdgpu_device_baco_enter(adev); 2916 } 2917 2918 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n"); 2919 2920 return 0; 2921 } 2922 2923 static void amdgpu_restore_umd_profile_pstate_after_runpm(struct amdgpu_device *adev) 2924 { 2925 enum amd_dpm_forced_level level; 2926 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 2927 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 2928 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 2929 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 2930 2931 level = amdgpu_dpm_get_performance_level(adev); 2932 if (level & profile_mode_mask) 2933 amdgpu_asic_update_umd_stable_pstate(adev, true); 2934 } 2935 2936 static int amdgpu_pmops_runtime_resume(struct device *dev) 2937 { 2938 struct pci_dev *pdev = to_pci_dev(dev); 2939 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2940 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2941 int ret; 2942 2943 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) 2944 return -EINVAL; 2945 2946 /* Avoids registers access if device is physically gone */ 2947 if (!pci_device_is_present(adev->pdev)) 2948 adev->no_hw_access = true; 2949 2950 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) { 2951 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2952 2953 /* Only need to handle PCI state in the driver for ATPX 2954 * PCI core handles it for _PR3. 2955 */ 2956 pci_set_power_state(pdev, PCI_D0); 2957 amdgpu_device_load_pci_state(pdev); 2958 ret = pci_enable_device(pdev); 2959 if (ret) 2960 return ret; 2961 pci_set_master(pdev); 2962 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) { 2963 /* Only need to handle PCI state in the driver for ATPX 2964 * PCI core handles it for _PR3. 2965 */ 2966 pci_set_master(pdev); 2967 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2968 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) { 2969 amdgpu_device_baco_exit(adev); 2970 } 2971 ret = amdgpu_device_resume(drm_dev, false); 2972 if (ret) { 2973 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2974 pci_disable_device(pdev); 2975 return ret; 2976 } 2977 2978 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2979 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2980 2981 amdgpu_restore_umd_profile_pstate_after_runpm(adev); 2982 adev->in_runpm = false; 2983 return 0; 2984 } 2985 2986 static int amdgpu_drm_release(struct inode *inode, struct file *filp) 2987 { 2988 struct drm_file *file_priv = filp->private_data; 2989 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2990 struct drm_device *dev = file_priv->minor->dev; 2991 int idx; 2992 2993 if (fpriv && drm_dev_enter(dev, &idx)) { 2994 amdgpu_evf_mgr_shutdown(&fpriv->evf_mgr); 2995 amdgpu_userq_mgr_cancel_resume(&fpriv->userq_mgr); 2996 amdgpu_evf_mgr_flush_suspend(&fpriv->evf_mgr); 2997 amdgpu_userq_mgr_fini(&fpriv->userq_mgr); 2998 amdgpu_evf_mgr_fini(&fpriv->evf_mgr); 2999 drm_dev_exit(idx); 3000 } 3001 3002 return drm_release(inode, filp); 3003 } 3004 3005 long amdgpu_drm_ioctl(struct file *filp, 3006 unsigned int cmd, unsigned long arg) 3007 { 3008 struct drm_file *file_priv = filp->private_data; 3009 struct drm_device *dev; 3010 long ret; 3011 3012 dev = file_priv->minor->dev; 3013 ret = pm_runtime_get_sync(dev->dev); 3014 if (ret < 0) 3015 goto out; 3016 3017 ret = drm_ioctl(filp, cmd, arg); 3018 3019 out: 3020 pm_runtime_put_autosuspend(dev->dev); 3021 return ret; 3022 } 3023 3024 static const struct dev_pm_ops amdgpu_pm_ops = { 3025 .prepare = pm_sleep_ptr(amdgpu_pmops_prepare), 3026 .complete = pm_sleep_ptr(amdgpu_pmops_complete), 3027 .suspend = pm_sleep_ptr(amdgpu_pmops_suspend), 3028 .suspend_noirq = pm_sleep_ptr(amdgpu_pmops_suspend_noirq), 3029 .resume = pm_sleep_ptr(amdgpu_pmops_resume), 3030 .freeze = pm_sleep_ptr(amdgpu_pmops_freeze), 3031 .thaw = pm_sleep_ptr(amdgpu_pmops_thaw), 3032 .poweroff = pm_sleep_ptr(amdgpu_pmops_poweroff), 3033 .restore = pm_sleep_ptr(amdgpu_pmops_restore), 3034 .runtime_suspend = amdgpu_pmops_runtime_suspend, 3035 .runtime_resume = amdgpu_pmops_runtime_resume, 3036 .runtime_idle = amdgpu_pmops_runtime_idle, 3037 }; 3038 3039 static int amdgpu_flush(struct file *f, fl_owner_t id) 3040 { 3041 struct drm_file *file_priv = f->private_data; 3042 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 3043 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 3044 3045 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 3046 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 3047 3048 return timeout >= 0 ? 0 : timeout; 3049 } 3050 3051 static const struct file_operations amdgpu_driver_kms_fops = { 3052 .owner = THIS_MODULE, 3053 .open = drm_open, 3054 .flush = amdgpu_flush, 3055 .release = amdgpu_drm_release, 3056 .unlocked_ioctl = amdgpu_drm_ioctl, 3057 .mmap = drm_gem_mmap, 3058 .poll = drm_poll, 3059 .read = drm_read, 3060 #ifdef CONFIG_COMPAT 3061 .compat_ioctl = amdgpu_kms_compat_ioctl, 3062 #endif 3063 #ifdef CONFIG_PROC_FS 3064 .show_fdinfo = drm_show_fdinfo, 3065 #endif 3066 .fop_flags = FOP_UNSIGNED_OFFSET, 3067 }; 3068 3069 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 3070 { 3071 struct drm_file *file; 3072 3073 if (!filp) 3074 return -EINVAL; 3075 3076 if (filp->f_op != &amdgpu_driver_kms_fops) 3077 return -EINVAL; 3078 3079 file = filp->private_data; 3080 *fpriv = file->driver_priv; 3081 return 0; 3082 } 3083 3084 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 3085 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3086 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3087 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3088 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 3089 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3090 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3091 /* KMS */ 3092 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3093 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3094 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3095 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3096 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3097 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3098 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3099 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3100 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3101 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3102 DRM_IOCTL_DEF_DRV(AMDGPU_USERQ, amdgpu_userq_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3103 DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_SIGNAL, amdgpu_userq_signal_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3104 DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_WAIT, amdgpu_userq_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3105 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_LIST_HANDLES, amdgpu_gem_list_handles_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3106 DRM_IOCTL_DEF_DRV(AMDGPU_PROC_OPTIONS, amdgpu_proc_options_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3107 }; 3108 3109 static const struct drm_driver amdgpu_kms_driver = { 3110 .driver_features = 3111 DRIVER_ATOMIC | 3112 DRIVER_GEM | 3113 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 3114 DRIVER_SYNCOBJ_TIMELINE, 3115 .open = amdgpu_driver_open_kms, 3116 .postclose = amdgpu_driver_postclose_kms, 3117 .ioctls = amdgpu_ioctls_kms, 3118 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 3119 .dumb_create = amdgpu_mode_dumb_create, 3120 .dumb_map_offset = amdgpu_mode_dumb_mmap, 3121 DRM_FBDEV_TTM_DRIVER_OPS, 3122 .fops = &amdgpu_driver_kms_fops, 3123 .release = &amdgpu_driver_release_kms, 3124 #ifdef CONFIG_PROC_FS 3125 .show_fdinfo = amdgpu_show_fdinfo, 3126 #endif 3127 3128 .gem_prime_import = amdgpu_gem_prime_import, 3129 3130 .name = DRIVER_NAME, 3131 .desc = DRIVER_DESC, 3132 .major = KMS_DRIVER_MAJOR, 3133 .minor = KMS_DRIVER_MINOR, 3134 .patchlevel = KMS_DRIVER_PATCHLEVEL, 3135 }; 3136 3137 const struct drm_driver amdgpu_partition_driver = { 3138 .driver_features = 3139 DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ | 3140 DRIVER_SYNCOBJ_TIMELINE, 3141 .open = amdgpu_driver_open_kms, 3142 .postclose = amdgpu_driver_postclose_kms, 3143 .ioctls = amdgpu_ioctls_kms, 3144 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 3145 .dumb_create = amdgpu_mode_dumb_create, 3146 .dumb_map_offset = amdgpu_mode_dumb_mmap, 3147 DRM_FBDEV_TTM_DRIVER_OPS, 3148 .fops = &amdgpu_driver_kms_fops, 3149 .release = &amdgpu_driver_release_kms, 3150 3151 .gem_prime_import = amdgpu_gem_prime_import, 3152 3153 .name = DRIVER_NAME, 3154 .desc = DRIVER_DESC, 3155 .major = KMS_DRIVER_MAJOR, 3156 .minor = KMS_DRIVER_MINOR, 3157 .patchlevel = KMS_DRIVER_PATCHLEVEL, 3158 }; 3159 3160 static struct pci_error_handlers amdgpu_pci_err_handler = { 3161 .error_detected = amdgpu_pci_error_detected, 3162 .mmio_enabled = amdgpu_pci_mmio_enabled, 3163 .slot_reset = amdgpu_pci_slot_reset, 3164 .resume = amdgpu_pci_resume, 3165 }; 3166 3167 static const struct attribute_group *amdgpu_sysfs_groups[] = { 3168 &amdgpu_vram_mgr_attr_group, 3169 &amdgpu_gtt_mgr_attr_group, 3170 &amdgpu_flash_attr_group, 3171 NULL, 3172 }; 3173 3174 static struct pci_driver amdgpu_kms_pci_driver = { 3175 .name = DRIVER_NAME, 3176 .id_table = pciidlist, 3177 .probe = amdgpu_pci_probe, 3178 .remove = amdgpu_pci_remove, 3179 .shutdown = amdgpu_pci_shutdown, 3180 .driver.pm = pm_ptr(&amdgpu_pm_ops), 3181 .err_handler = &amdgpu_pci_err_handler, 3182 .dev_groups = amdgpu_sysfs_groups, 3183 }; 3184 3185 static int __init amdgpu_init(void) 3186 { 3187 int r; 3188 3189 /* Train lockdep on correct lock ordering */ 3190 amdgpu_lockdep_init(); 3191 3192 r = amdgpu_sync_init(); 3193 if (r) 3194 return r; 3195 3196 amdgpu_register_atpx_handler(); 3197 amdgpu_acpi_detect(); 3198 3199 /* Ignore KFD init failures when CONFIG_HSA_AMD is not set. */ 3200 r = amdgpu_amdkfd_init(); 3201 if (r && r != -ENOENT) 3202 goto error_fini_sync; 3203 3204 if (amdgpu_pp_feature_mask & PP_OVERDRIVE_MASK) { 3205 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 3206 pr_crit("Overdrive is enabled, please disable it before " 3207 "reporting any bugs unrelated to overdrive.\n"); 3208 } 3209 3210 /* let modprobe override vga console setting */ 3211 return pci_register_driver(&amdgpu_kms_pci_driver); 3212 3213 error_fini_sync: 3214 amdgpu_sync_fini(); 3215 return r; 3216 } 3217 3218 static void __exit amdgpu_exit(void) 3219 { 3220 amdgpu_amdkfd_fini(); 3221 pci_unregister_driver(&amdgpu_kms_pci_driver); 3222 amdgpu_unregister_atpx_handler(); 3223 amdgpu_acpi_release(); 3224 amdgpu_sync_fini(); 3225 mmu_notifier_synchronize(); 3226 amdgpu_xcp_drv_release(); 3227 3228 /* 3229 * Flush outstanding call_rcu() callbacks before the 3230 * module text is freed. Otherwise a grace period elapsing after 3231 * unload invokes a callback in already-freed module memory and 3232 * faults in rcu_do_batch(). 3233 */ 3234 rcu_barrier(); 3235 } 3236 3237 module_init(amdgpu_init); 3238 module_exit(amdgpu_exit); 3239 3240 MODULE_AUTHOR(DRIVER_AUTHOR); 3241 MODULE_DESCRIPTION(DRIVER_DESC); 3242 MODULE_LICENSE("GPL and additional rights"); 3243