1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_drv.h> 27 #include <drm/drm_fbdev_generic.h> 28 #include <drm/drm_gem.h> 29 #include <drm/drm_managed.h> 30 #include <drm/drm_pciids.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/drm_vblank.h> 33 34 #include <linux/cc_platform.h> 35 #include <linux/dynamic_debug.h> 36 #include <linux/module.h> 37 #include <linux/mmu_notifier.h> 38 #include <linux/pm_runtime.h> 39 #include <linux/suspend.h> 40 #include <linux/vga_switcheroo.h> 41 42 #include "amdgpu.h" 43 #include "amdgpu_amdkfd.h" 44 #include "amdgpu_dma_buf.h" 45 #include "amdgpu_drv.h" 46 #include "amdgpu_fdinfo.h" 47 #include "amdgpu_irq.h" 48 #include "amdgpu_psp.h" 49 #include "amdgpu_ras.h" 50 #include "amdgpu_reset.h" 51 #include "amdgpu_sched.h" 52 #include "amdgpu_xgmi.h" 53 #include "../amdxcp/amdgpu_xcp_drv.h" 54 55 /* 56 * KMS wrapper. 57 * - 3.0.0 - initial driver 58 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 59 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 60 * at the end of IBs. 61 * - 3.3.0 - Add VM support for UVD on supported hardware. 62 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 63 * - 3.5.0 - Add support for new UVD_NO_OP register. 64 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 65 * - 3.7.0 - Add support for VCE clock list packet 66 * - 3.8.0 - Add support raster config init in the kernel 67 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 68 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 69 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 70 * - 3.12.0 - Add query for double offchip LDS buffers 71 * - 3.13.0 - Add PRT support 72 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 73 * - 3.15.0 - Export more gpu info for gfx9 74 * - 3.16.0 - Add reserved vmid support 75 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 76 * - 3.18.0 - Export gpu always on cu bitmap 77 * - 3.19.0 - Add support for UVD MJPEG decode 78 * - 3.20.0 - Add support for local BOs 79 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 80 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 81 * - 3.23.0 - Add query for VRAM lost counter 82 * - 3.24.0 - Add high priority compute support for gfx9 83 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 84 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 85 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation. 86 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 87 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 88 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 89 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 90 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 91 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 92 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 93 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 94 * - 3.36.0 - Allow reading more status registers on si/cik 95 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 96 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 97 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 98 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 99 * - 3.41.0 - Add video codec query 100 * - 3.42.0 - Add 16bpc fixed point display support 101 * - 3.43.0 - Add device hot plug/unplug support 102 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 103 * - 3.45.0 - Add context ioctl stable pstate interface 104 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm 105 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags 106 * - 3.48.0 - Add IP discovery version info to HW INFO 107 * - 3.49.0 - Add gang submit into CS IOCTL 108 * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock 109 * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock 110 * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl 111 * 3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields: 112 * tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size, 113 * gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi 114 * 3.53.0 - Support for GFX11 CP GFX shadowing 115 * 3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support 116 * - 3.55.0 - Add AMDGPU_INFO_GPUVM_FAULT query 117 * - 3.56.0 - Update IB start address and size alignment for decode and encode 118 */ 119 #define KMS_DRIVER_MAJOR 3 120 #define KMS_DRIVER_MINOR 56 121 #define KMS_DRIVER_PATCHLEVEL 0 122 123 /* 124 * amdgpu.debug module options. Are all disabled by default 125 */ 126 enum AMDGPU_DEBUG_MASK { 127 AMDGPU_DEBUG_VM = BIT(0), 128 AMDGPU_DEBUG_LARGEBAR = BIT(1), 129 AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY = BIT(2), 130 }; 131 132 unsigned int amdgpu_vram_limit = UINT_MAX; 133 int amdgpu_vis_vram_limit; 134 int amdgpu_gart_size = -1; /* auto */ 135 int amdgpu_gtt_size = -1; /* auto */ 136 int amdgpu_moverate = -1; /* auto */ 137 int amdgpu_audio = -1; 138 int amdgpu_disp_priority; 139 int amdgpu_hw_i2c; 140 int amdgpu_pcie_gen2 = -1; 141 int amdgpu_msi = -1; 142 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 143 int amdgpu_dpm = -1; 144 int amdgpu_fw_load_type = -1; 145 int amdgpu_aspm = -1; 146 int amdgpu_runtime_pm = -1; 147 uint amdgpu_ip_block_mask = 0xffffffff; 148 int amdgpu_bapm = -1; 149 int amdgpu_deep_color; 150 int amdgpu_vm_size = -1; 151 int amdgpu_vm_fragment_size = -1; 152 int amdgpu_vm_block_size = -1; 153 int amdgpu_vm_fault_stop; 154 int amdgpu_vm_update_mode = -1; 155 int amdgpu_exp_hw_support; 156 int amdgpu_dc = -1; 157 int amdgpu_sched_jobs = 32; 158 int amdgpu_sched_hw_submission = 2; 159 uint amdgpu_pcie_gen_cap; 160 uint amdgpu_pcie_lane_cap; 161 u64 amdgpu_cg_mask = 0xffffffffffffffff; 162 uint amdgpu_pg_mask = 0xffffffff; 163 uint amdgpu_sdma_phase_quantum = 32; 164 char *amdgpu_disable_cu; 165 char *amdgpu_virtual_display; 166 bool enforce_isolation; 167 /* 168 * OverDrive(bit 14) disabled by default 169 * GFX DCS(bit 19) disabled by default 170 */ 171 uint amdgpu_pp_feature_mask = 0xfff7bfff; 172 uint amdgpu_force_long_training; 173 int amdgpu_lbpw = -1; 174 int amdgpu_compute_multipipe = -1; 175 int amdgpu_gpu_recovery = -1; /* auto */ 176 int amdgpu_emu_mode; 177 uint amdgpu_smu_memory_pool_size; 178 int amdgpu_smu_pptable_id = -1; 179 /* 180 * FBC (bit 0) disabled by default 181 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 182 * - With this, for multiple monitors in sync(e.g. with the same model), 183 * mclk switching will be allowed. And the mclk will be not foced to the 184 * highest. That helps saving some idle power. 185 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 186 * PSR (bit 3) disabled by default 187 * EDP NO POWER SEQUENCING (bit 4) disabled by default 188 */ 189 uint amdgpu_dc_feature_mask = 2; 190 uint amdgpu_dc_debug_mask; 191 uint amdgpu_dc_visual_confirm; 192 int amdgpu_async_gfx_ring = 1; 193 int amdgpu_mcbp = -1; 194 int amdgpu_discovery = -1; 195 int amdgpu_mes; 196 int amdgpu_mes_kiq; 197 int amdgpu_noretry = -1; 198 int amdgpu_force_asic_type = -1; 199 int amdgpu_tmz = -1; /* auto */ 200 int amdgpu_reset_method = -1; /* auto */ 201 int amdgpu_num_kcq = -1; 202 int amdgpu_smartshift_bias; 203 int amdgpu_use_xgmi_p2p = 1; 204 int amdgpu_vcnfw_log; 205 int amdgpu_sg_display = -1; /* auto */ 206 int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE; 207 int amdgpu_umsch_mm; 208 int amdgpu_seamless = -1; /* auto */ 209 uint amdgpu_debug_mask; 210 int amdgpu_agp = -1; /* auto */ 211 212 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 213 214 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 215 "DRM_UT_CORE", 216 "DRM_UT_DRIVER", 217 "DRM_UT_KMS", 218 "DRM_UT_PRIME", 219 "DRM_UT_ATOMIC", 220 "DRM_UT_VBL", 221 "DRM_UT_STATE", 222 "DRM_UT_LEASE", 223 "DRM_UT_DP", 224 "DRM_UT_DRMRES"); 225 226 struct amdgpu_mgpu_info mgpu_info = { 227 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 228 .delayed_reset_work = __DELAYED_WORK_INITIALIZER( 229 mgpu_info.delayed_reset_work, 230 amdgpu_drv_delayed_reset_work_handler, 0), 231 }; 232 int amdgpu_ras_enable = -1; 233 uint amdgpu_ras_mask = 0xffffffff; 234 int amdgpu_bad_page_threshold = -1; 235 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 236 .timeout_fatal_disable = false, 237 .period = 0x0, /* default to 0x0 (timeout disable) */ 238 }; 239 240 /** 241 * DOC: vramlimit (int) 242 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 243 */ 244 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 245 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 246 247 /** 248 * DOC: vis_vramlimit (int) 249 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 250 */ 251 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 252 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 253 254 /** 255 * DOC: gartsize (uint) 256 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing. 257 * The default is -1 (The size depends on asic). 258 */ 259 MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)"); 260 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 261 262 /** 263 * DOC: gttsize (int) 264 * Restrict the size of GTT domain (for userspace use) in MiB for testing. 265 * The default is -1 (Use 1/2 RAM, minimum value is 3GB). 266 */ 267 MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)"); 268 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 269 270 /** 271 * DOC: moverate (int) 272 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 273 */ 274 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 275 module_param_named(moverate, amdgpu_moverate, int, 0600); 276 277 /** 278 * DOC: audio (int) 279 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 280 */ 281 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 282 module_param_named(audio, amdgpu_audio, int, 0444); 283 284 /** 285 * DOC: disp_priority (int) 286 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 287 */ 288 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 289 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 290 291 /** 292 * DOC: hw_i2c (int) 293 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 294 */ 295 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 296 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 297 298 /** 299 * DOC: pcie_gen2 (int) 300 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 301 */ 302 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 303 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 304 305 /** 306 * DOC: msi (int) 307 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 308 */ 309 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 310 module_param_named(msi, amdgpu_msi, int, 0444); 311 312 /** 313 * DOC: lockup_timeout (string) 314 * Set GPU scheduler timeout value in ms. 315 * 316 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 317 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 318 * to the default timeout. 319 * 320 * - With one value specified, the setting will apply to all non-compute jobs. 321 * - With multiple values specified, the first one will be for GFX. 322 * The second one is for Compute. The third and fourth ones are 323 * for SDMA and Video. 324 * 325 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 326 * jobs is 10000. The timeout for compute is 60000. 327 */ 328 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 329 "for passthrough or sriov, 10000 for all jobs. 0: keep default value. negative: infinity timeout), format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 330 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 331 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 332 333 /** 334 * DOC: dpm (int) 335 * Override for dynamic power management setting 336 * (0 = disable, 1 = enable) 337 * The default is -1 (auto). 338 */ 339 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 340 module_param_named(dpm, amdgpu_dpm, int, 0444); 341 342 /** 343 * DOC: fw_load_type (int) 344 * Set different firmware loading type for debugging, if supported. 345 * Set to 0 to force direct loading if supported by the ASIC. Set 346 * to -1 to select the default loading mode for the ASIC, as defined 347 * by the driver. The default is -1 (auto). 348 */ 349 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); 350 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 351 352 /** 353 * DOC: aspm (int) 354 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 355 */ 356 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 357 module_param_named(aspm, amdgpu_aspm, int, 0444); 358 359 /** 360 * DOC: runpm (int) 361 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 362 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 363 * Setting the value to 0 disables this functionality. 364 * Setting the value to -2 is auto enabled with power down when displays are attached. 365 */ 366 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto, -2 = autowith displays)"); 367 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 368 369 /** 370 * DOC: ip_block_mask (uint) 371 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 372 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 373 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 374 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 375 */ 376 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 377 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 378 379 /** 380 * DOC: bapm (int) 381 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 382 * The default -1 (auto, enabled) 383 */ 384 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 385 module_param_named(bapm, amdgpu_bapm, int, 0444); 386 387 /** 388 * DOC: deep_color (int) 389 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 390 */ 391 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 392 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 393 394 /** 395 * DOC: vm_size (int) 396 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 397 */ 398 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 399 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 400 401 /** 402 * DOC: vm_fragment_size (int) 403 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 404 */ 405 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 406 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 407 408 /** 409 * DOC: vm_block_size (int) 410 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 411 */ 412 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 413 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 414 415 /** 416 * DOC: vm_fault_stop (int) 417 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 418 */ 419 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 420 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 421 422 /** 423 * DOC: vm_update_mode (int) 424 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 425 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 426 */ 427 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 428 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 429 430 /** 431 * DOC: exp_hw_support (int) 432 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 433 */ 434 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 435 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 436 437 /** 438 * DOC: dc (int) 439 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 440 */ 441 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 442 module_param_named(dc, amdgpu_dc, int, 0444); 443 444 /** 445 * DOC: sched_jobs (int) 446 * Override the max number of jobs supported in the sw queue. The default is 32. 447 */ 448 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 449 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 450 451 /** 452 * DOC: sched_hw_submission (int) 453 * Override the max number of HW submissions. The default is 2. 454 */ 455 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 456 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 457 458 /** 459 * DOC: ppfeaturemask (hexint) 460 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 461 * The default is the current set of stable power features. 462 */ 463 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 464 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 465 466 /** 467 * DOC: forcelongtraining (uint) 468 * Force long memory training in resume. 469 * The default is zero, indicates short training in resume. 470 */ 471 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 472 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 473 474 /** 475 * DOC: pcie_gen_cap (uint) 476 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 477 * The default is 0 (automatic for each asic). 478 */ 479 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 480 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 481 482 /** 483 * DOC: pcie_lane_cap (uint) 484 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 485 * The default is 0 (automatic for each asic). 486 */ 487 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 488 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 489 490 /** 491 * DOC: cg_mask (ullong) 492 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 493 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 494 */ 495 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 496 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 497 498 /** 499 * DOC: pg_mask (uint) 500 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 501 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 502 */ 503 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 504 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 505 506 /** 507 * DOC: sdma_phase_quantum (uint) 508 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 509 */ 510 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 511 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 512 513 /** 514 * DOC: disable_cu (charp) 515 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 516 */ 517 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 518 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 519 520 /** 521 * DOC: virtual_display (charp) 522 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 523 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 524 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 525 * device at 26:00.0. The default is NULL. 526 */ 527 MODULE_PARM_DESC(virtual_display, 528 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 529 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 530 531 /** 532 * DOC: lbpw (int) 533 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 534 */ 535 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 536 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 537 538 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 539 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 540 541 /** 542 * DOC: gpu_recovery (int) 543 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 544 */ 545 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 546 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 547 548 /** 549 * DOC: emu_mode (int) 550 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 551 */ 552 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 553 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 554 555 /** 556 * DOC: ras_enable (int) 557 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 558 */ 559 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 560 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 561 562 /** 563 * DOC: ras_mask (uint) 564 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 565 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 566 */ 567 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 568 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 569 570 /** 571 * DOC: timeout_fatal_disable (bool) 572 * Disable Watchdog timeout fatal error event 573 */ 574 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 575 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 576 577 /** 578 * DOC: timeout_period (uint) 579 * Modify the watchdog timeout max_cycles as (1 << period) 580 */ 581 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 582 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 583 584 /** 585 * DOC: si_support (int) 586 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 587 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 588 * otherwise using amdgpu driver. 589 */ 590 #ifdef CONFIG_DRM_AMDGPU_SI 591 592 #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) 593 int amdgpu_si_support = 0; 594 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 595 #else 596 int amdgpu_si_support = 1; 597 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 598 #endif 599 600 module_param_named(si_support, amdgpu_si_support, int, 0444); 601 #endif 602 603 /** 604 * DOC: cik_support (int) 605 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 606 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 607 * otherwise using amdgpu driver. 608 */ 609 #ifdef CONFIG_DRM_AMDGPU_CIK 610 611 #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) 612 int amdgpu_cik_support = 0; 613 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 614 #else 615 int amdgpu_cik_support = 1; 616 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 617 #endif 618 619 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 620 #endif 621 622 /** 623 * DOC: smu_memory_pool_size (uint) 624 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 625 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 626 */ 627 MODULE_PARM_DESC(smu_memory_pool_size, 628 "reserve gtt for smu debug usage, 0 = disable,0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 629 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 630 631 /** 632 * DOC: async_gfx_ring (int) 633 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 634 */ 635 MODULE_PARM_DESC(async_gfx_ring, 636 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 637 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 638 639 /** 640 * DOC: mcbp (int) 641 * It is used to enable mid command buffer preemption. (0 = disabled, 1 = enabled, -1 auto (default)) 642 */ 643 MODULE_PARM_DESC(mcbp, 644 "Enable Mid-command buffer preemption (0 = disabled, 1 = enabled), -1 = auto (default)"); 645 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 646 647 /** 648 * DOC: discovery (int) 649 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 650 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 651 */ 652 MODULE_PARM_DESC(discovery, 653 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 654 module_param_named(discovery, amdgpu_discovery, int, 0444); 655 656 /** 657 * DOC: mes (int) 658 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 659 * (0 = disabled (default), 1 = enabled) 660 */ 661 MODULE_PARM_DESC(mes, 662 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 663 module_param_named(mes, amdgpu_mes, int, 0444); 664 665 /** 666 * DOC: mes_kiq (int) 667 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq. 668 * (0 = disabled (default), 1 = enabled) 669 */ 670 MODULE_PARM_DESC(mes_kiq, 671 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)"); 672 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444); 673 674 /** 675 * DOC: noretry (int) 676 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 677 * do not support per-process XNACK this also disables retry page faults. 678 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 679 */ 680 MODULE_PARM_DESC(noretry, 681 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 682 module_param_named(noretry, amdgpu_noretry, int, 0644); 683 684 /** 685 * DOC: force_asic_type (int) 686 * A non negative value used to specify the asic type for all supported GPUs. 687 */ 688 MODULE_PARM_DESC(force_asic_type, 689 "A non negative value used to specify the asic type for all supported GPUs"); 690 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 691 692 /** 693 * DOC: use_xgmi_p2p (int) 694 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 695 */ 696 MODULE_PARM_DESC(use_xgmi_p2p, 697 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 698 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 699 700 701 #ifdef CONFIG_HSA_AMD 702 /** 703 * DOC: sched_policy (int) 704 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 705 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 706 * assigns queues to HQDs. 707 */ 708 int sched_policy = KFD_SCHED_POLICY_HWS; 709 module_param(sched_policy, int, 0444); 710 MODULE_PARM_DESC(sched_policy, 711 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 712 713 /** 714 * DOC: hws_max_conc_proc (int) 715 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 716 * number of VMIDs assigned to the HWS, which is also the default. 717 */ 718 int hws_max_conc_proc = -1; 719 module_param(hws_max_conc_proc, int, 0444); 720 MODULE_PARM_DESC(hws_max_conc_proc, 721 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 722 723 /** 724 * DOC: cwsr_enable (int) 725 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 726 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 727 * disables it. 728 */ 729 int cwsr_enable = 1; 730 module_param(cwsr_enable, int, 0444); 731 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 732 733 /** 734 * DOC: max_num_of_queues_per_device (int) 735 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 736 * is 4096. 737 */ 738 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 739 module_param(max_num_of_queues_per_device, int, 0444); 740 MODULE_PARM_DESC(max_num_of_queues_per_device, 741 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 742 743 /** 744 * DOC: send_sigterm (int) 745 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 746 * but just print errors on dmesg. Setting 1 enables sending sigterm. 747 */ 748 int send_sigterm; 749 module_param(send_sigterm, int, 0444); 750 MODULE_PARM_DESC(send_sigterm, 751 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 752 753 /** 754 * DOC: halt_if_hws_hang (int) 755 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 756 * Setting 1 enables halt on hang. 757 */ 758 int halt_if_hws_hang; 759 module_param(halt_if_hws_hang, int, 0644); 760 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 761 762 /** 763 * DOC: hws_gws_support(bool) 764 * Assume that HWS supports GWS barriers regardless of what firmware version 765 * check says. Default value: false (rely on MEC2 firmware version check). 766 */ 767 bool hws_gws_support; 768 module_param(hws_gws_support, bool, 0444); 769 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 770 771 /** 772 * DOC: queue_preemption_timeout_ms (int) 773 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 774 */ 775 int queue_preemption_timeout_ms = 9000; 776 module_param(queue_preemption_timeout_ms, int, 0644); 777 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 778 779 /** 780 * DOC: debug_evictions(bool) 781 * Enable extra debug messages to help determine the cause of evictions 782 */ 783 bool debug_evictions; 784 module_param(debug_evictions, bool, 0644); 785 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 786 787 /** 788 * DOC: no_system_mem_limit(bool) 789 * Disable system memory limit, to support multiple process shared memory 790 */ 791 bool no_system_mem_limit; 792 module_param(no_system_mem_limit, bool, 0644); 793 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 794 795 /** 796 * DOC: no_queue_eviction_on_vm_fault (int) 797 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 798 */ 799 int amdgpu_no_queue_eviction_on_vm_fault; 800 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 801 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 802 #endif 803 804 /** 805 * DOC: mtype_local (int) 806 */ 807 int amdgpu_mtype_local; 808 MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (0 = MTYPE_RW (default), 1 = MTYPE_NC, 2 = MTYPE_CC)"); 809 module_param_named(mtype_local, amdgpu_mtype_local, int, 0444); 810 811 /** 812 * DOC: pcie_p2p (bool) 813 * Enable PCIe P2P (requires large-BAR). Default value: true (on) 814 */ 815 #ifdef CONFIG_HSA_AMD_P2P 816 bool pcie_p2p = true; 817 module_param(pcie_p2p, bool, 0444); 818 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); 819 #endif 820 821 /** 822 * DOC: dcfeaturemask (uint) 823 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 824 * The default is the current set of stable display features. 825 */ 826 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 827 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 828 829 /** 830 * DOC: dcdebugmask (uint) 831 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 832 */ 833 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 834 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 835 836 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)"); 837 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444); 838 839 /** 840 * DOC: abmlevel (uint) 841 * Override the default ABM (Adaptive Backlight Management) level used for DC 842 * enabled hardware. Requires DMCU to be supported and loaded. 843 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 844 * default. Values 1-4 control the maximum allowable brightness reduction via 845 * the ABM algorithm, with 1 being the least reduction and 4 being the most 846 * reduction. 847 * 848 * Defaults to 0, or disabled. Userspace can still override this level later 849 * after boot. 850 */ 851 uint amdgpu_dm_abm_level; 852 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 853 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 854 855 int amdgpu_backlight = -1; 856 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 857 module_param_named(backlight, amdgpu_backlight, bint, 0444); 858 859 /** 860 * DOC: tmz (int) 861 * Trusted Memory Zone (TMZ) is a method to protect data being written 862 * to or read from memory. 863 * 864 * The default value: 0 (off). TODO: change to auto till it is completed. 865 */ 866 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 867 module_param_named(tmz, amdgpu_tmz, int, 0444); 868 869 /** 870 * DOC: reset_method (int) 871 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 872 */ 873 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 874 module_param_named(reset_method, amdgpu_reset_method, int, 0444); 875 876 /** 877 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 878 * threshold value of faulty pages detected by RAS ECC, which may 879 * result in the GPU entering bad status when the number of total 880 * faulty pages by ECC exceeds the threshold value. 881 */ 882 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = driver sets threshold)"); 883 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 884 885 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 886 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 887 888 /** 889 * DOC: vcnfw_log (int) 890 * Enable vcnfw log output for debugging, the default is disabled. 891 */ 892 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 893 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 894 895 /** 896 * DOC: sg_display (int) 897 * Disable S/G (scatter/gather) display (i.e., display from system memory). 898 * This option is only relevant on APUs. Set this option to 0 to disable 899 * S/G display if you experience flickering or other issues under memory 900 * pressure and report the issue. 901 */ 902 MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)"); 903 module_param_named(sg_display, amdgpu_sg_display, int, 0444); 904 905 /** 906 * DOC: umsch_mm (int) 907 * Enable Multi Media User Mode Scheduler. This is a HW scheduling engine for VCN and VPE. 908 * (0 = disabled (default), 1 = enabled) 909 */ 910 MODULE_PARM_DESC(umsch_mm, 911 "Enable Multi Media User Mode Scheduler (0 = disabled (default), 1 = enabled)"); 912 module_param_named(umsch_mm, amdgpu_umsch_mm, int, 0444); 913 914 /** 915 * DOC: smu_pptable_id (int) 916 * Used to override pptable id. id = 0 use VBIOS pptable. 917 * id > 0 use the soft pptable with specicfied id. 918 */ 919 MODULE_PARM_DESC(smu_pptable_id, 920 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 921 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 922 923 /** 924 * DOC: partition_mode (int) 925 * Used to override the default SPX mode. 926 */ 927 MODULE_PARM_DESC( 928 user_partt_mode, 929 "specify partition mode to be used (-2 = AMDGPU_AUTO_COMPUTE_PARTITION_MODE(default value) \ 930 0 = AMDGPU_SPX_PARTITION_MODE, \ 931 1 = AMDGPU_DPX_PARTITION_MODE, \ 932 2 = AMDGPU_TPX_PARTITION_MODE, \ 933 3 = AMDGPU_QPX_PARTITION_MODE, \ 934 4 = AMDGPU_CPX_PARTITION_MODE)"); 935 module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint, 0444); 936 937 938 /** 939 * DOC: enforce_isolation (bool) 940 * enforce process isolation between graphics and compute via using the same reserved vmid. 941 */ 942 module_param(enforce_isolation, bool, 0444); 943 MODULE_PARM_DESC(enforce_isolation, "enforce process isolation between graphics and compute . enforce_isolation = on"); 944 945 /** 946 * DOC: seamless (int) 947 * Seamless boot will keep the image on the screen during the boot process. 948 */ 949 MODULE_PARM_DESC(seamless, "Seamless boot (-1 = auto (default), 0 = disable, 1 = enable)"); 950 module_param_named(seamless, amdgpu_seamless, int, 0444); 951 952 /** 953 * DOC: debug_mask (uint) 954 * Debug options for amdgpu, work as a binary mask with the following options: 955 * 956 * - 0x1: Debug VM handling 957 * - 0x2: Enable simulating large-bar capability on non-large bar system. This 958 * limits the VRAM size reported to ROCm applications to the visible 959 * size, usually 256MB. 960 * - 0x4: Disable GPU soft recovery, always do a full reset 961 */ 962 MODULE_PARM_DESC(debug_mask, "debug options for amdgpu, disabled by default"); 963 module_param_named(debug_mask, amdgpu_debug_mask, uint, 0444); 964 965 /** 966 * DOC: agp (int) 967 * Enable the AGP aperture. This provides an aperture in the GPU's internal 968 * address space for direct access to system memory. Note that these accesses 969 * are non-snooped, so they are only used for access to uncached memory. 970 */ 971 MODULE_PARM_DESC(agp, "AGP (-1 = auto (default), 0 = disable, 1 = enable)"); 972 module_param_named(agp, amdgpu_agp, int, 0444); 973 974 /* These devices are not supported by amdgpu. 975 * They are supported by the mach64, r128, radeon drivers 976 */ 977 static const u16 amdgpu_unsupported_pciidlist[] = { 978 /* mach64 */ 979 0x4354, 980 0x4358, 981 0x4554, 982 0x4742, 983 0x4744, 984 0x4749, 985 0x474C, 986 0x474D, 987 0x474E, 988 0x474F, 989 0x4750, 990 0x4751, 991 0x4752, 992 0x4753, 993 0x4754, 994 0x4755, 995 0x4756, 996 0x4757, 997 0x4758, 998 0x4759, 999 0x475A, 1000 0x4C42, 1001 0x4C44, 1002 0x4C47, 1003 0x4C49, 1004 0x4C4D, 1005 0x4C4E, 1006 0x4C50, 1007 0x4C51, 1008 0x4C52, 1009 0x4C53, 1010 0x5654, 1011 0x5655, 1012 0x5656, 1013 /* r128 */ 1014 0x4c45, 1015 0x4c46, 1016 0x4d46, 1017 0x4d4c, 1018 0x5041, 1019 0x5042, 1020 0x5043, 1021 0x5044, 1022 0x5045, 1023 0x5046, 1024 0x5047, 1025 0x5048, 1026 0x5049, 1027 0x504A, 1028 0x504B, 1029 0x504C, 1030 0x504D, 1031 0x504E, 1032 0x504F, 1033 0x5050, 1034 0x5051, 1035 0x5052, 1036 0x5053, 1037 0x5054, 1038 0x5055, 1039 0x5056, 1040 0x5057, 1041 0x5058, 1042 0x5245, 1043 0x5246, 1044 0x5247, 1045 0x524b, 1046 0x524c, 1047 0x534d, 1048 0x5446, 1049 0x544C, 1050 0x5452, 1051 /* radeon */ 1052 0x3150, 1053 0x3151, 1054 0x3152, 1055 0x3154, 1056 0x3155, 1057 0x3E50, 1058 0x3E54, 1059 0x4136, 1060 0x4137, 1061 0x4144, 1062 0x4145, 1063 0x4146, 1064 0x4147, 1065 0x4148, 1066 0x4149, 1067 0x414A, 1068 0x414B, 1069 0x4150, 1070 0x4151, 1071 0x4152, 1072 0x4153, 1073 0x4154, 1074 0x4155, 1075 0x4156, 1076 0x4237, 1077 0x4242, 1078 0x4336, 1079 0x4337, 1080 0x4437, 1081 0x4966, 1082 0x4967, 1083 0x4A48, 1084 0x4A49, 1085 0x4A4A, 1086 0x4A4B, 1087 0x4A4C, 1088 0x4A4D, 1089 0x4A4E, 1090 0x4A4F, 1091 0x4A50, 1092 0x4A54, 1093 0x4B48, 1094 0x4B49, 1095 0x4B4A, 1096 0x4B4B, 1097 0x4B4C, 1098 0x4C57, 1099 0x4C58, 1100 0x4C59, 1101 0x4C5A, 1102 0x4C64, 1103 0x4C66, 1104 0x4C67, 1105 0x4E44, 1106 0x4E45, 1107 0x4E46, 1108 0x4E47, 1109 0x4E48, 1110 0x4E49, 1111 0x4E4A, 1112 0x4E4B, 1113 0x4E50, 1114 0x4E51, 1115 0x4E52, 1116 0x4E53, 1117 0x4E54, 1118 0x4E56, 1119 0x5144, 1120 0x5145, 1121 0x5146, 1122 0x5147, 1123 0x5148, 1124 0x514C, 1125 0x514D, 1126 0x5157, 1127 0x5158, 1128 0x5159, 1129 0x515A, 1130 0x515E, 1131 0x5460, 1132 0x5462, 1133 0x5464, 1134 0x5548, 1135 0x5549, 1136 0x554A, 1137 0x554B, 1138 0x554C, 1139 0x554D, 1140 0x554E, 1141 0x554F, 1142 0x5550, 1143 0x5551, 1144 0x5552, 1145 0x5554, 1146 0x564A, 1147 0x564B, 1148 0x564F, 1149 0x5652, 1150 0x5653, 1151 0x5657, 1152 0x5834, 1153 0x5835, 1154 0x5954, 1155 0x5955, 1156 0x5974, 1157 0x5975, 1158 0x5960, 1159 0x5961, 1160 0x5962, 1161 0x5964, 1162 0x5965, 1163 0x5969, 1164 0x5a41, 1165 0x5a42, 1166 0x5a61, 1167 0x5a62, 1168 0x5b60, 1169 0x5b62, 1170 0x5b63, 1171 0x5b64, 1172 0x5b65, 1173 0x5c61, 1174 0x5c63, 1175 0x5d48, 1176 0x5d49, 1177 0x5d4a, 1178 0x5d4c, 1179 0x5d4d, 1180 0x5d4e, 1181 0x5d4f, 1182 0x5d50, 1183 0x5d52, 1184 0x5d57, 1185 0x5e48, 1186 0x5e4a, 1187 0x5e4b, 1188 0x5e4c, 1189 0x5e4d, 1190 0x5e4f, 1191 0x6700, 1192 0x6701, 1193 0x6702, 1194 0x6703, 1195 0x6704, 1196 0x6705, 1197 0x6706, 1198 0x6707, 1199 0x6708, 1200 0x6709, 1201 0x6718, 1202 0x6719, 1203 0x671c, 1204 0x671d, 1205 0x671f, 1206 0x6720, 1207 0x6721, 1208 0x6722, 1209 0x6723, 1210 0x6724, 1211 0x6725, 1212 0x6726, 1213 0x6727, 1214 0x6728, 1215 0x6729, 1216 0x6738, 1217 0x6739, 1218 0x673e, 1219 0x6740, 1220 0x6741, 1221 0x6742, 1222 0x6743, 1223 0x6744, 1224 0x6745, 1225 0x6746, 1226 0x6747, 1227 0x6748, 1228 0x6749, 1229 0x674A, 1230 0x6750, 1231 0x6751, 1232 0x6758, 1233 0x6759, 1234 0x675B, 1235 0x675D, 1236 0x675F, 1237 0x6760, 1238 0x6761, 1239 0x6762, 1240 0x6763, 1241 0x6764, 1242 0x6765, 1243 0x6766, 1244 0x6767, 1245 0x6768, 1246 0x6770, 1247 0x6771, 1248 0x6772, 1249 0x6778, 1250 0x6779, 1251 0x677B, 1252 0x6840, 1253 0x6841, 1254 0x6842, 1255 0x6843, 1256 0x6849, 1257 0x684C, 1258 0x6850, 1259 0x6858, 1260 0x6859, 1261 0x6880, 1262 0x6888, 1263 0x6889, 1264 0x688A, 1265 0x688C, 1266 0x688D, 1267 0x6898, 1268 0x6899, 1269 0x689b, 1270 0x689c, 1271 0x689d, 1272 0x689e, 1273 0x68a0, 1274 0x68a1, 1275 0x68a8, 1276 0x68a9, 1277 0x68b0, 1278 0x68b8, 1279 0x68b9, 1280 0x68ba, 1281 0x68be, 1282 0x68bf, 1283 0x68c0, 1284 0x68c1, 1285 0x68c7, 1286 0x68c8, 1287 0x68c9, 1288 0x68d8, 1289 0x68d9, 1290 0x68da, 1291 0x68de, 1292 0x68e0, 1293 0x68e1, 1294 0x68e4, 1295 0x68e5, 1296 0x68e8, 1297 0x68e9, 1298 0x68f1, 1299 0x68f2, 1300 0x68f8, 1301 0x68f9, 1302 0x68fa, 1303 0x68fe, 1304 0x7100, 1305 0x7101, 1306 0x7102, 1307 0x7103, 1308 0x7104, 1309 0x7105, 1310 0x7106, 1311 0x7108, 1312 0x7109, 1313 0x710A, 1314 0x710B, 1315 0x710C, 1316 0x710E, 1317 0x710F, 1318 0x7140, 1319 0x7141, 1320 0x7142, 1321 0x7143, 1322 0x7144, 1323 0x7145, 1324 0x7146, 1325 0x7147, 1326 0x7149, 1327 0x714A, 1328 0x714B, 1329 0x714C, 1330 0x714D, 1331 0x714E, 1332 0x714F, 1333 0x7151, 1334 0x7152, 1335 0x7153, 1336 0x715E, 1337 0x715F, 1338 0x7180, 1339 0x7181, 1340 0x7183, 1341 0x7186, 1342 0x7187, 1343 0x7188, 1344 0x718A, 1345 0x718B, 1346 0x718C, 1347 0x718D, 1348 0x718F, 1349 0x7193, 1350 0x7196, 1351 0x719B, 1352 0x719F, 1353 0x71C0, 1354 0x71C1, 1355 0x71C2, 1356 0x71C3, 1357 0x71C4, 1358 0x71C5, 1359 0x71C6, 1360 0x71C7, 1361 0x71CD, 1362 0x71CE, 1363 0x71D2, 1364 0x71D4, 1365 0x71D5, 1366 0x71D6, 1367 0x71DA, 1368 0x71DE, 1369 0x7200, 1370 0x7210, 1371 0x7211, 1372 0x7240, 1373 0x7243, 1374 0x7244, 1375 0x7245, 1376 0x7246, 1377 0x7247, 1378 0x7248, 1379 0x7249, 1380 0x724A, 1381 0x724B, 1382 0x724C, 1383 0x724D, 1384 0x724E, 1385 0x724F, 1386 0x7280, 1387 0x7281, 1388 0x7283, 1389 0x7284, 1390 0x7287, 1391 0x7288, 1392 0x7289, 1393 0x728B, 1394 0x728C, 1395 0x7290, 1396 0x7291, 1397 0x7293, 1398 0x7297, 1399 0x7834, 1400 0x7835, 1401 0x791e, 1402 0x791f, 1403 0x793f, 1404 0x7941, 1405 0x7942, 1406 0x796c, 1407 0x796d, 1408 0x796e, 1409 0x796f, 1410 0x9400, 1411 0x9401, 1412 0x9402, 1413 0x9403, 1414 0x9405, 1415 0x940A, 1416 0x940B, 1417 0x940F, 1418 0x94A0, 1419 0x94A1, 1420 0x94A3, 1421 0x94B1, 1422 0x94B3, 1423 0x94B4, 1424 0x94B5, 1425 0x94B9, 1426 0x9440, 1427 0x9441, 1428 0x9442, 1429 0x9443, 1430 0x9444, 1431 0x9446, 1432 0x944A, 1433 0x944B, 1434 0x944C, 1435 0x944E, 1436 0x9450, 1437 0x9452, 1438 0x9456, 1439 0x945A, 1440 0x945B, 1441 0x945E, 1442 0x9460, 1443 0x9462, 1444 0x946A, 1445 0x946B, 1446 0x947A, 1447 0x947B, 1448 0x9480, 1449 0x9487, 1450 0x9488, 1451 0x9489, 1452 0x948A, 1453 0x948F, 1454 0x9490, 1455 0x9491, 1456 0x9495, 1457 0x9498, 1458 0x949C, 1459 0x949E, 1460 0x949F, 1461 0x94C0, 1462 0x94C1, 1463 0x94C3, 1464 0x94C4, 1465 0x94C5, 1466 0x94C6, 1467 0x94C7, 1468 0x94C8, 1469 0x94C9, 1470 0x94CB, 1471 0x94CC, 1472 0x94CD, 1473 0x9500, 1474 0x9501, 1475 0x9504, 1476 0x9505, 1477 0x9506, 1478 0x9507, 1479 0x9508, 1480 0x9509, 1481 0x950F, 1482 0x9511, 1483 0x9515, 1484 0x9517, 1485 0x9519, 1486 0x9540, 1487 0x9541, 1488 0x9542, 1489 0x954E, 1490 0x954F, 1491 0x9552, 1492 0x9553, 1493 0x9555, 1494 0x9557, 1495 0x955f, 1496 0x9580, 1497 0x9581, 1498 0x9583, 1499 0x9586, 1500 0x9587, 1501 0x9588, 1502 0x9589, 1503 0x958A, 1504 0x958B, 1505 0x958C, 1506 0x958D, 1507 0x958E, 1508 0x958F, 1509 0x9590, 1510 0x9591, 1511 0x9593, 1512 0x9595, 1513 0x9596, 1514 0x9597, 1515 0x9598, 1516 0x9599, 1517 0x959B, 1518 0x95C0, 1519 0x95C2, 1520 0x95C4, 1521 0x95C5, 1522 0x95C6, 1523 0x95C7, 1524 0x95C9, 1525 0x95CC, 1526 0x95CD, 1527 0x95CE, 1528 0x95CF, 1529 0x9610, 1530 0x9611, 1531 0x9612, 1532 0x9613, 1533 0x9614, 1534 0x9615, 1535 0x9616, 1536 0x9640, 1537 0x9641, 1538 0x9642, 1539 0x9643, 1540 0x9644, 1541 0x9645, 1542 0x9647, 1543 0x9648, 1544 0x9649, 1545 0x964a, 1546 0x964b, 1547 0x964c, 1548 0x964e, 1549 0x964f, 1550 0x9710, 1551 0x9711, 1552 0x9712, 1553 0x9713, 1554 0x9714, 1555 0x9715, 1556 0x9802, 1557 0x9803, 1558 0x9804, 1559 0x9805, 1560 0x9806, 1561 0x9807, 1562 0x9808, 1563 0x9809, 1564 0x980A, 1565 0x9900, 1566 0x9901, 1567 0x9903, 1568 0x9904, 1569 0x9905, 1570 0x9906, 1571 0x9907, 1572 0x9908, 1573 0x9909, 1574 0x990A, 1575 0x990B, 1576 0x990C, 1577 0x990D, 1578 0x990E, 1579 0x990F, 1580 0x9910, 1581 0x9913, 1582 0x9917, 1583 0x9918, 1584 0x9919, 1585 0x9990, 1586 0x9991, 1587 0x9992, 1588 0x9993, 1589 0x9994, 1590 0x9995, 1591 0x9996, 1592 0x9997, 1593 0x9998, 1594 0x9999, 1595 0x999A, 1596 0x999B, 1597 0x999C, 1598 0x999D, 1599 0x99A0, 1600 0x99A2, 1601 0x99A4, 1602 /* radeon secondary ids */ 1603 0x3171, 1604 0x3e70, 1605 0x4164, 1606 0x4165, 1607 0x4166, 1608 0x4168, 1609 0x4170, 1610 0x4171, 1611 0x4172, 1612 0x4173, 1613 0x496e, 1614 0x4a69, 1615 0x4a6a, 1616 0x4a6b, 1617 0x4a70, 1618 0x4a74, 1619 0x4b69, 1620 0x4b6b, 1621 0x4b6c, 1622 0x4c6e, 1623 0x4e64, 1624 0x4e65, 1625 0x4e66, 1626 0x4e67, 1627 0x4e68, 1628 0x4e69, 1629 0x4e6a, 1630 0x4e71, 1631 0x4f73, 1632 0x5569, 1633 0x556b, 1634 0x556d, 1635 0x556f, 1636 0x5571, 1637 0x5854, 1638 0x5874, 1639 0x5940, 1640 0x5941, 1641 0x5b70, 1642 0x5b72, 1643 0x5b73, 1644 0x5b74, 1645 0x5b75, 1646 0x5d44, 1647 0x5d45, 1648 0x5d6d, 1649 0x5d6f, 1650 0x5d72, 1651 0x5d77, 1652 0x5e6b, 1653 0x5e6d, 1654 0x7120, 1655 0x7124, 1656 0x7129, 1657 0x712e, 1658 0x712f, 1659 0x7162, 1660 0x7163, 1661 0x7166, 1662 0x7167, 1663 0x7172, 1664 0x7173, 1665 0x71a0, 1666 0x71a1, 1667 0x71a3, 1668 0x71a7, 1669 0x71bb, 1670 0x71e0, 1671 0x71e1, 1672 0x71e2, 1673 0x71e6, 1674 0x71e7, 1675 0x71f2, 1676 0x7269, 1677 0x726b, 1678 0x726e, 1679 0x72a0, 1680 0x72a8, 1681 0x72b1, 1682 0x72b3, 1683 0x793f, 1684 }; 1685 1686 static const struct pci_device_id pciidlist[] = { 1687 #ifdef CONFIG_DRM_AMDGPU_SI 1688 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1689 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1690 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1691 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1692 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1693 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1694 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1695 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1696 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1697 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1698 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1699 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1700 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1701 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1702 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1703 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1704 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1705 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1706 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1707 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1708 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1709 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1710 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1711 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1712 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1713 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1714 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1715 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1716 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1717 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1718 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1719 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1720 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1721 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1722 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1723 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1724 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1725 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1726 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1727 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1728 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1729 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1730 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1731 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1732 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1733 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1734 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1735 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1736 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1737 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1738 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1739 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1740 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1741 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1742 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1743 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1744 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1745 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1746 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1747 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1748 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1749 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1750 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1751 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1752 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1753 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1754 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1755 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1756 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1757 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1758 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1759 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1760 #endif 1761 #ifdef CONFIG_DRM_AMDGPU_CIK 1762 /* Kaveri */ 1763 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1764 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1765 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1766 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1767 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1768 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1769 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1770 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1771 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1772 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1773 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1774 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1775 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1776 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1777 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1778 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1779 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1780 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1781 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1782 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1783 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1784 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1785 /* Bonaire */ 1786 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1787 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1788 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1789 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1790 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1791 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1792 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1793 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1794 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1795 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1796 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1797 /* Hawaii */ 1798 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1799 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1800 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1801 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1802 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1803 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1804 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1805 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1806 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1807 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1808 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1809 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1810 /* Kabini */ 1811 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1812 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1813 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1814 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1815 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1816 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1817 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1818 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1819 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1820 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1821 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1822 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1823 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1824 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1825 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1826 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1827 /* mullins */ 1828 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1829 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1830 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1831 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1832 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1833 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1834 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1835 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1836 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1837 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1838 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1839 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1840 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1841 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1842 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1843 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1844 #endif 1845 /* topaz */ 1846 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1847 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1848 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1849 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1850 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1851 /* tonga */ 1852 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1853 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1854 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1855 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1856 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1857 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1858 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1859 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1860 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1861 /* fiji */ 1862 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1863 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1864 /* carrizo */ 1865 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1866 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1867 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1868 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1869 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1870 /* stoney */ 1871 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1872 /* Polaris11 */ 1873 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1874 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1875 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1876 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1877 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1878 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1879 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1880 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1881 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1882 /* Polaris10 */ 1883 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1884 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1885 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1886 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1887 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1888 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1889 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1890 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1891 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1892 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1893 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1894 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1895 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1896 /* Polaris12 */ 1897 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1898 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1899 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1900 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1901 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1902 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1903 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1904 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1905 /* VEGAM */ 1906 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1907 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1908 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1909 /* Vega 10 */ 1910 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1911 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1912 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1913 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1914 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1915 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1916 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1917 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1918 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1919 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1920 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1921 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1922 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1923 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1924 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1925 /* Vega 12 */ 1926 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1927 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1928 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1929 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1930 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1931 /* Vega 20 */ 1932 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1933 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1934 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1935 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1936 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1937 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1938 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1939 /* Raven */ 1940 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1941 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1942 /* Arcturus */ 1943 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1944 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1945 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1946 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1947 /* Navi10 */ 1948 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1949 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1950 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1951 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1952 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1953 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1954 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1955 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1956 /* Navi14 */ 1957 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1958 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1959 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1960 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1961 1962 /* Renoir */ 1963 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1964 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1965 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1966 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1967 1968 /* Navi12 */ 1969 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1970 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1971 1972 /* Sienna_Cichlid */ 1973 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1974 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1975 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1976 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1977 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1978 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1979 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1980 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1981 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1982 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1983 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1984 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1985 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1986 1987 /* Yellow Carp */ 1988 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1989 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1990 1991 /* Navy_Flounder */ 1992 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1993 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1994 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1995 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1996 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1997 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1998 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1999 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2000 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2001 2002 /* DIMGREY_CAVEFISH */ 2003 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2004 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2005 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2006 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2007 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2008 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2009 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2010 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2011 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2012 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2013 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2014 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2015 2016 /* Aldebaran */ 2017 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2018 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2019 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2020 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2021 2022 /* CYAN_SKILLFISH */ 2023 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2024 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2025 2026 /* BEIGE_GOBY */ 2027 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2028 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2029 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2030 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2031 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2032 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2033 2034 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2035 .class = PCI_CLASS_DISPLAY_VGA << 8, 2036 .class_mask = 0xffffff, 2037 .driver_data = CHIP_IP_DISCOVERY }, 2038 2039 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2040 .class = PCI_CLASS_DISPLAY_OTHER << 8, 2041 .class_mask = 0xffffff, 2042 .driver_data = CHIP_IP_DISCOVERY }, 2043 2044 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2045 .class = PCI_CLASS_ACCELERATOR_PROCESSING << 8, 2046 .class_mask = 0xffffff, 2047 .driver_data = CHIP_IP_DISCOVERY }, 2048 2049 {0, 0, 0} 2050 }; 2051 2052 MODULE_DEVICE_TABLE(pci, pciidlist); 2053 2054 static const struct amdgpu_asic_type_quirk asic_type_quirks[] = { 2055 /* differentiate between P10 and P11 asics with the same DID */ 2056 {0x67FF, 0xE3, CHIP_POLARIS10}, 2057 {0x67FF, 0xE7, CHIP_POLARIS10}, 2058 {0x67FF, 0xF3, CHIP_POLARIS10}, 2059 {0x67FF, 0xF7, CHIP_POLARIS10}, 2060 }; 2061 2062 static const struct drm_driver amdgpu_kms_driver; 2063 2064 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 2065 { 2066 struct pci_dev *p = NULL; 2067 int i; 2068 2069 /* 0 - GPU 2070 * 1 - audio 2071 * 2 - USB 2072 * 3 - UCSI 2073 */ 2074 for (i = 1; i < 4; i++) { 2075 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 2076 adev->pdev->bus->number, i); 2077 if (p) { 2078 pm_runtime_get_sync(&p->dev); 2079 pm_runtime_mark_last_busy(&p->dev); 2080 pm_runtime_put_autosuspend(&p->dev); 2081 pci_dev_put(p); 2082 } 2083 } 2084 } 2085 2086 static void amdgpu_init_debug_options(struct amdgpu_device *adev) 2087 { 2088 if (amdgpu_debug_mask & AMDGPU_DEBUG_VM) { 2089 pr_info("debug: VM handling debug enabled\n"); 2090 adev->debug_vm = true; 2091 } 2092 2093 if (amdgpu_debug_mask & AMDGPU_DEBUG_LARGEBAR) { 2094 pr_info("debug: enabled simulating large-bar capability on non-large bar system\n"); 2095 adev->debug_largebar = true; 2096 } 2097 2098 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY) { 2099 pr_info("debug: soft reset for GPU recovery disabled\n"); 2100 adev->debug_disable_soft_recovery = true; 2101 } 2102 } 2103 2104 static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long flags) 2105 { 2106 int i; 2107 2108 for (i = 0; i < ARRAY_SIZE(asic_type_quirks); i++) { 2109 if (pdev->device == asic_type_quirks[i].device && 2110 pdev->revision == asic_type_quirks[i].revision) { 2111 flags &= ~AMD_ASIC_MASK; 2112 flags |= asic_type_quirks[i].type; 2113 break; 2114 } 2115 } 2116 2117 return flags; 2118 } 2119 2120 static int amdgpu_pci_probe(struct pci_dev *pdev, 2121 const struct pci_device_id *ent) 2122 { 2123 struct drm_device *ddev; 2124 struct amdgpu_device *adev; 2125 unsigned long flags = ent->driver_data; 2126 int ret, retry = 0, i; 2127 bool supports_atomic = false; 2128 2129 /* skip devices which are owned by radeon */ 2130 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2131 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2132 return -ENODEV; 2133 } 2134 2135 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) 2136 amdgpu_aspm = 0; 2137 2138 if (amdgpu_virtual_display || 2139 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 2140 supports_atomic = true; 2141 2142 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2143 DRM_INFO("This hardware requires experimental hardware support.\n" 2144 "See modparam exp_hw_support\n"); 2145 return -ENODEV; 2146 } 2147 2148 flags = amdgpu_fix_asic_type(pdev, flags); 2149 2150 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2151 * however, SME requires an indirect IOMMU mapping because the encryption 2152 * bit is beyond the DMA mask of the chip. 2153 */ 2154 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2155 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2156 dev_info(&pdev->dev, 2157 "SME is not compatible with RAVEN\n"); 2158 return -ENOTSUPP; 2159 } 2160 2161 #ifdef CONFIG_DRM_AMDGPU_SI 2162 if (!amdgpu_si_support) { 2163 switch (flags & AMD_ASIC_MASK) { 2164 case CHIP_TAHITI: 2165 case CHIP_PITCAIRN: 2166 case CHIP_VERDE: 2167 case CHIP_OLAND: 2168 case CHIP_HAINAN: 2169 dev_info(&pdev->dev, 2170 "SI support provided by radeon.\n"); 2171 dev_info(&pdev->dev, 2172 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 2173 ); 2174 return -ENODEV; 2175 } 2176 } 2177 #endif 2178 #ifdef CONFIG_DRM_AMDGPU_CIK 2179 if (!amdgpu_cik_support) { 2180 switch (flags & AMD_ASIC_MASK) { 2181 case CHIP_KAVERI: 2182 case CHIP_BONAIRE: 2183 case CHIP_HAWAII: 2184 case CHIP_KABINI: 2185 case CHIP_MULLINS: 2186 dev_info(&pdev->dev, 2187 "CIK support provided by radeon.\n"); 2188 dev_info(&pdev->dev, 2189 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 2190 ); 2191 return -ENODEV; 2192 } 2193 } 2194 #endif 2195 2196 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2197 if (IS_ERR(adev)) 2198 return PTR_ERR(adev); 2199 2200 adev->dev = &pdev->dev; 2201 adev->pdev = pdev; 2202 ddev = adev_to_drm(adev); 2203 2204 if (!supports_atomic) 2205 ddev->driver_features &= ~DRIVER_ATOMIC; 2206 2207 ret = pci_enable_device(pdev); 2208 if (ret) 2209 return ret; 2210 2211 pci_set_drvdata(pdev, ddev); 2212 2213 ret = amdgpu_driver_load_kms(adev, flags); 2214 if (ret) 2215 goto err_pci; 2216 2217 retry_init: 2218 ret = drm_dev_register(ddev, flags); 2219 if (ret == -EAGAIN && ++retry <= 3) { 2220 DRM_INFO("retry init %d\n", retry); 2221 /* Don't request EX mode too frequently which is attacking */ 2222 msleep(5000); 2223 goto retry_init; 2224 } else if (ret) { 2225 goto err_pci; 2226 } 2227 2228 ret = amdgpu_xcp_dev_register(adev, ent); 2229 if (ret) 2230 goto err_pci; 2231 2232 /* 2233 * 1. don't init fbdev on hw without DCE 2234 * 2. don't init fbdev if there are no connectors 2235 */ 2236 if (adev->mode_info.mode_config_initialized && 2237 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2238 /* select 8 bpp console on low vram cards */ 2239 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2240 drm_fbdev_generic_setup(adev_to_drm(adev), 8); 2241 else 2242 drm_fbdev_generic_setup(adev_to_drm(adev), 32); 2243 } 2244 2245 ret = amdgpu_debugfs_init(adev); 2246 if (ret) 2247 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2248 2249 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2250 /* only need to skip on ATPX */ 2251 if (amdgpu_device_supports_px(ddev)) 2252 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2253 /* we want direct complete for BOCO */ 2254 if (amdgpu_device_supports_boco(ddev)) 2255 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2256 DPM_FLAG_SMART_SUSPEND | 2257 DPM_FLAG_MAY_SKIP_RESUME); 2258 pm_runtime_use_autosuspend(ddev->dev); 2259 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2260 2261 pm_runtime_allow(ddev->dev); 2262 2263 pm_runtime_mark_last_busy(ddev->dev); 2264 pm_runtime_put_autosuspend(ddev->dev); 2265 2266 pci_wake_from_d3(pdev, TRUE); 2267 2268 /* 2269 * For runpm implemented via BACO, PMFW will handle the 2270 * timing for BACO in and out: 2271 * - put ASIC into BACO state only when both video and 2272 * audio functions are in D3 state. 2273 * - pull ASIC out of BACO state when either video or 2274 * audio function is in D0 state. 2275 * Also, at startup, PMFW assumes both functions are in 2276 * D0 state. 2277 * 2278 * So if snd driver was loaded prior to amdgpu driver 2279 * and audio function was put into D3 state, there will 2280 * be no PMFW-aware D-state transition(D0->D3) on runpm 2281 * suspend. Thus the BACO will be not correctly kicked in. 2282 * 2283 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2284 * into D0 state. Then there will be a PMFW-aware D-state 2285 * transition(D0->D3) on runpm suspend. 2286 */ 2287 if (amdgpu_device_supports_baco(ddev) && 2288 !(adev->flags & AMD_IS_APU) && 2289 (adev->asic_type >= CHIP_NAVI10)) 2290 amdgpu_get_secondary_funcs(adev); 2291 } 2292 2293 amdgpu_init_debug_options(adev); 2294 2295 return 0; 2296 2297 err_pci: 2298 pci_disable_device(pdev); 2299 return ret; 2300 } 2301 2302 static void 2303 amdgpu_pci_remove(struct pci_dev *pdev) 2304 { 2305 struct drm_device *dev = pci_get_drvdata(pdev); 2306 struct amdgpu_device *adev = drm_to_adev(dev); 2307 2308 amdgpu_xcp_dev_unplug(adev); 2309 drm_dev_unplug(dev); 2310 2311 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2312 pm_runtime_get_sync(dev->dev); 2313 pm_runtime_forbid(dev->dev); 2314 } 2315 2316 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 2) && 2317 !amdgpu_sriov_vf(adev)) { 2318 bool need_to_reset_gpu = false; 2319 2320 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2321 struct amdgpu_hive_info *hive; 2322 2323 hive = amdgpu_get_xgmi_hive(adev); 2324 if (hive->device_remove_count == 0) 2325 need_to_reset_gpu = true; 2326 hive->device_remove_count++; 2327 amdgpu_put_xgmi_hive(hive); 2328 } else { 2329 need_to_reset_gpu = true; 2330 } 2331 2332 /* Workaround for ASICs need to reset SMU. 2333 * Called only when the first device is removed. 2334 */ 2335 if (need_to_reset_gpu) { 2336 struct amdgpu_reset_context reset_context; 2337 2338 adev->shutdown = true; 2339 memset(&reset_context, 0, sizeof(reset_context)); 2340 reset_context.method = AMD_RESET_METHOD_NONE; 2341 reset_context.reset_req_dev = adev; 2342 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2343 set_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context.flags); 2344 amdgpu_device_gpu_recover(adev, NULL, &reset_context); 2345 } 2346 } 2347 2348 amdgpu_driver_unload_kms(dev); 2349 2350 /* 2351 * Flush any in flight DMA operations from device. 2352 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2353 * StatusTransactions Pending bit. 2354 */ 2355 pci_disable_device(pdev); 2356 pci_wait_for_pending_transaction(pdev); 2357 } 2358 2359 static void 2360 amdgpu_pci_shutdown(struct pci_dev *pdev) 2361 { 2362 struct drm_device *dev = pci_get_drvdata(pdev); 2363 struct amdgpu_device *adev = drm_to_adev(dev); 2364 2365 if (amdgpu_ras_intr_triggered()) 2366 return; 2367 2368 /* if we are running in a VM, make sure the device 2369 * torn down properly on reboot/shutdown. 2370 * unfortunately we can't detect certain 2371 * hypervisors so just do this all the time. 2372 */ 2373 if (!amdgpu_passthrough(adev)) 2374 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2375 amdgpu_device_ip_suspend(adev); 2376 adev->mp1_state = PP_MP1_STATE_NONE; 2377 } 2378 2379 /** 2380 * amdgpu_drv_delayed_reset_work_handler - work handler for reset 2381 * 2382 * @work: work_struct. 2383 */ 2384 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) 2385 { 2386 struct list_head device_list; 2387 struct amdgpu_device *adev; 2388 int i, r; 2389 struct amdgpu_reset_context reset_context; 2390 2391 memset(&reset_context, 0, sizeof(reset_context)); 2392 2393 mutex_lock(&mgpu_info.mutex); 2394 if (mgpu_info.pending_reset == true) { 2395 mutex_unlock(&mgpu_info.mutex); 2396 return; 2397 } 2398 mgpu_info.pending_reset = true; 2399 mutex_unlock(&mgpu_info.mutex); 2400 2401 /* Use a common context, just need to make sure full reset is done */ 2402 reset_context.method = AMD_RESET_METHOD_NONE; 2403 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2404 2405 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2406 adev = mgpu_info.gpu_ins[i].adev; 2407 reset_context.reset_req_dev = adev; 2408 r = amdgpu_device_pre_asic_reset(adev, &reset_context); 2409 if (r) { 2410 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", 2411 r, adev_to_drm(adev)->unique); 2412 } 2413 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) 2414 r = -EALREADY; 2415 } 2416 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2417 adev = mgpu_info.gpu_ins[i].adev; 2418 flush_work(&adev->xgmi_reset_work); 2419 adev->gmc.xgmi.pending_reset = false; 2420 } 2421 2422 /* reset function will rebuild the xgmi hive info , clear it now */ 2423 for (i = 0; i < mgpu_info.num_dgpu; i++) 2424 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); 2425 2426 INIT_LIST_HEAD(&device_list); 2427 2428 for (i = 0; i < mgpu_info.num_dgpu; i++) 2429 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); 2430 2431 /* unregister the GPU first, reset function will add them back */ 2432 list_for_each_entry(adev, &device_list, reset_list) 2433 amdgpu_unregister_gpu_instance(adev); 2434 2435 /* Use a common context, just need to make sure full reset is done */ 2436 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); 2437 r = amdgpu_do_asic_reset(&device_list, &reset_context); 2438 2439 if (r) { 2440 DRM_ERROR("reinit gpus failure"); 2441 return; 2442 } 2443 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2444 adev = mgpu_info.gpu_ins[i].adev; 2445 if (!adev->kfd.init_complete) 2446 amdgpu_amdkfd_device_init(adev); 2447 amdgpu_ttm_set_buffer_funcs_status(adev, true); 2448 } 2449 } 2450 2451 static int amdgpu_pmops_prepare(struct device *dev) 2452 { 2453 struct drm_device *drm_dev = dev_get_drvdata(dev); 2454 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2455 2456 /* Return a positive number here so 2457 * DPM_FLAG_SMART_SUSPEND works properly 2458 */ 2459 if (amdgpu_device_supports_boco(drm_dev) && 2460 pm_runtime_suspended(dev)) 2461 return 1; 2462 2463 /* if we will not support s3 or s2i for the device 2464 * then skip suspend 2465 */ 2466 if (!amdgpu_acpi_is_s0ix_active(adev) && 2467 !amdgpu_acpi_is_s3_active(adev)) 2468 return 1; 2469 2470 return amdgpu_device_prepare(drm_dev); 2471 } 2472 2473 static void amdgpu_pmops_complete(struct device *dev) 2474 { 2475 /* nothing to do */ 2476 } 2477 2478 static int amdgpu_pmops_suspend(struct device *dev) 2479 { 2480 struct drm_device *drm_dev = dev_get_drvdata(dev); 2481 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2482 2483 if (amdgpu_acpi_is_s0ix_active(adev)) 2484 adev->in_s0ix = true; 2485 else if (amdgpu_acpi_is_s3_active(adev)) 2486 adev->in_s3 = true; 2487 if (!adev->in_s0ix && !adev->in_s3) 2488 return 0; 2489 return amdgpu_device_suspend(drm_dev, true); 2490 } 2491 2492 static int amdgpu_pmops_suspend_noirq(struct device *dev) 2493 { 2494 struct drm_device *drm_dev = dev_get_drvdata(dev); 2495 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2496 2497 if (amdgpu_acpi_should_gpu_reset(adev)) 2498 return amdgpu_asic_reset(adev); 2499 2500 return 0; 2501 } 2502 2503 static int amdgpu_pmops_resume(struct device *dev) 2504 { 2505 struct drm_device *drm_dev = dev_get_drvdata(dev); 2506 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2507 int r; 2508 2509 if (!adev->in_s0ix && !adev->in_s3) 2510 return 0; 2511 2512 /* Avoids registers access if device is physically gone */ 2513 if (!pci_device_is_present(adev->pdev)) 2514 adev->no_hw_access = true; 2515 2516 r = amdgpu_device_resume(drm_dev, true); 2517 if (amdgpu_acpi_is_s0ix_active(adev)) 2518 adev->in_s0ix = false; 2519 else 2520 adev->in_s3 = false; 2521 return r; 2522 } 2523 2524 static int amdgpu_pmops_freeze(struct device *dev) 2525 { 2526 struct drm_device *drm_dev = dev_get_drvdata(dev); 2527 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2528 int r; 2529 2530 adev->in_s4 = true; 2531 r = amdgpu_device_suspend(drm_dev, true); 2532 adev->in_s4 = false; 2533 if (r) 2534 return r; 2535 2536 if (amdgpu_acpi_should_gpu_reset(adev)) 2537 return amdgpu_asic_reset(adev); 2538 return 0; 2539 } 2540 2541 static int amdgpu_pmops_thaw(struct device *dev) 2542 { 2543 struct drm_device *drm_dev = dev_get_drvdata(dev); 2544 2545 return amdgpu_device_resume(drm_dev, true); 2546 } 2547 2548 static int amdgpu_pmops_poweroff(struct device *dev) 2549 { 2550 struct drm_device *drm_dev = dev_get_drvdata(dev); 2551 2552 return amdgpu_device_suspend(drm_dev, true); 2553 } 2554 2555 static int amdgpu_pmops_restore(struct device *dev) 2556 { 2557 struct drm_device *drm_dev = dev_get_drvdata(dev); 2558 2559 return amdgpu_device_resume(drm_dev, true); 2560 } 2561 2562 static int amdgpu_runtime_idle_check_display(struct device *dev) 2563 { 2564 struct pci_dev *pdev = to_pci_dev(dev); 2565 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2566 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2567 2568 if (adev->mode_info.num_crtc) { 2569 struct drm_connector *list_connector; 2570 struct drm_connector_list_iter iter; 2571 int ret = 0; 2572 2573 if (amdgpu_runtime_pm != -2) { 2574 /* XXX: Return busy if any displays are connected to avoid 2575 * possible display wakeups after runtime resume due to 2576 * hotplug events in case any displays were connected while 2577 * the GPU was in suspend. Remove this once that is fixed. 2578 */ 2579 mutex_lock(&drm_dev->mode_config.mutex); 2580 drm_connector_list_iter_begin(drm_dev, &iter); 2581 drm_for_each_connector_iter(list_connector, &iter) { 2582 if (list_connector->status == connector_status_connected) { 2583 ret = -EBUSY; 2584 break; 2585 } 2586 } 2587 drm_connector_list_iter_end(&iter); 2588 mutex_unlock(&drm_dev->mode_config.mutex); 2589 2590 if (ret) 2591 return ret; 2592 } 2593 2594 if (adev->dc_enabled) { 2595 struct drm_crtc *crtc; 2596 2597 drm_for_each_crtc(crtc, drm_dev) { 2598 drm_modeset_lock(&crtc->mutex, NULL); 2599 if (crtc->state->active) 2600 ret = -EBUSY; 2601 drm_modeset_unlock(&crtc->mutex); 2602 if (ret < 0) 2603 break; 2604 } 2605 } else { 2606 mutex_lock(&drm_dev->mode_config.mutex); 2607 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2608 2609 drm_connector_list_iter_begin(drm_dev, &iter); 2610 drm_for_each_connector_iter(list_connector, &iter) { 2611 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2612 ret = -EBUSY; 2613 break; 2614 } 2615 } 2616 2617 drm_connector_list_iter_end(&iter); 2618 2619 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2620 mutex_unlock(&drm_dev->mode_config.mutex); 2621 } 2622 if (ret) 2623 return ret; 2624 } 2625 2626 return 0; 2627 } 2628 2629 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2630 { 2631 struct pci_dev *pdev = to_pci_dev(dev); 2632 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2633 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2634 int ret, i; 2635 2636 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2637 pm_runtime_forbid(dev); 2638 return -EBUSY; 2639 } 2640 2641 ret = amdgpu_runtime_idle_check_display(dev); 2642 if (ret) 2643 return ret; 2644 2645 /* wait for all rings to drain before suspending */ 2646 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2647 struct amdgpu_ring *ring = adev->rings[i]; 2648 2649 if (ring && ring->sched.ready) { 2650 ret = amdgpu_fence_wait_empty(ring); 2651 if (ret) 2652 return -EBUSY; 2653 } 2654 } 2655 2656 adev->in_runpm = true; 2657 if (amdgpu_device_supports_px(drm_dev)) 2658 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2659 2660 /* 2661 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2662 * proper cleanups and put itself into a state ready for PNP. That 2663 * can address some random resuming failure observed on BOCO capable 2664 * platforms. 2665 * TODO: this may be also needed for PX capable platform. 2666 */ 2667 if (amdgpu_device_supports_boco(drm_dev)) 2668 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2669 2670 ret = amdgpu_device_prepare(drm_dev); 2671 if (ret) 2672 return ret; 2673 ret = amdgpu_device_suspend(drm_dev, false); 2674 if (ret) { 2675 adev->in_runpm = false; 2676 if (amdgpu_device_supports_boco(drm_dev)) 2677 adev->mp1_state = PP_MP1_STATE_NONE; 2678 return ret; 2679 } 2680 2681 if (amdgpu_device_supports_boco(drm_dev)) 2682 adev->mp1_state = PP_MP1_STATE_NONE; 2683 2684 if (amdgpu_device_supports_px(drm_dev)) { 2685 /* Only need to handle PCI state in the driver for ATPX 2686 * PCI core handles it for _PR3. 2687 */ 2688 amdgpu_device_cache_pci_state(pdev); 2689 pci_disable_device(pdev); 2690 pci_ignore_hotplug(pdev); 2691 pci_set_power_state(pdev, PCI_D3cold); 2692 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2693 } else if (amdgpu_device_supports_boco(drm_dev)) { 2694 /* nothing to do */ 2695 } else if (amdgpu_device_supports_baco(drm_dev)) { 2696 amdgpu_device_baco_enter(drm_dev); 2697 } 2698 2699 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n"); 2700 2701 return 0; 2702 } 2703 2704 static int amdgpu_pmops_runtime_resume(struct device *dev) 2705 { 2706 struct pci_dev *pdev = to_pci_dev(dev); 2707 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2708 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2709 int ret; 2710 2711 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) 2712 return -EINVAL; 2713 2714 /* Avoids registers access if device is physically gone */ 2715 if (!pci_device_is_present(adev->pdev)) 2716 adev->no_hw_access = true; 2717 2718 if (amdgpu_device_supports_px(drm_dev)) { 2719 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2720 2721 /* Only need to handle PCI state in the driver for ATPX 2722 * PCI core handles it for _PR3. 2723 */ 2724 pci_set_power_state(pdev, PCI_D0); 2725 amdgpu_device_load_pci_state(pdev); 2726 ret = pci_enable_device(pdev); 2727 if (ret) 2728 return ret; 2729 pci_set_master(pdev); 2730 } else if (amdgpu_device_supports_boco(drm_dev)) { 2731 /* Only need to handle PCI state in the driver for ATPX 2732 * PCI core handles it for _PR3. 2733 */ 2734 pci_set_master(pdev); 2735 } else if (amdgpu_device_supports_baco(drm_dev)) { 2736 amdgpu_device_baco_exit(drm_dev); 2737 } 2738 ret = amdgpu_device_resume(drm_dev, false); 2739 if (ret) { 2740 if (amdgpu_device_supports_px(drm_dev)) 2741 pci_disable_device(pdev); 2742 return ret; 2743 } 2744 2745 if (amdgpu_device_supports_px(drm_dev)) 2746 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2747 adev->in_runpm = false; 2748 return 0; 2749 } 2750 2751 static int amdgpu_pmops_runtime_idle(struct device *dev) 2752 { 2753 struct drm_device *drm_dev = dev_get_drvdata(dev); 2754 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2755 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 2756 int ret = 1; 2757 2758 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2759 pm_runtime_forbid(dev); 2760 return -EBUSY; 2761 } 2762 2763 ret = amdgpu_runtime_idle_check_display(dev); 2764 2765 pm_runtime_mark_last_busy(dev); 2766 pm_runtime_autosuspend(dev); 2767 return ret; 2768 } 2769 2770 long amdgpu_drm_ioctl(struct file *filp, 2771 unsigned int cmd, unsigned long arg) 2772 { 2773 struct drm_file *file_priv = filp->private_data; 2774 struct drm_device *dev; 2775 long ret; 2776 2777 dev = file_priv->minor->dev; 2778 ret = pm_runtime_get_sync(dev->dev); 2779 if (ret < 0) 2780 goto out; 2781 2782 ret = drm_ioctl(filp, cmd, arg); 2783 2784 pm_runtime_mark_last_busy(dev->dev); 2785 out: 2786 pm_runtime_put_autosuspend(dev->dev); 2787 return ret; 2788 } 2789 2790 static const struct dev_pm_ops amdgpu_pm_ops = { 2791 .prepare = amdgpu_pmops_prepare, 2792 .complete = amdgpu_pmops_complete, 2793 .suspend = amdgpu_pmops_suspend, 2794 .suspend_noirq = amdgpu_pmops_suspend_noirq, 2795 .resume = amdgpu_pmops_resume, 2796 .freeze = amdgpu_pmops_freeze, 2797 .thaw = amdgpu_pmops_thaw, 2798 .poweroff = amdgpu_pmops_poweroff, 2799 .restore = amdgpu_pmops_restore, 2800 .runtime_suspend = amdgpu_pmops_runtime_suspend, 2801 .runtime_resume = amdgpu_pmops_runtime_resume, 2802 .runtime_idle = amdgpu_pmops_runtime_idle, 2803 }; 2804 2805 static int amdgpu_flush(struct file *f, fl_owner_t id) 2806 { 2807 struct drm_file *file_priv = f->private_data; 2808 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2809 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2810 2811 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 2812 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 2813 2814 return timeout >= 0 ? 0 : timeout; 2815 } 2816 2817 static const struct file_operations amdgpu_driver_kms_fops = { 2818 .owner = THIS_MODULE, 2819 .open = drm_open, 2820 .flush = amdgpu_flush, 2821 .release = drm_release, 2822 .unlocked_ioctl = amdgpu_drm_ioctl, 2823 .mmap = drm_gem_mmap, 2824 .poll = drm_poll, 2825 .read = drm_read, 2826 #ifdef CONFIG_COMPAT 2827 .compat_ioctl = amdgpu_kms_compat_ioctl, 2828 #endif 2829 #ifdef CONFIG_PROC_FS 2830 .show_fdinfo = drm_show_fdinfo, 2831 #endif 2832 }; 2833 2834 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 2835 { 2836 struct drm_file *file; 2837 2838 if (!filp) 2839 return -EINVAL; 2840 2841 if (filp->f_op != &amdgpu_driver_kms_fops) 2842 return -EINVAL; 2843 2844 file = filp->private_data; 2845 *fpriv = file->driver_priv; 2846 return 0; 2847 } 2848 2849 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 2850 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2851 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2852 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2853 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 2854 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2855 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2856 /* KMS */ 2857 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2858 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2859 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2860 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2861 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2862 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2863 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2864 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2865 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2866 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2867 }; 2868 2869 static const struct drm_driver amdgpu_kms_driver = { 2870 .driver_features = 2871 DRIVER_ATOMIC | 2872 DRIVER_GEM | 2873 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 2874 DRIVER_SYNCOBJ_TIMELINE, 2875 .open = amdgpu_driver_open_kms, 2876 .postclose = amdgpu_driver_postclose_kms, 2877 .lastclose = amdgpu_driver_lastclose_kms, 2878 .ioctls = amdgpu_ioctls_kms, 2879 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2880 .dumb_create = amdgpu_mode_dumb_create, 2881 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2882 .fops = &amdgpu_driver_kms_fops, 2883 .release = &amdgpu_driver_release_kms, 2884 #ifdef CONFIG_PROC_FS 2885 .show_fdinfo = amdgpu_show_fdinfo, 2886 #endif 2887 2888 .gem_prime_import = amdgpu_gem_prime_import, 2889 2890 .name = DRIVER_NAME, 2891 .desc = DRIVER_DESC, 2892 .date = DRIVER_DATE, 2893 .major = KMS_DRIVER_MAJOR, 2894 .minor = KMS_DRIVER_MINOR, 2895 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2896 }; 2897 2898 const struct drm_driver amdgpu_partition_driver = { 2899 .driver_features = 2900 DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ | 2901 DRIVER_SYNCOBJ_TIMELINE, 2902 .open = amdgpu_driver_open_kms, 2903 .postclose = amdgpu_driver_postclose_kms, 2904 .lastclose = amdgpu_driver_lastclose_kms, 2905 .ioctls = amdgpu_ioctls_kms, 2906 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2907 .dumb_create = amdgpu_mode_dumb_create, 2908 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2909 .fops = &amdgpu_driver_kms_fops, 2910 .release = &amdgpu_driver_release_kms, 2911 2912 .gem_prime_import = amdgpu_gem_prime_import, 2913 2914 .name = DRIVER_NAME, 2915 .desc = DRIVER_DESC, 2916 .date = DRIVER_DATE, 2917 .major = KMS_DRIVER_MAJOR, 2918 .minor = KMS_DRIVER_MINOR, 2919 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2920 }; 2921 2922 static struct pci_error_handlers amdgpu_pci_err_handler = { 2923 .error_detected = amdgpu_pci_error_detected, 2924 .mmio_enabled = amdgpu_pci_mmio_enabled, 2925 .slot_reset = amdgpu_pci_slot_reset, 2926 .resume = amdgpu_pci_resume, 2927 }; 2928 2929 static const struct attribute_group *amdgpu_sysfs_groups[] = { 2930 &amdgpu_vram_mgr_attr_group, 2931 &amdgpu_gtt_mgr_attr_group, 2932 &amdgpu_flash_attr_group, 2933 NULL, 2934 }; 2935 2936 static struct pci_driver amdgpu_kms_pci_driver = { 2937 .name = DRIVER_NAME, 2938 .id_table = pciidlist, 2939 .probe = amdgpu_pci_probe, 2940 .remove = amdgpu_pci_remove, 2941 .shutdown = amdgpu_pci_shutdown, 2942 .driver.pm = &amdgpu_pm_ops, 2943 .err_handler = &amdgpu_pci_err_handler, 2944 .dev_groups = amdgpu_sysfs_groups, 2945 }; 2946 2947 static int __init amdgpu_init(void) 2948 { 2949 int r; 2950 2951 if (drm_firmware_drivers_only()) 2952 return -EINVAL; 2953 2954 r = amdgpu_sync_init(); 2955 if (r) 2956 goto error_sync; 2957 2958 r = amdgpu_fence_slab_init(); 2959 if (r) 2960 goto error_fence; 2961 2962 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 2963 amdgpu_register_atpx_handler(); 2964 amdgpu_acpi_detect(); 2965 2966 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 2967 amdgpu_amdkfd_init(); 2968 2969 /* let modprobe override vga console setting */ 2970 return pci_register_driver(&amdgpu_kms_pci_driver); 2971 2972 error_fence: 2973 amdgpu_sync_fini(); 2974 2975 error_sync: 2976 return r; 2977 } 2978 2979 static void __exit amdgpu_exit(void) 2980 { 2981 amdgpu_amdkfd_fini(); 2982 pci_unregister_driver(&amdgpu_kms_pci_driver); 2983 amdgpu_unregister_atpx_handler(); 2984 amdgpu_acpi_release(); 2985 amdgpu_sync_fini(); 2986 amdgpu_fence_slab_fini(); 2987 mmu_notifier_synchronize(); 2988 amdgpu_xcp_drv_release(); 2989 } 2990 2991 module_init(amdgpu_init); 2992 module_exit(amdgpu_exit); 2993 2994 MODULE_AUTHOR(DRIVER_AUTHOR); 2995 MODULE_DESCRIPTION(DRIVER_DESC); 2996 MODULE_LICENSE("GPL and additional rights"); 2997