1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_drv.h> 27 #include <drm/drm_gem.h> 28 #include <drm/drm_vblank.h> 29 #include "amdgpu_drv.h" 30 31 #include <drm/drm_pciids.h> 32 #include <linux/console.h> 33 #include <linux/module.h> 34 #include <linux/pci.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/vga_switcheroo.h> 37 #include <drm/drm_probe_helper.h> 38 39 #include "amdgpu.h" 40 #include "amdgpu_irq.h" 41 #include "amdgpu_dma_buf.h" 42 43 #include "amdgpu_amdkfd.h" 44 45 #include "amdgpu_ras.h" 46 47 /* 48 * KMS wrapper. 49 * - 3.0.0 - initial driver 50 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 51 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 52 * at the end of IBs. 53 * - 3.3.0 - Add VM support for UVD on supported hardware. 54 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 55 * - 3.5.0 - Add support for new UVD_NO_OP register. 56 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 57 * - 3.7.0 - Add support for VCE clock list packet 58 * - 3.8.0 - Add support raster config init in the kernel 59 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 60 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 61 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 62 * - 3.12.0 - Add query for double offchip LDS buffers 63 * - 3.13.0 - Add PRT support 64 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 65 * - 3.15.0 - Export more gpu info for gfx9 66 * - 3.16.0 - Add reserved vmid support 67 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 68 * - 3.18.0 - Export gpu always on cu bitmap 69 * - 3.19.0 - Add support for UVD MJPEG decode 70 * - 3.20.0 - Add support for local BOs 71 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 72 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 73 * - 3.23.0 - Add query for VRAM lost counter 74 * - 3.24.0 - Add high priority compute support for gfx9 75 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 76 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 77 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation. 78 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 79 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 80 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 81 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 82 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 83 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 84 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 85 */ 86 #define KMS_DRIVER_MAJOR 3 87 #define KMS_DRIVER_MINOR 34 88 #define KMS_DRIVER_PATCHLEVEL 0 89 90 #define AMDGPU_MAX_TIMEOUT_PARAM_LENTH 256 91 92 int amdgpu_vram_limit = 0; 93 int amdgpu_vis_vram_limit = 0; 94 int amdgpu_gart_size = -1; /* auto */ 95 int amdgpu_gtt_size = -1; /* auto */ 96 int amdgpu_moverate = -1; /* auto */ 97 int amdgpu_benchmarking = 0; 98 int amdgpu_testing = 0; 99 int amdgpu_audio = -1; 100 int amdgpu_disp_priority = 0; 101 int amdgpu_hw_i2c = 0; 102 int amdgpu_pcie_gen2 = -1; 103 int amdgpu_msi = -1; 104 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENTH]; 105 int amdgpu_dpm = -1; 106 int amdgpu_fw_load_type = -1; 107 int amdgpu_aspm = -1; 108 int amdgpu_runtime_pm = -1; 109 uint amdgpu_ip_block_mask = 0xffffffff; 110 int amdgpu_bapm = -1; 111 int amdgpu_deep_color = 0; 112 int amdgpu_vm_size = -1; 113 int amdgpu_vm_fragment_size = -1; 114 int amdgpu_vm_block_size = -1; 115 int amdgpu_vm_fault_stop = 0; 116 int amdgpu_vm_debug = 0; 117 int amdgpu_vm_update_mode = -1; 118 int amdgpu_exp_hw_support = 0; 119 int amdgpu_dc = -1; 120 int amdgpu_sched_jobs = 32; 121 int amdgpu_sched_hw_submission = 2; 122 uint amdgpu_pcie_gen_cap = 0; 123 uint amdgpu_pcie_lane_cap = 0; 124 uint amdgpu_cg_mask = 0xffffffff; 125 uint amdgpu_pg_mask = 0xffffffff; 126 uint amdgpu_sdma_phase_quantum = 32; 127 char *amdgpu_disable_cu = NULL; 128 char *amdgpu_virtual_display = NULL; 129 /* OverDrive(bit 14) disabled by default*/ 130 uint amdgpu_pp_feature_mask = 0xffffbfff; 131 int amdgpu_ngg = 0; 132 int amdgpu_prim_buf_per_se = 0; 133 int amdgpu_pos_buf_per_se = 0; 134 int amdgpu_cntl_sb_buf_per_se = 0; 135 int amdgpu_param_buf_per_se = 0; 136 int amdgpu_job_hang_limit = 0; 137 int amdgpu_lbpw = -1; 138 int amdgpu_compute_multipipe = -1; 139 int amdgpu_gpu_recovery = -1; /* auto */ 140 int amdgpu_emu_mode = 0; 141 uint amdgpu_smu_memory_pool_size = 0; 142 /* FBC (bit 0) disabled by default*/ 143 uint amdgpu_dc_feature_mask = 0; 144 int amdgpu_async_gfx_ring = 1; 145 int amdgpu_mcbp = 0; 146 int amdgpu_discovery = -1; 147 int amdgpu_mes = 0; 148 int amdgpu_noretry = 1; 149 int amdgpu_force_asic_type = -1; 150 151 struct amdgpu_mgpu_info mgpu_info = { 152 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 153 }; 154 int amdgpu_ras_enable = -1; 155 uint amdgpu_ras_mask = 0xfffffffb; 156 157 /** 158 * DOC: vramlimit (int) 159 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 160 */ 161 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 162 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 163 164 /** 165 * DOC: vis_vramlimit (int) 166 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 167 */ 168 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 169 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 170 171 /** 172 * DOC: gartsize (uint) 173 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic). 174 */ 175 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); 176 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 177 178 /** 179 * DOC: gttsize (int) 180 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM, 181 * otherwise 3/4 RAM size). 182 */ 183 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); 184 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 185 186 /** 187 * DOC: moverate (int) 188 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 189 */ 190 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 191 module_param_named(moverate, amdgpu_moverate, int, 0600); 192 193 /** 194 * DOC: benchmark (int) 195 * Run benchmarks. The default is 0 (Skip benchmarks). 196 */ 197 MODULE_PARM_DESC(benchmark, "Run benchmark"); 198 module_param_named(benchmark, amdgpu_benchmarking, int, 0444); 199 200 /** 201 * DOC: test (int) 202 * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test). 203 */ 204 MODULE_PARM_DESC(test, "Run tests"); 205 module_param_named(test, amdgpu_testing, int, 0444); 206 207 /** 208 * DOC: audio (int) 209 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 210 */ 211 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 212 module_param_named(audio, amdgpu_audio, int, 0444); 213 214 /** 215 * DOC: disp_priority (int) 216 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 217 */ 218 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 219 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 220 221 /** 222 * DOC: hw_i2c (int) 223 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 224 */ 225 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 226 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 227 228 /** 229 * DOC: pcie_gen2 (int) 230 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 231 */ 232 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 233 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 234 235 /** 236 * DOC: msi (int) 237 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 238 */ 239 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 240 module_param_named(msi, amdgpu_msi, int, 0444); 241 242 /** 243 * DOC: lockup_timeout (string) 244 * Set GPU scheduler timeout value in ms. 245 * 246 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 247 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 248 * to default timeout. 249 * - With one value specified, the setting will apply to all non-compute jobs. 250 * - With multiple values specified, the first one will be for GFX. The second one is for Compute. 251 * And the third and fourth ones are for SDMA and Video. 252 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 253 * jobs is 10000. And there is no timeout enforced on compute jobs. 254 */ 255 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: 10000 for non-compute jobs and infinity timeout for compute jobs." 256 " 0: keep default value. negative: infinity timeout), " 257 "format is [Non-Compute] or [GFX,Compute,SDMA,Video]"); 258 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 259 260 /** 261 * DOC: dpm (int) 262 * Override for dynamic power management setting 263 * (0 = disable, 1 = enable, 2 = enable sw smu driver for vega20) 264 * The default is -1 (auto). 265 */ 266 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 267 module_param_named(dpm, amdgpu_dpm, int, 0444); 268 269 /** 270 * DOC: fw_load_type (int) 271 * Set different firmware loading type for debugging (0 = direct, 1 = SMU, 2 = PSP). The default is -1 (auto). 272 */ 273 MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)"); 274 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 275 276 /** 277 * DOC: aspm (int) 278 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 279 */ 280 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 281 module_param_named(aspm, amdgpu_aspm, int, 0444); 282 283 /** 284 * DOC: runpm (int) 285 * Override for runtime power management control for dGPUs in PX/HG laptops. The amdgpu driver can dynamically power down 286 * the dGPU on PX/HG laptops when it is idle. The default is -1 (auto enable). Setting the value to 0 disables this functionality. 287 */ 288 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 289 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 290 291 /** 292 * DOC: ip_block_mask (uint) 293 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 294 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 295 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 296 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 297 */ 298 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 299 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 300 301 /** 302 * DOC: bapm (int) 303 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 304 * The default -1 (auto, enabled) 305 */ 306 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 307 module_param_named(bapm, amdgpu_bapm, int, 0444); 308 309 /** 310 * DOC: deep_color (int) 311 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 312 */ 313 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 314 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 315 316 /** 317 * DOC: vm_size (int) 318 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 319 */ 320 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 321 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 322 323 /** 324 * DOC: vm_fragment_size (int) 325 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 326 */ 327 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 328 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 329 330 /** 331 * DOC: vm_block_size (int) 332 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 333 */ 334 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 335 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 336 337 /** 338 * DOC: vm_fault_stop (int) 339 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 340 */ 341 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 342 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 343 344 /** 345 * DOC: vm_debug (int) 346 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 347 */ 348 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 349 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 350 351 /** 352 * DOC: vm_update_mode (int) 353 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 354 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 355 */ 356 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 357 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 358 359 /** 360 * DOC: exp_hw_support (int) 361 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 362 */ 363 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 364 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 365 366 /** 367 * DOC: dc (int) 368 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 369 */ 370 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 371 module_param_named(dc, amdgpu_dc, int, 0444); 372 373 /** 374 * DOC: sched_jobs (int) 375 * Override the max number of jobs supported in the sw queue. The default is 32. 376 */ 377 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 378 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 379 380 /** 381 * DOC: sched_hw_submission (int) 382 * Override the max number of HW submissions. The default is 2. 383 */ 384 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 385 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 386 387 /** 388 * DOC: ppfeaturemask (uint) 389 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 390 * The default is the current set of stable power features. 391 */ 392 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 393 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, uint, 0444); 394 395 /** 396 * DOC: pcie_gen_cap (uint) 397 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 398 * The default is 0 (automatic for each asic). 399 */ 400 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 401 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 402 403 /** 404 * DOC: pcie_lane_cap (uint) 405 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 406 * The default is 0 (automatic for each asic). 407 */ 408 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 409 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 410 411 /** 412 * DOC: cg_mask (uint) 413 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 414 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 415 */ 416 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 417 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); 418 419 /** 420 * DOC: pg_mask (uint) 421 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 422 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 423 */ 424 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 425 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 426 427 /** 428 * DOC: sdma_phase_quantum (uint) 429 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 430 */ 431 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 432 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 433 434 /** 435 * DOC: disable_cu (charp) 436 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 437 */ 438 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 439 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 440 441 /** 442 * DOC: virtual_display (charp) 443 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 444 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 445 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 446 * device at 26:00.0. The default is NULL. 447 */ 448 MODULE_PARM_DESC(virtual_display, 449 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 450 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 451 452 /** 453 * DOC: ngg (int) 454 * Set to enable Next Generation Graphics (1 = enable). The default is 0 (disabled). 455 */ 456 MODULE_PARM_DESC(ngg, "Next Generation Graphics (1 = enable, 0 = disable(default depending on gfx))"); 457 module_param_named(ngg, amdgpu_ngg, int, 0444); 458 459 /** 460 * DOC: prim_buf_per_se (int) 461 * Override the size of Primitive Buffer per Shader Engine in Byte. The default is 0 (depending on gfx). 462 */ 463 MODULE_PARM_DESC(prim_buf_per_se, "the size of Primitive Buffer per Shader Engine (default depending on gfx)"); 464 module_param_named(prim_buf_per_se, amdgpu_prim_buf_per_se, int, 0444); 465 466 /** 467 * DOC: pos_buf_per_se (int) 468 * Override the size of Position Buffer per Shader Engine in Byte. The default is 0 (depending on gfx). 469 */ 470 MODULE_PARM_DESC(pos_buf_per_se, "the size of Position Buffer per Shader Engine (default depending on gfx)"); 471 module_param_named(pos_buf_per_se, amdgpu_pos_buf_per_se, int, 0444); 472 473 /** 474 * DOC: cntl_sb_buf_per_se (int) 475 * Override the size of Control Sideband per Shader Engine in Byte. The default is 0 (depending on gfx). 476 */ 477 MODULE_PARM_DESC(cntl_sb_buf_per_se, "the size of Control Sideband per Shader Engine (default depending on gfx)"); 478 module_param_named(cntl_sb_buf_per_se, amdgpu_cntl_sb_buf_per_se, int, 0444); 479 480 /** 481 * DOC: param_buf_per_se (int) 482 * Override the size of Off-Chip Parameter Cache per Shader Engine in Byte. 483 * The default is 0 (depending on gfx). 484 */ 485 MODULE_PARM_DESC(param_buf_per_se, "the size of Off-Chip Parameter Cache per Shader Engine (default depending on gfx)"); 486 module_param_named(param_buf_per_se, amdgpu_param_buf_per_se, int, 0444); 487 488 /** 489 * DOC: job_hang_limit (int) 490 * Set how much time allow a job hang and not drop it. The default is 0. 491 */ 492 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 493 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 494 495 /** 496 * DOC: lbpw (int) 497 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 498 */ 499 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 500 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 501 502 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 503 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 504 505 /** 506 * DOC: gpu_recovery (int) 507 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 508 */ 509 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 510 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 511 512 /** 513 * DOC: emu_mode (int) 514 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 515 */ 516 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 517 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 518 519 /** 520 * DOC: ras_enable (int) 521 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 522 */ 523 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 524 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 525 526 /** 527 * DOC: ras_mask (uint) 528 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 529 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 530 */ 531 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 532 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 533 534 /** 535 * DOC: si_support (int) 536 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 537 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 538 * otherwise using amdgpu driver. 539 */ 540 #ifdef CONFIG_DRM_AMDGPU_SI 541 542 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 543 int amdgpu_si_support = 0; 544 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 545 #else 546 int amdgpu_si_support = 1; 547 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 548 #endif 549 550 module_param_named(si_support, amdgpu_si_support, int, 0444); 551 #endif 552 553 /** 554 * DOC: cik_support (int) 555 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 556 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 557 * otherwise using amdgpu driver. 558 */ 559 #ifdef CONFIG_DRM_AMDGPU_CIK 560 561 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 562 int amdgpu_cik_support = 0; 563 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 564 #else 565 int amdgpu_cik_support = 1; 566 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 567 #endif 568 569 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 570 #endif 571 572 /** 573 * DOC: smu_memory_pool_size (uint) 574 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 575 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 576 */ 577 MODULE_PARM_DESC(smu_memory_pool_size, 578 "reserve gtt for smu debug usage, 0 = disable," 579 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 580 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 581 582 /** 583 * DOC: async_gfx_ring (int) 584 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 585 */ 586 MODULE_PARM_DESC(async_gfx_ring, 587 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 588 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 589 590 /** 591 * DOC: mcbp (int) 592 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled) 593 */ 594 MODULE_PARM_DESC(mcbp, 595 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); 596 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 597 598 /** 599 * DOC: discovery (int) 600 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 601 * (-1 = auto (default), 0 = disabled, 1 = enabled) 602 */ 603 MODULE_PARM_DESC(discovery, 604 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 605 module_param_named(discovery, amdgpu_discovery, int, 0444); 606 607 /** 608 * DOC: mes (int) 609 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 610 * (0 = disabled (default), 1 = enabled) 611 */ 612 MODULE_PARM_DESC(mes, 613 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 614 module_param_named(mes, amdgpu_mes, int, 0444); 615 616 MODULE_PARM_DESC(noretry, 617 "Disable retry faults (0 = retry enabled, 1 = retry disabled (default))"); 618 module_param_named(noretry, amdgpu_noretry, int, 0644); 619 620 /** 621 * DOC: force_asic_type (int) 622 * A non negative value used to specify the asic type for all supported GPUs. 623 */ 624 MODULE_PARM_DESC(force_asic_type, 625 "A non negative value used to specify the asic type for all supported GPUs"); 626 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 627 628 629 630 #ifdef CONFIG_HSA_AMD 631 /** 632 * DOC: sched_policy (int) 633 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 634 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 635 * assigns queues to HQDs. 636 */ 637 int sched_policy = KFD_SCHED_POLICY_HWS; 638 module_param(sched_policy, int, 0444); 639 MODULE_PARM_DESC(sched_policy, 640 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 641 642 /** 643 * DOC: hws_max_conc_proc (int) 644 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 645 * number of VMIDs assigned to the HWS, which is also the default. 646 */ 647 int hws_max_conc_proc = 8; 648 module_param(hws_max_conc_proc, int, 0444); 649 MODULE_PARM_DESC(hws_max_conc_proc, 650 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 651 652 /** 653 * DOC: cwsr_enable (int) 654 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 655 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 656 * disables it. 657 */ 658 int cwsr_enable = 1; 659 module_param(cwsr_enable, int, 0444); 660 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 661 662 /** 663 * DOC: max_num_of_queues_per_device (int) 664 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 665 * is 4096. 666 */ 667 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 668 module_param(max_num_of_queues_per_device, int, 0444); 669 MODULE_PARM_DESC(max_num_of_queues_per_device, 670 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 671 672 /** 673 * DOC: send_sigterm (int) 674 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 675 * but just print errors on dmesg. Setting 1 enables sending sigterm. 676 */ 677 int send_sigterm; 678 module_param(send_sigterm, int, 0444); 679 MODULE_PARM_DESC(send_sigterm, 680 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 681 682 /** 683 * DOC: debug_largebar (int) 684 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 685 * system. This limits the VRAM size reported to ROCm applications to the visible 686 * size, usually 256MB. 687 * Default value is 0, diabled. 688 */ 689 int debug_largebar; 690 module_param(debug_largebar, int, 0444); 691 MODULE_PARM_DESC(debug_largebar, 692 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 693 694 /** 695 * DOC: ignore_crat (int) 696 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 697 * table to get information about AMD APUs. This option can serve as a workaround on 698 * systems with a broken CRAT table. 699 */ 700 int ignore_crat; 701 module_param(ignore_crat, int, 0444); 702 MODULE_PARM_DESC(ignore_crat, 703 "Ignore CRAT table during KFD initialization (0 = use CRAT (default), 1 = ignore CRAT)"); 704 705 /** 706 * DOC: halt_if_hws_hang (int) 707 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 708 * Setting 1 enables halt on hang. 709 */ 710 int halt_if_hws_hang; 711 module_param(halt_if_hws_hang, int, 0644); 712 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 713 714 /** 715 * DOC: hws_gws_support(bool) 716 * Whether HWS support gws barriers. Default value: false (not supported) 717 * This will be replaced with a MEC firmware version check once firmware 718 * is ready 719 */ 720 bool hws_gws_support; 721 module_param(hws_gws_support, bool, 0444); 722 MODULE_PARM_DESC(hws_gws_support, "MEC FW support gws barriers (false = not supported (Default), true = supported)"); 723 724 /** 725 * DOC: queue_preemption_timeout_ms (int) 726 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 727 */ 728 int queue_preemption_timeout_ms = 9000; 729 module_param(queue_preemption_timeout_ms, int, 0644); 730 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 731 #endif 732 733 /** 734 * DOC: dcfeaturemask (uint) 735 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 736 * The default is the current set of stable display features. 737 */ 738 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 739 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 740 741 /** 742 * DOC: abmlevel (uint) 743 * Override the default ABM (Adaptive Backlight Management) level used for DC 744 * enabled hardware. Requires DMCU to be supported and loaded. 745 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 746 * default. Values 1-4 control the maximum allowable brightness reduction via 747 * the ABM algorithm, with 1 being the least reduction and 4 being the most 748 * reduction. 749 * 750 * Defaults to 0, or disabled. Userspace can still override this level later 751 * after boot. 752 */ 753 uint amdgpu_dm_abm_level = 0; 754 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 755 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 756 757 static const struct pci_device_id pciidlist[] = { 758 #ifdef CONFIG_DRM_AMDGPU_SI 759 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 760 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 761 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 762 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 763 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 764 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 765 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 766 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 767 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 768 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 769 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 770 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 771 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 772 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 773 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 774 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 775 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 776 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 777 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 778 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 779 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 780 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 781 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 782 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 783 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 784 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 785 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 786 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 787 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 788 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 789 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 790 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 791 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 792 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 793 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 794 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 795 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 796 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 797 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 798 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 799 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 800 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 801 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 802 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 803 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 804 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 805 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 806 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 807 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 808 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 809 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 810 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 811 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 812 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 813 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 814 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 815 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 816 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 817 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 818 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 819 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 820 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 821 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 822 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 823 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 824 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 825 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 826 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 827 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 828 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 829 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 830 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 831 #endif 832 #ifdef CONFIG_DRM_AMDGPU_CIK 833 /* Kaveri */ 834 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 835 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 836 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 837 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 838 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 839 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 840 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 841 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 842 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 843 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 844 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 845 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 846 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 847 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 848 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 849 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 850 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 851 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 852 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 853 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 854 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 855 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 856 /* Bonaire */ 857 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 858 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 859 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 860 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 861 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 862 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 863 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 864 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 865 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 866 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 867 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 868 /* Hawaii */ 869 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 870 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 871 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 872 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 873 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 874 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 875 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 876 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 877 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 878 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 879 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 880 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 881 /* Kabini */ 882 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 883 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 884 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 885 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 886 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 887 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 888 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 889 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 890 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 891 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 892 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 893 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 894 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 895 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 896 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 897 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 898 /* mullins */ 899 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 900 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 901 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 902 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 903 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 904 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 905 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 906 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 907 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 908 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 909 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 910 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 911 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 912 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 913 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 914 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 915 #endif 916 /* topaz */ 917 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 918 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 919 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 920 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 921 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 922 /* tonga */ 923 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 924 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 925 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 926 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 927 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 928 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 929 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 930 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 931 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 932 /* fiji */ 933 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 934 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 935 /* carrizo */ 936 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 937 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 938 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 939 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 940 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 941 /* stoney */ 942 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 943 /* Polaris11 */ 944 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 945 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 946 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 947 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 948 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 949 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 950 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 951 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 952 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 953 /* Polaris10 */ 954 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 955 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 956 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 957 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 958 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 959 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 960 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 961 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 962 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 963 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 964 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 965 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 966 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 967 /* Polaris12 */ 968 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 969 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 970 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 971 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 972 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 973 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 974 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 975 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 976 /* VEGAM */ 977 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 978 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 979 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 980 /* Vega 10 */ 981 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 982 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 983 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 984 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 985 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 986 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 987 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 988 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 989 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 990 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 991 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 992 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 993 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 994 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 995 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 996 /* Vega 12 */ 997 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 998 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 999 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1000 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1001 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1002 /* Vega 20 */ 1003 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1004 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1005 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1006 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1007 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1008 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1009 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1010 /* Raven */ 1011 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1012 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1013 /* Arcturus */ 1014 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT}, 1015 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT}, 1016 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT}, 1017 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT}, 1018 /* Navi10 */ 1019 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1020 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1021 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1022 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1023 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1024 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1025 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1026 /* Navi14 */ 1027 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1028 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1029 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1030 1031 /* Renoir */ 1032 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU|AMD_EXP_HW_SUPPORT}, 1033 1034 {0, 0, 0} 1035 }; 1036 1037 MODULE_DEVICE_TABLE(pci, pciidlist); 1038 1039 static struct drm_driver kms_driver; 1040 1041 static int amdgpu_pci_probe(struct pci_dev *pdev, 1042 const struct pci_device_id *ent) 1043 { 1044 struct drm_device *dev; 1045 unsigned long flags = ent->driver_data; 1046 int ret, retry = 0; 1047 bool supports_atomic = false; 1048 1049 if (!amdgpu_virtual_display && 1050 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 1051 supports_atomic = true; 1052 1053 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 1054 DRM_INFO("This hardware requires experimental hardware support.\n" 1055 "See modparam exp_hw_support\n"); 1056 return -ENODEV; 1057 } 1058 1059 /* Get rid of things like offb */ 1060 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, 0, "amdgpudrmfb"); 1061 if (ret) 1062 return ret; 1063 1064 dev = drm_dev_alloc(&kms_driver, &pdev->dev); 1065 if (IS_ERR(dev)) 1066 return PTR_ERR(dev); 1067 1068 if (!supports_atomic) 1069 dev->driver_features &= ~DRIVER_ATOMIC; 1070 1071 ret = pci_enable_device(pdev); 1072 if (ret) 1073 goto err_free; 1074 1075 dev->pdev = pdev; 1076 1077 pci_set_drvdata(pdev, dev); 1078 1079 retry_init: 1080 ret = drm_dev_register(dev, ent->driver_data); 1081 if (ret == -EAGAIN && ++retry <= 3) { 1082 DRM_INFO("retry init %d\n", retry); 1083 /* Don't request EX mode too frequently which is attacking */ 1084 msleep(5000); 1085 goto retry_init; 1086 } else if (ret) 1087 goto err_pci; 1088 1089 return 0; 1090 1091 err_pci: 1092 pci_disable_device(pdev); 1093 err_free: 1094 drm_dev_put(dev); 1095 return ret; 1096 } 1097 1098 static void 1099 amdgpu_pci_remove(struct pci_dev *pdev) 1100 { 1101 struct drm_device *dev = pci_get_drvdata(pdev); 1102 1103 DRM_ERROR("Device removal is currently not supported outside of fbcon\n"); 1104 drm_dev_unplug(dev); 1105 drm_dev_put(dev); 1106 pci_disable_device(pdev); 1107 pci_set_drvdata(pdev, NULL); 1108 } 1109 1110 static void 1111 amdgpu_pci_shutdown(struct pci_dev *pdev) 1112 { 1113 struct drm_device *dev = pci_get_drvdata(pdev); 1114 struct amdgpu_device *adev = dev->dev_private; 1115 1116 if (amdgpu_ras_intr_triggered()) 1117 return; 1118 1119 /* if we are running in a VM, make sure the device 1120 * torn down properly on reboot/shutdown. 1121 * unfortunately we can't detect certain 1122 * hypervisors so just do this all the time. 1123 */ 1124 adev->mp1_state = PP_MP1_STATE_UNLOAD; 1125 amdgpu_device_ip_suspend(adev); 1126 adev->mp1_state = PP_MP1_STATE_NONE; 1127 } 1128 1129 static int amdgpu_pmops_suspend(struct device *dev) 1130 { 1131 struct drm_device *drm_dev = dev_get_drvdata(dev); 1132 1133 return amdgpu_device_suspend(drm_dev, true, true); 1134 } 1135 1136 static int amdgpu_pmops_resume(struct device *dev) 1137 { 1138 struct drm_device *drm_dev = dev_get_drvdata(dev); 1139 1140 /* GPU comes up enabled by the bios on resume */ 1141 if (amdgpu_device_is_px(drm_dev)) { 1142 pm_runtime_disable(dev); 1143 pm_runtime_set_active(dev); 1144 pm_runtime_enable(dev); 1145 } 1146 1147 return amdgpu_device_resume(drm_dev, true, true); 1148 } 1149 1150 static int amdgpu_pmops_freeze(struct device *dev) 1151 { 1152 struct drm_device *drm_dev = dev_get_drvdata(dev); 1153 1154 return amdgpu_device_suspend(drm_dev, false, true); 1155 } 1156 1157 static int amdgpu_pmops_thaw(struct device *dev) 1158 { 1159 struct drm_device *drm_dev = dev_get_drvdata(dev); 1160 1161 return amdgpu_device_resume(drm_dev, false, true); 1162 } 1163 1164 static int amdgpu_pmops_poweroff(struct device *dev) 1165 { 1166 struct drm_device *drm_dev = dev_get_drvdata(dev); 1167 1168 return amdgpu_device_suspend(drm_dev, true, true); 1169 } 1170 1171 static int amdgpu_pmops_restore(struct device *dev) 1172 { 1173 struct drm_device *drm_dev = dev_get_drvdata(dev); 1174 1175 return amdgpu_device_resume(drm_dev, false, true); 1176 } 1177 1178 static int amdgpu_pmops_runtime_suspend(struct device *dev) 1179 { 1180 struct pci_dev *pdev = to_pci_dev(dev); 1181 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1182 int ret; 1183 1184 if (!amdgpu_device_is_px(drm_dev)) { 1185 pm_runtime_forbid(dev); 1186 return -EBUSY; 1187 } 1188 1189 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1190 drm_kms_helper_poll_disable(drm_dev); 1191 1192 ret = amdgpu_device_suspend(drm_dev, false, false); 1193 pci_save_state(pdev); 1194 pci_disable_device(pdev); 1195 pci_ignore_hotplug(pdev); 1196 if (amdgpu_is_atpx_hybrid()) 1197 pci_set_power_state(pdev, PCI_D3cold); 1198 else if (!amdgpu_has_atpx_dgpu_power_cntl()) 1199 pci_set_power_state(pdev, PCI_D3hot); 1200 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 1201 1202 return 0; 1203 } 1204 1205 static int amdgpu_pmops_runtime_resume(struct device *dev) 1206 { 1207 struct pci_dev *pdev = to_pci_dev(dev); 1208 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1209 int ret; 1210 1211 if (!amdgpu_device_is_px(drm_dev)) 1212 return -EINVAL; 1213 1214 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1215 1216 if (amdgpu_is_atpx_hybrid() || 1217 !amdgpu_has_atpx_dgpu_power_cntl()) 1218 pci_set_power_state(pdev, PCI_D0); 1219 pci_restore_state(pdev); 1220 ret = pci_enable_device(pdev); 1221 if (ret) 1222 return ret; 1223 pci_set_master(pdev); 1224 1225 ret = amdgpu_device_resume(drm_dev, false, false); 1226 drm_kms_helper_poll_enable(drm_dev); 1227 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 1228 return 0; 1229 } 1230 1231 static int amdgpu_pmops_runtime_idle(struct device *dev) 1232 { 1233 struct drm_device *drm_dev = dev_get_drvdata(dev); 1234 struct drm_crtc *crtc; 1235 1236 if (!amdgpu_device_is_px(drm_dev)) { 1237 pm_runtime_forbid(dev); 1238 return -EBUSY; 1239 } 1240 1241 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 1242 if (crtc->enabled) { 1243 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 1244 return -EBUSY; 1245 } 1246 } 1247 1248 pm_runtime_mark_last_busy(dev); 1249 pm_runtime_autosuspend(dev); 1250 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 1251 return 1; 1252 } 1253 1254 long amdgpu_drm_ioctl(struct file *filp, 1255 unsigned int cmd, unsigned long arg) 1256 { 1257 struct drm_file *file_priv = filp->private_data; 1258 struct drm_device *dev; 1259 long ret; 1260 dev = file_priv->minor->dev; 1261 ret = pm_runtime_get_sync(dev->dev); 1262 if (ret < 0) 1263 return ret; 1264 1265 ret = drm_ioctl(filp, cmd, arg); 1266 1267 pm_runtime_mark_last_busy(dev->dev); 1268 pm_runtime_put_autosuspend(dev->dev); 1269 return ret; 1270 } 1271 1272 static const struct dev_pm_ops amdgpu_pm_ops = { 1273 .suspend = amdgpu_pmops_suspend, 1274 .resume = amdgpu_pmops_resume, 1275 .freeze = amdgpu_pmops_freeze, 1276 .thaw = amdgpu_pmops_thaw, 1277 .poweroff = amdgpu_pmops_poweroff, 1278 .restore = amdgpu_pmops_restore, 1279 .runtime_suspend = amdgpu_pmops_runtime_suspend, 1280 .runtime_resume = amdgpu_pmops_runtime_resume, 1281 .runtime_idle = amdgpu_pmops_runtime_idle, 1282 }; 1283 1284 static int amdgpu_flush(struct file *f, fl_owner_t id) 1285 { 1286 struct drm_file *file_priv = f->private_data; 1287 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1288 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 1289 1290 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 1291 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 1292 1293 return timeout >= 0 ? 0 : timeout; 1294 } 1295 1296 static const struct file_operations amdgpu_driver_kms_fops = { 1297 .owner = THIS_MODULE, 1298 .open = drm_open, 1299 .flush = amdgpu_flush, 1300 .release = drm_release, 1301 .unlocked_ioctl = amdgpu_drm_ioctl, 1302 .mmap = amdgpu_mmap, 1303 .poll = drm_poll, 1304 .read = drm_read, 1305 #ifdef CONFIG_COMPAT 1306 .compat_ioctl = amdgpu_kms_compat_ioctl, 1307 #endif 1308 }; 1309 1310 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 1311 { 1312 struct drm_file *file; 1313 1314 if (!filp) 1315 return -EINVAL; 1316 1317 if (filp->f_op != &amdgpu_driver_kms_fops) { 1318 return -EINVAL; 1319 } 1320 1321 file = filp->private_data; 1322 *fpriv = file->driver_priv; 1323 return 0; 1324 } 1325 1326 int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev) 1327 { 1328 char *input = amdgpu_lockup_timeout; 1329 char *timeout_setting = NULL; 1330 int index = 0; 1331 long timeout; 1332 int ret = 0; 1333 1334 /* 1335 * By default timeout for non compute jobs is 10000. 1336 * And there is no timeout enforced on compute jobs. 1337 */ 1338 adev->gfx_timeout = msecs_to_jiffies(10000); 1339 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout; 1340 adev->compute_timeout = MAX_SCHEDULE_TIMEOUT; 1341 1342 if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENTH)) { 1343 while ((timeout_setting = strsep(&input, ",")) && 1344 strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENTH)) { 1345 ret = kstrtol(timeout_setting, 0, &timeout); 1346 if (ret) 1347 return ret; 1348 1349 if (timeout == 0) { 1350 index++; 1351 continue; 1352 } else if (timeout < 0) { 1353 timeout = MAX_SCHEDULE_TIMEOUT; 1354 } else { 1355 timeout = msecs_to_jiffies(timeout); 1356 } 1357 1358 switch (index++) { 1359 case 0: 1360 adev->gfx_timeout = timeout; 1361 break; 1362 case 1: 1363 adev->compute_timeout = timeout; 1364 break; 1365 case 2: 1366 adev->sdma_timeout = timeout; 1367 break; 1368 case 3: 1369 adev->video_timeout = timeout; 1370 break; 1371 default: 1372 break; 1373 } 1374 } 1375 /* 1376 * There is only one value specified and 1377 * it should apply to all non-compute jobs. 1378 */ 1379 if (index == 1) 1380 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout; 1381 } 1382 1383 return ret; 1384 } 1385 1386 static bool 1387 amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe, 1388 bool in_vblank_irq, int *vpos, int *hpos, 1389 ktime_t *stime, ktime_t *etime, 1390 const struct drm_display_mode *mode) 1391 { 1392 return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos, 1393 stime, etime, mode); 1394 } 1395 1396 static struct drm_driver kms_driver = { 1397 .driver_features = 1398 DRIVER_USE_AGP | DRIVER_ATOMIC | 1399 DRIVER_GEM | 1400 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ, 1401 .load = amdgpu_driver_load_kms, 1402 .open = amdgpu_driver_open_kms, 1403 .postclose = amdgpu_driver_postclose_kms, 1404 .lastclose = amdgpu_driver_lastclose_kms, 1405 .unload = amdgpu_driver_unload_kms, 1406 .get_vblank_counter = amdgpu_get_vblank_counter_kms, 1407 .enable_vblank = amdgpu_enable_vblank_kms, 1408 .disable_vblank = amdgpu_disable_vblank_kms, 1409 .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos, 1410 .get_scanout_position = amdgpu_get_crtc_scanout_position, 1411 .irq_handler = amdgpu_irq_handler, 1412 .ioctls = amdgpu_ioctls_kms, 1413 .gem_free_object_unlocked = amdgpu_gem_object_free, 1414 .gem_open_object = amdgpu_gem_object_open, 1415 .gem_close_object = amdgpu_gem_object_close, 1416 .dumb_create = amdgpu_mode_dumb_create, 1417 .dumb_map_offset = amdgpu_mode_dumb_mmap, 1418 .fops = &amdgpu_driver_kms_fops, 1419 1420 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 1421 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 1422 .gem_prime_export = amdgpu_gem_prime_export, 1423 .gem_prime_import = amdgpu_gem_prime_import, 1424 .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table, 1425 .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table, 1426 .gem_prime_vmap = amdgpu_gem_prime_vmap, 1427 .gem_prime_vunmap = amdgpu_gem_prime_vunmap, 1428 .gem_prime_mmap = amdgpu_gem_prime_mmap, 1429 1430 .name = DRIVER_NAME, 1431 .desc = DRIVER_DESC, 1432 .date = DRIVER_DATE, 1433 .major = KMS_DRIVER_MAJOR, 1434 .minor = KMS_DRIVER_MINOR, 1435 .patchlevel = KMS_DRIVER_PATCHLEVEL, 1436 }; 1437 1438 static struct pci_driver amdgpu_kms_pci_driver = { 1439 .name = DRIVER_NAME, 1440 .id_table = pciidlist, 1441 .probe = amdgpu_pci_probe, 1442 .remove = amdgpu_pci_remove, 1443 .shutdown = amdgpu_pci_shutdown, 1444 .driver.pm = &amdgpu_pm_ops, 1445 }; 1446 1447 1448 1449 static int __init amdgpu_init(void) 1450 { 1451 int r; 1452 1453 if (vgacon_text_force()) { 1454 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); 1455 return -EINVAL; 1456 } 1457 1458 r = amdgpu_sync_init(); 1459 if (r) 1460 goto error_sync; 1461 1462 r = amdgpu_fence_slab_init(); 1463 if (r) 1464 goto error_fence; 1465 1466 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 1467 kms_driver.num_ioctls = amdgpu_max_kms_ioctl; 1468 amdgpu_register_atpx_handler(); 1469 1470 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 1471 amdgpu_amdkfd_init(); 1472 1473 /* let modprobe override vga console setting */ 1474 return pci_register_driver(&amdgpu_kms_pci_driver); 1475 1476 error_fence: 1477 amdgpu_sync_fini(); 1478 1479 error_sync: 1480 return r; 1481 } 1482 1483 static void __exit amdgpu_exit(void) 1484 { 1485 amdgpu_amdkfd_fini(); 1486 pci_unregister_driver(&amdgpu_kms_pci_driver); 1487 amdgpu_unregister_atpx_handler(); 1488 amdgpu_sync_fini(); 1489 amdgpu_fence_slab_fini(); 1490 } 1491 1492 module_init(amdgpu_init); 1493 module_exit(amdgpu_exit); 1494 1495 MODULE_AUTHOR(DRIVER_AUTHOR); 1496 MODULE_DESCRIPTION(DRIVER_DESC); 1497 MODULE_LICENSE("GPL and additional rights"); 1498