1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_drv.h> 27 #include <drm/drm_fbdev_generic.h> 28 #include <drm/drm_gem.h> 29 #include <drm/drm_managed.h> 30 #include <drm/drm_pciids.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/drm_vblank.h> 33 34 #include <linux/cc_platform.h> 35 #include <linux/dynamic_debug.h> 36 #include <linux/module.h> 37 #include <linux/mmu_notifier.h> 38 #include <linux/pm_runtime.h> 39 #include <linux/suspend.h> 40 #include <linux/vga_switcheroo.h> 41 42 #include "amdgpu.h" 43 #include "amdgpu_amdkfd.h" 44 #include "amdgpu_dma_buf.h" 45 #include "amdgpu_drv.h" 46 #include "amdgpu_fdinfo.h" 47 #include "amdgpu_irq.h" 48 #include "amdgpu_psp.h" 49 #include "amdgpu_ras.h" 50 #include "amdgpu_reset.h" 51 #include "amdgpu_sched.h" 52 #include "amdgpu_xgmi.h" 53 #include "../amdxcp/amdgpu_xcp_drv.h" 54 55 /* 56 * KMS wrapper. 57 * - 3.0.0 - initial driver 58 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 59 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 60 * at the end of IBs. 61 * - 3.3.0 - Add VM support for UVD on supported hardware. 62 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 63 * - 3.5.0 - Add support for new UVD_NO_OP register. 64 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 65 * - 3.7.0 - Add support for VCE clock list packet 66 * - 3.8.0 - Add support raster config init in the kernel 67 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 68 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 69 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 70 * - 3.12.0 - Add query for double offchip LDS buffers 71 * - 3.13.0 - Add PRT support 72 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 73 * - 3.15.0 - Export more gpu info for gfx9 74 * - 3.16.0 - Add reserved vmid support 75 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 76 * - 3.18.0 - Export gpu always on cu bitmap 77 * - 3.19.0 - Add support for UVD MJPEG decode 78 * - 3.20.0 - Add support for local BOs 79 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 80 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 81 * - 3.23.0 - Add query for VRAM lost counter 82 * - 3.24.0 - Add high priority compute support for gfx9 83 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 84 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 85 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation. 86 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 87 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 88 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 89 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 90 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 91 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 92 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 93 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 94 * - 3.36.0 - Allow reading more status registers on si/cik 95 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 96 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 97 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 98 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 99 * - 3.41.0 - Add video codec query 100 * - 3.42.0 - Add 16bpc fixed point display support 101 * - 3.43.0 - Add device hot plug/unplug support 102 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 103 * - 3.45.0 - Add context ioctl stable pstate interface 104 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm 105 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags 106 * - 3.48.0 - Add IP discovery version info to HW INFO 107 * - 3.49.0 - Add gang submit into CS IOCTL 108 * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock 109 * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock 110 * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl 111 * 3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields: 112 * tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size, 113 * gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi 114 * 3.53.0 - Support for GFX11 CP GFX shadowing 115 * 3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support 116 * - 3.55.0 - Add AMDGPU_INFO_GPUVM_FAULT query 117 * - 3.56.0 - Update IB start address and size alignment for decode and encode 118 * - 3.57.0 - Compute tunneling on GFX10+ 119 */ 120 #define KMS_DRIVER_MAJOR 3 121 #define KMS_DRIVER_MINOR 57 122 #define KMS_DRIVER_PATCHLEVEL 0 123 124 /* 125 * amdgpu.debug module options. Are all disabled by default 126 */ 127 enum AMDGPU_DEBUG_MASK { 128 AMDGPU_DEBUG_VM = BIT(0), 129 AMDGPU_DEBUG_LARGEBAR = BIT(1), 130 AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY = BIT(2), 131 AMDGPU_DEBUG_USE_VRAM_FW_BUF = BIT(3), 132 AMDGPU_DEBUG_ENABLE_RAS_ACA = BIT(4), 133 }; 134 135 unsigned int amdgpu_vram_limit = UINT_MAX; 136 int amdgpu_vis_vram_limit; 137 int amdgpu_gart_size = -1; /* auto */ 138 int amdgpu_gtt_size = -1; /* auto */ 139 int amdgpu_moverate = -1; /* auto */ 140 int amdgpu_audio = -1; 141 int amdgpu_disp_priority; 142 int amdgpu_hw_i2c; 143 int amdgpu_pcie_gen2 = -1; 144 int amdgpu_msi = -1; 145 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 146 int amdgpu_dpm = -1; 147 int amdgpu_fw_load_type = -1; 148 int amdgpu_aspm = -1; 149 int amdgpu_runtime_pm = -1; 150 uint amdgpu_ip_block_mask = 0xffffffff; 151 int amdgpu_bapm = -1; 152 int amdgpu_deep_color; 153 int amdgpu_vm_size = -1; 154 int amdgpu_vm_fragment_size = -1; 155 int amdgpu_vm_block_size = -1; 156 int amdgpu_vm_fault_stop; 157 int amdgpu_vm_update_mode = -1; 158 int amdgpu_exp_hw_support; 159 int amdgpu_dc = -1; 160 int amdgpu_sched_jobs = 32; 161 int amdgpu_sched_hw_submission = 2; 162 uint amdgpu_pcie_gen_cap; 163 uint amdgpu_pcie_lane_cap; 164 u64 amdgpu_cg_mask = 0xffffffffffffffff; 165 uint amdgpu_pg_mask = 0xffffffff; 166 uint amdgpu_sdma_phase_quantum = 32; 167 char *amdgpu_disable_cu; 168 char *amdgpu_virtual_display; 169 bool enforce_isolation; 170 /* 171 * OverDrive(bit 14) disabled by default 172 * GFX DCS(bit 19) disabled by default 173 */ 174 uint amdgpu_pp_feature_mask = 0xfff7bfff; 175 uint amdgpu_force_long_training; 176 int amdgpu_lbpw = -1; 177 int amdgpu_compute_multipipe = -1; 178 int amdgpu_gpu_recovery = -1; /* auto */ 179 int amdgpu_emu_mode; 180 uint amdgpu_smu_memory_pool_size; 181 int amdgpu_smu_pptable_id = -1; 182 /* 183 * FBC (bit 0) disabled by default 184 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 185 * - With this, for multiple monitors in sync(e.g. with the same model), 186 * mclk switching will be allowed. And the mclk will be not foced to the 187 * highest. That helps saving some idle power. 188 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 189 * PSR (bit 3) disabled by default 190 * EDP NO POWER SEQUENCING (bit 4) disabled by default 191 */ 192 uint amdgpu_dc_feature_mask = 2; 193 uint amdgpu_dc_debug_mask; 194 uint amdgpu_dc_visual_confirm; 195 int amdgpu_async_gfx_ring = 1; 196 int amdgpu_mcbp = -1; 197 int amdgpu_discovery = -1; 198 int amdgpu_mes; 199 int amdgpu_mes_log_enable = 0; 200 int amdgpu_mes_kiq; 201 int amdgpu_uni_mes = 1; 202 int amdgpu_noretry = -1; 203 int amdgpu_force_asic_type = -1; 204 int amdgpu_tmz = -1; /* auto */ 205 uint amdgpu_freesync_vid_mode; 206 int amdgpu_reset_method = -1; /* auto */ 207 int amdgpu_jpeg_test; 208 int amdgpu_num_kcq = -1; 209 int amdgpu_smartshift_bias; 210 int amdgpu_use_xgmi_p2p = 1; 211 int amdgpu_vcnfw_log; 212 int amdgpu_sg_display = -1; /* auto */ 213 int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE; 214 int amdgpu_umsch_mm; 215 int amdgpu_seamless = -1; /* auto */ 216 uint amdgpu_debug_mask; 217 int amdgpu_agp = -1; /* auto */ 218 int amdgpu_wbrf = -1; 219 int amdgpu_damage_clips = -1; /* auto */ 220 int amdgpu_umsch_mm_fwlog; 221 222 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 223 224 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 225 "DRM_UT_CORE", 226 "DRM_UT_DRIVER", 227 "DRM_UT_KMS", 228 "DRM_UT_PRIME", 229 "DRM_UT_ATOMIC", 230 "DRM_UT_VBL", 231 "DRM_UT_STATE", 232 "DRM_UT_LEASE", 233 "DRM_UT_DP", 234 "DRM_UT_DRMRES"); 235 236 struct amdgpu_mgpu_info mgpu_info = { 237 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 238 .delayed_reset_work = __DELAYED_WORK_INITIALIZER( 239 mgpu_info.delayed_reset_work, 240 amdgpu_drv_delayed_reset_work_handler, 0), 241 }; 242 int amdgpu_ras_enable = -1; 243 uint amdgpu_ras_mask = 0xffffffff; 244 int amdgpu_bad_page_threshold = -1; 245 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 246 .timeout_fatal_disable = false, 247 .period = 0x0, /* default to 0x0 (timeout disable) */ 248 }; 249 250 /** 251 * DOC: vramlimit (int) 252 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 253 */ 254 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 255 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 256 257 /** 258 * DOC: vis_vramlimit (int) 259 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 260 */ 261 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 262 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 263 264 /** 265 * DOC: gartsize (uint) 266 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing. 267 * The default is -1 (The size depends on asic). 268 */ 269 MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)"); 270 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 271 272 /** 273 * DOC: gttsize (int) 274 * Restrict the size of GTT domain (for userspace use) in MiB for testing. 275 * The default is -1 (Use 1/2 RAM, minimum value is 3GB). 276 */ 277 MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)"); 278 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 279 280 /** 281 * DOC: moverate (int) 282 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 283 */ 284 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 285 module_param_named(moverate, amdgpu_moverate, int, 0600); 286 287 /** 288 * DOC: audio (int) 289 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 290 */ 291 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 292 module_param_named(audio, amdgpu_audio, int, 0444); 293 294 /** 295 * DOC: disp_priority (int) 296 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 297 */ 298 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 299 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 300 301 /** 302 * DOC: hw_i2c (int) 303 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 304 */ 305 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 306 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 307 308 /** 309 * DOC: pcie_gen2 (int) 310 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 311 */ 312 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 313 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 314 315 /** 316 * DOC: msi (int) 317 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 318 */ 319 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 320 module_param_named(msi, amdgpu_msi, int, 0444); 321 322 /** 323 * DOC: lockup_timeout (string) 324 * Set GPU scheduler timeout value in ms. 325 * 326 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 327 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 328 * to the default timeout. 329 * 330 * - With one value specified, the setting will apply to all non-compute jobs. 331 * - With multiple values specified, the first one will be for GFX. 332 * The second one is for Compute. The third and fourth ones are 333 * for SDMA and Video. 334 * 335 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 336 * jobs is 10000. The timeout for compute is 60000. 337 */ 338 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 339 "for passthrough or sriov, 10000 for all jobs. 0: keep default value. negative: infinity timeout), format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 340 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 341 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 342 343 /** 344 * DOC: dpm (int) 345 * Override for dynamic power management setting 346 * (0 = disable, 1 = enable) 347 * The default is -1 (auto). 348 */ 349 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 350 module_param_named(dpm, amdgpu_dpm, int, 0444); 351 352 /** 353 * DOC: fw_load_type (int) 354 * Set different firmware loading type for debugging, if supported. 355 * Set to 0 to force direct loading if supported by the ASIC. Set 356 * to -1 to select the default loading mode for the ASIC, as defined 357 * by the driver. The default is -1 (auto). 358 */ 359 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); 360 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 361 362 /** 363 * DOC: aspm (int) 364 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 365 */ 366 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 367 module_param_named(aspm, amdgpu_aspm, int, 0444); 368 369 /** 370 * DOC: runpm (int) 371 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 372 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 373 * Setting the value to 0 disables this functionality. 374 * Setting the value to -2 is auto enabled with power down when displays are attached. 375 */ 376 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto, -2 = auto with displays)"); 377 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 378 379 /** 380 * DOC: ip_block_mask (uint) 381 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 382 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 383 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 384 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 385 */ 386 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 387 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 388 389 /** 390 * DOC: bapm (int) 391 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 392 * The default -1 (auto, enabled) 393 */ 394 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 395 module_param_named(bapm, amdgpu_bapm, int, 0444); 396 397 /** 398 * DOC: deep_color (int) 399 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 400 */ 401 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 402 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 403 404 /** 405 * DOC: vm_size (int) 406 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 407 */ 408 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 409 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 410 411 /** 412 * DOC: vm_fragment_size (int) 413 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 414 */ 415 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 416 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 417 418 /** 419 * DOC: vm_block_size (int) 420 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 421 */ 422 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 423 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 424 425 /** 426 * DOC: vm_fault_stop (int) 427 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 428 */ 429 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 430 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 431 432 /** 433 * DOC: vm_update_mode (int) 434 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 435 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 436 */ 437 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 438 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 439 440 /** 441 * DOC: exp_hw_support (int) 442 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 443 */ 444 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 445 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 446 447 /** 448 * DOC: dc (int) 449 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 450 */ 451 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 452 module_param_named(dc, amdgpu_dc, int, 0444); 453 454 /** 455 * DOC: sched_jobs (int) 456 * Override the max number of jobs supported in the sw queue. The default is 32. 457 */ 458 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 459 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 460 461 /** 462 * DOC: sched_hw_submission (int) 463 * Override the max number of HW submissions. The default is 2. 464 */ 465 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 466 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 467 468 /** 469 * DOC: ppfeaturemask (hexint) 470 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 471 * The default is the current set of stable power features. 472 */ 473 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 474 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 475 476 /** 477 * DOC: forcelongtraining (uint) 478 * Force long memory training in resume. 479 * The default is zero, indicates short training in resume. 480 */ 481 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 482 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 483 484 /** 485 * DOC: pcie_gen_cap (uint) 486 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 487 * The default is 0 (automatic for each asic). 488 */ 489 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 490 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 491 492 /** 493 * DOC: pcie_lane_cap (uint) 494 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 495 * The default is 0 (automatic for each asic). 496 */ 497 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 498 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 499 500 /** 501 * DOC: cg_mask (ullong) 502 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 503 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 504 */ 505 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 506 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 507 508 /** 509 * DOC: pg_mask (uint) 510 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 511 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 512 */ 513 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 514 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 515 516 /** 517 * DOC: sdma_phase_quantum (uint) 518 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 519 */ 520 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 521 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 522 523 /** 524 * DOC: disable_cu (charp) 525 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 526 */ 527 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 528 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 529 530 /** 531 * DOC: virtual_display (charp) 532 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 533 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 534 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 535 * device at 26:00.0. The default is NULL. 536 */ 537 MODULE_PARM_DESC(virtual_display, 538 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 539 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 540 541 /** 542 * DOC: lbpw (int) 543 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 544 */ 545 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 546 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 547 548 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 549 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 550 551 /** 552 * DOC: gpu_recovery (int) 553 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 554 */ 555 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 556 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 557 558 /** 559 * DOC: emu_mode (int) 560 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 561 */ 562 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 563 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 564 565 /** 566 * DOC: ras_enable (int) 567 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 568 */ 569 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 570 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 571 572 /** 573 * DOC: ras_mask (uint) 574 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 575 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 576 */ 577 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 578 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 579 580 /** 581 * DOC: timeout_fatal_disable (bool) 582 * Disable Watchdog timeout fatal error event 583 */ 584 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 585 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 586 587 /** 588 * DOC: timeout_period (uint) 589 * Modify the watchdog timeout max_cycles as (1 << period) 590 */ 591 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 592 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 593 594 /** 595 * DOC: si_support (int) 596 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 597 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 598 * otherwise using amdgpu driver. 599 */ 600 #ifdef CONFIG_DRM_AMDGPU_SI 601 602 #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) 603 int amdgpu_si_support; 604 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 605 #else 606 int amdgpu_si_support = 1; 607 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 608 #endif 609 610 module_param_named(si_support, amdgpu_si_support, int, 0444); 611 #endif 612 613 /** 614 * DOC: cik_support (int) 615 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 616 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 617 * otherwise using amdgpu driver. 618 */ 619 #ifdef CONFIG_DRM_AMDGPU_CIK 620 621 #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) 622 int amdgpu_cik_support; 623 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 624 #else 625 int amdgpu_cik_support = 1; 626 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 627 #endif 628 629 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 630 #endif 631 632 /** 633 * DOC: smu_memory_pool_size (uint) 634 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 635 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 636 */ 637 MODULE_PARM_DESC(smu_memory_pool_size, 638 "reserve gtt for smu debug usage, 0 = disable,0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 639 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 640 641 /** 642 * DOC: async_gfx_ring (int) 643 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 644 */ 645 MODULE_PARM_DESC(async_gfx_ring, 646 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 647 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 648 649 /** 650 * DOC: mcbp (int) 651 * It is used to enable mid command buffer preemption. (0 = disabled, 1 = enabled, -1 auto (default)) 652 */ 653 MODULE_PARM_DESC(mcbp, 654 "Enable Mid-command buffer preemption (0 = disabled, 1 = enabled), -1 = auto (default)"); 655 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 656 657 /** 658 * DOC: discovery (int) 659 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 660 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 661 */ 662 MODULE_PARM_DESC(discovery, 663 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 664 module_param_named(discovery, amdgpu_discovery, int, 0444); 665 666 /** 667 * DOC: mes (int) 668 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 669 * (0 = disabled (default), 1 = enabled) 670 */ 671 MODULE_PARM_DESC(mes, 672 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 673 module_param_named(mes, amdgpu_mes, int, 0444); 674 675 /** 676 * DOC: mes_log_enable (int) 677 * Enable Micro Engine Scheduler log. This is used to enable/disable MES internal log. 678 * (0 = disabled (default), 1 = enabled) 679 */ 680 MODULE_PARM_DESC(mes_log_enable, 681 "Enable Micro Engine Scheduler log (0 = disabled (default), 1 = enabled)"); 682 module_param_named(mes_log_enable, amdgpu_mes_log_enable, int, 0444); 683 684 /** 685 * DOC: mes_kiq (int) 686 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq. 687 * (0 = disabled (default), 1 = enabled) 688 */ 689 MODULE_PARM_DESC(mes_kiq, 690 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)"); 691 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444); 692 693 /** 694 * DOC: uni_mes (int) 695 * Enable Unified Micro Engine Scheduler. This is a new engine pipe for unified scheduler. 696 * (0 = disabled (default), 1 = enabled) 697 */ 698 MODULE_PARM_DESC(uni_mes, 699 "Enable Unified Micro Engine Scheduler (0 = disabled, 1 = enabled(default)"); 700 module_param_named(uni_mes, amdgpu_uni_mes, int, 0444); 701 702 /** 703 * DOC: noretry (int) 704 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 705 * do not support per-process XNACK this also disables retry page faults. 706 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 707 */ 708 MODULE_PARM_DESC(noretry, 709 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 710 module_param_named(noretry, amdgpu_noretry, int, 0644); 711 712 /** 713 * DOC: force_asic_type (int) 714 * A non negative value used to specify the asic type for all supported GPUs. 715 */ 716 MODULE_PARM_DESC(force_asic_type, 717 "A non negative value used to specify the asic type for all supported GPUs"); 718 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 719 720 /** 721 * DOC: use_xgmi_p2p (int) 722 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 723 */ 724 MODULE_PARM_DESC(use_xgmi_p2p, 725 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 726 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 727 728 729 #ifdef CONFIG_HSA_AMD 730 /** 731 * DOC: sched_policy (int) 732 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 733 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 734 * assigns queues to HQDs. 735 */ 736 int sched_policy = KFD_SCHED_POLICY_HWS; 737 module_param(sched_policy, int, 0444); 738 MODULE_PARM_DESC(sched_policy, 739 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 740 741 /** 742 * DOC: hws_max_conc_proc (int) 743 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 744 * number of VMIDs assigned to the HWS, which is also the default. 745 */ 746 int hws_max_conc_proc = -1; 747 module_param(hws_max_conc_proc, int, 0444); 748 MODULE_PARM_DESC(hws_max_conc_proc, 749 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 750 751 /** 752 * DOC: cwsr_enable (int) 753 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 754 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 755 * disables it. 756 */ 757 int cwsr_enable = 1; 758 module_param(cwsr_enable, int, 0444); 759 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 760 761 /** 762 * DOC: max_num_of_queues_per_device (int) 763 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 764 * is 4096. 765 */ 766 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 767 module_param(max_num_of_queues_per_device, int, 0444); 768 MODULE_PARM_DESC(max_num_of_queues_per_device, 769 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 770 771 /** 772 * DOC: send_sigterm (int) 773 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 774 * but just print errors on dmesg. Setting 1 enables sending sigterm. 775 */ 776 int send_sigterm; 777 module_param(send_sigterm, int, 0444); 778 MODULE_PARM_DESC(send_sigterm, 779 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 780 781 /** 782 * DOC: halt_if_hws_hang (int) 783 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 784 * Setting 1 enables halt on hang. 785 */ 786 int halt_if_hws_hang; 787 module_param(halt_if_hws_hang, int, 0644); 788 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 789 790 /** 791 * DOC: hws_gws_support(bool) 792 * Assume that HWS supports GWS barriers regardless of what firmware version 793 * check says. Default value: false (rely on MEC2 firmware version check). 794 */ 795 bool hws_gws_support; 796 module_param(hws_gws_support, bool, 0444); 797 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 798 799 /** 800 * DOC: queue_preemption_timeout_ms (int) 801 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 802 */ 803 int queue_preemption_timeout_ms = 9000; 804 module_param(queue_preemption_timeout_ms, int, 0644); 805 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 806 807 /** 808 * DOC: debug_evictions(bool) 809 * Enable extra debug messages to help determine the cause of evictions 810 */ 811 bool debug_evictions; 812 module_param(debug_evictions, bool, 0644); 813 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 814 815 /** 816 * DOC: no_system_mem_limit(bool) 817 * Disable system memory limit, to support multiple process shared memory 818 */ 819 bool no_system_mem_limit; 820 module_param(no_system_mem_limit, bool, 0644); 821 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 822 823 /** 824 * DOC: no_queue_eviction_on_vm_fault (int) 825 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 826 */ 827 int amdgpu_no_queue_eviction_on_vm_fault; 828 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 829 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 830 #endif 831 832 /** 833 * DOC: mtype_local (int) 834 */ 835 int amdgpu_mtype_local; 836 MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (0 = MTYPE_RW (default), 1 = MTYPE_NC, 2 = MTYPE_CC)"); 837 module_param_named(mtype_local, amdgpu_mtype_local, int, 0444); 838 839 /** 840 * DOC: pcie_p2p (bool) 841 * Enable PCIe P2P (requires large-BAR). Default value: true (on) 842 */ 843 #ifdef CONFIG_HSA_AMD_P2P 844 bool pcie_p2p = true; 845 module_param(pcie_p2p, bool, 0444); 846 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); 847 #endif 848 849 /** 850 * DOC: dcfeaturemask (uint) 851 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 852 * The default is the current set of stable display features. 853 */ 854 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 855 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 856 857 /** 858 * DOC: dcdebugmask (uint) 859 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 860 */ 861 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 862 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 863 864 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)"); 865 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444); 866 867 /** 868 * DOC: abmlevel (uint) 869 * Override the default ABM (Adaptive Backlight Management) level used for DC 870 * enabled hardware. Requires DMCU to be supported and loaded. 871 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 872 * default. Values 1-4 control the maximum allowable brightness reduction via 873 * the ABM algorithm, with 1 being the least reduction and 4 being the most 874 * reduction. 875 * 876 * Defaults to -1, or disabled. Userspace can only override this level after 877 * boot if it's set to auto. 878 */ 879 int amdgpu_dm_abm_level = -1; 880 MODULE_PARM_DESC(abmlevel, 881 "ABM level (0 = off, 1-4 = backlight reduction level, -1 auto (default))"); 882 module_param_named(abmlevel, amdgpu_dm_abm_level, int, 0444); 883 884 int amdgpu_backlight = -1; 885 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 886 module_param_named(backlight, amdgpu_backlight, bint, 0444); 887 888 /** 889 * DOC: damageclips (int) 890 * Enable or disable damage clips support. If damage clips support is disabled, 891 * we will force full frame updates, irrespective of what user space sends to 892 * us. 893 * 894 * Defaults to -1 (where it is enabled unless a PSR-SU display is detected). 895 */ 896 MODULE_PARM_DESC(damageclips, 897 "Damage clips support (0 = disable, 1 = enable, -1 auto (default))"); 898 module_param_named(damageclips, amdgpu_damage_clips, int, 0444); 899 900 /** 901 * DOC: tmz (int) 902 * Trusted Memory Zone (TMZ) is a method to protect data being written 903 * to or read from memory. 904 * 905 * The default value: 0 (off). TODO: change to auto till it is completed. 906 */ 907 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 908 module_param_named(tmz, amdgpu_tmz, int, 0444); 909 910 /** 911 * DOC: freesync_video (uint) 912 * Enable the optimization to adjust front porch timing to achieve seamless 913 * mode change experience when setting a freesync supported mode for which full 914 * modeset is not needed. 915 * 916 * The Display Core will add a set of modes derived from the base FreeSync 917 * video mode into the corresponding connector's mode list based on commonly 918 * used refresh rates and VRR range of the connected display, when users enable 919 * this feature. From the userspace perspective, they can see a seamless mode 920 * change experience when the change between different refresh rates under the 921 * same resolution. Additionally, userspace applications such as Video playback 922 * can read this modeset list and change the refresh rate based on the video 923 * frame rate. Finally, the userspace can also derive an appropriate mode for a 924 * particular refresh rate based on the FreeSync Mode and add it to the 925 * connector's mode list. 926 * 927 * Note: This is an experimental feature. 928 * 929 * The default value: 0 (off). 930 */ 931 MODULE_PARM_DESC( 932 freesync_video, 933 "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)"); 934 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); 935 936 /** 937 * DOC: reset_method (int) 938 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 939 */ 940 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 941 module_param_named(reset_method, amdgpu_reset_method, int, 0644); 942 943 MODULE_PARM_DESC(jpeg_test, "jpeg test(0 = disable (default), 1 = enable)"); 944 module_param_named(jpeg_test, amdgpu_jpeg_test, int, 0444); 945 946 /** 947 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 948 * threshold value of faulty pages detected by RAS ECC, which may 949 * result in the GPU entering bad status when the number of total 950 * faulty pages by ECC exceeds the threshold value. 951 */ 952 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = driver sets threshold)"); 953 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 954 955 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 956 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 957 958 /** 959 * DOC: vcnfw_log (int) 960 * Enable vcnfw log output for debugging, the default is disabled. 961 */ 962 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 963 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 964 965 /** 966 * DOC: sg_display (int) 967 * Disable S/G (scatter/gather) display (i.e., display from system memory). 968 * This option is only relevant on APUs. Set this option to 0 to disable 969 * S/G display if you experience flickering or other issues under memory 970 * pressure and report the issue. 971 */ 972 MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)"); 973 module_param_named(sg_display, amdgpu_sg_display, int, 0444); 974 975 /** 976 * DOC: umsch_mm (int) 977 * Enable Multi Media User Mode Scheduler. This is a HW scheduling engine for VCN and VPE. 978 * (0 = disabled (default), 1 = enabled) 979 */ 980 MODULE_PARM_DESC(umsch_mm, 981 "Enable Multi Media User Mode Scheduler (0 = disabled (default), 1 = enabled)"); 982 module_param_named(umsch_mm, amdgpu_umsch_mm, int, 0444); 983 984 /** 985 * DOC: umsch_mm_fwlog (int) 986 * Enable umschfw log output for debugging, the default is disabled. 987 */ 988 MODULE_PARM_DESC(umsch_mm_fwlog, "Enable umschfw log(0 = disable (default value), 1 = enable)"); 989 module_param_named(umsch_mm_fwlog, amdgpu_umsch_mm_fwlog, int, 0444); 990 991 /** 992 * DOC: smu_pptable_id (int) 993 * Used to override pptable id. id = 0 use VBIOS pptable. 994 * id > 0 use the soft pptable with specicfied id. 995 */ 996 MODULE_PARM_DESC(smu_pptable_id, 997 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 998 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 999 1000 /** 1001 * DOC: partition_mode (int) 1002 * Used to override the default SPX mode. 1003 */ 1004 MODULE_PARM_DESC( 1005 user_partt_mode, 1006 "specify partition mode to be used (-2 = AMDGPU_AUTO_COMPUTE_PARTITION_MODE(default value) \ 1007 0 = AMDGPU_SPX_PARTITION_MODE, \ 1008 1 = AMDGPU_DPX_PARTITION_MODE, \ 1009 2 = AMDGPU_TPX_PARTITION_MODE, \ 1010 3 = AMDGPU_QPX_PARTITION_MODE, \ 1011 4 = AMDGPU_CPX_PARTITION_MODE)"); 1012 module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint, 0444); 1013 1014 1015 /** 1016 * DOC: enforce_isolation (bool) 1017 * enforce process isolation between graphics and compute via using the same reserved vmid. 1018 */ 1019 module_param(enforce_isolation, bool, 0444); 1020 MODULE_PARM_DESC(enforce_isolation, "enforce process isolation between graphics and compute . enforce_isolation = on"); 1021 1022 /** 1023 * DOC: seamless (int) 1024 * Seamless boot will keep the image on the screen during the boot process. 1025 */ 1026 MODULE_PARM_DESC(seamless, "Seamless boot (-1 = auto (default), 0 = disable, 1 = enable)"); 1027 module_param_named(seamless, amdgpu_seamless, int, 0444); 1028 1029 /** 1030 * DOC: debug_mask (uint) 1031 * Debug options for amdgpu, work as a binary mask with the following options: 1032 * 1033 * - 0x1: Debug VM handling 1034 * - 0x2: Enable simulating large-bar capability on non-large bar system. This 1035 * limits the VRAM size reported to ROCm applications to the visible 1036 * size, usually 256MB. 1037 * - 0x4: Disable GPU soft recovery, always do a full reset 1038 */ 1039 MODULE_PARM_DESC(debug_mask, "debug options for amdgpu, disabled by default"); 1040 module_param_named(debug_mask, amdgpu_debug_mask, uint, 0444); 1041 1042 /** 1043 * DOC: agp (int) 1044 * Enable the AGP aperture. This provides an aperture in the GPU's internal 1045 * address space for direct access to system memory. Note that these accesses 1046 * are non-snooped, so they are only used for access to uncached memory. 1047 */ 1048 MODULE_PARM_DESC(agp, "AGP (-1 = auto (default), 0 = disable, 1 = enable)"); 1049 module_param_named(agp, amdgpu_agp, int, 0444); 1050 1051 /** 1052 * DOC: wbrf (int) 1053 * Enable Wifi RFI interference mitigation feature. 1054 * Due to electrical and mechanical constraints there may be likely interference of 1055 * relatively high-powered harmonics of the (G-)DDR memory clocks with local radio 1056 * module frequency bands used by Wifi 6/6e/7. To mitigate the possible RFI interference, 1057 * with this feature enabled, PMFW will use either “shadowed P-State” or “P-State” based 1058 * on active list of frequencies in-use (to be avoided) as part of initial setting or 1059 * P-state transition. However, there may be potential performance impact with this 1060 * feature enabled. 1061 * (0 = disabled, 1 = enabled, -1 = auto (default setting, will be enabled if supported)) 1062 */ 1063 MODULE_PARM_DESC(wbrf, 1064 "Enable Wifi RFI interference mitigation (0 = disabled, 1 = enabled, -1 = auto(default)"); 1065 module_param_named(wbrf, amdgpu_wbrf, int, 0444); 1066 1067 /* These devices are not supported by amdgpu. 1068 * They are supported by the mach64, r128, radeon drivers 1069 */ 1070 static const u16 amdgpu_unsupported_pciidlist[] = { 1071 /* mach64 */ 1072 0x4354, 1073 0x4358, 1074 0x4554, 1075 0x4742, 1076 0x4744, 1077 0x4749, 1078 0x474C, 1079 0x474D, 1080 0x474E, 1081 0x474F, 1082 0x4750, 1083 0x4751, 1084 0x4752, 1085 0x4753, 1086 0x4754, 1087 0x4755, 1088 0x4756, 1089 0x4757, 1090 0x4758, 1091 0x4759, 1092 0x475A, 1093 0x4C42, 1094 0x4C44, 1095 0x4C47, 1096 0x4C49, 1097 0x4C4D, 1098 0x4C4E, 1099 0x4C50, 1100 0x4C51, 1101 0x4C52, 1102 0x4C53, 1103 0x5654, 1104 0x5655, 1105 0x5656, 1106 /* r128 */ 1107 0x4c45, 1108 0x4c46, 1109 0x4d46, 1110 0x4d4c, 1111 0x5041, 1112 0x5042, 1113 0x5043, 1114 0x5044, 1115 0x5045, 1116 0x5046, 1117 0x5047, 1118 0x5048, 1119 0x5049, 1120 0x504A, 1121 0x504B, 1122 0x504C, 1123 0x504D, 1124 0x504E, 1125 0x504F, 1126 0x5050, 1127 0x5051, 1128 0x5052, 1129 0x5053, 1130 0x5054, 1131 0x5055, 1132 0x5056, 1133 0x5057, 1134 0x5058, 1135 0x5245, 1136 0x5246, 1137 0x5247, 1138 0x524b, 1139 0x524c, 1140 0x534d, 1141 0x5446, 1142 0x544C, 1143 0x5452, 1144 /* radeon */ 1145 0x3150, 1146 0x3151, 1147 0x3152, 1148 0x3154, 1149 0x3155, 1150 0x3E50, 1151 0x3E54, 1152 0x4136, 1153 0x4137, 1154 0x4144, 1155 0x4145, 1156 0x4146, 1157 0x4147, 1158 0x4148, 1159 0x4149, 1160 0x414A, 1161 0x414B, 1162 0x4150, 1163 0x4151, 1164 0x4152, 1165 0x4153, 1166 0x4154, 1167 0x4155, 1168 0x4156, 1169 0x4237, 1170 0x4242, 1171 0x4336, 1172 0x4337, 1173 0x4437, 1174 0x4966, 1175 0x4967, 1176 0x4A48, 1177 0x4A49, 1178 0x4A4A, 1179 0x4A4B, 1180 0x4A4C, 1181 0x4A4D, 1182 0x4A4E, 1183 0x4A4F, 1184 0x4A50, 1185 0x4A54, 1186 0x4B48, 1187 0x4B49, 1188 0x4B4A, 1189 0x4B4B, 1190 0x4B4C, 1191 0x4C57, 1192 0x4C58, 1193 0x4C59, 1194 0x4C5A, 1195 0x4C64, 1196 0x4C66, 1197 0x4C67, 1198 0x4E44, 1199 0x4E45, 1200 0x4E46, 1201 0x4E47, 1202 0x4E48, 1203 0x4E49, 1204 0x4E4A, 1205 0x4E4B, 1206 0x4E50, 1207 0x4E51, 1208 0x4E52, 1209 0x4E53, 1210 0x4E54, 1211 0x4E56, 1212 0x5144, 1213 0x5145, 1214 0x5146, 1215 0x5147, 1216 0x5148, 1217 0x514C, 1218 0x514D, 1219 0x5157, 1220 0x5158, 1221 0x5159, 1222 0x515A, 1223 0x515E, 1224 0x5460, 1225 0x5462, 1226 0x5464, 1227 0x5548, 1228 0x5549, 1229 0x554A, 1230 0x554B, 1231 0x554C, 1232 0x554D, 1233 0x554E, 1234 0x554F, 1235 0x5550, 1236 0x5551, 1237 0x5552, 1238 0x5554, 1239 0x564A, 1240 0x564B, 1241 0x564F, 1242 0x5652, 1243 0x5653, 1244 0x5657, 1245 0x5834, 1246 0x5835, 1247 0x5954, 1248 0x5955, 1249 0x5974, 1250 0x5975, 1251 0x5960, 1252 0x5961, 1253 0x5962, 1254 0x5964, 1255 0x5965, 1256 0x5969, 1257 0x5a41, 1258 0x5a42, 1259 0x5a61, 1260 0x5a62, 1261 0x5b60, 1262 0x5b62, 1263 0x5b63, 1264 0x5b64, 1265 0x5b65, 1266 0x5c61, 1267 0x5c63, 1268 0x5d48, 1269 0x5d49, 1270 0x5d4a, 1271 0x5d4c, 1272 0x5d4d, 1273 0x5d4e, 1274 0x5d4f, 1275 0x5d50, 1276 0x5d52, 1277 0x5d57, 1278 0x5e48, 1279 0x5e4a, 1280 0x5e4b, 1281 0x5e4c, 1282 0x5e4d, 1283 0x5e4f, 1284 0x6700, 1285 0x6701, 1286 0x6702, 1287 0x6703, 1288 0x6704, 1289 0x6705, 1290 0x6706, 1291 0x6707, 1292 0x6708, 1293 0x6709, 1294 0x6718, 1295 0x6719, 1296 0x671c, 1297 0x671d, 1298 0x671f, 1299 0x6720, 1300 0x6721, 1301 0x6722, 1302 0x6723, 1303 0x6724, 1304 0x6725, 1305 0x6726, 1306 0x6727, 1307 0x6728, 1308 0x6729, 1309 0x6738, 1310 0x6739, 1311 0x673e, 1312 0x6740, 1313 0x6741, 1314 0x6742, 1315 0x6743, 1316 0x6744, 1317 0x6745, 1318 0x6746, 1319 0x6747, 1320 0x6748, 1321 0x6749, 1322 0x674A, 1323 0x6750, 1324 0x6751, 1325 0x6758, 1326 0x6759, 1327 0x675B, 1328 0x675D, 1329 0x675F, 1330 0x6760, 1331 0x6761, 1332 0x6762, 1333 0x6763, 1334 0x6764, 1335 0x6765, 1336 0x6766, 1337 0x6767, 1338 0x6768, 1339 0x6770, 1340 0x6771, 1341 0x6772, 1342 0x6778, 1343 0x6779, 1344 0x677B, 1345 0x6840, 1346 0x6841, 1347 0x6842, 1348 0x6843, 1349 0x6849, 1350 0x684C, 1351 0x6850, 1352 0x6858, 1353 0x6859, 1354 0x6880, 1355 0x6888, 1356 0x6889, 1357 0x688A, 1358 0x688C, 1359 0x688D, 1360 0x6898, 1361 0x6899, 1362 0x689b, 1363 0x689c, 1364 0x689d, 1365 0x689e, 1366 0x68a0, 1367 0x68a1, 1368 0x68a8, 1369 0x68a9, 1370 0x68b0, 1371 0x68b8, 1372 0x68b9, 1373 0x68ba, 1374 0x68be, 1375 0x68bf, 1376 0x68c0, 1377 0x68c1, 1378 0x68c7, 1379 0x68c8, 1380 0x68c9, 1381 0x68d8, 1382 0x68d9, 1383 0x68da, 1384 0x68de, 1385 0x68e0, 1386 0x68e1, 1387 0x68e4, 1388 0x68e5, 1389 0x68e8, 1390 0x68e9, 1391 0x68f1, 1392 0x68f2, 1393 0x68f8, 1394 0x68f9, 1395 0x68fa, 1396 0x68fe, 1397 0x7100, 1398 0x7101, 1399 0x7102, 1400 0x7103, 1401 0x7104, 1402 0x7105, 1403 0x7106, 1404 0x7108, 1405 0x7109, 1406 0x710A, 1407 0x710B, 1408 0x710C, 1409 0x710E, 1410 0x710F, 1411 0x7140, 1412 0x7141, 1413 0x7142, 1414 0x7143, 1415 0x7144, 1416 0x7145, 1417 0x7146, 1418 0x7147, 1419 0x7149, 1420 0x714A, 1421 0x714B, 1422 0x714C, 1423 0x714D, 1424 0x714E, 1425 0x714F, 1426 0x7151, 1427 0x7152, 1428 0x7153, 1429 0x715E, 1430 0x715F, 1431 0x7180, 1432 0x7181, 1433 0x7183, 1434 0x7186, 1435 0x7187, 1436 0x7188, 1437 0x718A, 1438 0x718B, 1439 0x718C, 1440 0x718D, 1441 0x718F, 1442 0x7193, 1443 0x7196, 1444 0x719B, 1445 0x719F, 1446 0x71C0, 1447 0x71C1, 1448 0x71C2, 1449 0x71C3, 1450 0x71C4, 1451 0x71C5, 1452 0x71C6, 1453 0x71C7, 1454 0x71CD, 1455 0x71CE, 1456 0x71D2, 1457 0x71D4, 1458 0x71D5, 1459 0x71D6, 1460 0x71DA, 1461 0x71DE, 1462 0x7200, 1463 0x7210, 1464 0x7211, 1465 0x7240, 1466 0x7243, 1467 0x7244, 1468 0x7245, 1469 0x7246, 1470 0x7247, 1471 0x7248, 1472 0x7249, 1473 0x724A, 1474 0x724B, 1475 0x724C, 1476 0x724D, 1477 0x724E, 1478 0x724F, 1479 0x7280, 1480 0x7281, 1481 0x7283, 1482 0x7284, 1483 0x7287, 1484 0x7288, 1485 0x7289, 1486 0x728B, 1487 0x728C, 1488 0x7290, 1489 0x7291, 1490 0x7293, 1491 0x7297, 1492 0x7834, 1493 0x7835, 1494 0x791e, 1495 0x791f, 1496 0x793f, 1497 0x7941, 1498 0x7942, 1499 0x796c, 1500 0x796d, 1501 0x796e, 1502 0x796f, 1503 0x9400, 1504 0x9401, 1505 0x9402, 1506 0x9403, 1507 0x9405, 1508 0x940A, 1509 0x940B, 1510 0x940F, 1511 0x94A0, 1512 0x94A1, 1513 0x94A3, 1514 0x94B1, 1515 0x94B3, 1516 0x94B4, 1517 0x94B5, 1518 0x94B9, 1519 0x9440, 1520 0x9441, 1521 0x9442, 1522 0x9443, 1523 0x9444, 1524 0x9446, 1525 0x944A, 1526 0x944B, 1527 0x944C, 1528 0x944E, 1529 0x9450, 1530 0x9452, 1531 0x9456, 1532 0x945A, 1533 0x945B, 1534 0x945E, 1535 0x9460, 1536 0x9462, 1537 0x946A, 1538 0x946B, 1539 0x947A, 1540 0x947B, 1541 0x9480, 1542 0x9487, 1543 0x9488, 1544 0x9489, 1545 0x948A, 1546 0x948F, 1547 0x9490, 1548 0x9491, 1549 0x9495, 1550 0x9498, 1551 0x949C, 1552 0x949E, 1553 0x949F, 1554 0x94C0, 1555 0x94C1, 1556 0x94C3, 1557 0x94C4, 1558 0x94C5, 1559 0x94C6, 1560 0x94C7, 1561 0x94C8, 1562 0x94C9, 1563 0x94CB, 1564 0x94CC, 1565 0x94CD, 1566 0x9500, 1567 0x9501, 1568 0x9504, 1569 0x9505, 1570 0x9506, 1571 0x9507, 1572 0x9508, 1573 0x9509, 1574 0x950F, 1575 0x9511, 1576 0x9515, 1577 0x9517, 1578 0x9519, 1579 0x9540, 1580 0x9541, 1581 0x9542, 1582 0x954E, 1583 0x954F, 1584 0x9552, 1585 0x9553, 1586 0x9555, 1587 0x9557, 1588 0x955f, 1589 0x9580, 1590 0x9581, 1591 0x9583, 1592 0x9586, 1593 0x9587, 1594 0x9588, 1595 0x9589, 1596 0x958A, 1597 0x958B, 1598 0x958C, 1599 0x958D, 1600 0x958E, 1601 0x958F, 1602 0x9590, 1603 0x9591, 1604 0x9593, 1605 0x9595, 1606 0x9596, 1607 0x9597, 1608 0x9598, 1609 0x9599, 1610 0x959B, 1611 0x95C0, 1612 0x95C2, 1613 0x95C4, 1614 0x95C5, 1615 0x95C6, 1616 0x95C7, 1617 0x95C9, 1618 0x95CC, 1619 0x95CD, 1620 0x95CE, 1621 0x95CF, 1622 0x9610, 1623 0x9611, 1624 0x9612, 1625 0x9613, 1626 0x9614, 1627 0x9615, 1628 0x9616, 1629 0x9640, 1630 0x9641, 1631 0x9642, 1632 0x9643, 1633 0x9644, 1634 0x9645, 1635 0x9647, 1636 0x9648, 1637 0x9649, 1638 0x964a, 1639 0x964b, 1640 0x964c, 1641 0x964e, 1642 0x964f, 1643 0x9710, 1644 0x9711, 1645 0x9712, 1646 0x9713, 1647 0x9714, 1648 0x9715, 1649 0x9802, 1650 0x9803, 1651 0x9804, 1652 0x9805, 1653 0x9806, 1654 0x9807, 1655 0x9808, 1656 0x9809, 1657 0x980A, 1658 0x9900, 1659 0x9901, 1660 0x9903, 1661 0x9904, 1662 0x9905, 1663 0x9906, 1664 0x9907, 1665 0x9908, 1666 0x9909, 1667 0x990A, 1668 0x990B, 1669 0x990C, 1670 0x990D, 1671 0x990E, 1672 0x990F, 1673 0x9910, 1674 0x9913, 1675 0x9917, 1676 0x9918, 1677 0x9919, 1678 0x9990, 1679 0x9991, 1680 0x9992, 1681 0x9993, 1682 0x9994, 1683 0x9995, 1684 0x9996, 1685 0x9997, 1686 0x9998, 1687 0x9999, 1688 0x999A, 1689 0x999B, 1690 0x999C, 1691 0x999D, 1692 0x99A0, 1693 0x99A2, 1694 0x99A4, 1695 /* radeon secondary ids */ 1696 0x3171, 1697 0x3e70, 1698 0x4164, 1699 0x4165, 1700 0x4166, 1701 0x4168, 1702 0x4170, 1703 0x4171, 1704 0x4172, 1705 0x4173, 1706 0x496e, 1707 0x4a69, 1708 0x4a6a, 1709 0x4a6b, 1710 0x4a70, 1711 0x4a74, 1712 0x4b69, 1713 0x4b6b, 1714 0x4b6c, 1715 0x4c6e, 1716 0x4e64, 1717 0x4e65, 1718 0x4e66, 1719 0x4e67, 1720 0x4e68, 1721 0x4e69, 1722 0x4e6a, 1723 0x4e71, 1724 0x4f73, 1725 0x5569, 1726 0x556b, 1727 0x556d, 1728 0x556f, 1729 0x5571, 1730 0x5854, 1731 0x5874, 1732 0x5940, 1733 0x5941, 1734 0x5b70, 1735 0x5b72, 1736 0x5b73, 1737 0x5b74, 1738 0x5b75, 1739 0x5d44, 1740 0x5d45, 1741 0x5d6d, 1742 0x5d6f, 1743 0x5d72, 1744 0x5d77, 1745 0x5e6b, 1746 0x5e6d, 1747 0x7120, 1748 0x7124, 1749 0x7129, 1750 0x712e, 1751 0x712f, 1752 0x7162, 1753 0x7163, 1754 0x7166, 1755 0x7167, 1756 0x7172, 1757 0x7173, 1758 0x71a0, 1759 0x71a1, 1760 0x71a3, 1761 0x71a7, 1762 0x71bb, 1763 0x71e0, 1764 0x71e1, 1765 0x71e2, 1766 0x71e6, 1767 0x71e7, 1768 0x71f2, 1769 0x7269, 1770 0x726b, 1771 0x726e, 1772 0x72a0, 1773 0x72a8, 1774 0x72b1, 1775 0x72b3, 1776 0x793f, 1777 }; 1778 1779 static const struct pci_device_id pciidlist[] = { 1780 #ifdef CONFIG_DRM_AMDGPU_SI 1781 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1782 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1783 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1784 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1785 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1786 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1787 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1788 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1789 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1790 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1791 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1792 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1793 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1794 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1795 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1796 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1797 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1798 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1799 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1800 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1801 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1802 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1803 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1804 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1805 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1806 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1807 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1808 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1809 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1810 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1811 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1812 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1813 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1814 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1815 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1816 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1817 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1818 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1819 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1820 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1821 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1822 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1823 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1824 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1825 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1826 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1827 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1828 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1829 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1830 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1831 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1832 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1833 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1834 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1835 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1836 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1837 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1838 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1839 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1840 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1841 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1842 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1843 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1844 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1845 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1846 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1847 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1848 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1849 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1850 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1851 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1852 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1853 #endif 1854 #ifdef CONFIG_DRM_AMDGPU_CIK 1855 /* Kaveri */ 1856 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1857 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1858 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1859 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1860 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1861 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1862 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1863 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1864 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1865 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1866 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1867 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1868 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1869 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1870 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1871 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1872 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1873 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1874 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1875 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1876 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1877 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1878 /* Bonaire */ 1879 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1880 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1881 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1882 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1883 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1884 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1885 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1886 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1887 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1888 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1889 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1890 /* Hawaii */ 1891 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1892 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1893 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1894 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1895 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1896 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1897 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1898 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1899 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1900 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1901 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1902 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1903 /* Kabini */ 1904 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1905 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1906 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1907 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1908 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1909 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1910 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1911 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1912 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1913 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1914 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1915 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1916 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1917 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1918 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1919 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1920 /* mullins */ 1921 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1922 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1923 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1924 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1925 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1926 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1927 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1928 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1929 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1930 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1931 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1932 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1933 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1934 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1935 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1936 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1937 #endif 1938 /* topaz */ 1939 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1940 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1941 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1942 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1943 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1944 /* tonga */ 1945 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1946 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1947 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1948 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1949 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1950 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1951 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1952 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1953 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1954 /* fiji */ 1955 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1956 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1957 /* carrizo */ 1958 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1959 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1960 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1961 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1962 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1963 /* stoney */ 1964 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1965 /* Polaris11 */ 1966 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1967 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1968 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1969 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1970 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1971 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1972 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1973 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1974 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1975 /* Polaris10 */ 1976 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1977 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1978 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1979 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1980 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1981 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1982 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1983 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1984 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1985 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1986 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1987 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1988 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1989 /* Polaris12 */ 1990 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1991 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1992 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1993 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1994 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1995 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1996 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1997 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1998 /* VEGAM */ 1999 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 2000 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 2001 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 2002 /* Vega 10 */ 2003 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2004 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2005 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2006 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2007 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2008 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2009 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2010 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2011 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2012 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2013 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2014 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2015 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2016 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2017 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2018 /* Vega 12 */ 2019 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2020 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2021 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2022 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2023 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2024 /* Vega 20 */ 2025 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2026 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2027 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2028 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2029 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2030 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2031 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2032 /* Raven */ 2033 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 2034 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 2035 /* Arcturus */ 2036 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2037 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2038 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2039 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2040 /* Navi10 */ 2041 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2042 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2043 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2044 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2045 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2046 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2047 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2048 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2049 /* Navi14 */ 2050 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2051 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2052 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2053 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2054 2055 /* Renoir */ 2056 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2057 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2058 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2059 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2060 2061 /* Navi12 */ 2062 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 2063 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 2064 2065 /* Sienna_Cichlid */ 2066 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2067 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2068 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2069 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2070 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2071 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2072 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2073 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2074 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2075 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2076 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2077 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2078 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2079 2080 /* Yellow Carp */ 2081 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 2082 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 2083 2084 /* Navy_Flounder */ 2085 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2086 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2087 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2088 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2089 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2090 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2091 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2092 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2093 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2094 2095 /* DIMGREY_CAVEFISH */ 2096 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2097 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2098 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2099 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2100 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2101 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2102 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2103 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2104 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2105 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2106 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2107 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2108 2109 /* Aldebaran */ 2110 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2111 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2112 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2113 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2114 2115 /* CYAN_SKILLFISH */ 2116 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2117 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2118 2119 /* BEIGE_GOBY */ 2120 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2121 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2122 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2123 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2124 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2125 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2126 2127 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2128 .class = PCI_CLASS_DISPLAY_VGA << 8, 2129 .class_mask = 0xffffff, 2130 .driver_data = CHIP_IP_DISCOVERY }, 2131 2132 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2133 .class = PCI_CLASS_DISPLAY_OTHER << 8, 2134 .class_mask = 0xffffff, 2135 .driver_data = CHIP_IP_DISCOVERY }, 2136 2137 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2138 .class = PCI_CLASS_ACCELERATOR_PROCESSING << 8, 2139 .class_mask = 0xffffff, 2140 .driver_data = CHIP_IP_DISCOVERY }, 2141 2142 {0, 0, 0} 2143 }; 2144 2145 MODULE_DEVICE_TABLE(pci, pciidlist); 2146 2147 static const struct amdgpu_asic_type_quirk asic_type_quirks[] = { 2148 /* differentiate between P10 and P11 asics with the same DID */ 2149 {0x67FF, 0xE3, CHIP_POLARIS10}, 2150 {0x67FF, 0xE7, CHIP_POLARIS10}, 2151 {0x67FF, 0xF3, CHIP_POLARIS10}, 2152 {0x67FF, 0xF7, CHIP_POLARIS10}, 2153 }; 2154 2155 static const struct drm_driver amdgpu_kms_driver; 2156 2157 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 2158 { 2159 struct pci_dev *p = NULL; 2160 int i; 2161 2162 /* 0 - GPU 2163 * 1 - audio 2164 * 2 - USB 2165 * 3 - UCSI 2166 */ 2167 for (i = 1; i < 4; i++) { 2168 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 2169 adev->pdev->bus->number, i); 2170 if (p) { 2171 pm_runtime_get_sync(&p->dev); 2172 pm_runtime_mark_last_busy(&p->dev); 2173 pm_runtime_put_autosuspend(&p->dev); 2174 pci_dev_put(p); 2175 } 2176 } 2177 } 2178 2179 static void amdgpu_init_debug_options(struct amdgpu_device *adev) 2180 { 2181 if (amdgpu_debug_mask & AMDGPU_DEBUG_VM) { 2182 pr_info("debug: VM handling debug enabled\n"); 2183 adev->debug_vm = true; 2184 } 2185 2186 if (amdgpu_debug_mask & AMDGPU_DEBUG_LARGEBAR) { 2187 pr_info("debug: enabled simulating large-bar capability on non-large bar system\n"); 2188 adev->debug_largebar = true; 2189 } 2190 2191 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY) { 2192 pr_info("debug: soft reset for GPU recovery disabled\n"); 2193 adev->debug_disable_soft_recovery = true; 2194 } 2195 2196 if (amdgpu_debug_mask & AMDGPU_DEBUG_USE_VRAM_FW_BUF) { 2197 pr_info("debug: place fw in vram for frontdoor loading\n"); 2198 adev->debug_use_vram_fw_buf = true; 2199 } 2200 2201 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_RAS_ACA) { 2202 pr_info("debug: enable RAS ACA\n"); 2203 adev->debug_enable_ras_aca = true; 2204 } 2205 } 2206 2207 static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long flags) 2208 { 2209 int i; 2210 2211 for (i = 0; i < ARRAY_SIZE(asic_type_quirks); i++) { 2212 if (pdev->device == asic_type_quirks[i].device && 2213 pdev->revision == asic_type_quirks[i].revision) { 2214 flags &= ~AMD_ASIC_MASK; 2215 flags |= asic_type_quirks[i].type; 2216 break; 2217 } 2218 } 2219 2220 return flags; 2221 } 2222 2223 static int amdgpu_pci_probe(struct pci_dev *pdev, 2224 const struct pci_device_id *ent) 2225 { 2226 struct drm_device *ddev; 2227 struct amdgpu_device *adev; 2228 unsigned long flags = ent->driver_data; 2229 int ret, retry = 0, i; 2230 bool supports_atomic = false; 2231 2232 /* skip devices which are owned by radeon */ 2233 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2234 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2235 return -ENODEV; 2236 } 2237 2238 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) 2239 amdgpu_aspm = 0; 2240 2241 if (amdgpu_virtual_display || 2242 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 2243 supports_atomic = true; 2244 2245 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2246 DRM_INFO("This hardware requires experimental hardware support.\n" 2247 "See modparam exp_hw_support\n"); 2248 return -ENODEV; 2249 } 2250 2251 flags = amdgpu_fix_asic_type(pdev, flags); 2252 2253 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2254 * however, SME requires an indirect IOMMU mapping because the encryption 2255 * bit is beyond the DMA mask of the chip. 2256 */ 2257 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2258 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2259 dev_info(&pdev->dev, 2260 "SME is not compatible with RAVEN\n"); 2261 return -ENOTSUPP; 2262 } 2263 2264 #ifdef CONFIG_DRM_AMDGPU_SI 2265 if (!amdgpu_si_support) { 2266 switch (flags & AMD_ASIC_MASK) { 2267 case CHIP_TAHITI: 2268 case CHIP_PITCAIRN: 2269 case CHIP_VERDE: 2270 case CHIP_OLAND: 2271 case CHIP_HAINAN: 2272 dev_info(&pdev->dev, 2273 "SI support provided by radeon.\n"); 2274 dev_info(&pdev->dev, 2275 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 2276 ); 2277 return -ENODEV; 2278 } 2279 } 2280 #endif 2281 #ifdef CONFIG_DRM_AMDGPU_CIK 2282 if (!amdgpu_cik_support) { 2283 switch (flags & AMD_ASIC_MASK) { 2284 case CHIP_KAVERI: 2285 case CHIP_BONAIRE: 2286 case CHIP_HAWAII: 2287 case CHIP_KABINI: 2288 case CHIP_MULLINS: 2289 dev_info(&pdev->dev, 2290 "CIK support provided by radeon.\n"); 2291 dev_info(&pdev->dev, 2292 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 2293 ); 2294 return -ENODEV; 2295 } 2296 } 2297 #endif 2298 2299 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2300 if (IS_ERR(adev)) 2301 return PTR_ERR(adev); 2302 2303 adev->dev = &pdev->dev; 2304 adev->pdev = pdev; 2305 ddev = adev_to_drm(adev); 2306 2307 if (!supports_atomic) 2308 ddev->driver_features &= ~DRIVER_ATOMIC; 2309 2310 ret = pci_enable_device(pdev); 2311 if (ret) 2312 return ret; 2313 2314 pci_set_drvdata(pdev, ddev); 2315 2316 amdgpu_init_debug_options(adev); 2317 2318 ret = amdgpu_driver_load_kms(adev, flags); 2319 if (ret) 2320 goto err_pci; 2321 2322 retry_init: 2323 ret = drm_dev_register(ddev, flags); 2324 if (ret == -EAGAIN && ++retry <= 3) { 2325 DRM_INFO("retry init %d\n", retry); 2326 /* Don't request EX mode too frequently which is attacking */ 2327 msleep(5000); 2328 goto retry_init; 2329 } else if (ret) { 2330 goto err_pci; 2331 } 2332 2333 ret = amdgpu_xcp_dev_register(adev, ent); 2334 if (ret) 2335 goto err_pci; 2336 2337 ret = amdgpu_amdkfd_drm_client_create(adev); 2338 if (ret) 2339 goto err_pci; 2340 2341 /* 2342 * 1. don't init fbdev on hw without DCE 2343 * 2. don't init fbdev if there are no connectors 2344 */ 2345 if (adev->mode_info.mode_config_initialized && 2346 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2347 /* select 8 bpp console on low vram cards */ 2348 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2349 drm_fbdev_generic_setup(adev_to_drm(adev), 8); 2350 else 2351 drm_fbdev_generic_setup(adev_to_drm(adev), 32); 2352 } 2353 2354 ret = amdgpu_debugfs_init(adev); 2355 if (ret) 2356 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2357 2358 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2359 /* only need to skip on ATPX */ 2360 if (amdgpu_device_supports_px(ddev)) 2361 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2362 /* we want direct complete for BOCO */ 2363 if (amdgpu_device_supports_boco(ddev)) 2364 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2365 DPM_FLAG_SMART_SUSPEND | 2366 DPM_FLAG_MAY_SKIP_RESUME); 2367 pm_runtime_use_autosuspend(ddev->dev); 2368 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2369 2370 pm_runtime_allow(ddev->dev); 2371 2372 pm_runtime_mark_last_busy(ddev->dev); 2373 pm_runtime_put_autosuspend(ddev->dev); 2374 2375 pci_wake_from_d3(pdev, TRUE); 2376 2377 /* 2378 * For runpm implemented via BACO, PMFW will handle the 2379 * timing for BACO in and out: 2380 * - put ASIC into BACO state only when both video and 2381 * audio functions are in D3 state. 2382 * - pull ASIC out of BACO state when either video or 2383 * audio function is in D0 state. 2384 * Also, at startup, PMFW assumes both functions are in 2385 * D0 state. 2386 * 2387 * So if snd driver was loaded prior to amdgpu driver 2388 * and audio function was put into D3 state, there will 2389 * be no PMFW-aware D-state transition(D0->D3) on runpm 2390 * suspend. Thus the BACO will be not correctly kicked in. 2391 * 2392 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2393 * into D0 state. Then there will be a PMFW-aware D-state 2394 * transition(D0->D3) on runpm suspend. 2395 */ 2396 if (amdgpu_device_supports_baco(ddev) && 2397 !(adev->flags & AMD_IS_APU) && 2398 (adev->asic_type >= CHIP_NAVI10)) 2399 amdgpu_get_secondary_funcs(adev); 2400 } 2401 2402 return 0; 2403 2404 err_pci: 2405 pci_disable_device(pdev); 2406 return ret; 2407 } 2408 2409 static void 2410 amdgpu_pci_remove(struct pci_dev *pdev) 2411 { 2412 struct drm_device *dev = pci_get_drvdata(pdev); 2413 struct amdgpu_device *adev = drm_to_adev(dev); 2414 2415 amdgpu_xcp_dev_unplug(adev); 2416 drm_dev_unplug(dev); 2417 2418 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2419 pm_runtime_get_sync(dev->dev); 2420 pm_runtime_forbid(dev->dev); 2421 } 2422 2423 amdgpu_driver_unload_kms(dev); 2424 2425 /* 2426 * Flush any in flight DMA operations from device. 2427 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2428 * StatusTransactions Pending bit. 2429 */ 2430 pci_disable_device(pdev); 2431 pci_wait_for_pending_transaction(pdev); 2432 } 2433 2434 static void 2435 amdgpu_pci_shutdown(struct pci_dev *pdev) 2436 { 2437 struct drm_device *dev = pci_get_drvdata(pdev); 2438 struct amdgpu_device *adev = drm_to_adev(dev); 2439 2440 if (amdgpu_ras_intr_triggered()) 2441 return; 2442 2443 /* if we are running in a VM, make sure the device 2444 * torn down properly on reboot/shutdown. 2445 * unfortunately we can't detect certain 2446 * hypervisors so just do this all the time. 2447 */ 2448 if (!amdgpu_passthrough(adev)) 2449 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2450 amdgpu_device_ip_suspend(adev); 2451 adev->mp1_state = PP_MP1_STATE_NONE; 2452 } 2453 2454 /** 2455 * amdgpu_drv_delayed_reset_work_handler - work handler for reset 2456 * 2457 * @work: work_struct. 2458 */ 2459 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) 2460 { 2461 struct list_head device_list; 2462 struct amdgpu_device *adev; 2463 int i, r; 2464 struct amdgpu_reset_context reset_context; 2465 2466 memset(&reset_context, 0, sizeof(reset_context)); 2467 2468 mutex_lock(&mgpu_info.mutex); 2469 if (mgpu_info.pending_reset == true) { 2470 mutex_unlock(&mgpu_info.mutex); 2471 return; 2472 } 2473 mgpu_info.pending_reset = true; 2474 mutex_unlock(&mgpu_info.mutex); 2475 2476 /* Use a common context, just need to make sure full reset is done */ 2477 reset_context.method = AMD_RESET_METHOD_NONE; 2478 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2479 2480 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2481 adev = mgpu_info.gpu_ins[i].adev; 2482 reset_context.reset_req_dev = adev; 2483 r = amdgpu_device_pre_asic_reset(adev, &reset_context); 2484 if (r) { 2485 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", 2486 r, adev_to_drm(adev)->unique); 2487 } 2488 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) 2489 r = -EALREADY; 2490 } 2491 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2492 adev = mgpu_info.gpu_ins[i].adev; 2493 flush_work(&adev->xgmi_reset_work); 2494 adev->gmc.xgmi.pending_reset = false; 2495 } 2496 2497 /* reset function will rebuild the xgmi hive info , clear it now */ 2498 for (i = 0; i < mgpu_info.num_dgpu; i++) 2499 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); 2500 2501 INIT_LIST_HEAD(&device_list); 2502 2503 for (i = 0; i < mgpu_info.num_dgpu; i++) 2504 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); 2505 2506 /* unregister the GPU first, reset function will add them back */ 2507 list_for_each_entry(adev, &device_list, reset_list) 2508 amdgpu_unregister_gpu_instance(adev); 2509 2510 /* Use a common context, just need to make sure full reset is done */ 2511 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); 2512 set_bit(AMDGPU_SKIP_COREDUMP, &reset_context.flags); 2513 r = amdgpu_do_asic_reset(&device_list, &reset_context); 2514 2515 if (r) { 2516 DRM_ERROR("reinit gpus failure"); 2517 return; 2518 } 2519 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2520 adev = mgpu_info.gpu_ins[i].adev; 2521 if (!adev->kfd.init_complete) { 2522 kgd2kfd_init_zone_device(adev); 2523 amdgpu_amdkfd_device_init(adev); 2524 amdgpu_amdkfd_drm_client_create(adev); 2525 } 2526 amdgpu_ttm_set_buffer_funcs_status(adev, true); 2527 } 2528 } 2529 2530 static int amdgpu_pmops_prepare(struct device *dev) 2531 { 2532 struct drm_device *drm_dev = dev_get_drvdata(dev); 2533 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2534 2535 /* Return a positive number here so 2536 * DPM_FLAG_SMART_SUSPEND works properly 2537 */ 2538 if (amdgpu_device_supports_boco(drm_dev) && 2539 pm_runtime_suspended(dev)) 2540 return 1; 2541 2542 /* if we will not support s3 or s2i for the device 2543 * then skip suspend 2544 */ 2545 if (!amdgpu_acpi_is_s0ix_active(adev) && 2546 !amdgpu_acpi_is_s3_active(adev)) 2547 return 1; 2548 2549 return amdgpu_device_prepare(drm_dev); 2550 } 2551 2552 static void amdgpu_pmops_complete(struct device *dev) 2553 { 2554 /* nothing to do */ 2555 } 2556 2557 static int amdgpu_pmops_suspend(struct device *dev) 2558 { 2559 struct drm_device *drm_dev = dev_get_drvdata(dev); 2560 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2561 2562 adev->suspend_complete = false; 2563 if (amdgpu_acpi_is_s0ix_active(adev)) 2564 adev->in_s0ix = true; 2565 else if (amdgpu_acpi_is_s3_active(adev)) 2566 adev->in_s3 = true; 2567 if (!adev->in_s0ix && !adev->in_s3) 2568 return 0; 2569 return amdgpu_device_suspend(drm_dev, true); 2570 } 2571 2572 static int amdgpu_pmops_suspend_noirq(struct device *dev) 2573 { 2574 struct drm_device *drm_dev = dev_get_drvdata(dev); 2575 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2576 2577 adev->suspend_complete = true; 2578 if (amdgpu_acpi_should_gpu_reset(adev)) 2579 return amdgpu_asic_reset(adev); 2580 2581 return 0; 2582 } 2583 2584 static int amdgpu_pmops_resume(struct device *dev) 2585 { 2586 struct drm_device *drm_dev = dev_get_drvdata(dev); 2587 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2588 int r; 2589 2590 if (!adev->in_s0ix && !adev->in_s3) 2591 return 0; 2592 2593 /* Avoids registers access if device is physically gone */ 2594 if (!pci_device_is_present(adev->pdev)) 2595 adev->no_hw_access = true; 2596 2597 r = amdgpu_device_resume(drm_dev, true); 2598 if (amdgpu_acpi_is_s0ix_active(adev)) 2599 adev->in_s0ix = false; 2600 else 2601 adev->in_s3 = false; 2602 return r; 2603 } 2604 2605 static int amdgpu_pmops_freeze(struct device *dev) 2606 { 2607 struct drm_device *drm_dev = dev_get_drvdata(dev); 2608 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2609 int r; 2610 2611 adev->in_s4 = true; 2612 r = amdgpu_device_suspend(drm_dev, true); 2613 adev->in_s4 = false; 2614 if (r) 2615 return r; 2616 2617 if (amdgpu_acpi_should_gpu_reset(adev)) 2618 return amdgpu_asic_reset(adev); 2619 return 0; 2620 } 2621 2622 static int amdgpu_pmops_thaw(struct device *dev) 2623 { 2624 struct drm_device *drm_dev = dev_get_drvdata(dev); 2625 2626 return amdgpu_device_resume(drm_dev, true); 2627 } 2628 2629 static int amdgpu_pmops_poweroff(struct device *dev) 2630 { 2631 struct drm_device *drm_dev = dev_get_drvdata(dev); 2632 2633 return amdgpu_device_suspend(drm_dev, true); 2634 } 2635 2636 static int amdgpu_pmops_restore(struct device *dev) 2637 { 2638 struct drm_device *drm_dev = dev_get_drvdata(dev); 2639 2640 return amdgpu_device_resume(drm_dev, true); 2641 } 2642 2643 static int amdgpu_runtime_idle_check_display(struct device *dev) 2644 { 2645 struct pci_dev *pdev = to_pci_dev(dev); 2646 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2647 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2648 2649 if (adev->mode_info.num_crtc) { 2650 struct drm_connector *list_connector; 2651 struct drm_connector_list_iter iter; 2652 int ret = 0; 2653 2654 if (amdgpu_runtime_pm != -2) { 2655 /* XXX: Return busy if any displays are connected to avoid 2656 * possible display wakeups after runtime resume due to 2657 * hotplug events in case any displays were connected while 2658 * the GPU was in suspend. Remove this once that is fixed. 2659 */ 2660 mutex_lock(&drm_dev->mode_config.mutex); 2661 drm_connector_list_iter_begin(drm_dev, &iter); 2662 drm_for_each_connector_iter(list_connector, &iter) { 2663 if (list_connector->status == connector_status_connected) { 2664 ret = -EBUSY; 2665 break; 2666 } 2667 } 2668 drm_connector_list_iter_end(&iter); 2669 mutex_unlock(&drm_dev->mode_config.mutex); 2670 2671 if (ret) 2672 return ret; 2673 } 2674 2675 if (adev->dc_enabled) { 2676 struct drm_crtc *crtc; 2677 2678 drm_for_each_crtc(crtc, drm_dev) { 2679 drm_modeset_lock(&crtc->mutex, NULL); 2680 if (crtc->state->active) 2681 ret = -EBUSY; 2682 drm_modeset_unlock(&crtc->mutex); 2683 if (ret < 0) 2684 break; 2685 } 2686 } else { 2687 mutex_lock(&drm_dev->mode_config.mutex); 2688 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2689 2690 drm_connector_list_iter_begin(drm_dev, &iter); 2691 drm_for_each_connector_iter(list_connector, &iter) { 2692 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2693 ret = -EBUSY; 2694 break; 2695 } 2696 } 2697 2698 drm_connector_list_iter_end(&iter); 2699 2700 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2701 mutex_unlock(&drm_dev->mode_config.mutex); 2702 } 2703 if (ret) 2704 return ret; 2705 } 2706 2707 return 0; 2708 } 2709 2710 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2711 { 2712 struct pci_dev *pdev = to_pci_dev(dev); 2713 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2714 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2715 int ret, i; 2716 2717 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2718 pm_runtime_forbid(dev); 2719 return -EBUSY; 2720 } 2721 2722 ret = amdgpu_runtime_idle_check_display(dev); 2723 if (ret) 2724 return ret; 2725 2726 /* wait for all rings to drain before suspending */ 2727 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2728 struct amdgpu_ring *ring = adev->rings[i]; 2729 2730 if (ring && ring->sched.ready) { 2731 ret = amdgpu_fence_wait_empty(ring); 2732 if (ret) 2733 return -EBUSY; 2734 } 2735 } 2736 2737 adev->in_runpm = true; 2738 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2739 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2740 2741 /* 2742 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2743 * proper cleanups and put itself into a state ready for PNP. That 2744 * can address some random resuming failure observed on BOCO capable 2745 * platforms. 2746 * TODO: this may be also needed for PX capable platform. 2747 */ 2748 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2749 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2750 2751 ret = amdgpu_device_prepare(drm_dev); 2752 if (ret) 2753 return ret; 2754 ret = amdgpu_device_suspend(drm_dev, false); 2755 if (ret) { 2756 adev->in_runpm = false; 2757 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2758 adev->mp1_state = PP_MP1_STATE_NONE; 2759 return ret; 2760 } 2761 2762 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2763 adev->mp1_state = PP_MP1_STATE_NONE; 2764 2765 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) { 2766 /* Only need to handle PCI state in the driver for ATPX 2767 * PCI core handles it for _PR3. 2768 */ 2769 amdgpu_device_cache_pci_state(pdev); 2770 pci_disable_device(pdev); 2771 pci_ignore_hotplug(pdev); 2772 pci_set_power_state(pdev, PCI_D3cold); 2773 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2774 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) { 2775 /* nothing to do */ 2776 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2777 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) { 2778 amdgpu_device_baco_enter(drm_dev); 2779 } 2780 2781 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n"); 2782 2783 return 0; 2784 } 2785 2786 static int amdgpu_pmops_runtime_resume(struct device *dev) 2787 { 2788 struct pci_dev *pdev = to_pci_dev(dev); 2789 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2790 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2791 int ret; 2792 2793 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) 2794 return -EINVAL; 2795 2796 /* Avoids registers access if device is physically gone */ 2797 if (!pci_device_is_present(adev->pdev)) 2798 adev->no_hw_access = true; 2799 2800 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) { 2801 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2802 2803 /* Only need to handle PCI state in the driver for ATPX 2804 * PCI core handles it for _PR3. 2805 */ 2806 pci_set_power_state(pdev, PCI_D0); 2807 amdgpu_device_load_pci_state(pdev); 2808 ret = pci_enable_device(pdev); 2809 if (ret) 2810 return ret; 2811 pci_set_master(pdev); 2812 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) { 2813 /* Only need to handle PCI state in the driver for ATPX 2814 * PCI core handles it for _PR3. 2815 */ 2816 pci_set_master(pdev); 2817 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2818 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) { 2819 amdgpu_device_baco_exit(drm_dev); 2820 } 2821 ret = amdgpu_device_resume(drm_dev, false); 2822 if (ret) { 2823 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2824 pci_disable_device(pdev); 2825 return ret; 2826 } 2827 2828 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2829 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2830 adev->in_runpm = false; 2831 return 0; 2832 } 2833 2834 static int amdgpu_pmops_runtime_idle(struct device *dev) 2835 { 2836 struct drm_device *drm_dev = dev_get_drvdata(dev); 2837 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2838 int ret; 2839 2840 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2841 pm_runtime_forbid(dev); 2842 return -EBUSY; 2843 } 2844 2845 ret = amdgpu_runtime_idle_check_display(dev); 2846 2847 pm_runtime_mark_last_busy(dev); 2848 pm_runtime_autosuspend(dev); 2849 return ret; 2850 } 2851 2852 long amdgpu_drm_ioctl(struct file *filp, 2853 unsigned int cmd, unsigned long arg) 2854 { 2855 struct drm_file *file_priv = filp->private_data; 2856 struct drm_device *dev; 2857 long ret; 2858 2859 dev = file_priv->minor->dev; 2860 ret = pm_runtime_get_sync(dev->dev); 2861 if (ret < 0) 2862 goto out; 2863 2864 ret = drm_ioctl(filp, cmd, arg); 2865 2866 pm_runtime_mark_last_busy(dev->dev); 2867 out: 2868 pm_runtime_put_autosuspend(dev->dev); 2869 return ret; 2870 } 2871 2872 static const struct dev_pm_ops amdgpu_pm_ops = { 2873 .prepare = amdgpu_pmops_prepare, 2874 .complete = amdgpu_pmops_complete, 2875 .suspend = amdgpu_pmops_suspend, 2876 .suspend_noirq = amdgpu_pmops_suspend_noirq, 2877 .resume = amdgpu_pmops_resume, 2878 .freeze = amdgpu_pmops_freeze, 2879 .thaw = amdgpu_pmops_thaw, 2880 .poweroff = amdgpu_pmops_poweroff, 2881 .restore = amdgpu_pmops_restore, 2882 .runtime_suspend = amdgpu_pmops_runtime_suspend, 2883 .runtime_resume = amdgpu_pmops_runtime_resume, 2884 .runtime_idle = amdgpu_pmops_runtime_idle, 2885 }; 2886 2887 static int amdgpu_flush(struct file *f, fl_owner_t id) 2888 { 2889 struct drm_file *file_priv = f->private_data; 2890 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2891 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2892 2893 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 2894 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 2895 2896 return timeout >= 0 ? 0 : timeout; 2897 } 2898 2899 static const struct file_operations amdgpu_driver_kms_fops = { 2900 .owner = THIS_MODULE, 2901 .open = drm_open, 2902 .flush = amdgpu_flush, 2903 .release = drm_release, 2904 .unlocked_ioctl = amdgpu_drm_ioctl, 2905 .mmap = drm_gem_mmap, 2906 .poll = drm_poll, 2907 .read = drm_read, 2908 #ifdef CONFIG_COMPAT 2909 .compat_ioctl = amdgpu_kms_compat_ioctl, 2910 #endif 2911 #ifdef CONFIG_PROC_FS 2912 .show_fdinfo = drm_show_fdinfo, 2913 #endif 2914 }; 2915 2916 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 2917 { 2918 struct drm_file *file; 2919 2920 if (!filp) 2921 return -EINVAL; 2922 2923 if (filp->f_op != &amdgpu_driver_kms_fops) 2924 return -EINVAL; 2925 2926 file = filp->private_data; 2927 *fpriv = file->driver_priv; 2928 return 0; 2929 } 2930 2931 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 2932 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2933 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2934 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2935 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 2936 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2937 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2938 /* KMS */ 2939 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2940 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2941 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2942 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2943 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2944 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2945 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2946 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2947 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2948 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2949 }; 2950 2951 static const struct drm_driver amdgpu_kms_driver = { 2952 .driver_features = 2953 DRIVER_ATOMIC | 2954 DRIVER_GEM | 2955 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 2956 DRIVER_SYNCOBJ_TIMELINE, 2957 .open = amdgpu_driver_open_kms, 2958 .postclose = amdgpu_driver_postclose_kms, 2959 .lastclose = amdgpu_driver_lastclose_kms, 2960 .ioctls = amdgpu_ioctls_kms, 2961 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2962 .dumb_create = amdgpu_mode_dumb_create, 2963 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2964 .fops = &amdgpu_driver_kms_fops, 2965 .release = &amdgpu_driver_release_kms, 2966 #ifdef CONFIG_PROC_FS 2967 .show_fdinfo = amdgpu_show_fdinfo, 2968 #endif 2969 2970 .gem_prime_import = amdgpu_gem_prime_import, 2971 2972 .name = DRIVER_NAME, 2973 .desc = DRIVER_DESC, 2974 .date = DRIVER_DATE, 2975 .major = KMS_DRIVER_MAJOR, 2976 .minor = KMS_DRIVER_MINOR, 2977 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2978 }; 2979 2980 const struct drm_driver amdgpu_partition_driver = { 2981 .driver_features = 2982 DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ | 2983 DRIVER_SYNCOBJ_TIMELINE, 2984 .open = amdgpu_driver_open_kms, 2985 .postclose = amdgpu_driver_postclose_kms, 2986 .lastclose = amdgpu_driver_lastclose_kms, 2987 .ioctls = amdgpu_ioctls_kms, 2988 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2989 .dumb_create = amdgpu_mode_dumb_create, 2990 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2991 .fops = &amdgpu_driver_kms_fops, 2992 .release = &amdgpu_driver_release_kms, 2993 2994 .gem_prime_import = amdgpu_gem_prime_import, 2995 2996 .name = DRIVER_NAME, 2997 .desc = DRIVER_DESC, 2998 .date = DRIVER_DATE, 2999 .major = KMS_DRIVER_MAJOR, 3000 .minor = KMS_DRIVER_MINOR, 3001 .patchlevel = KMS_DRIVER_PATCHLEVEL, 3002 }; 3003 3004 static struct pci_error_handlers amdgpu_pci_err_handler = { 3005 .error_detected = amdgpu_pci_error_detected, 3006 .mmio_enabled = amdgpu_pci_mmio_enabled, 3007 .slot_reset = amdgpu_pci_slot_reset, 3008 .resume = amdgpu_pci_resume, 3009 }; 3010 3011 static const struct attribute_group *amdgpu_sysfs_groups[] = { 3012 &amdgpu_vram_mgr_attr_group, 3013 &amdgpu_gtt_mgr_attr_group, 3014 &amdgpu_flash_attr_group, 3015 NULL, 3016 }; 3017 3018 static struct pci_driver amdgpu_kms_pci_driver = { 3019 .name = DRIVER_NAME, 3020 .id_table = pciidlist, 3021 .probe = amdgpu_pci_probe, 3022 .remove = amdgpu_pci_remove, 3023 .shutdown = amdgpu_pci_shutdown, 3024 .driver.pm = &amdgpu_pm_ops, 3025 .err_handler = &amdgpu_pci_err_handler, 3026 .dev_groups = amdgpu_sysfs_groups, 3027 }; 3028 3029 static int __init amdgpu_init(void) 3030 { 3031 int r; 3032 3033 if (drm_firmware_drivers_only()) 3034 return -EINVAL; 3035 3036 r = amdgpu_sync_init(); 3037 if (r) 3038 goto error_sync; 3039 3040 r = amdgpu_fence_slab_init(); 3041 if (r) 3042 goto error_fence; 3043 3044 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 3045 amdgpu_register_atpx_handler(); 3046 amdgpu_acpi_detect(); 3047 3048 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 3049 amdgpu_amdkfd_init(); 3050 3051 /* let modprobe override vga console setting */ 3052 return pci_register_driver(&amdgpu_kms_pci_driver); 3053 3054 error_fence: 3055 amdgpu_sync_fini(); 3056 3057 error_sync: 3058 return r; 3059 } 3060 3061 static void __exit amdgpu_exit(void) 3062 { 3063 amdgpu_amdkfd_fini(); 3064 pci_unregister_driver(&amdgpu_kms_pci_driver); 3065 amdgpu_unregister_atpx_handler(); 3066 amdgpu_acpi_release(); 3067 amdgpu_sync_fini(); 3068 amdgpu_fence_slab_fini(); 3069 mmu_notifier_synchronize(); 3070 amdgpu_xcp_drv_release(); 3071 } 3072 3073 module_init(amdgpu_init); 3074 module_exit(amdgpu_exit); 3075 3076 MODULE_AUTHOR(DRIVER_AUTHOR); 3077 MODULE_DESCRIPTION(DRIVER_DESC); 3078 MODULE_LICENSE("GPL and additional rights"); 3079