1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_aperture.h> 27 #include <drm/drm_drv.h> 28 #include <drm/drm_fbdev_generic.h> 29 #include <drm/drm_gem.h> 30 #include <drm/drm_vblank.h> 31 #include <drm/drm_managed.h> 32 #include "amdgpu_drv.h" 33 34 #include <drm/drm_pciids.h> 35 #include <linux/module.h> 36 #include <linux/pm_runtime.h> 37 #include <linux/vga_switcheroo.h> 38 #include <drm/drm_probe_helper.h> 39 #include <linux/mmu_notifier.h> 40 #include <linux/suspend.h> 41 #include <linux/cc_platform.h> 42 #include <linux/fb.h> 43 #include <linux/dynamic_debug.h> 44 45 #include "amdgpu.h" 46 #include "amdgpu_irq.h" 47 #include "amdgpu_dma_buf.h" 48 #include "amdgpu_sched.h" 49 #include "amdgpu_fdinfo.h" 50 #include "amdgpu_amdkfd.h" 51 52 #include "amdgpu_ras.h" 53 #include "amdgpu_xgmi.h" 54 #include "amdgpu_reset.h" 55 56 /* 57 * KMS wrapper. 58 * - 3.0.0 - initial driver 59 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 60 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 61 * at the end of IBs. 62 * - 3.3.0 - Add VM support for UVD on supported hardware. 63 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 64 * - 3.5.0 - Add support for new UVD_NO_OP register. 65 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 66 * - 3.7.0 - Add support for VCE clock list packet 67 * - 3.8.0 - Add support raster config init in the kernel 68 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 69 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 70 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 71 * - 3.12.0 - Add query for double offchip LDS buffers 72 * - 3.13.0 - Add PRT support 73 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 74 * - 3.15.0 - Export more gpu info for gfx9 75 * - 3.16.0 - Add reserved vmid support 76 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 77 * - 3.18.0 - Export gpu always on cu bitmap 78 * - 3.19.0 - Add support for UVD MJPEG decode 79 * - 3.20.0 - Add support for local BOs 80 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 81 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 82 * - 3.23.0 - Add query for VRAM lost counter 83 * - 3.24.0 - Add high priority compute support for gfx9 84 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 85 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 86 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation. 87 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 88 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 89 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 90 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 91 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 92 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 93 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 94 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 95 * - 3.36.0 - Allow reading more status registers on si/cik 96 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 97 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 98 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 99 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 100 * - 3.41.0 - Add video codec query 101 * - 3.42.0 - Add 16bpc fixed point display support 102 * - 3.43.0 - Add device hot plug/unplug support 103 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 104 * - 3.45.0 - Add context ioctl stable pstate interface 105 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm 106 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags 107 * - 3.48.0 - Add IP discovery version info to HW INFO 108 * - 3.49.0 - Add gang submit into CS IOCTL 109 * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock 110 * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock 111 */ 112 #define KMS_DRIVER_MAJOR 3 113 #define KMS_DRIVER_MINOR 50 114 #define KMS_DRIVER_PATCHLEVEL 0 115 116 unsigned int amdgpu_vram_limit = UINT_MAX; 117 int amdgpu_vis_vram_limit; 118 int amdgpu_gart_size = -1; /* auto */ 119 int amdgpu_gtt_size = -1; /* auto */ 120 int amdgpu_moverate = -1; /* auto */ 121 int amdgpu_audio = -1; 122 int amdgpu_disp_priority; 123 int amdgpu_hw_i2c; 124 int amdgpu_pcie_gen2 = -1; 125 int amdgpu_msi = -1; 126 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 127 int amdgpu_dpm = -1; 128 int amdgpu_fw_load_type = -1; 129 int amdgpu_aspm = -1; 130 int amdgpu_runtime_pm = -1; 131 uint amdgpu_ip_block_mask = 0xffffffff; 132 int amdgpu_bapm = -1; 133 int amdgpu_deep_color; 134 int amdgpu_vm_size = -1; 135 int amdgpu_vm_fragment_size = -1; 136 int amdgpu_vm_block_size = -1; 137 int amdgpu_vm_fault_stop; 138 int amdgpu_vm_debug; 139 int amdgpu_vm_update_mode = -1; 140 int amdgpu_exp_hw_support; 141 int amdgpu_dc = -1; 142 int amdgpu_sched_jobs = 32; 143 int amdgpu_sched_hw_submission = 2; 144 uint amdgpu_pcie_gen_cap; 145 uint amdgpu_pcie_lane_cap; 146 u64 amdgpu_cg_mask = 0xffffffffffffffff; 147 uint amdgpu_pg_mask = 0xffffffff; 148 uint amdgpu_sdma_phase_quantum = 32; 149 char *amdgpu_disable_cu = NULL; 150 char *amdgpu_virtual_display = NULL; 151 152 /* 153 * OverDrive(bit 14) disabled by default 154 * GFX DCS(bit 19) disabled by default 155 */ 156 uint amdgpu_pp_feature_mask = 0xfff7bfff; 157 uint amdgpu_force_long_training; 158 int amdgpu_job_hang_limit; 159 int amdgpu_lbpw = -1; 160 int amdgpu_compute_multipipe = -1; 161 int amdgpu_gpu_recovery = -1; /* auto */ 162 int amdgpu_emu_mode; 163 uint amdgpu_smu_memory_pool_size; 164 int amdgpu_smu_pptable_id = -1; 165 /* 166 * FBC (bit 0) disabled by default 167 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 168 * - With this, for multiple monitors in sync(e.g. with the same model), 169 * mclk switching will be allowed. And the mclk will be not foced to the 170 * highest. That helps saving some idle power. 171 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 172 * PSR (bit 3) disabled by default 173 * EDP NO POWER SEQUENCING (bit 4) disabled by default 174 */ 175 uint amdgpu_dc_feature_mask = 2; 176 uint amdgpu_dc_debug_mask; 177 uint amdgpu_dc_visual_confirm; 178 int amdgpu_async_gfx_ring = 1; 179 int amdgpu_mcbp; 180 int amdgpu_discovery = -1; 181 int amdgpu_mes; 182 int amdgpu_mes_kiq; 183 int amdgpu_noretry = -1; 184 int amdgpu_force_asic_type = -1; 185 int amdgpu_tmz = -1; /* auto */ 186 int amdgpu_reset_method = -1; /* auto */ 187 int amdgpu_num_kcq = -1; 188 int amdgpu_smartshift_bias; 189 int amdgpu_use_xgmi_p2p = 1; 190 int amdgpu_vcnfw_log; 191 192 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 193 194 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 195 "DRM_UT_CORE", 196 "DRM_UT_DRIVER", 197 "DRM_UT_KMS", 198 "DRM_UT_PRIME", 199 "DRM_UT_ATOMIC", 200 "DRM_UT_VBL", 201 "DRM_UT_STATE", 202 "DRM_UT_LEASE", 203 "DRM_UT_DP", 204 "DRM_UT_DRMRES"); 205 206 struct amdgpu_mgpu_info mgpu_info = { 207 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 208 .delayed_reset_work = __DELAYED_WORK_INITIALIZER( 209 mgpu_info.delayed_reset_work, 210 amdgpu_drv_delayed_reset_work_handler, 0), 211 }; 212 int amdgpu_ras_enable = -1; 213 uint amdgpu_ras_mask = 0xffffffff; 214 int amdgpu_bad_page_threshold = -1; 215 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 216 .timeout_fatal_disable = false, 217 .period = 0x0, /* default to 0x0 (timeout disable) */ 218 }; 219 220 /** 221 * DOC: vramlimit (int) 222 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 223 */ 224 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 225 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 226 227 /** 228 * DOC: vis_vramlimit (int) 229 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 230 */ 231 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 232 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 233 234 /** 235 * DOC: gartsize (uint) 236 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing. 237 * The default is -1 (The size depends on asic). 238 */ 239 MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)"); 240 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 241 242 /** 243 * DOC: gttsize (int) 244 * Restrict the size of GTT domain (for userspace use) in MiB for testing. 245 * The default is -1 (Use 1/2 RAM, minimum value is 3GB). 246 */ 247 MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)"); 248 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 249 250 /** 251 * DOC: moverate (int) 252 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 253 */ 254 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 255 module_param_named(moverate, amdgpu_moverate, int, 0600); 256 257 /** 258 * DOC: audio (int) 259 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 260 */ 261 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 262 module_param_named(audio, amdgpu_audio, int, 0444); 263 264 /** 265 * DOC: disp_priority (int) 266 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 267 */ 268 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 269 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 270 271 /** 272 * DOC: hw_i2c (int) 273 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 274 */ 275 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 276 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 277 278 /** 279 * DOC: pcie_gen2 (int) 280 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 281 */ 282 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 283 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 284 285 /** 286 * DOC: msi (int) 287 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 288 */ 289 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 290 module_param_named(msi, amdgpu_msi, int, 0444); 291 292 /** 293 * DOC: lockup_timeout (string) 294 * Set GPU scheduler timeout value in ms. 295 * 296 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 297 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 298 * to the default timeout. 299 * 300 * - With one value specified, the setting will apply to all non-compute jobs. 301 * - With multiple values specified, the first one will be for GFX. 302 * The second one is for Compute. The third and fourth ones are 303 * for SDMA and Video. 304 * 305 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 306 * jobs is 10000. The timeout for compute is 60000. 307 */ 308 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 309 "for passthrough or sriov, 10000 for all jobs." 310 " 0: keep default value. negative: infinity timeout), " 311 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 312 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 313 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 314 315 /** 316 * DOC: dpm (int) 317 * Override for dynamic power management setting 318 * (0 = disable, 1 = enable) 319 * The default is -1 (auto). 320 */ 321 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 322 module_param_named(dpm, amdgpu_dpm, int, 0444); 323 324 /** 325 * DOC: fw_load_type (int) 326 * Set different firmware loading type for debugging, if supported. 327 * Set to 0 to force direct loading if supported by the ASIC. Set 328 * to -1 to select the default loading mode for the ASIC, as defined 329 * by the driver. The default is -1 (auto). 330 */ 331 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); 332 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 333 334 /** 335 * DOC: aspm (int) 336 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 337 */ 338 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 339 module_param_named(aspm, amdgpu_aspm, int, 0444); 340 341 /** 342 * DOC: runpm (int) 343 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 344 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 345 * Setting the value to 0 disables this functionality. 346 */ 347 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto)"); 348 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 349 350 /** 351 * DOC: ip_block_mask (uint) 352 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 353 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 354 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 355 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 356 */ 357 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 358 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 359 360 /** 361 * DOC: bapm (int) 362 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 363 * The default -1 (auto, enabled) 364 */ 365 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 366 module_param_named(bapm, amdgpu_bapm, int, 0444); 367 368 /** 369 * DOC: deep_color (int) 370 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 371 */ 372 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 373 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 374 375 /** 376 * DOC: vm_size (int) 377 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 378 */ 379 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 380 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 381 382 /** 383 * DOC: vm_fragment_size (int) 384 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 385 */ 386 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 387 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 388 389 /** 390 * DOC: vm_block_size (int) 391 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 392 */ 393 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 394 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 395 396 /** 397 * DOC: vm_fault_stop (int) 398 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 399 */ 400 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 401 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 402 403 /** 404 * DOC: vm_debug (int) 405 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 406 */ 407 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 408 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 409 410 /** 411 * DOC: vm_update_mode (int) 412 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 413 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 414 */ 415 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 416 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 417 418 /** 419 * DOC: exp_hw_support (int) 420 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 421 */ 422 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 423 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 424 425 /** 426 * DOC: dc (int) 427 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 428 */ 429 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 430 module_param_named(dc, amdgpu_dc, int, 0444); 431 432 /** 433 * DOC: sched_jobs (int) 434 * Override the max number of jobs supported in the sw queue. The default is 32. 435 */ 436 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 437 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 438 439 /** 440 * DOC: sched_hw_submission (int) 441 * Override the max number of HW submissions. The default is 2. 442 */ 443 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 444 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 445 446 /** 447 * DOC: ppfeaturemask (hexint) 448 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 449 * The default is the current set of stable power features. 450 */ 451 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 452 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 453 454 /** 455 * DOC: forcelongtraining (uint) 456 * Force long memory training in resume. 457 * The default is zero, indicates short training in resume. 458 */ 459 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 460 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 461 462 /** 463 * DOC: pcie_gen_cap (uint) 464 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 465 * The default is 0 (automatic for each asic). 466 */ 467 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 468 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 469 470 /** 471 * DOC: pcie_lane_cap (uint) 472 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 473 * The default is 0 (automatic for each asic). 474 */ 475 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 476 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 477 478 /** 479 * DOC: cg_mask (ullong) 480 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 481 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 482 */ 483 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 484 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 485 486 /** 487 * DOC: pg_mask (uint) 488 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 489 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 490 */ 491 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 492 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 493 494 /** 495 * DOC: sdma_phase_quantum (uint) 496 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 497 */ 498 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 499 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 500 501 /** 502 * DOC: disable_cu (charp) 503 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 504 */ 505 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 506 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 507 508 /** 509 * DOC: virtual_display (charp) 510 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 511 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 512 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 513 * device at 26:00.0. The default is NULL. 514 */ 515 MODULE_PARM_DESC(virtual_display, 516 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 517 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 518 519 /** 520 * DOC: job_hang_limit (int) 521 * Set how much time allow a job hang and not drop it. The default is 0. 522 */ 523 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 524 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 525 526 /** 527 * DOC: lbpw (int) 528 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 529 */ 530 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 531 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 532 533 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 534 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 535 536 /** 537 * DOC: gpu_recovery (int) 538 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 539 */ 540 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 541 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 542 543 /** 544 * DOC: emu_mode (int) 545 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 546 */ 547 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 548 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 549 550 /** 551 * DOC: ras_enable (int) 552 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 553 */ 554 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 555 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 556 557 /** 558 * DOC: ras_mask (uint) 559 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 560 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 561 */ 562 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 563 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 564 565 /** 566 * DOC: timeout_fatal_disable (bool) 567 * Disable Watchdog timeout fatal error event 568 */ 569 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 570 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 571 572 /** 573 * DOC: timeout_period (uint) 574 * Modify the watchdog timeout max_cycles as (1 << period) 575 */ 576 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 577 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 578 579 /** 580 * DOC: si_support (int) 581 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 582 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 583 * otherwise using amdgpu driver. 584 */ 585 #ifdef CONFIG_DRM_AMDGPU_SI 586 587 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 588 int amdgpu_si_support = 0; 589 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 590 #else 591 int amdgpu_si_support = 1; 592 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 593 #endif 594 595 module_param_named(si_support, amdgpu_si_support, int, 0444); 596 #endif 597 598 /** 599 * DOC: cik_support (int) 600 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 601 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 602 * otherwise using amdgpu driver. 603 */ 604 #ifdef CONFIG_DRM_AMDGPU_CIK 605 606 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 607 int amdgpu_cik_support = 0; 608 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 609 #else 610 int amdgpu_cik_support = 1; 611 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 612 #endif 613 614 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 615 #endif 616 617 /** 618 * DOC: smu_memory_pool_size (uint) 619 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 620 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 621 */ 622 MODULE_PARM_DESC(smu_memory_pool_size, 623 "reserve gtt for smu debug usage, 0 = disable," 624 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 625 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 626 627 /** 628 * DOC: async_gfx_ring (int) 629 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 630 */ 631 MODULE_PARM_DESC(async_gfx_ring, 632 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 633 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 634 635 /** 636 * DOC: mcbp (int) 637 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled) 638 */ 639 MODULE_PARM_DESC(mcbp, 640 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); 641 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 642 643 /** 644 * DOC: discovery (int) 645 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 646 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 647 */ 648 MODULE_PARM_DESC(discovery, 649 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 650 module_param_named(discovery, amdgpu_discovery, int, 0444); 651 652 /** 653 * DOC: mes (int) 654 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 655 * (0 = disabled (default), 1 = enabled) 656 */ 657 MODULE_PARM_DESC(mes, 658 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 659 module_param_named(mes, amdgpu_mes, int, 0444); 660 661 /** 662 * DOC: mes_kiq (int) 663 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq. 664 * (0 = disabled (default), 1 = enabled) 665 */ 666 MODULE_PARM_DESC(mes_kiq, 667 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)"); 668 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444); 669 670 /** 671 * DOC: noretry (int) 672 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 673 * do not support per-process XNACK this also disables retry page faults. 674 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 675 */ 676 MODULE_PARM_DESC(noretry, 677 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 678 module_param_named(noretry, amdgpu_noretry, int, 0644); 679 680 /** 681 * DOC: force_asic_type (int) 682 * A non negative value used to specify the asic type for all supported GPUs. 683 */ 684 MODULE_PARM_DESC(force_asic_type, 685 "A non negative value used to specify the asic type for all supported GPUs"); 686 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 687 688 /** 689 * DOC: use_xgmi_p2p (int) 690 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 691 */ 692 MODULE_PARM_DESC(use_xgmi_p2p, 693 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 694 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 695 696 697 #ifdef CONFIG_HSA_AMD 698 /** 699 * DOC: sched_policy (int) 700 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 701 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 702 * assigns queues to HQDs. 703 */ 704 int sched_policy = KFD_SCHED_POLICY_HWS; 705 module_param(sched_policy, int, 0444); 706 MODULE_PARM_DESC(sched_policy, 707 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 708 709 /** 710 * DOC: hws_max_conc_proc (int) 711 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 712 * number of VMIDs assigned to the HWS, which is also the default. 713 */ 714 int hws_max_conc_proc = -1; 715 module_param(hws_max_conc_proc, int, 0444); 716 MODULE_PARM_DESC(hws_max_conc_proc, 717 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 718 719 /** 720 * DOC: cwsr_enable (int) 721 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 722 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 723 * disables it. 724 */ 725 int cwsr_enable = 1; 726 module_param(cwsr_enable, int, 0444); 727 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 728 729 /** 730 * DOC: max_num_of_queues_per_device (int) 731 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 732 * is 4096. 733 */ 734 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 735 module_param(max_num_of_queues_per_device, int, 0444); 736 MODULE_PARM_DESC(max_num_of_queues_per_device, 737 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 738 739 /** 740 * DOC: send_sigterm (int) 741 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 742 * but just print errors on dmesg. Setting 1 enables sending sigterm. 743 */ 744 int send_sigterm; 745 module_param(send_sigterm, int, 0444); 746 MODULE_PARM_DESC(send_sigterm, 747 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 748 749 /** 750 * DOC: debug_largebar (int) 751 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 752 * system. This limits the VRAM size reported to ROCm applications to the visible 753 * size, usually 256MB. 754 * Default value is 0, diabled. 755 */ 756 int debug_largebar; 757 module_param(debug_largebar, int, 0444); 758 MODULE_PARM_DESC(debug_largebar, 759 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 760 761 /** 762 * DOC: ignore_crat (int) 763 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 764 * table to get information about AMD APUs. This option can serve as a workaround on 765 * systems with a broken CRAT table. 766 * 767 * Default is auto (according to asic type, iommu_v2, and crat table, to decide 768 * whether use CRAT) 769 */ 770 int ignore_crat; 771 module_param(ignore_crat, int, 0444); 772 MODULE_PARM_DESC(ignore_crat, 773 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)"); 774 775 /** 776 * DOC: halt_if_hws_hang (int) 777 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 778 * Setting 1 enables halt on hang. 779 */ 780 int halt_if_hws_hang; 781 module_param(halt_if_hws_hang, int, 0644); 782 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 783 784 /** 785 * DOC: hws_gws_support(bool) 786 * Assume that HWS supports GWS barriers regardless of what firmware version 787 * check says. Default value: false (rely on MEC2 firmware version check). 788 */ 789 bool hws_gws_support; 790 module_param(hws_gws_support, bool, 0444); 791 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 792 793 /** 794 * DOC: queue_preemption_timeout_ms (int) 795 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 796 */ 797 int queue_preemption_timeout_ms = 9000; 798 module_param(queue_preemption_timeout_ms, int, 0644); 799 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 800 801 /** 802 * DOC: debug_evictions(bool) 803 * Enable extra debug messages to help determine the cause of evictions 804 */ 805 bool debug_evictions; 806 module_param(debug_evictions, bool, 0644); 807 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 808 809 /** 810 * DOC: no_system_mem_limit(bool) 811 * Disable system memory limit, to support multiple process shared memory 812 */ 813 bool no_system_mem_limit; 814 module_param(no_system_mem_limit, bool, 0644); 815 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 816 817 /** 818 * DOC: no_queue_eviction_on_vm_fault (int) 819 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 820 */ 821 int amdgpu_no_queue_eviction_on_vm_fault = 0; 822 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 823 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 824 #endif 825 826 /** 827 * DOC: pcie_p2p (bool) 828 * Enable PCIe P2P (requires large-BAR). Default value: true (on) 829 */ 830 #ifdef CONFIG_HSA_AMD_P2P 831 bool pcie_p2p = true; 832 module_param(pcie_p2p, bool, 0444); 833 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); 834 #endif 835 836 /** 837 * DOC: dcfeaturemask (uint) 838 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 839 * The default is the current set of stable display features. 840 */ 841 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 842 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 843 844 /** 845 * DOC: dcdebugmask (uint) 846 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 847 */ 848 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 849 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 850 851 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)"); 852 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444); 853 854 /** 855 * DOC: abmlevel (uint) 856 * Override the default ABM (Adaptive Backlight Management) level used for DC 857 * enabled hardware. Requires DMCU to be supported and loaded. 858 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 859 * default. Values 1-4 control the maximum allowable brightness reduction via 860 * the ABM algorithm, with 1 being the least reduction and 4 being the most 861 * reduction. 862 * 863 * Defaults to 0, or disabled. Userspace can still override this level later 864 * after boot. 865 */ 866 uint amdgpu_dm_abm_level; 867 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 868 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 869 870 int amdgpu_backlight = -1; 871 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 872 module_param_named(backlight, amdgpu_backlight, bint, 0444); 873 874 /** 875 * DOC: tmz (int) 876 * Trusted Memory Zone (TMZ) is a method to protect data being written 877 * to or read from memory. 878 * 879 * The default value: 0 (off). TODO: change to auto till it is completed. 880 */ 881 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 882 module_param_named(tmz, amdgpu_tmz, int, 0444); 883 884 /** 885 * DOC: reset_method (int) 886 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 887 */ 888 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 889 module_param_named(reset_method, amdgpu_reset_method, int, 0444); 890 891 /** 892 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 893 * threshold value of faulty pages detected by RAS ECC, which may 894 * result in the GPU entering bad status when the number of total 895 * faulty pages by ECC exceeds the threshold value. 896 */ 897 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement, -2 = ignore bad page threshold)"); 898 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 899 900 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 901 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 902 903 /** 904 * DOC: vcnfw_log (int) 905 * Enable vcnfw log output for debugging, the default is disabled. 906 */ 907 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 908 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 909 910 /** 911 * DOC: smu_pptable_id (int) 912 * Used to override pptable id. id = 0 use VBIOS pptable. 913 * id > 0 use the soft pptable with specicfied id. 914 */ 915 MODULE_PARM_DESC(smu_pptable_id, 916 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 917 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 918 919 /* These devices are not supported by amdgpu. 920 * They are supported by the mach64, r128, radeon drivers 921 */ 922 static const u16 amdgpu_unsupported_pciidlist[] = { 923 /* mach64 */ 924 0x4354, 925 0x4358, 926 0x4554, 927 0x4742, 928 0x4744, 929 0x4749, 930 0x474C, 931 0x474D, 932 0x474E, 933 0x474F, 934 0x4750, 935 0x4751, 936 0x4752, 937 0x4753, 938 0x4754, 939 0x4755, 940 0x4756, 941 0x4757, 942 0x4758, 943 0x4759, 944 0x475A, 945 0x4C42, 946 0x4C44, 947 0x4C47, 948 0x4C49, 949 0x4C4D, 950 0x4C4E, 951 0x4C50, 952 0x4C51, 953 0x4C52, 954 0x4C53, 955 0x5654, 956 0x5655, 957 0x5656, 958 /* r128 */ 959 0x4c45, 960 0x4c46, 961 0x4d46, 962 0x4d4c, 963 0x5041, 964 0x5042, 965 0x5043, 966 0x5044, 967 0x5045, 968 0x5046, 969 0x5047, 970 0x5048, 971 0x5049, 972 0x504A, 973 0x504B, 974 0x504C, 975 0x504D, 976 0x504E, 977 0x504F, 978 0x5050, 979 0x5051, 980 0x5052, 981 0x5053, 982 0x5054, 983 0x5055, 984 0x5056, 985 0x5057, 986 0x5058, 987 0x5245, 988 0x5246, 989 0x5247, 990 0x524b, 991 0x524c, 992 0x534d, 993 0x5446, 994 0x544C, 995 0x5452, 996 /* radeon */ 997 0x3150, 998 0x3151, 999 0x3152, 1000 0x3154, 1001 0x3155, 1002 0x3E50, 1003 0x3E54, 1004 0x4136, 1005 0x4137, 1006 0x4144, 1007 0x4145, 1008 0x4146, 1009 0x4147, 1010 0x4148, 1011 0x4149, 1012 0x414A, 1013 0x414B, 1014 0x4150, 1015 0x4151, 1016 0x4152, 1017 0x4153, 1018 0x4154, 1019 0x4155, 1020 0x4156, 1021 0x4237, 1022 0x4242, 1023 0x4336, 1024 0x4337, 1025 0x4437, 1026 0x4966, 1027 0x4967, 1028 0x4A48, 1029 0x4A49, 1030 0x4A4A, 1031 0x4A4B, 1032 0x4A4C, 1033 0x4A4D, 1034 0x4A4E, 1035 0x4A4F, 1036 0x4A50, 1037 0x4A54, 1038 0x4B48, 1039 0x4B49, 1040 0x4B4A, 1041 0x4B4B, 1042 0x4B4C, 1043 0x4C57, 1044 0x4C58, 1045 0x4C59, 1046 0x4C5A, 1047 0x4C64, 1048 0x4C66, 1049 0x4C67, 1050 0x4E44, 1051 0x4E45, 1052 0x4E46, 1053 0x4E47, 1054 0x4E48, 1055 0x4E49, 1056 0x4E4A, 1057 0x4E4B, 1058 0x4E50, 1059 0x4E51, 1060 0x4E52, 1061 0x4E53, 1062 0x4E54, 1063 0x4E56, 1064 0x5144, 1065 0x5145, 1066 0x5146, 1067 0x5147, 1068 0x5148, 1069 0x514C, 1070 0x514D, 1071 0x5157, 1072 0x5158, 1073 0x5159, 1074 0x515A, 1075 0x515E, 1076 0x5460, 1077 0x5462, 1078 0x5464, 1079 0x5548, 1080 0x5549, 1081 0x554A, 1082 0x554B, 1083 0x554C, 1084 0x554D, 1085 0x554E, 1086 0x554F, 1087 0x5550, 1088 0x5551, 1089 0x5552, 1090 0x5554, 1091 0x564A, 1092 0x564B, 1093 0x564F, 1094 0x5652, 1095 0x5653, 1096 0x5657, 1097 0x5834, 1098 0x5835, 1099 0x5954, 1100 0x5955, 1101 0x5974, 1102 0x5975, 1103 0x5960, 1104 0x5961, 1105 0x5962, 1106 0x5964, 1107 0x5965, 1108 0x5969, 1109 0x5a41, 1110 0x5a42, 1111 0x5a61, 1112 0x5a62, 1113 0x5b60, 1114 0x5b62, 1115 0x5b63, 1116 0x5b64, 1117 0x5b65, 1118 0x5c61, 1119 0x5c63, 1120 0x5d48, 1121 0x5d49, 1122 0x5d4a, 1123 0x5d4c, 1124 0x5d4d, 1125 0x5d4e, 1126 0x5d4f, 1127 0x5d50, 1128 0x5d52, 1129 0x5d57, 1130 0x5e48, 1131 0x5e4a, 1132 0x5e4b, 1133 0x5e4c, 1134 0x5e4d, 1135 0x5e4f, 1136 0x6700, 1137 0x6701, 1138 0x6702, 1139 0x6703, 1140 0x6704, 1141 0x6705, 1142 0x6706, 1143 0x6707, 1144 0x6708, 1145 0x6709, 1146 0x6718, 1147 0x6719, 1148 0x671c, 1149 0x671d, 1150 0x671f, 1151 0x6720, 1152 0x6721, 1153 0x6722, 1154 0x6723, 1155 0x6724, 1156 0x6725, 1157 0x6726, 1158 0x6727, 1159 0x6728, 1160 0x6729, 1161 0x6738, 1162 0x6739, 1163 0x673e, 1164 0x6740, 1165 0x6741, 1166 0x6742, 1167 0x6743, 1168 0x6744, 1169 0x6745, 1170 0x6746, 1171 0x6747, 1172 0x6748, 1173 0x6749, 1174 0x674A, 1175 0x6750, 1176 0x6751, 1177 0x6758, 1178 0x6759, 1179 0x675B, 1180 0x675D, 1181 0x675F, 1182 0x6760, 1183 0x6761, 1184 0x6762, 1185 0x6763, 1186 0x6764, 1187 0x6765, 1188 0x6766, 1189 0x6767, 1190 0x6768, 1191 0x6770, 1192 0x6771, 1193 0x6772, 1194 0x6778, 1195 0x6779, 1196 0x677B, 1197 0x6840, 1198 0x6841, 1199 0x6842, 1200 0x6843, 1201 0x6849, 1202 0x684C, 1203 0x6850, 1204 0x6858, 1205 0x6859, 1206 0x6880, 1207 0x6888, 1208 0x6889, 1209 0x688A, 1210 0x688C, 1211 0x688D, 1212 0x6898, 1213 0x6899, 1214 0x689b, 1215 0x689c, 1216 0x689d, 1217 0x689e, 1218 0x68a0, 1219 0x68a1, 1220 0x68a8, 1221 0x68a9, 1222 0x68b0, 1223 0x68b8, 1224 0x68b9, 1225 0x68ba, 1226 0x68be, 1227 0x68bf, 1228 0x68c0, 1229 0x68c1, 1230 0x68c7, 1231 0x68c8, 1232 0x68c9, 1233 0x68d8, 1234 0x68d9, 1235 0x68da, 1236 0x68de, 1237 0x68e0, 1238 0x68e1, 1239 0x68e4, 1240 0x68e5, 1241 0x68e8, 1242 0x68e9, 1243 0x68f1, 1244 0x68f2, 1245 0x68f8, 1246 0x68f9, 1247 0x68fa, 1248 0x68fe, 1249 0x7100, 1250 0x7101, 1251 0x7102, 1252 0x7103, 1253 0x7104, 1254 0x7105, 1255 0x7106, 1256 0x7108, 1257 0x7109, 1258 0x710A, 1259 0x710B, 1260 0x710C, 1261 0x710E, 1262 0x710F, 1263 0x7140, 1264 0x7141, 1265 0x7142, 1266 0x7143, 1267 0x7144, 1268 0x7145, 1269 0x7146, 1270 0x7147, 1271 0x7149, 1272 0x714A, 1273 0x714B, 1274 0x714C, 1275 0x714D, 1276 0x714E, 1277 0x714F, 1278 0x7151, 1279 0x7152, 1280 0x7153, 1281 0x715E, 1282 0x715F, 1283 0x7180, 1284 0x7181, 1285 0x7183, 1286 0x7186, 1287 0x7187, 1288 0x7188, 1289 0x718A, 1290 0x718B, 1291 0x718C, 1292 0x718D, 1293 0x718F, 1294 0x7193, 1295 0x7196, 1296 0x719B, 1297 0x719F, 1298 0x71C0, 1299 0x71C1, 1300 0x71C2, 1301 0x71C3, 1302 0x71C4, 1303 0x71C5, 1304 0x71C6, 1305 0x71C7, 1306 0x71CD, 1307 0x71CE, 1308 0x71D2, 1309 0x71D4, 1310 0x71D5, 1311 0x71D6, 1312 0x71DA, 1313 0x71DE, 1314 0x7200, 1315 0x7210, 1316 0x7211, 1317 0x7240, 1318 0x7243, 1319 0x7244, 1320 0x7245, 1321 0x7246, 1322 0x7247, 1323 0x7248, 1324 0x7249, 1325 0x724A, 1326 0x724B, 1327 0x724C, 1328 0x724D, 1329 0x724E, 1330 0x724F, 1331 0x7280, 1332 0x7281, 1333 0x7283, 1334 0x7284, 1335 0x7287, 1336 0x7288, 1337 0x7289, 1338 0x728B, 1339 0x728C, 1340 0x7290, 1341 0x7291, 1342 0x7293, 1343 0x7297, 1344 0x7834, 1345 0x7835, 1346 0x791e, 1347 0x791f, 1348 0x793f, 1349 0x7941, 1350 0x7942, 1351 0x796c, 1352 0x796d, 1353 0x796e, 1354 0x796f, 1355 0x9400, 1356 0x9401, 1357 0x9402, 1358 0x9403, 1359 0x9405, 1360 0x940A, 1361 0x940B, 1362 0x940F, 1363 0x94A0, 1364 0x94A1, 1365 0x94A3, 1366 0x94B1, 1367 0x94B3, 1368 0x94B4, 1369 0x94B5, 1370 0x94B9, 1371 0x9440, 1372 0x9441, 1373 0x9442, 1374 0x9443, 1375 0x9444, 1376 0x9446, 1377 0x944A, 1378 0x944B, 1379 0x944C, 1380 0x944E, 1381 0x9450, 1382 0x9452, 1383 0x9456, 1384 0x945A, 1385 0x945B, 1386 0x945E, 1387 0x9460, 1388 0x9462, 1389 0x946A, 1390 0x946B, 1391 0x947A, 1392 0x947B, 1393 0x9480, 1394 0x9487, 1395 0x9488, 1396 0x9489, 1397 0x948A, 1398 0x948F, 1399 0x9490, 1400 0x9491, 1401 0x9495, 1402 0x9498, 1403 0x949C, 1404 0x949E, 1405 0x949F, 1406 0x94C0, 1407 0x94C1, 1408 0x94C3, 1409 0x94C4, 1410 0x94C5, 1411 0x94C6, 1412 0x94C7, 1413 0x94C8, 1414 0x94C9, 1415 0x94CB, 1416 0x94CC, 1417 0x94CD, 1418 0x9500, 1419 0x9501, 1420 0x9504, 1421 0x9505, 1422 0x9506, 1423 0x9507, 1424 0x9508, 1425 0x9509, 1426 0x950F, 1427 0x9511, 1428 0x9515, 1429 0x9517, 1430 0x9519, 1431 0x9540, 1432 0x9541, 1433 0x9542, 1434 0x954E, 1435 0x954F, 1436 0x9552, 1437 0x9553, 1438 0x9555, 1439 0x9557, 1440 0x955f, 1441 0x9580, 1442 0x9581, 1443 0x9583, 1444 0x9586, 1445 0x9587, 1446 0x9588, 1447 0x9589, 1448 0x958A, 1449 0x958B, 1450 0x958C, 1451 0x958D, 1452 0x958E, 1453 0x958F, 1454 0x9590, 1455 0x9591, 1456 0x9593, 1457 0x9595, 1458 0x9596, 1459 0x9597, 1460 0x9598, 1461 0x9599, 1462 0x959B, 1463 0x95C0, 1464 0x95C2, 1465 0x95C4, 1466 0x95C5, 1467 0x95C6, 1468 0x95C7, 1469 0x95C9, 1470 0x95CC, 1471 0x95CD, 1472 0x95CE, 1473 0x95CF, 1474 0x9610, 1475 0x9611, 1476 0x9612, 1477 0x9613, 1478 0x9614, 1479 0x9615, 1480 0x9616, 1481 0x9640, 1482 0x9641, 1483 0x9642, 1484 0x9643, 1485 0x9644, 1486 0x9645, 1487 0x9647, 1488 0x9648, 1489 0x9649, 1490 0x964a, 1491 0x964b, 1492 0x964c, 1493 0x964e, 1494 0x964f, 1495 0x9710, 1496 0x9711, 1497 0x9712, 1498 0x9713, 1499 0x9714, 1500 0x9715, 1501 0x9802, 1502 0x9803, 1503 0x9804, 1504 0x9805, 1505 0x9806, 1506 0x9807, 1507 0x9808, 1508 0x9809, 1509 0x980A, 1510 0x9900, 1511 0x9901, 1512 0x9903, 1513 0x9904, 1514 0x9905, 1515 0x9906, 1516 0x9907, 1517 0x9908, 1518 0x9909, 1519 0x990A, 1520 0x990B, 1521 0x990C, 1522 0x990D, 1523 0x990E, 1524 0x990F, 1525 0x9910, 1526 0x9913, 1527 0x9917, 1528 0x9918, 1529 0x9919, 1530 0x9990, 1531 0x9991, 1532 0x9992, 1533 0x9993, 1534 0x9994, 1535 0x9995, 1536 0x9996, 1537 0x9997, 1538 0x9998, 1539 0x9999, 1540 0x999A, 1541 0x999B, 1542 0x999C, 1543 0x999D, 1544 0x99A0, 1545 0x99A2, 1546 0x99A4, 1547 /* radeon secondary ids */ 1548 0x3171, 1549 0x3e70, 1550 0x4164, 1551 0x4165, 1552 0x4166, 1553 0x4168, 1554 0x4170, 1555 0x4171, 1556 0x4172, 1557 0x4173, 1558 0x496e, 1559 0x4a69, 1560 0x4a6a, 1561 0x4a6b, 1562 0x4a70, 1563 0x4a74, 1564 0x4b69, 1565 0x4b6b, 1566 0x4b6c, 1567 0x4c6e, 1568 0x4e64, 1569 0x4e65, 1570 0x4e66, 1571 0x4e67, 1572 0x4e68, 1573 0x4e69, 1574 0x4e6a, 1575 0x4e71, 1576 0x4f73, 1577 0x5569, 1578 0x556b, 1579 0x556d, 1580 0x556f, 1581 0x5571, 1582 0x5854, 1583 0x5874, 1584 0x5940, 1585 0x5941, 1586 0x5b72, 1587 0x5b73, 1588 0x5b74, 1589 0x5b75, 1590 0x5d44, 1591 0x5d45, 1592 0x5d6d, 1593 0x5d6f, 1594 0x5d72, 1595 0x5d77, 1596 0x5e6b, 1597 0x5e6d, 1598 0x7120, 1599 0x7124, 1600 0x7129, 1601 0x712e, 1602 0x712f, 1603 0x7162, 1604 0x7163, 1605 0x7166, 1606 0x7167, 1607 0x7172, 1608 0x7173, 1609 0x71a0, 1610 0x71a1, 1611 0x71a3, 1612 0x71a7, 1613 0x71bb, 1614 0x71e0, 1615 0x71e1, 1616 0x71e2, 1617 0x71e6, 1618 0x71e7, 1619 0x71f2, 1620 0x7269, 1621 0x726b, 1622 0x726e, 1623 0x72a0, 1624 0x72a8, 1625 0x72b1, 1626 0x72b3, 1627 0x793f, 1628 }; 1629 1630 static const struct pci_device_id pciidlist[] = { 1631 #ifdef CONFIG_DRM_AMDGPU_SI 1632 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1633 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1634 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1635 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1636 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1637 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1638 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1639 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1640 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1641 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1642 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1643 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1644 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1645 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1646 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1647 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1648 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1649 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1650 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1651 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1652 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1653 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1654 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1655 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1656 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1657 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1658 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1659 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1660 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1661 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1662 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1663 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1664 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1665 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1666 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1667 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1668 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1669 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1670 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1671 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1672 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1673 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1674 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1675 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1676 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1677 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1678 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1679 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1680 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1681 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1682 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1683 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1684 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1685 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1686 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1687 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1688 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1689 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1690 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1691 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1692 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1693 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1694 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1695 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1696 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1697 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1698 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1699 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1700 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1701 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1702 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1703 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1704 #endif 1705 #ifdef CONFIG_DRM_AMDGPU_CIK 1706 /* Kaveri */ 1707 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1708 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1709 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1710 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1711 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1712 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1713 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1714 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1715 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1716 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1717 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1718 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1719 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1720 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1721 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1722 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1723 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1724 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1725 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1726 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1727 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1728 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1729 /* Bonaire */ 1730 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1731 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1732 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1733 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1734 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1735 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1736 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1737 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1738 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1739 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1740 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1741 /* Hawaii */ 1742 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1743 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1744 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1745 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1746 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1747 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1748 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1749 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1750 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1751 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1752 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1753 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1754 /* Kabini */ 1755 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1756 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1757 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1758 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1759 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1760 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1761 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1762 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1763 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1764 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1765 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1766 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1767 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1768 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1769 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1770 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1771 /* mullins */ 1772 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1773 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1774 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1775 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1776 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1777 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1778 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1779 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1780 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1781 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1782 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1783 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1784 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1785 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1786 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1787 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1788 #endif 1789 /* topaz */ 1790 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1791 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1792 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1793 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1794 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1795 /* tonga */ 1796 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1797 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1798 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1799 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1800 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1801 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1802 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1803 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1804 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1805 /* fiji */ 1806 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1807 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1808 /* carrizo */ 1809 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1810 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1811 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1812 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1813 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1814 /* stoney */ 1815 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1816 /* Polaris11 */ 1817 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1818 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1819 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1820 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1821 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1822 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1823 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1824 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1825 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1826 /* Polaris10 */ 1827 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1828 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1829 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1830 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1831 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1832 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1833 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1834 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1835 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1836 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1837 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1838 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1839 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1840 /* Polaris12 */ 1841 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1842 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1843 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1844 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1845 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1846 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1847 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1848 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1849 /* VEGAM */ 1850 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1851 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1852 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1853 /* Vega 10 */ 1854 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1855 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1856 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1857 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1858 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1859 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1860 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1861 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1862 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1863 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1864 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1865 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1866 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1867 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1868 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1869 /* Vega 12 */ 1870 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1871 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1872 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1873 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1874 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1875 /* Vega 20 */ 1876 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1877 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1878 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1879 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1880 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1881 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1882 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1883 /* Raven */ 1884 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1885 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1886 /* Arcturus */ 1887 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1888 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1889 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1890 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1891 /* Navi10 */ 1892 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1893 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1894 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1895 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1896 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1897 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1898 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1899 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1900 /* Navi14 */ 1901 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1902 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1903 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1904 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1905 1906 /* Renoir */ 1907 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1908 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1909 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1910 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1911 1912 /* Navi12 */ 1913 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1914 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1915 1916 /* Sienna_Cichlid */ 1917 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1918 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1919 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1920 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1921 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1922 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1923 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1924 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1925 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1926 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1927 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1928 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1929 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1930 1931 /* Yellow Carp */ 1932 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1933 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1934 1935 /* Navy_Flounder */ 1936 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1937 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1938 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1939 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1940 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1941 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1942 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1943 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1944 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1945 1946 /* DIMGREY_CAVEFISH */ 1947 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1948 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1949 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1950 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1951 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1952 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1953 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1954 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1955 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1956 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1957 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1958 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1959 1960 /* Aldebaran */ 1961 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1962 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1963 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1964 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1965 1966 /* CYAN_SKILLFISH */ 1967 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 1968 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 1969 1970 /* BEIGE_GOBY */ 1971 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1972 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1973 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1974 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1975 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1976 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1977 1978 { PCI_DEVICE(0x1002, PCI_ANY_ID), 1979 .class = PCI_CLASS_DISPLAY_VGA << 8, 1980 .class_mask = 0xffffff, 1981 .driver_data = CHIP_IP_DISCOVERY }, 1982 1983 { PCI_DEVICE(0x1002, PCI_ANY_ID), 1984 .class = PCI_CLASS_DISPLAY_OTHER << 8, 1985 .class_mask = 0xffffff, 1986 .driver_data = CHIP_IP_DISCOVERY }, 1987 1988 {0, 0, 0} 1989 }; 1990 1991 MODULE_DEVICE_TABLE(pci, pciidlist); 1992 1993 static const struct drm_driver amdgpu_kms_driver; 1994 1995 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 1996 { 1997 struct pci_dev *p = NULL; 1998 int i; 1999 2000 /* 0 - GPU 2001 * 1 - audio 2002 * 2 - USB 2003 * 3 - UCSI 2004 */ 2005 for (i = 1; i < 4; i++) { 2006 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 2007 adev->pdev->bus->number, i); 2008 if (p) { 2009 pm_runtime_get_sync(&p->dev); 2010 pm_runtime_mark_last_busy(&p->dev); 2011 pm_runtime_put_autosuspend(&p->dev); 2012 pci_dev_put(p); 2013 } 2014 } 2015 } 2016 2017 static int amdgpu_pci_probe(struct pci_dev *pdev, 2018 const struct pci_device_id *ent) 2019 { 2020 struct drm_device *ddev; 2021 struct amdgpu_device *adev; 2022 unsigned long flags = ent->driver_data; 2023 int ret, retry = 0, i; 2024 bool supports_atomic = false; 2025 2026 /* skip devices which are owned by radeon */ 2027 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2028 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2029 return -ENODEV; 2030 } 2031 2032 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) 2033 amdgpu_aspm = 0; 2034 2035 if (amdgpu_virtual_display || 2036 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 2037 supports_atomic = true; 2038 2039 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2040 DRM_INFO("This hardware requires experimental hardware support.\n" 2041 "See modparam exp_hw_support\n"); 2042 return -ENODEV; 2043 } 2044 /* differentiate between P10 and P11 asics with the same DID */ 2045 if (pdev->device == 0x67FF && 2046 (pdev->revision == 0xE3 || 2047 pdev->revision == 0xE7 || 2048 pdev->revision == 0xF3 || 2049 pdev->revision == 0xF7)) { 2050 flags &= ~AMD_ASIC_MASK; 2051 flags |= CHIP_POLARIS10; 2052 } 2053 2054 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2055 * however, SME requires an indirect IOMMU mapping because the encryption 2056 * bit is beyond the DMA mask of the chip. 2057 */ 2058 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2059 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2060 dev_info(&pdev->dev, 2061 "SME is not compatible with RAVEN\n"); 2062 return -ENOTSUPP; 2063 } 2064 2065 #ifdef CONFIG_DRM_AMDGPU_SI 2066 if (!amdgpu_si_support) { 2067 switch (flags & AMD_ASIC_MASK) { 2068 case CHIP_TAHITI: 2069 case CHIP_PITCAIRN: 2070 case CHIP_VERDE: 2071 case CHIP_OLAND: 2072 case CHIP_HAINAN: 2073 dev_info(&pdev->dev, 2074 "SI support provided by radeon.\n"); 2075 dev_info(&pdev->dev, 2076 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 2077 ); 2078 return -ENODEV; 2079 } 2080 } 2081 #endif 2082 #ifdef CONFIG_DRM_AMDGPU_CIK 2083 if (!amdgpu_cik_support) { 2084 switch (flags & AMD_ASIC_MASK) { 2085 case CHIP_KAVERI: 2086 case CHIP_BONAIRE: 2087 case CHIP_HAWAII: 2088 case CHIP_KABINI: 2089 case CHIP_MULLINS: 2090 dev_info(&pdev->dev, 2091 "CIK support provided by radeon.\n"); 2092 dev_info(&pdev->dev, 2093 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 2094 ); 2095 return -ENODEV; 2096 } 2097 } 2098 #endif 2099 2100 /* Get rid of things like offb */ 2101 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &amdgpu_kms_driver); 2102 if (ret) 2103 return ret; 2104 2105 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2106 if (IS_ERR(adev)) 2107 return PTR_ERR(adev); 2108 2109 adev->dev = &pdev->dev; 2110 adev->pdev = pdev; 2111 ddev = adev_to_drm(adev); 2112 2113 if (!supports_atomic) 2114 ddev->driver_features &= ~DRIVER_ATOMIC; 2115 2116 ret = pci_enable_device(pdev); 2117 if (ret) 2118 return ret; 2119 2120 pci_set_drvdata(pdev, ddev); 2121 2122 ret = amdgpu_driver_load_kms(adev, flags); 2123 if (ret) 2124 goto err_pci; 2125 2126 retry_init: 2127 ret = drm_dev_register(ddev, flags); 2128 if (ret == -EAGAIN && ++retry <= 3) { 2129 DRM_INFO("retry init %d\n", retry); 2130 /* Don't request EX mode too frequently which is attacking */ 2131 msleep(5000); 2132 goto retry_init; 2133 } else if (ret) { 2134 goto err_pci; 2135 } 2136 2137 /* 2138 * 1. don't init fbdev on hw without DCE 2139 * 2. don't init fbdev if there are no connectors 2140 */ 2141 if (adev->mode_info.mode_config_initialized && 2142 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2143 /* select 8 bpp console on low vram cards */ 2144 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2145 drm_fbdev_generic_setup(adev_to_drm(adev), 8); 2146 else 2147 drm_fbdev_generic_setup(adev_to_drm(adev), 32); 2148 } 2149 2150 ret = amdgpu_debugfs_init(adev); 2151 if (ret) 2152 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2153 2154 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2155 /* only need to skip on ATPX */ 2156 if (amdgpu_device_supports_px(ddev)) 2157 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2158 /* we want direct complete for BOCO */ 2159 if (amdgpu_device_supports_boco(ddev)) 2160 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2161 DPM_FLAG_SMART_SUSPEND | 2162 DPM_FLAG_MAY_SKIP_RESUME); 2163 pm_runtime_use_autosuspend(ddev->dev); 2164 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2165 2166 pm_runtime_allow(ddev->dev); 2167 2168 pm_runtime_mark_last_busy(ddev->dev); 2169 pm_runtime_put_autosuspend(ddev->dev); 2170 2171 /* 2172 * For runpm implemented via BACO, PMFW will handle the 2173 * timing for BACO in and out: 2174 * - put ASIC into BACO state only when both video and 2175 * audio functions are in D3 state. 2176 * - pull ASIC out of BACO state when either video or 2177 * audio function is in D0 state. 2178 * Also, at startup, PMFW assumes both functions are in 2179 * D0 state. 2180 * 2181 * So if snd driver was loaded prior to amdgpu driver 2182 * and audio function was put into D3 state, there will 2183 * be no PMFW-aware D-state transition(D0->D3) on runpm 2184 * suspend. Thus the BACO will be not correctly kicked in. 2185 * 2186 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2187 * into D0 state. Then there will be a PMFW-aware D-state 2188 * transition(D0->D3) on runpm suspend. 2189 */ 2190 if (amdgpu_device_supports_baco(ddev) && 2191 !(adev->flags & AMD_IS_APU) && 2192 (adev->asic_type >= CHIP_NAVI10)) 2193 amdgpu_get_secondary_funcs(adev); 2194 } 2195 2196 return 0; 2197 2198 err_pci: 2199 pci_disable_device(pdev); 2200 return ret; 2201 } 2202 2203 static void 2204 amdgpu_pci_remove(struct pci_dev *pdev) 2205 { 2206 struct drm_device *dev = pci_get_drvdata(pdev); 2207 struct amdgpu_device *adev = drm_to_adev(dev); 2208 2209 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2210 pm_runtime_get_sync(dev->dev); 2211 pm_runtime_forbid(dev->dev); 2212 } 2213 2214 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2) && 2215 !amdgpu_sriov_vf(adev)) { 2216 bool need_to_reset_gpu = false; 2217 2218 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2219 struct amdgpu_hive_info *hive; 2220 2221 hive = amdgpu_get_xgmi_hive(adev); 2222 if (hive->device_remove_count == 0) 2223 need_to_reset_gpu = true; 2224 hive->device_remove_count++; 2225 amdgpu_put_xgmi_hive(hive); 2226 } else { 2227 need_to_reset_gpu = true; 2228 } 2229 2230 /* Workaround for ASICs need to reset SMU. 2231 * Called only when the first device is removed. 2232 */ 2233 if (need_to_reset_gpu) { 2234 struct amdgpu_reset_context reset_context; 2235 2236 adev->shutdown = true; 2237 memset(&reset_context, 0, sizeof(reset_context)); 2238 reset_context.method = AMD_RESET_METHOD_NONE; 2239 reset_context.reset_req_dev = adev; 2240 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2241 set_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context.flags); 2242 amdgpu_device_gpu_recover(adev, NULL, &reset_context); 2243 } 2244 } 2245 2246 amdgpu_driver_unload_kms(dev); 2247 2248 drm_dev_unplug(dev); 2249 2250 /* 2251 * Flush any in flight DMA operations from device. 2252 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2253 * StatusTransactions Pending bit. 2254 */ 2255 pci_disable_device(pdev); 2256 pci_wait_for_pending_transaction(pdev); 2257 } 2258 2259 static void 2260 amdgpu_pci_shutdown(struct pci_dev *pdev) 2261 { 2262 struct drm_device *dev = pci_get_drvdata(pdev); 2263 struct amdgpu_device *adev = drm_to_adev(dev); 2264 2265 if (amdgpu_ras_intr_triggered()) 2266 return; 2267 2268 /* if we are running in a VM, make sure the device 2269 * torn down properly on reboot/shutdown. 2270 * unfortunately we can't detect certain 2271 * hypervisors so just do this all the time. 2272 */ 2273 if (!amdgpu_passthrough(adev)) 2274 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2275 amdgpu_device_ip_suspend(adev); 2276 adev->mp1_state = PP_MP1_STATE_NONE; 2277 } 2278 2279 /** 2280 * amdgpu_drv_delayed_reset_work_handler - work handler for reset 2281 * 2282 * @work: work_struct. 2283 */ 2284 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) 2285 { 2286 struct list_head device_list; 2287 struct amdgpu_device *adev; 2288 int i, r; 2289 struct amdgpu_reset_context reset_context; 2290 2291 memset(&reset_context, 0, sizeof(reset_context)); 2292 2293 mutex_lock(&mgpu_info.mutex); 2294 if (mgpu_info.pending_reset == true) { 2295 mutex_unlock(&mgpu_info.mutex); 2296 return; 2297 } 2298 mgpu_info.pending_reset = true; 2299 mutex_unlock(&mgpu_info.mutex); 2300 2301 /* Use a common context, just need to make sure full reset is done */ 2302 reset_context.method = AMD_RESET_METHOD_NONE; 2303 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2304 2305 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2306 adev = mgpu_info.gpu_ins[i].adev; 2307 reset_context.reset_req_dev = adev; 2308 r = amdgpu_device_pre_asic_reset(adev, &reset_context); 2309 if (r) { 2310 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", 2311 r, adev_to_drm(adev)->unique); 2312 } 2313 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) 2314 r = -EALREADY; 2315 } 2316 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2317 adev = mgpu_info.gpu_ins[i].adev; 2318 flush_work(&adev->xgmi_reset_work); 2319 adev->gmc.xgmi.pending_reset = false; 2320 } 2321 2322 /* reset function will rebuild the xgmi hive info , clear it now */ 2323 for (i = 0; i < mgpu_info.num_dgpu; i++) 2324 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); 2325 2326 INIT_LIST_HEAD(&device_list); 2327 2328 for (i = 0; i < mgpu_info.num_dgpu; i++) 2329 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); 2330 2331 /* unregister the GPU first, reset function will add them back */ 2332 list_for_each_entry(adev, &device_list, reset_list) 2333 amdgpu_unregister_gpu_instance(adev); 2334 2335 /* Use a common context, just need to make sure full reset is done */ 2336 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); 2337 r = amdgpu_do_asic_reset(&device_list, &reset_context); 2338 2339 if (r) { 2340 DRM_ERROR("reinit gpus failure"); 2341 return; 2342 } 2343 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2344 adev = mgpu_info.gpu_ins[i].adev; 2345 if (!adev->kfd.init_complete) 2346 amdgpu_amdkfd_device_init(adev); 2347 amdgpu_ttm_set_buffer_funcs_status(adev, true); 2348 } 2349 return; 2350 } 2351 2352 static int amdgpu_pmops_prepare(struct device *dev) 2353 { 2354 struct drm_device *drm_dev = dev_get_drvdata(dev); 2355 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2356 2357 /* Return a positive number here so 2358 * DPM_FLAG_SMART_SUSPEND works properly 2359 */ 2360 if (amdgpu_device_supports_boco(drm_dev)) 2361 return pm_runtime_suspended(dev); 2362 2363 /* if we will not support s3 or s2i for the device 2364 * then skip suspend 2365 */ 2366 if (!amdgpu_acpi_is_s0ix_active(adev) && 2367 !amdgpu_acpi_is_s3_active(adev)) 2368 return 1; 2369 2370 return 0; 2371 } 2372 2373 static void amdgpu_pmops_complete(struct device *dev) 2374 { 2375 /* nothing to do */ 2376 } 2377 2378 static int amdgpu_pmops_suspend(struct device *dev) 2379 { 2380 struct drm_device *drm_dev = dev_get_drvdata(dev); 2381 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2382 2383 if (amdgpu_acpi_is_s0ix_active(adev)) 2384 adev->in_s0ix = true; 2385 else 2386 adev->in_s3 = true; 2387 return amdgpu_device_suspend(drm_dev, true); 2388 } 2389 2390 static int amdgpu_pmops_suspend_noirq(struct device *dev) 2391 { 2392 struct drm_device *drm_dev = dev_get_drvdata(dev); 2393 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2394 2395 if (amdgpu_acpi_should_gpu_reset(adev)) 2396 return amdgpu_asic_reset(adev); 2397 2398 return 0; 2399 } 2400 2401 static int amdgpu_pmops_resume(struct device *dev) 2402 { 2403 struct drm_device *drm_dev = dev_get_drvdata(dev); 2404 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2405 int r; 2406 2407 /* Avoids registers access if device is physically gone */ 2408 if (!pci_device_is_present(adev->pdev)) 2409 adev->no_hw_access = true; 2410 2411 r = amdgpu_device_resume(drm_dev, true); 2412 if (amdgpu_acpi_is_s0ix_active(adev)) 2413 adev->in_s0ix = false; 2414 else 2415 adev->in_s3 = false; 2416 return r; 2417 } 2418 2419 static int amdgpu_pmops_freeze(struct device *dev) 2420 { 2421 struct drm_device *drm_dev = dev_get_drvdata(dev); 2422 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2423 int r; 2424 2425 adev->in_s4 = true; 2426 r = amdgpu_device_suspend(drm_dev, true); 2427 adev->in_s4 = false; 2428 if (r) 2429 return r; 2430 return amdgpu_asic_reset(adev); 2431 } 2432 2433 static int amdgpu_pmops_thaw(struct device *dev) 2434 { 2435 struct drm_device *drm_dev = dev_get_drvdata(dev); 2436 2437 return amdgpu_device_resume(drm_dev, true); 2438 } 2439 2440 static int amdgpu_pmops_poweroff(struct device *dev) 2441 { 2442 struct drm_device *drm_dev = dev_get_drvdata(dev); 2443 2444 return amdgpu_device_suspend(drm_dev, true); 2445 } 2446 2447 static int amdgpu_pmops_restore(struct device *dev) 2448 { 2449 struct drm_device *drm_dev = dev_get_drvdata(dev); 2450 2451 return amdgpu_device_resume(drm_dev, true); 2452 } 2453 2454 static int amdgpu_runtime_idle_check_display(struct device *dev) 2455 { 2456 struct pci_dev *pdev = to_pci_dev(dev); 2457 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2458 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2459 2460 if (adev->mode_info.num_crtc) { 2461 struct drm_connector *list_connector; 2462 struct drm_connector_list_iter iter; 2463 int ret = 0; 2464 2465 /* XXX: Return busy if any displays are connected to avoid 2466 * possible display wakeups after runtime resume due to 2467 * hotplug events in case any displays were connected while 2468 * the GPU was in suspend. Remove this once that is fixed. 2469 */ 2470 mutex_lock(&drm_dev->mode_config.mutex); 2471 drm_connector_list_iter_begin(drm_dev, &iter); 2472 drm_for_each_connector_iter(list_connector, &iter) { 2473 if (list_connector->status == connector_status_connected) { 2474 ret = -EBUSY; 2475 break; 2476 } 2477 } 2478 drm_connector_list_iter_end(&iter); 2479 mutex_unlock(&drm_dev->mode_config.mutex); 2480 2481 if (ret) 2482 return ret; 2483 2484 if (adev->dc_enabled) { 2485 struct drm_crtc *crtc; 2486 2487 drm_for_each_crtc(crtc, drm_dev) { 2488 drm_modeset_lock(&crtc->mutex, NULL); 2489 if (crtc->state->active) 2490 ret = -EBUSY; 2491 drm_modeset_unlock(&crtc->mutex); 2492 if (ret < 0) 2493 break; 2494 } 2495 } else { 2496 mutex_lock(&drm_dev->mode_config.mutex); 2497 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2498 2499 drm_connector_list_iter_begin(drm_dev, &iter); 2500 drm_for_each_connector_iter(list_connector, &iter) { 2501 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2502 ret = -EBUSY; 2503 break; 2504 } 2505 } 2506 2507 drm_connector_list_iter_end(&iter); 2508 2509 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2510 mutex_unlock(&drm_dev->mode_config.mutex); 2511 } 2512 if (ret) 2513 return ret; 2514 } 2515 2516 return 0; 2517 } 2518 2519 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2520 { 2521 struct pci_dev *pdev = to_pci_dev(dev); 2522 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2523 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2524 int ret, i; 2525 2526 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2527 pm_runtime_forbid(dev); 2528 return -EBUSY; 2529 } 2530 2531 ret = amdgpu_runtime_idle_check_display(dev); 2532 if (ret) 2533 return ret; 2534 2535 /* wait for all rings to drain before suspending */ 2536 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2537 struct amdgpu_ring *ring = adev->rings[i]; 2538 if (ring && ring->sched.ready) { 2539 ret = amdgpu_fence_wait_empty(ring); 2540 if (ret) 2541 return -EBUSY; 2542 } 2543 } 2544 2545 adev->in_runpm = true; 2546 if (amdgpu_device_supports_px(drm_dev)) 2547 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2548 2549 /* 2550 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2551 * proper cleanups and put itself into a state ready for PNP. That 2552 * can address some random resuming failure observed on BOCO capable 2553 * platforms. 2554 * TODO: this may be also needed for PX capable platform. 2555 */ 2556 if (amdgpu_device_supports_boco(drm_dev)) 2557 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2558 2559 ret = amdgpu_device_suspend(drm_dev, false); 2560 if (ret) { 2561 adev->in_runpm = false; 2562 if (amdgpu_device_supports_boco(drm_dev)) 2563 adev->mp1_state = PP_MP1_STATE_NONE; 2564 return ret; 2565 } 2566 2567 if (amdgpu_device_supports_boco(drm_dev)) 2568 adev->mp1_state = PP_MP1_STATE_NONE; 2569 2570 if (amdgpu_device_supports_px(drm_dev)) { 2571 /* Only need to handle PCI state in the driver for ATPX 2572 * PCI core handles it for _PR3. 2573 */ 2574 amdgpu_device_cache_pci_state(pdev); 2575 pci_disable_device(pdev); 2576 pci_ignore_hotplug(pdev); 2577 pci_set_power_state(pdev, PCI_D3cold); 2578 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2579 } else if (amdgpu_device_supports_boco(drm_dev)) { 2580 /* nothing to do */ 2581 } else if (amdgpu_device_supports_baco(drm_dev)) { 2582 amdgpu_device_baco_enter(drm_dev); 2583 } 2584 2585 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n"); 2586 2587 return 0; 2588 } 2589 2590 static int amdgpu_pmops_runtime_resume(struct device *dev) 2591 { 2592 struct pci_dev *pdev = to_pci_dev(dev); 2593 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2594 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2595 int ret; 2596 2597 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) 2598 return -EINVAL; 2599 2600 /* Avoids registers access if device is physically gone */ 2601 if (!pci_device_is_present(adev->pdev)) 2602 adev->no_hw_access = true; 2603 2604 if (amdgpu_device_supports_px(drm_dev)) { 2605 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2606 2607 /* Only need to handle PCI state in the driver for ATPX 2608 * PCI core handles it for _PR3. 2609 */ 2610 pci_set_power_state(pdev, PCI_D0); 2611 amdgpu_device_load_pci_state(pdev); 2612 ret = pci_enable_device(pdev); 2613 if (ret) 2614 return ret; 2615 pci_set_master(pdev); 2616 } else if (amdgpu_device_supports_boco(drm_dev)) { 2617 /* Only need to handle PCI state in the driver for ATPX 2618 * PCI core handles it for _PR3. 2619 */ 2620 pci_set_master(pdev); 2621 } else if (amdgpu_device_supports_baco(drm_dev)) { 2622 amdgpu_device_baco_exit(drm_dev); 2623 } 2624 ret = amdgpu_device_resume(drm_dev, false); 2625 if (ret) { 2626 if (amdgpu_device_supports_px(drm_dev)) 2627 pci_disable_device(pdev); 2628 return ret; 2629 } 2630 2631 if (amdgpu_device_supports_px(drm_dev)) 2632 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2633 adev->in_runpm = false; 2634 return 0; 2635 } 2636 2637 static int amdgpu_pmops_runtime_idle(struct device *dev) 2638 { 2639 struct drm_device *drm_dev = dev_get_drvdata(dev); 2640 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2641 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 2642 int ret = 1; 2643 2644 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2645 pm_runtime_forbid(dev); 2646 return -EBUSY; 2647 } 2648 2649 ret = amdgpu_runtime_idle_check_display(dev); 2650 2651 pm_runtime_mark_last_busy(dev); 2652 pm_runtime_autosuspend(dev); 2653 return ret; 2654 } 2655 2656 long amdgpu_drm_ioctl(struct file *filp, 2657 unsigned int cmd, unsigned long arg) 2658 { 2659 struct drm_file *file_priv = filp->private_data; 2660 struct drm_device *dev; 2661 long ret; 2662 dev = file_priv->minor->dev; 2663 ret = pm_runtime_get_sync(dev->dev); 2664 if (ret < 0) 2665 goto out; 2666 2667 ret = drm_ioctl(filp, cmd, arg); 2668 2669 pm_runtime_mark_last_busy(dev->dev); 2670 out: 2671 pm_runtime_put_autosuspend(dev->dev); 2672 return ret; 2673 } 2674 2675 static const struct dev_pm_ops amdgpu_pm_ops = { 2676 .prepare = amdgpu_pmops_prepare, 2677 .complete = amdgpu_pmops_complete, 2678 .suspend = amdgpu_pmops_suspend, 2679 .suspend_noirq = amdgpu_pmops_suspend_noirq, 2680 .resume = amdgpu_pmops_resume, 2681 .freeze = amdgpu_pmops_freeze, 2682 .thaw = amdgpu_pmops_thaw, 2683 .poweroff = amdgpu_pmops_poweroff, 2684 .restore = amdgpu_pmops_restore, 2685 .runtime_suspend = amdgpu_pmops_runtime_suspend, 2686 .runtime_resume = amdgpu_pmops_runtime_resume, 2687 .runtime_idle = amdgpu_pmops_runtime_idle, 2688 }; 2689 2690 static int amdgpu_flush(struct file *f, fl_owner_t id) 2691 { 2692 struct drm_file *file_priv = f->private_data; 2693 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2694 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2695 2696 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 2697 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 2698 2699 return timeout >= 0 ? 0 : timeout; 2700 } 2701 2702 static const struct file_operations amdgpu_driver_kms_fops = { 2703 .owner = THIS_MODULE, 2704 .open = drm_open, 2705 .flush = amdgpu_flush, 2706 .release = drm_release, 2707 .unlocked_ioctl = amdgpu_drm_ioctl, 2708 .mmap = drm_gem_mmap, 2709 .poll = drm_poll, 2710 .read = drm_read, 2711 #ifdef CONFIG_COMPAT 2712 .compat_ioctl = amdgpu_kms_compat_ioctl, 2713 #endif 2714 #ifdef CONFIG_PROC_FS 2715 .show_fdinfo = amdgpu_show_fdinfo 2716 #endif 2717 }; 2718 2719 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 2720 { 2721 struct drm_file *file; 2722 2723 if (!filp) 2724 return -EINVAL; 2725 2726 if (filp->f_op != &amdgpu_driver_kms_fops) { 2727 return -EINVAL; 2728 } 2729 2730 file = filp->private_data; 2731 *fpriv = file->driver_priv; 2732 return 0; 2733 } 2734 2735 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 2736 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2737 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2738 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2739 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 2740 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2741 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2742 /* KMS */ 2743 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2744 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2745 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2746 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2747 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2748 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2749 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2750 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2751 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2752 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2753 }; 2754 2755 static const struct drm_driver amdgpu_kms_driver = { 2756 .driver_features = 2757 DRIVER_ATOMIC | 2758 DRIVER_GEM | 2759 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 2760 DRIVER_SYNCOBJ_TIMELINE, 2761 .open = amdgpu_driver_open_kms, 2762 .postclose = amdgpu_driver_postclose_kms, 2763 .lastclose = amdgpu_driver_lastclose_kms, 2764 .ioctls = amdgpu_ioctls_kms, 2765 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2766 .dumb_create = amdgpu_mode_dumb_create, 2767 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2768 .fops = &amdgpu_driver_kms_fops, 2769 .release = &amdgpu_driver_release_kms, 2770 2771 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 2772 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 2773 .gem_prime_import = amdgpu_gem_prime_import, 2774 .gem_prime_mmap = drm_gem_prime_mmap, 2775 2776 .name = DRIVER_NAME, 2777 .desc = DRIVER_DESC, 2778 .date = DRIVER_DATE, 2779 .major = KMS_DRIVER_MAJOR, 2780 .minor = KMS_DRIVER_MINOR, 2781 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2782 }; 2783 2784 static struct pci_error_handlers amdgpu_pci_err_handler = { 2785 .error_detected = amdgpu_pci_error_detected, 2786 .mmio_enabled = amdgpu_pci_mmio_enabled, 2787 .slot_reset = amdgpu_pci_slot_reset, 2788 .resume = amdgpu_pci_resume, 2789 }; 2790 2791 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 2792 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 2793 extern const struct attribute_group amdgpu_vbios_version_attr_group; 2794 2795 static const struct attribute_group *amdgpu_sysfs_groups[] = { 2796 &amdgpu_vram_mgr_attr_group, 2797 &amdgpu_gtt_mgr_attr_group, 2798 &amdgpu_vbios_version_attr_group, 2799 NULL, 2800 }; 2801 2802 2803 static struct pci_driver amdgpu_kms_pci_driver = { 2804 .name = DRIVER_NAME, 2805 .id_table = pciidlist, 2806 .probe = amdgpu_pci_probe, 2807 .remove = amdgpu_pci_remove, 2808 .shutdown = amdgpu_pci_shutdown, 2809 .driver.pm = &amdgpu_pm_ops, 2810 .err_handler = &amdgpu_pci_err_handler, 2811 .dev_groups = amdgpu_sysfs_groups, 2812 }; 2813 2814 static int __init amdgpu_init(void) 2815 { 2816 int r; 2817 2818 if (drm_firmware_drivers_only()) 2819 return -EINVAL; 2820 2821 r = amdgpu_sync_init(); 2822 if (r) 2823 goto error_sync; 2824 2825 r = amdgpu_fence_slab_init(); 2826 if (r) 2827 goto error_fence; 2828 2829 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 2830 amdgpu_register_atpx_handler(); 2831 amdgpu_acpi_detect(); 2832 2833 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 2834 amdgpu_amdkfd_init(); 2835 2836 /* let modprobe override vga console setting */ 2837 return pci_register_driver(&amdgpu_kms_pci_driver); 2838 2839 error_fence: 2840 amdgpu_sync_fini(); 2841 2842 error_sync: 2843 return r; 2844 } 2845 2846 static void __exit amdgpu_exit(void) 2847 { 2848 amdgpu_amdkfd_fini(); 2849 pci_unregister_driver(&amdgpu_kms_pci_driver); 2850 amdgpu_unregister_atpx_handler(); 2851 amdgpu_sync_fini(); 2852 amdgpu_fence_slab_fini(); 2853 mmu_notifier_synchronize(); 2854 } 2855 2856 module_init(amdgpu_init); 2857 module_exit(amdgpu_exit); 2858 2859 MODULE_AUTHOR(DRIVER_AUTHOR); 2860 MODULE_DESCRIPTION(DRIVER_DESC); 2861 MODULE_LICENSE("GPL and additional rights"); 2862