1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_drv.h> 27 #include <drm/drm_fbdev_generic.h> 28 #include <drm/drm_gem.h> 29 #include <drm/drm_managed.h> 30 #include <drm/drm_pciids.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/drm_vblank.h> 33 34 #include <linux/cc_platform.h> 35 #include <linux/dynamic_debug.h> 36 #include <linux/module.h> 37 #include <linux/mmu_notifier.h> 38 #include <linux/pm_runtime.h> 39 #include <linux/suspend.h> 40 #include <linux/vga_switcheroo.h> 41 42 #include "amdgpu.h" 43 #include "amdgpu_amdkfd.h" 44 #include "amdgpu_dma_buf.h" 45 #include "amdgpu_drv.h" 46 #include "amdgpu_fdinfo.h" 47 #include "amdgpu_irq.h" 48 #include "amdgpu_psp.h" 49 #include "amdgpu_ras.h" 50 #include "amdgpu_reset.h" 51 #include "amdgpu_sched.h" 52 #include "amdgpu_xgmi.h" 53 #include "../amdxcp/amdgpu_xcp_drv.h" 54 55 /* 56 * KMS wrapper. 57 * - 3.0.0 - initial driver 58 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 59 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 60 * at the end of IBs. 61 * - 3.3.0 - Add VM support for UVD on supported hardware. 62 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 63 * - 3.5.0 - Add support for new UVD_NO_OP register. 64 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 65 * - 3.7.0 - Add support for VCE clock list packet 66 * - 3.8.0 - Add support raster config init in the kernel 67 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 68 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 69 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 70 * - 3.12.0 - Add query for double offchip LDS buffers 71 * - 3.13.0 - Add PRT support 72 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 73 * - 3.15.0 - Export more gpu info for gfx9 74 * - 3.16.0 - Add reserved vmid support 75 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 76 * - 3.18.0 - Export gpu always on cu bitmap 77 * - 3.19.0 - Add support for UVD MJPEG decode 78 * - 3.20.0 - Add support for local BOs 79 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 80 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 81 * - 3.23.0 - Add query for VRAM lost counter 82 * - 3.24.0 - Add high priority compute support for gfx9 83 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 84 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 85 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation. 86 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 87 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 88 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 89 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 90 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 91 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 92 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 93 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 94 * - 3.36.0 - Allow reading more status registers on si/cik 95 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 96 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 97 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 98 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 99 * - 3.41.0 - Add video codec query 100 * - 3.42.0 - Add 16bpc fixed point display support 101 * - 3.43.0 - Add device hot plug/unplug support 102 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 103 * - 3.45.0 - Add context ioctl stable pstate interface 104 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm 105 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags 106 * - 3.48.0 - Add IP discovery version info to HW INFO 107 * - 3.49.0 - Add gang submit into CS IOCTL 108 * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock 109 * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock 110 * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl 111 * 3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields: 112 * tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size, 113 * gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi 114 * 3.53.0 - Support for GFX11 CP GFX shadowing 115 * 3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support 116 * - 3.55.0 - Add AMDGPU_INFO_GPUVM_FAULT query 117 * - 3.56.0 - Update IB start address and size alignment for decode and encode 118 * - 3.57.0 - Compute tunneling on GFX10+ 119 */ 120 #define KMS_DRIVER_MAJOR 3 121 #define KMS_DRIVER_MINOR 57 122 #define KMS_DRIVER_PATCHLEVEL 0 123 124 /* 125 * amdgpu.debug module options. Are all disabled by default 126 */ 127 enum AMDGPU_DEBUG_MASK { 128 AMDGPU_DEBUG_VM = BIT(0), 129 AMDGPU_DEBUG_LARGEBAR = BIT(1), 130 AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY = BIT(2), 131 }; 132 133 unsigned int amdgpu_vram_limit = UINT_MAX; 134 int amdgpu_vis_vram_limit; 135 int amdgpu_gart_size = -1; /* auto */ 136 int amdgpu_gtt_size = -1; /* auto */ 137 int amdgpu_moverate = -1; /* auto */ 138 int amdgpu_audio = -1; 139 int amdgpu_disp_priority; 140 int amdgpu_hw_i2c; 141 int amdgpu_pcie_gen2 = -1; 142 int amdgpu_msi = -1; 143 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 144 int amdgpu_dpm = -1; 145 int amdgpu_fw_load_type = -1; 146 int amdgpu_aspm = -1; 147 int amdgpu_runtime_pm = -1; 148 uint amdgpu_ip_block_mask = 0xffffffff; 149 int amdgpu_bapm = -1; 150 int amdgpu_deep_color; 151 int amdgpu_vm_size = -1; 152 int amdgpu_vm_fragment_size = -1; 153 int amdgpu_vm_block_size = -1; 154 int amdgpu_vm_fault_stop; 155 int amdgpu_vm_update_mode = -1; 156 int amdgpu_exp_hw_support; 157 int amdgpu_dc = -1; 158 int amdgpu_sched_jobs = 32; 159 int amdgpu_sched_hw_submission = 2; 160 uint amdgpu_pcie_gen_cap; 161 uint amdgpu_pcie_lane_cap; 162 u64 amdgpu_cg_mask = 0xffffffffffffffff; 163 uint amdgpu_pg_mask = 0xffffffff; 164 uint amdgpu_sdma_phase_quantum = 32; 165 char *amdgpu_disable_cu; 166 char *amdgpu_virtual_display; 167 bool enforce_isolation; 168 /* 169 * OverDrive(bit 14) disabled by default 170 * GFX DCS(bit 19) disabled by default 171 */ 172 uint amdgpu_pp_feature_mask = 0xfff7bfff; 173 uint amdgpu_force_long_training; 174 int amdgpu_lbpw = -1; 175 int amdgpu_compute_multipipe = -1; 176 int amdgpu_gpu_recovery = -1; /* auto */ 177 int amdgpu_emu_mode; 178 uint amdgpu_smu_memory_pool_size; 179 int amdgpu_smu_pptable_id = -1; 180 /* 181 * FBC (bit 0) disabled by default 182 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 183 * - With this, for multiple monitors in sync(e.g. with the same model), 184 * mclk switching will be allowed. And the mclk will be not foced to the 185 * highest. That helps saving some idle power. 186 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 187 * PSR (bit 3) disabled by default 188 * EDP NO POWER SEQUENCING (bit 4) disabled by default 189 */ 190 uint amdgpu_dc_feature_mask = 2; 191 uint amdgpu_dc_debug_mask; 192 uint amdgpu_dc_visual_confirm; 193 int amdgpu_async_gfx_ring = 1; 194 int amdgpu_mcbp = -1; 195 int amdgpu_discovery = -1; 196 int amdgpu_mes; 197 int amdgpu_mes_kiq; 198 int amdgpu_noretry = -1; 199 int amdgpu_force_asic_type = -1; 200 int amdgpu_tmz = -1; /* auto */ 201 int amdgpu_reset_method = -1; /* auto */ 202 int amdgpu_num_kcq = -1; 203 int amdgpu_smartshift_bias; 204 int amdgpu_use_xgmi_p2p = 1; 205 int amdgpu_vcnfw_log; 206 int amdgpu_sg_display = -1; /* auto */ 207 int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE; 208 int amdgpu_umsch_mm; 209 int amdgpu_seamless = -1; /* auto */ 210 uint amdgpu_debug_mask; 211 int amdgpu_agp = -1; /* auto */ 212 int amdgpu_wbrf = -1; 213 214 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 215 216 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 217 "DRM_UT_CORE", 218 "DRM_UT_DRIVER", 219 "DRM_UT_KMS", 220 "DRM_UT_PRIME", 221 "DRM_UT_ATOMIC", 222 "DRM_UT_VBL", 223 "DRM_UT_STATE", 224 "DRM_UT_LEASE", 225 "DRM_UT_DP", 226 "DRM_UT_DRMRES"); 227 228 struct amdgpu_mgpu_info mgpu_info = { 229 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 230 .delayed_reset_work = __DELAYED_WORK_INITIALIZER( 231 mgpu_info.delayed_reset_work, 232 amdgpu_drv_delayed_reset_work_handler, 0), 233 }; 234 int amdgpu_ras_enable = -1; 235 uint amdgpu_ras_mask = 0xffffffff; 236 int amdgpu_bad_page_threshold = -1; 237 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 238 .timeout_fatal_disable = false, 239 .period = 0x0, /* default to 0x0 (timeout disable) */ 240 }; 241 242 /** 243 * DOC: vramlimit (int) 244 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 245 */ 246 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 247 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 248 249 /** 250 * DOC: vis_vramlimit (int) 251 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 252 */ 253 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 254 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 255 256 /** 257 * DOC: gartsize (uint) 258 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing. 259 * The default is -1 (The size depends on asic). 260 */ 261 MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)"); 262 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 263 264 /** 265 * DOC: gttsize (int) 266 * Restrict the size of GTT domain (for userspace use) in MiB for testing. 267 * The default is -1 (Use 1/2 RAM, minimum value is 3GB). 268 */ 269 MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)"); 270 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 271 272 /** 273 * DOC: moverate (int) 274 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 275 */ 276 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 277 module_param_named(moverate, amdgpu_moverate, int, 0600); 278 279 /** 280 * DOC: audio (int) 281 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 282 */ 283 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 284 module_param_named(audio, amdgpu_audio, int, 0444); 285 286 /** 287 * DOC: disp_priority (int) 288 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 289 */ 290 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 291 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 292 293 /** 294 * DOC: hw_i2c (int) 295 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 296 */ 297 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 298 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 299 300 /** 301 * DOC: pcie_gen2 (int) 302 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 303 */ 304 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 305 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 306 307 /** 308 * DOC: msi (int) 309 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 310 */ 311 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 312 module_param_named(msi, amdgpu_msi, int, 0444); 313 314 /** 315 * DOC: lockup_timeout (string) 316 * Set GPU scheduler timeout value in ms. 317 * 318 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 319 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 320 * to the default timeout. 321 * 322 * - With one value specified, the setting will apply to all non-compute jobs. 323 * - With multiple values specified, the first one will be for GFX. 324 * The second one is for Compute. The third and fourth ones are 325 * for SDMA and Video. 326 * 327 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 328 * jobs is 10000. The timeout for compute is 60000. 329 */ 330 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 331 "for passthrough or sriov, 10000 for all jobs. 0: keep default value. negative: infinity timeout), format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 332 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 333 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 334 335 /** 336 * DOC: dpm (int) 337 * Override for dynamic power management setting 338 * (0 = disable, 1 = enable) 339 * The default is -1 (auto). 340 */ 341 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 342 module_param_named(dpm, amdgpu_dpm, int, 0444); 343 344 /** 345 * DOC: fw_load_type (int) 346 * Set different firmware loading type for debugging, if supported. 347 * Set to 0 to force direct loading if supported by the ASIC. Set 348 * to -1 to select the default loading mode for the ASIC, as defined 349 * by the driver. The default is -1 (auto). 350 */ 351 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); 352 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 353 354 /** 355 * DOC: aspm (int) 356 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 357 */ 358 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 359 module_param_named(aspm, amdgpu_aspm, int, 0444); 360 361 /** 362 * DOC: runpm (int) 363 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 364 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 365 * Setting the value to 0 disables this functionality. 366 * Setting the value to -2 is auto enabled with power down when displays are attached. 367 */ 368 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto, -2 = autowith displays)"); 369 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 370 371 /** 372 * DOC: ip_block_mask (uint) 373 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 374 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 375 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 376 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 377 */ 378 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 379 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 380 381 /** 382 * DOC: bapm (int) 383 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 384 * The default -1 (auto, enabled) 385 */ 386 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 387 module_param_named(bapm, amdgpu_bapm, int, 0444); 388 389 /** 390 * DOC: deep_color (int) 391 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 392 */ 393 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 394 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 395 396 /** 397 * DOC: vm_size (int) 398 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 399 */ 400 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 401 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 402 403 /** 404 * DOC: vm_fragment_size (int) 405 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 406 */ 407 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 408 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 409 410 /** 411 * DOC: vm_block_size (int) 412 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 413 */ 414 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 415 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 416 417 /** 418 * DOC: vm_fault_stop (int) 419 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 420 */ 421 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 422 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 423 424 /** 425 * DOC: vm_update_mode (int) 426 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 427 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 428 */ 429 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 430 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 431 432 /** 433 * DOC: exp_hw_support (int) 434 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 435 */ 436 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 437 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 438 439 /** 440 * DOC: dc (int) 441 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 442 */ 443 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 444 module_param_named(dc, amdgpu_dc, int, 0444); 445 446 /** 447 * DOC: sched_jobs (int) 448 * Override the max number of jobs supported in the sw queue. The default is 32. 449 */ 450 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 451 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 452 453 /** 454 * DOC: sched_hw_submission (int) 455 * Override the max number of HW submissions. The default is 2. 456 */ 457 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 458 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 459 460 /** 461 * DOC: ppfeaturemask (hexint) 462 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 463 * The default is the current set of stable power features. 464 */ 465 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 466 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 467 468 /** 469 * DOC: forcelongtraining (uint) 470 * Force long memory training in resume. 471 * The default is zero, indicates short training in resume. 472 */ 473 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 474 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 475 476 /** 477 * DOC: pcie_gen_cap (uint) 478 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 479 * The default is 0 (automatic for each asic). 480 */ 481 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 482 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 483 484 /** 485 * DOC: pcie_lane_cap (uint) 486 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 487 * The default is 0 (automatic for each asic). 488 */ 489 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 490 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 491 492 /** 493 * DOC: cg_mask (ullong) 494 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 495 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 496 */ 497 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 498 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 499 500 /** 501 * DOC: pg_mask (uint) 502 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 503 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 504 */ 505 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 506 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 507 508 /** 509 * DOC: sdma_phase_quantum (uint) 510 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 511 */ 512 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 513 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 514 515 /** 516 * DOC: disable_cu (charp) 517 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 518 */ 519 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 520 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 521 522 /** 523 * DOC: virtual_display (charp) 524 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 525 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 526 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 527 * device at 26:00.0. The default is NULL. 528 */ 529 MODULE_PARM_DESC(virtual_display, 530 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 531 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 532 533 /** 534 * DOC: lbpw (int) 535 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 536 */ 537 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 538 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 539 540 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 541 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 542 543 /** 544 * DOC: gpu_recovery (int) 545 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 546 */ 547 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 548 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 549 550 /** 551 * DOC: emu_mode (int) 552 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 553 */ 554 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 555 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 556 557 /** 558 * DOC: ras_enable (int) 559 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 560 */ 561 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 562 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 563 564 /** 565 * DOC: ras_mask (uint) 566 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 567 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 568 */ 569 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 570 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 571 572 /** 573 * DOC: timeout_fatal_disable (bool) 574 * Disable Watchdog timeout fatal error event 575 */ 576 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 577 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 578 579 /** 580 * DOC: timeout_period (uint) 581 * Modify the watchdog timeout max_cycles as (1 << period) 582 */ 583 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 584 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 585 586 /** 587 * DOC: si_support (int) 588 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 589 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 590 * otherwise using amdgpu driver. 591 */ 592 #ifdef CONFIG_DRM_AMDGPU_SI 593 594 #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) 595 int amdgpu_si_support = 0; 596 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 597 #else 598 int amdgpu_si_support = 1; 599 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 600 #endif 601 602 module_param_named(si_support, amdgpu_si_support, int, 0444); 603 #endif 604 605 /** 606 * DOC: cik_support (int) 607 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 608 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 609 * otherwise using amdgpu driver. 610 */ 611 #ifdef CONFIG_DRM_AMDGPU_CIK 612 613 #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) 614 int amdgpu_cik_support = 0; 615 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 616 #else 617 int amdgpu_cik_support = 1; 618 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 619 #endif 620 621 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 622 #endif 623 624 /** 625 * DOC: smu_memory_pool_size (uint) 626 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 627 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 628 */ 629 MODULE_PARM_DESC(smu_memory_pool_size, 630 "reserve gtt for smu debug usage, 0 = disable,0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 631 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 632 633 /** 634 * DOC: async_gfx_ring (int) 635 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 636 */ 637 MODULE_PARM_DESC(async_gfx_ring, 638 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 639 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 640 641 /** 642 * DOC: mcbp (int) 643 * It is used to enable mid command buffer preemption. (0 = disabled, 1 = enabled, -1 auto (default)) 644 */ 645 MODULE_PARM_DESC(mcbp, 646 "Enable Mid-command buffer preemption (0 = disabled, 1 = enabled), -1 = auto (default)"); 647 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 648 649 /** 650 * DOC: discovery (int) 651 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 652 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 653 */ 654 MODULE_PARM_DESC(discovery, 655 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 656 module_param_named(discovery, amdgpu_discovery, int, 0444); 657 658 /** 659 * DOC: mes (int) 660 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 661 * (0 = disabled (default), 1 = enabled) 662 */ 663 MODULE_PARM_DESC(mes, 664 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 665 module_param_named(mes, amdgpu_mes, int, 0444); 666 667 /** 668 * DOC: mes_kiq (int) 669 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq. 670 * (0 = disabled (default), 1 = enabled) 671 */ 672 MODULE_PARM_DESC(mes_kiq, 673 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)"); 674 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444); 675 676 /** 677 * DOC: noretry (int) 678 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 679 * do not support per-process XNACK this also disables retry page faults. 680 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 681 */ 682 MODULE_PARM_DESC(noretry, 683 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 684 module_param_named(noretry, amdgpu_noretry, int, 0644); 685 686 /** 687 * DOC: force_asic_type (int) 688 * A non negative value used to specify the asic type for all supported GPUs. 689 */ 690 MODULE_PARM_DESC(force_asic_type, 691 "A non negative value used to specify the asic type for all supported GPUs"); 692 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 693 694 /** 695 * DOC: use_xgmi_p2p (int) 696 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 697 */ 698 MODULE_PARM_DESC(use_xgmi_p2p, 699 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 700 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 701 702 703 #ifdef CONFIG_HSA_AMD 704 /** 705 * DOC: sched_policy (int) 706 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 707 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 708 * assigns queues to HQDs. 709 */ 710 int sched_policy = KFD_SCHED_POLICY_HWS; 711 module_param(sched_policy, int, 0444); 712 MODULE_PARM_DESC(sched_policy, 713 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 714 715 /** 716 * DOC: hws_max_conc_proc (int) 717 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 718 * number of VMIDs assigned to the HWS, which is also the default. 719 */ 720 int hws_max_conc_proc = -1; 721 module_param(hws_max_conc_proc, int, 0444); 722 MODULE_PARM_DESC(hws_max_conc_proc, 723 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 724 725 /** 726 * DOC: cwsr_enable (int) 727 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 728 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 729 * disables it. 730 */ 731 int cwsr_enable = 1; 732 module_param(cwsr_enable, int, 0444); 733 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 734 735 /** 736 * DOC: max_num_of_queues_per_device (int) 737 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 738 * is 4096. 739 */ 740 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 741 module_param(max_num_of_queues_per_device, int, 0444); 742 MODULE_PARM_DESC(max_num_of_queues_per_device, 743 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 744 745 /** 746 * DOC: send_sigterm (int) 747 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 748 * but just print errors on dmesg. Setting 1 enables sending sigterm. 749 */ 750 int send_sigterm; 751 module_param(send_sigterm, int, 0444); 752 MODULE_PARM_DESC(send_sigterm, 753 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 754 755 /** 756 * DOC: halt_if_hws_hang (int) 757 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 758 * Setting 1 enables halt on hang. 759 */ 760 int halt_if_hws_hang; 761 module_param(halt_if_hws_hang, int, 0644); 762 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 763 764 /** 765 * DOC: hws_gws_support(bool) 766 * Assume that HWS supports GWS barriers regardless of what firmware version 767 * check says. Default value: false (rely on MEC2 firmware version check). 768 */ 769 bool hws_gws_support; 770 module_param(hws_gws_support, bool, 0444); 771 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 772 773 /** 774 * DOC: queue_preemption_timeout_ms (int) 775 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 776 */ 777 int queue_preemption_timeout_ms = 9000; 778 module_param(queue_preemption_timeout_ms, int, 0644); 779 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 780 781 /** 782 * DOC: debug_evictions(bool) 783 * Enable extra debug messages to help determine the cause of evictions 784 */ 785 bool debug_evictions; 786 module_param(debug_evictions, bool, 0644); 787 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 788 789 /** 790 * DOC: no_system_mem_limit(bool) 791 * Disable system memory limit, to support multiple process shared memory 792 */ 793 bool no_system_mem_limit; 794 module_param(no_system_mem_limit, bool, 0644); 795 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 796 797 /** 798 * DOC: no_queue_eviction_on_vm_fault (int) 799 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 800 */ 801 int amdgpu_no_queue_eviction_on_vm_fault; 802 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 803 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 804 #endif 805 806 /** 807 * DOC: mtype_local (int) 808 */ 809 int amdgpu_mtype_local; 810 MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (0 = MTYPE_RW (default), 1 = MTYPE_NC, 2 = MTYPE_CC)"); 811 module_param_named(mtype_local, amdgpu_mtype_local, int, 0444); 812 813 /** 814 * DOC: pcie_p2p (bool) 815 * Enable PCIe P2P (requires large-BAR). Default value: true (on) 816 */ 817 #ifdef CONFIG_HSA_AMD_P2P 818 bool pcie_p2p = true; 819 module_param(pcie_p2p, bool, 0444); 820 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); 821 #endif 822 823 /** 824 * DOC: dcfeaturemask (uint) 825 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 826 * The default is the current set of stable display features. 827 */ 828 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 829 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 830 831 /** 832 * DOC: dcdebugmask (uint) 833 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 834 */ 835 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 836 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 837 838 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)"); 839 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444); 840 841 /** 842 * DOC: abmlevel (uint) 843 * Override the default ABM (Adaptive Backlight Management) level used for DC 844 * enabled hardware. Requires DMCU to be supported and loaded. 845 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 846 * default. Values 1-4 control the maximum allowable brightness reduction via 847 * the ABM algorithm, with 1 being the least reduction and 4 being the most 848 * reduction. 849 * 850 * Defaults to 0, or disabled. Userspace can still override this level later 851 * after boot. 852 */ 853 uint amdgpu_dm_abm_level; 854 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 855 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 856 857 int amdgpu_backlight = -1; 858 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 859 module_param_named(backlight, amdgpu_backlight, bint, 0444); 860 861 /** 862 * DOC: tmz (int) 863 * Trusted Memory Zone (TMZ) is a method to protect data being written 864 * to or read from memory. 865 * 866 * The default value: 0 (off). TODO: change to auto till it is completed. 867 */ 868 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 869 module_param_named(tmz, amdgpu_tmz, int, 0444); 870 871 /** 872 * DOC: reset_method (int) 873 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 874 */ 875 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 876 module_param_named(reset_method, amdgpu_reset_method, int, 0444); 877 878 /** 879 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 880 * threshold value of faulty pages detected by RAS ECC, which may 881 * result in the GPU entering bad status when the number of total 882 * faulty pages by ECC exceeds the threshold value. 883 */ 884 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = driver sets threshold)"); 885 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 886 887 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 888 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 889 890 /** 891 * DOC: vcnfw_log (int) 892 * Enable vcnfw log output for debugging, the default is disabled. 893 */ 894 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 895 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 896 897 /** 898 * DOC: sg_display (int) 899 * Disable S/G (scatter/gather) display (i.e., display from system memory). 900 * This option is only relevant on APUs. Set this option to 0 to disable 901 * S/G display if you experience flickering or other issues under memory 902 * pressure and report the issue. 903 */ 904 MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)"); 905 module_param_named(sg_display, amdgpu_sg_display, int, 0444); 906 907 /** 908 * DOC: umsch_mm (int) 909 * Enable Multi Media User Mode Scheduler. This is a HW scheduling engine for VCN and VPE. 910 * (0 = disabled (default), 1 = enabled) 911 */ 912 MODULE_PARM_DESC(umsch_mm, 913 "Enable Multi Media User Mode Scheduler (0 = disabled (default), 1 = enabled)"); 914 module_param_named(umsch_mm, amdgpu_umsch_mm, int, 0444); 915 916 /** 917 * DOC: smu_pptable_id (int) 918 * Used to override pptable id. id = 0 use VBIOS pptable. 919 * id > 0 use the soft pptable with specicfied id. 920 */ 921 MODULE_PARM_DESC(smu_pptable_id, 922 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 923 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 924 925 /** 926 * DOC: partition_mode (int) 927 * Used to override the default SPX mode. 928 */ 929 MODULE_PARM_DESC( 930 user_partt_mode, 931 "specify partition mode to be used (-2 = AMDGPU_AUTO_COMPUTE_PARTITION_MODE(default value) \ 932 0 = AMDGPU_SPX_PARTITION_MODE, \ 933 1 = AMDGPU_DPX_PARTITION_MODE, \ 934 2 = AMDGPU_TPX_PARTITION_MODE, \ 935 3 = AMDGPU_QPX_PARTITION_MODE, \ 936 4 = AMDGPU_CPX_PARTITION_MODE)"); 937 module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint, 0444); 938 939 940 /** 941 * DOC: enforce_isolation (bool) 942 * enforce process isolation between graphics and compute via using the same reserved vmid. 943 */ 944 module_param(enforce_isolation, bool, 0444); 945 MODULE_PARM_DESC(enforce_isolation, "enforce process isolation between graphics and compute . enforce_isolation = on"); 946 947 /** 948 * DOC: seamless (int) 949 * Seamless boot will keep the image on the screen during the boot process. 950 */ 951 MODULE_PARM_DESC(seamless, "Seamless boot (-1 = auto (default), 0 = disable, 1 = enable)"); 952 module_param_named(seamless, amdgpu_seamless, int, 0444); 953 954 /** 955 * DOC: debug_mask (uint) 956 * Debug options for amdgpu, work as a binary mask with the following options: 957 * 958 * - 0x1: Debug VM handling 959 * - 0x2: Enable simulating large-bar capability on non-large bar system. This 960 * limits the VRAM size reported to ROCm applications to the visible 961 * size, usually 256MB. 962 * - 0x4: Disable GPU soft recovery, always do a full reset 963 */ 964 MODULE_PARM_DESC(debug_mask, "debug options for amdgpu, disabled by default"); 965 module_param_named(debug_mask, amdgpu_debug_mask, uint, 0444); 966 967 /** 968 * DOC: agp (int) 969 * Enable the AGP aperture. This provides an aperture in the GPU's internal 970 * address space for direct access to system memory. Note that these accesses 971 * are non-snooped, so they are only used for access to uncached memory. 972 */ 973 MODULE_PARM_DESC(agp, "AGP (-1 = auto (default), 0 = disable, 1 = enable)"); 974 module_param_named(agp, amdgpu_agp, int, 0444); 975 976 /** 977 * DOC: wbrf (int) 978 * Enable Wifi RFI interference mitigation feature. 979 * Due to electrical and mechanical constraints there may be likely interference of 980 * relatively high-powered harmonics of the (G-)DDR memory clocks with local radio 981 * module frequency bands used by Wifi 6/6e/7. To mitigate the possible RFI interference, 982 * with this feature enabled, PMFW will use either “shadowed P-State” or “P-State” based 983 * on active list of frequencies in-use (to be avoided) as part of initial setting or 984 * P-state transition. However, there may be potential performance impact with this 985 * feature enabled. 986 * (0 = disabled, 1 = enabled, -1 = auto (default setting, will be enabled if supported)) 987 */ 988 MODULE_PARM_DESC(wbrf, 989 "Enable Wifi RFI interference mitigation (0 = disabled, 1 = enabled, -1 = auto(default)"); 990 module_param_named(wbrf, amdgpu_wbrf, int, 0444); 991 992 /* These devices are not supported by amdgpu. 993 * They are supported by the mach64, r128, radeon drivers 994 */ 995 static const u16 amdgpu_unsupported_pciidlist[] = { 996 /* mach64 */ 997 0x4354, 998 0x4358, 999 0x4554, 1000 0x4742, 1001 0x4744, 1002 0x4749, 1003 0x474C, 1004 0x474D, 1005 0x474E, 1006 0x474F, 1007 0x4750, 1008 0x4751, 1009 0x4752, 1010 0x4753, 1011 0x4754, 1012 0x4755, 1013 0x4756, 1014 0x4757, 1015 0x4758, 1016 0x4759, 1017 0x475A, 1018 0x4C42, 1019 0x4C44, 1020 0x4C47, 1021 0x4C49, 1022 0x4C4D, 1023 0x4C4E, 1024 0x4C50, 1025 0x4C51, 1026 0x4C52, 1027 0x4C53, 1028 0x5654, 1029 0x5655, 1030 0x5656, 1031 /* r128 */ 1032 0x4c45, 1033 0x4c46, 1034 0x4d46, 1035 0x4d4c, 1036 0x5041, 1037 0x5042, 1038 0x5043, 1039 0x5044, 1040 0x5045, 1041 0x5046, 1042 0x5047, 1043 0x5048, 1044 0x5049, 1045 0x504A, 1046 0x504B, 1047 0x504C, 1048 0x504D, 1049 0x504E, 1050 0x504F, 1051 0x5050, 1052 0x5051, 1053 0x5052, 1054 0x5053, 1055 0x5054, 1056 0x5055, 1057 0x5056, 1058 0x5057, 1059 0x5058, 1060 0x5245, 1061 0x5246, 1062 0x5247, 1063 0x524b, 1064 0x524c, 1065 0x534d, 1066 0x5446, 1067 0x544C, 1068 0x5452, 1069 /* radeon */ 1070 0x3150, 1071 0x3151, 1072 0x3152, 1073 0x3154, 1074 0x3155, 1075 0x3E50, 1076 0x3E54, 1077 0x4136, 1078 0x4137, 1079 0x4144, 1080 0x4145, 1081 0x4146, 1082 0x4147, 1083 0x4148, 1084 0x4149, 1085 0x414A, 1086 0x414B, 1087 0x4150, 1088 0x4151, 1089 0x4152, 1090 0x4153, 1091 0x4154, 1092 0x4155, 1093 0x4156, 1094 0x4237, 1095 0x4242, 1096 0x4336, 1097 0x4337, 1098 0x4437, 1099 0x4966, 1100 0x4967, 1101 0x4A48, 1102 0x4A49, 1103 0x4A4A, 1104 0x4A4B, 1105 0x4A4C, 1106 0x4A4D, 1107 0x4A4E, 1108 0x4A4F, 1109 0x4A50, 1110 0x4A54, 1111 0x4B48, 1112 0x4B49, 1113 0x4B4A, 1114 0x4B4B, 1115 0x4B4C, 1116 0x4C57, 1117 0x4C58, 1118 0x4C59, 1119 0x4C5A, 1120 0x4C64, 1121 0x4C66, 1122 0x4C67, 1123 0x4E44, 1124 0x4E45, 1125 0x4E46, 1126 0x4E47, 1127 0x4E48, 1128 0x4E49, 1129 0x4E4A, 1130 0x4E4B, 1131 0x4E50, 1132 0x4E51, 1133 0x4E52, 1134 0x4E53, 1135 0x4E54, 1136 0x4E56, 1137 0x5144, 1138 0x5145, 1139 0x5146, 1140 0x5147, 1141 0x5148, 1142 0x514C, 1143 0x514D, 1144 0x5157, 1145 0x5158, 1146 0x5159, 1147 0x515A, 1148 0x515E, 1149 0x5460, 1150 0x5462, 1151 0x5464, 1152 0x5548, 1153 0x5549, 1154 0x554A, 1155 0x554B, 1156 0x554C, 1157 0x554D, 1158 0x554E, 1159 0x554F, 1160 0x5550, 1161 0x5551, 1162 0x5552, 1163 0x5554, 1164 0x564A, 1165 0x564B, 1166 0x564F, 1167 0x5652, 1168 0x5653, 1169 0x5657, 1170 0x5834, 1171 0x5835, 1172 0x5954, 1173 0x5955, 1174 0x5974, 1175 0x5975, 1176 0x5960, 1177 0x5961, 1178 0x5962, 1179 0x5964, 1180 0x5965, 1181 0x5969, 1182 0x5a41, 1183 0x5a42, 1184 0x5a61, 1185 0x5a62, 1186 0x5b60, 1187 0x5b62, 1188 0x5b63, 1189 0x5b64, 1190 0x5b65, 1191 0x5c61, 1192 0x5c63, 1193 0x5d48, 1194 0x5d49, 1195 0x5d4a, 1196 0x5d4c, 1197 0x5d4d, 1198 0x5d4e, 1199 0x5d4f, 1200 0x5d50, 1201 0x5d52, 1202 0x5d57, 1203 0x5e48, 1204 0x5e4a, 1205 0x5e4b, 1206 0x5e4c, 1207 0x5e4d, 1208 0x5e4f, 1209 0x6700, 1210 0x6701, 1211 0x6702, 1212 0x6703, 1213 0x6704, 1214 0x6705, 1215 0x6706, 1216 0x6707, 1217 0x6708, 1218 0x6709, 1219 0x6718, 1220 0x6719, 1221 0x671c, 1222 0x671d, 1223 0x671f, 1224 0x6720, 1225 0x6721, 1226 0x6722, 1227 0x6723, 1228 0x6724, 1229 0x6725, 1230 0x6726, 1231 0x6727, 1232 0x6728, 1233 0x6729, 1234 0x6738, 1235 0x6739, 1236 0x673e, 1237 0x6740, 1238 0x6741, 1239 0x6742, 1240 0x6743, 1241 0x6744, 1242 0x6745, 1243 0x6746, 1244 0x6747, 1245 0x6748, 1246 0x6749, 1247 0x674A, 1248 0x6750, 1249 0x6751, 1250 0x6758, 1251 0x6759, 1252 0x675B, 1253 0x675D, 1254 0x675F, 1255 0x6760, 1256 0x6761, 1257 0x6762, 1258 0x6763, 1259 0x6764, 1260 0x6765, 1261 0x6766, 1262 0x6767, 1263 0x6768, 1264 0x6770, 1265 0x6771, 1266 0x6772, 1267 0x6778, 1268 0x6779, 1269 0x677B, 1270 0x6840, 1271 0x6841, 1272 0x6842, 1273 0x6843, 1274 0x6849, 1275 0x684C, 1276 0x6850, 1277 0x6858, 1278 0x6859, 1279 0x6880, 1280 0x6888, 1281 0x6889, 1282 0x688A, 1283 0x688C, 1284 0x688D, 1285 0x6898, 1286 0x6899, 1287 0x689b, 1288 0x689c, 1289 0x689d, 1290 0x689e, 1291 0x68a0, 1292 0x68a1, 1293 0x68a8, 1294 0x68a9, 1295 0x68b0, 1296 0x68b8, 1297 0x68b9, 1298 0x68ba, 1299 0x68be, 1300 0x68bf, 1301 0x68c0, 1302 0x68c1, 1303 0x68c7, 1304 0x68c8, 1305 0x68c9, 1306 0x68d8, 1307 0x68d9, 1308 0x68da, 1309 0x68de, 1310 0x68e0, 1311 0x68e1, 1312 0x68e4, 1313 0x68e5, 1314 0x68e8, 1315 0x68e9, 1316 0x68f1, 1317 0x68f2, 1318 0x68f8, 1319 0x68f9, 1320 0x68fa, 1321 0x68fe, 1322 0x7100, 1323 0x7101, 1324 0x7102, 1325 0x7103, 1326 0x7104, 1327 0x7105, 1328 0x7106, 1329 0x7108, 1330 0x7109, 1331 0x710A, 1332 0x710B, 1333 0x710C, 1334 0x710E, 1335 0x710F, 1336 0x7140, 1337 0x7141, 1338 0x7142, 1339 0x7143, 1340 0x7144, 1341 0x7145, 1342 0x7146, 1343 0x7147, 1344 0x7149, 1345 0x714A, 1346 0x714B, 1347 0x714C, 1348 0x714D, 1349 0x714E, 1350 0x714F, 1351 0x7151, 1352 0x7152, 1353 0x7153, 1354 0x715E, 1355 0x715F, 1356 0x7180, 1357 0x7181, 1358 0x7183, 1359 0x7186, 1360 0x7187, 1361 0x7188, 1362 0x718A, 1363 0x718B, 1364 0x718C, 1365 0x718D, 1366 0x718F, 1367 0x7193, 1368 0x7196, 1369 0x719B, 1370 0x719F, 1371 0x71C0, 1372 0x71C1, 1373 0x71C2, 1374 0x71C3, 1375 0x71C4, 1376 0x71C5, 1377 0x71C6, 1378 0x71C7, 1379 0x71CD, 1380 0x71CE, 1381 0x71D2, 1382 0x71D4, 1383 0x71D5, 1384 0x71D6, 1385 0x71DA, 1386 0x71DE, 1387 0x7200, 1388 0x7210, 1389 0x7211, 1390 0x7240, 1391 0x7243, 1392 0x7244, 1393 0x7245, 1394 0x7246, 1395 0x7247, 1396 0x7248, 1397 0x7249, 1398 0x724A, 1399 0x724B, 1400 0x724C, 1401 0x724D, 1402 0x724E, 1403 0x724F, 1404 0x7280, 1405 0x7281, 1406 0x7283, 1407 0x7284, 1408 0x7287, 1409 0x7288, 1410 0x7289, 1411 0x728B, 1412 0x728C, 1413 0x7290, 1414 0x7291, 1415 0x7293, 1416 0x7297, 1417 0x7834, 1418 0x7835, 1419 0x791e, 1420 0x791f, 1421 0x793f, 1422 0x7941, 1423 0x7942, 1424 0x796c, 1425 0x796d, 1426 0x796e, 1427 0x796f, 1428 0x9400, 1429 0x9401, 1430 0x9402, 1431 0x9403, 1432 0x9405, 1433 0x940A, 1434 0x940B, 1435 0x940F, 1436 0x94A0, 1437 0x94A1, 1438 0x94A3, 1439 0x94B1, 1440 0x94B3, 1441 0x94B4, 1442 0x94B5, 1443 0x94B9, 1444 0x9440, 1445 0x9441, 1446 0x9442, 1447 0x9443, 1448 0x9444, 1449 0x9446, 1450 0x944A, 1451 0x944B, 1452 0x944C, 1453 0x944E, 1454 0x9450, 1455 0x9452, 1456 0x9456, 1457 0x945A, 1458 0x945B, 1459 0x945E, 1460 0x9460, 1461 0x9462, 1462 0x946A, 1463 0x946B, 1464 0x947A, 1465 0x947B, 1466 0x9480, 1467 0x9487, 1468 0x9488, 1469 0x9489, 1470 0x948A, 1471 0x948F, 1472 0x9490, 1473 0x9491, 1474 0x9495, 1475 0x9498, 1476 0x949C, 1477 0x949E, 1478 0x949F, 1479 0x94C0, 1480 0x94C1, 1481 0x94C3, 1482 0x94C4, 1483 0x94C5, 1484 0x94C6, 1485 0x94C7, 1486 0x94C8, 1487 0x94C9, 1488 0x94CB, 1489 0x94CC, 1490 0x94CD, 1491 0x9500, 1492 0x9501, 1493 0x9504, 1494 0x9505, 1495 0x9506, 1496 0x9507, 1497 0x9508, 1498 0x9509, 1499 0x950F, 1500 0x9511, 1501 0x9515, 1502 0x9517, 1503 0x9519, 1504 0x9540, 1505 0x9541, 1506 0x9542, 1507 0x954E, 1508 0x954F, 1509 0x9552, 1510 0x9553, 1511 0x9555, 1512 0x9557, 1513 0x955f, 1514 0x9580, 1515 0x9581, 1516 0x9583, 1517 0x9586, 1518 0x9587, 1519 0x9588, 1520 0x9589, 1521 0x958A, 1522 0x958B, 1523 0x958C, 1524 0x958D, 1525 0x958E, 1526 0x958F, 1527 0x9590, 1528 0x9591, 1529 0x9593, 1530 0x9595, 1531 0x9596, 1532 0x9597, 1533 0x9598, 1534 0x9599, 1535 0x959B, 1536 0x95C0, 1537 0x95C2, 1538 0x95C4, 1539 0x95C5, 1540 0x95C6, 1541 0x95C7, 1542 0x95C9, 1543 0x95CC, 1544 0x95CD, 1545 0x95CE, 1546 0x95CF, 1547 0x9610, 1548 0x9611, 1549 0x9612, 1550 0x9613, 1551 0x9614, 1552 0x9615, 1553 0x9616, 1554 0x9640, 1555 0x9641, 1556 0x9642, 1557 0x9643, 1558 0x9644, 1559 0x9645, 1560 0x9647, 1561 0x9648, 1562 0x9649, 1563 0x964a, 1564 0x964b, 1565 0x964c, 1566 0x964e, 1567 0x964f, 1568 0x9710, 1569 0x9711, 1570 0x9712, 1571 0x9713, 1572 0x9714, 1573 0x9715, 1574 0x9802, 1575 0x9803, 1576 0x9804, 1577 0x9805, 1578 0x9806, 1579 0x9807, 1580 0x9808, 1581 0x9809, 1582 0x980A, 1583 0x9900, 1584 0x9901, 1585 0x9903, 1586 0x9904, 1587 0x9905, 1588 0x9906, 1589 0x9907, 1590 0x9908, 1591 0x9909, 1592 0x990A, 1593 0x990B, 1594 0x990C, 1595 0x990D, 1596 0x990E, 1597 0x990F, 1598 0x9910, 1599 0x9913, 1600 0x9917, 1601 0x9918, 1602 0x9919, 1603 0x9990, 1604 0x9991, 1605 0x9992, 1606 0x9993, 1607 0x9994, 1608 0x9995, 1609 0x9996, 1610 0x9997, 1611 0x9998, 1612 0x9999, 1613 0x999A, 1614 0x999B, 1615 0x999C, 1616 0x999D, 1617 0x99A0, 1618 0x99A2, 1619 0x99A4, 1620 /* radeon secondary ids */ 1621 0x3171, 1622 0x3e70, 1623 0x4164, 1624 0x4165, 1625 0x4166, 1626 0x4168, 1627 0x4170, 1628 0x4171, 1629 0x4172, 1630 0x4173, 1631 0x496e, 1632 0x4a69, 1633 0x4a6a, 1634 0x4a6b, 1635 0x4a70, 1636 0x4a74, 1637 0x4b69, 1638 0x4b6b, 1639 0x4b6c, 1640 0x4c6e, 1641 0x4e64, 1642 0x4e65, 1643 0x4e66, 1644 0x4e67, 1645 0x4e68, 1646 0x4e69, 1647 0x4e6a, 1648 0x4e71, 1649 0x4f73, 1650 0x5569, 1651 0x556b, 1652 0x556d, 1653 0x556f, 1654 0x5571, 1655 0x5854, 1656 0x5874, 1657 0x5940, 1658 0x5941, 1659 0x5b70, 1660 0x5b72, 1661 0x5b73, 1662 0x5b74, 1663 0x5b75, 1664 0x5d44, 1665 0x5d45, 1666 0x5d6d, 1667 0x5d6f, 1668 0x5d72, 1669 0x5d77, 1670 0x5e6b, 1671 0x5e6d, 1672 0x7120, 1673 0x7124, 1674 0x7129, 1675 0x712e, 1676 0x712f, 1677 0x7162, 1678 0x7163, 1679 0x7166, 1680 0x7167, 1681 0x7172, 1682 0x7173, 1683 0x71a0, 1684 0x71a1, 1685 0x71a3, 1686 0x71a7, 1687 0x71bb, 1688 0x71e0, 1689 0x71e1, 1690 0x71e2, 1691 0x71e6, 1692 0x71e7, 1693 0x71f2, 1694 0x7269, 1695 0x726b, 1696 0x726e, 1697 0x72a0, 1698 0x72a8, 1699 0x72b1, 1700 0x72b3, 1701 0x793f, 1702 }; 1703 1704 static const struct pci_device_id pciidlist[] = { 1705 #ifdef CONFIG_DRM_AMDGPU_SI 1706 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1707 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1708 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1709 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1710 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1711 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1712 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1713 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1714 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1715 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1716 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1717 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1718 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1719 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1720 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1721 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1722 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1723 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1724 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1725 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1726 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1727 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1728 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1729 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1730 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1731 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1732 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1733 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1734 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1735 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1736 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1737 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1738 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1739 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1740 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1741 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1742 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1743 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1744 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1745 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1746 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1747 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1748 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1749 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1750 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1751 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1752 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1753 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1754 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1755 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1756 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1757 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1758 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1759 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1760 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1761 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1762 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1763 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1764 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1765 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1766 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1767 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1768 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1769 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1770 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1771 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1772 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1773 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1774 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1775 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1776 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1777 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1778 #endif 1779 #ifdef CONFIG_DRM_AMDGPU_CIK 1780 /* Kaveri */ 1781 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1782 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1783 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1784 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1785 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1786 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1787 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1788 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1789 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1790 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1791 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1792 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1793 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1794 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1795 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1796 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1797 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1798 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1799 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1800 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1801 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1802 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1803 /* Bonaire */ 1804 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1805 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1806 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1807 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1808 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1809 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1810 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1811 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1812 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1813 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1814 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1815 /* Hawaii */ 1816 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1817 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1818 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1819 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1820 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1821 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1822 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1823 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1824 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1825 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1826 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1827 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1828 /* Kabini */ 1829 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1830 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1831 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1832 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1833 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1834 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1835 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1836 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1837 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1838 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1839 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1840 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1841 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1842 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1843 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1844 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1845 /* mullins */ 1846 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1847 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1848 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1849 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1850 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1851 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1852 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1853 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1854 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1855 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1856 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1857 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1858 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1859 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1860 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1861 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1862 #endif 1863 /* topaz */ 1864 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1865 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1866 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1867 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1868 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1869 /* tonga */ 1870 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1871 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1872 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1873 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1874 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1875 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1876 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1877 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1878 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1879 /* fiji */ 1880 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1881 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1882 /* carrizo */ 1883 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1884 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1885 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1886 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1887 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1888 /* stoney */ 1889 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1890 /* Polaris11 */ 1891 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1892 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1893 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1894 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1895 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1896 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1897 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1898 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1899 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1900 /* Polaris10 */ 1901 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1902 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1903 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1904 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1905 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1906 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1907 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1908 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1909 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1910 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1911 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1912 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1913 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1914 /* Polaris12 */ 1915 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1916 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1917 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1918 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1919 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1920 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1921 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1922 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1923 /* VEGAM */ 1924 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1925 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1926 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1927 /* Vega 10 */ 1928 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1929 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1930 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1931 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1932 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1933 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1934 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1935 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1936 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1937 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1938 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1939 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1940 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1941 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1942 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1943 /* Vega 12 */ 1944 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1945 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1946 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1947 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1948 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1949 /* Vega 20 */ 1950 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1951 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1952 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1953 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1954 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1955 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1956 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1957 /* Raven */ 1958 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1959 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1960 /* Arcturus */ 1961 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1962 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1963 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1964 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1965 /* Navi10 */ 1966 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1967 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1968 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1969 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1970 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1971 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1972 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1973 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1974 /* Navi14 */ 1975 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1976 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1977 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1978 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1979 1980 /* Renoir */ 1981 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1982 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1983 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1984 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1985 1986 /* Navi12 */ 1987 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1988 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1989 1990 /* Sienna_Cichlid */ 1991 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1992 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1993 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1994 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1995 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1996 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1997 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1998 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1999 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2000 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2001 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2002 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2003 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2004 2005 /* Yellow Carp */ 2006 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 2007 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 2008 2009 /* Navy_Flounder */ 2010 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2011 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2012 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2013 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2014 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2015 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2016 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2017 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2018 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2019 2020 /* DIMGREY_CAVEFISH */ 2021 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2022 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2023 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2024 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2025 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2026 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2027 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2028 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2029 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2030 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2031 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2032 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2033 2034 /* Aldebaran */ 2035 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2036 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2037 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2038 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2039 2040 /* CYAN_SKILLFISH */ 2041 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2042 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2043 2044 /* BEIGE_GOBY */ 2045 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2046 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2047 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2048 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2049 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2050 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2051 2052 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2053 .class = PCI_CLASS_DISPLAY_VGA << 8, 2054 .class_mask = 0xffffff, 2055 .driver_data = CHIP_IP_DISCOVERY }, 2056 2057 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2058 .class = PCI_CLASS_DISPLAY_OTHER << 8, 2059 .class_mask = 0xffffff, 2060 .driver_data = CHIP_IP_DISCOVERY }, 2061 2062 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2063 .class = PCI_CLASS_ACCELERATOR_PROCESSING << 8, 2064 .class_mask = 0xffffff, 2065 .driver_data = CHIP_IP_DISCOVERY }, 2066 2067 {0, 0, 0} 2068 }; 2069 2070 MODULE_DEVICE_TABLE(pci, pciidlist); 2071 2072 static const struct amdgpu_asic_type_quirk asic_type_quirks[] = { 2073 /* differentiate between P10 and P11 asics with the same DID */ 2074 {0x67FF, 0xE3, CHIP_POLARIS10}, 2075 {0x67FF, 0xE7, CHIP_POLARIS10}, 2076 {0x67FF, 0xF3, CHIP_POLARIS10}, 2077 {0x67FF, 0xF7, CHIP_POLARIS10}, 2078 }; 2079 2080 static const struct drm_driver amdgpu_kms_driver; 2081 2082 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 2083 { 2084 struct pci_dev *p = NULL; 2085 int i; 2086 2087 /* 0 - GPU 2088 * 1 - audio 2089 * 2 - USB 2090 * 3 - UCSI 2091 */ 2092 for (i = 1; i < 4; i++) { 2093 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 2094 adev->pdev->bus->number, i); 2095 if (p) { 2096 pm_runtime_get_sync(&p->dev); 2097 pm_runtime_mark_last_busy(&p->dev); 2098 pm_runtime_put_autosuspend(&p->dev); 2099 pci_dev_put(p); 2100 } 2101 } 2102 } 2103 2104 static void amdgpu_init_debug_options(struct amdgpu_device *adev) 2105 { 2106 if (amdgpu_debug_mask & AMDGPU_DEBUG_VM) { 2107 pr_info("debug: VM handling debug enabled\n"); 2108 adev->debug_vm = true; 2109 } 2110 2111 if (amdgpu_debug_mask & AMDGPU_DEBUG_LARGEBAR) { 2112 pr_info("debug: enabled simulating large-bar capability on non-large bar system\n"); 2113 adev->debug_largebar = true; 2114 } 2115 2116 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY) { 2117 pr_info("debug: soft reset for GPU recovery disabled\n"); 2118 adev->debug_disable_soft_recovery = true; 2119 } 2120 } 2121 2122 static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long flags) 2123 { 2124 int i; 2125 2126 for (i = 0; i < ARRAY_SIZE(asic_type_quirks); i++) { 2127 if (pdev->device == asic_type_quirks[i].device && 2128 pdev->revision == asic_type_quirks[i].revision) { 2129 flags &= ~AMD_ASIC_MASK; 2130 flags |= asic_type_quirks[i].type; 2131 break; 2132 } 2133 } 2134 2135 return flags; 2136 } 2137 2138 static int amdgpu_pci_probe(struct pci_dev *pdev, 2139 const struct pci_device_id *ent) 2140 { 2141 struct drm_device *ddev; 2142 struct amdgpu_device *adev; 2143 unsigned long flags = ent->driver_data; 2144 int ret, retry = 0, i; 2145 bool supports_atomic = false; 2146 2147 /* skip devices which are owned by radeon */ 2148 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2149 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2150 return -ENODEV; 2151 } 2152 2153 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) 2154 amdgpu_aspm = 0; 2155 2156 if (amdgpu_virtual_display || 2157 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 2158 supports_atomic = true; 2159 2160 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2161 DRM_INFO("This hardware requires experimental hardware support.\n" 2162 "See modparam exp_hw_support\n"); 2163 return -ENODEV; 2164 } 2165 2166 flags = amdgpu_fix_asic_type(pdev, flags); 2167 2168 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2169 * however, SME requires an indirect IOMMU mapping because the encryption 2170 * bit is beyond the DMA mask of the chip. 2171 */ 2172 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2173 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2174 dev_info(&pdev->dev, 2175 "SME is not compatible with RAVEN\n"); 2176 return -ENOTSUPP; 2177 } 2178 2179 #ifdef CONFIG_DRM_AMDGPU_SI 2180 if (!amdgpu_si_support) { 2181 switch (flags & AMD_ASIC_MASK) { 2182 case CHIP_TAHITI: 2183 case CHIP_PITCAIRN: 2184 case CHIP_VERDE: 2185 case CHIP_OLAND: 2186 case CHIP_HAINAN: 2187 dev_info(&pdev->dev, 2188 "SI support provided by radeon.\n"); 2189 dev_info(&pdev->dev, 2190 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 2191 ); 2192 return -ENODEV; 2193 } 2194 } 2195 #endif 2196 #ifdef CONFIG_DRM_AMDGPU_CIK 2197 if (!amdgpu_cik_support) { 2198 switch (flags & AMD_ASIC_MASK) { 2199 case CHIP_KAVERI: 2200 case CHIP_BONAIRE: 2201 case CHIP_HAWAII: 2202 case CHIP_KABINI: 2203 case CHIP_MULLINS: 2204 dev_info(&pdev->dev, 2205 "CIK support provided by radeon.\n"); 2206 dev_info(&pdev->dev, 2207 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 2208 ); 2209 return -ENODEV; 2210 } 2211 } 2212 #endif 2213 2214 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2215 if (IS_ERR(adev)) 2216 return PTR_ERR(adev); 2217 2218 adev->dev = &pdev->dev; 2219 adev->pdev = pdev; 2220 ddev = adev_to_drm(adev); 2221 2222 if (!supports_atomic) 2223 ddev->driver_features &= ~DRIVER_ATOMIC; 2224 2225 ret = pci_enable_device(pdev); 2226 if (ret) 2227 return ret; 2228 2229 pci_set_drvdata(pdev, ddev); 2230 2231 ret = amdgpu_driver_load_kms(adev, flags); 2232 if (ret) 2233 goto err_pci; 2234 2235 retry_init: 2236 ret = drm_dev_register(ddev, flags); 2237 if (ret == -EAGAIN && ++retry <= 3) { 2238 DRM_INFO("retry init %d\n", retry); 2239 /* Don't request EX mode too frequently which is attacking */ 2240 msleep(5000); 2241 goto retry_init; 2242 } else if (ret) { 2243 goto err_pci; 2244 } 2245 2246 ret = amdgpu_xcp_dev_register(adev, ent); 2247 if (ret) 2248 goto err_pci; 2249 2250 /* 2251 * 1. don't init fbdev on hw without DCE 2252 * 2. don't init fbdev if there are no connectors 2253 */ 2254 if (adev->mode_info.mode_config_initialized && 2255 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2256 /* select 8 bpp console on low vram cards */ 2257 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2258 drm_fbdev_generic_setup(adev_to_drm(adev), 8); 2259 else 2260 drm_fbdev_generic_setup(adev_to_drm(adev), 32); 2261 } 2262 2263 ret = amdgpu_debugfs_init(adev); 2264 if (ret) 2265 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2266 2267 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2268 /* only need to skip on ATPX */ 2269 if (amdgpu_device_supports_px(ddev)) 2270 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2271 /* we want direct complete for BOCO */ 2272 if (amdgpu_device_supports_boco(ddev)) 2273 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2274 DPM_FLAG_SMART_SUSPEND | 2275 DPM_FLAG_MAY_SKIP_RESUME); 2276 pm_runtime_use_autosuspend(ddev->dev); 2277 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2278 2279 pm_runtime_allow(ddev->dev); 2280 2281 pm_runtime_mark_last_busy(ddev->dev); 2282 pm_runtime_put_autosuspend(ddev->dev); 2283 2284 pci_wake_from_d3(pdev, TRUE); 2285 2286 /* 2287 * For runpm implemented via BACO, PMFW will handle the 2288 * timing for BACO in and out: 2289 * - put ASIC into BACO state only when both video and 2290 * audio functions are in D3 state. 2291 * - pull ASIC out of BACO state when either video or 2292 * audio function is in D0 state. 2293 * Also, at startup, PMFW assumes both functions are in 2294 * D0 state. 2295 * 2296 * So if snd driver was loaded prior to amdgpu driver 2297 * and audio function was put into D3 state, there will 2298 * be no PMFW-aware D-state transition(D0->D3) on runpm 2299 * suspend. Thus the BACO will be not correctly kicked in. 2300 * 2301 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2302 * into D0 state. Then there will be a PMFW-aware D-state 2303 * transition(D0->D3) on runpm suspend. 2304 */ 2305 if (amdgpu_device_supports_baco(ddev) && 2306 !(adev->flags & AMD_IS_APU) && 2307 (adev->asic_type >= CHIP_NAVI10)) 2308 amdgpu_get_secondary_funcs(adev); 2309 } 2310 2311 amdgpu_init_debug_options(adev); 2312 2313 return 0; 2314 2315 err_pci: 2316 pci_disable_device(pdev); 2317 return ret; 2318 } 2319 2320 static void 2321 amdgpu_pci_remove(struct pci_dev *pdev) 2322 { 2323 struct drm_device *dev = pci_get_drvdata(pdev); 2324 struct amdgpu_device *adev = drm_to_adev(dev); 2325 2326 amdgpu_xcp_dev_unplug(adev); 2327 drm_dev_unplug(dev); 2328 2329 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2330 pm_runtime_get_sync(dev->dev); 2331 pm_runtime_forbid(dev->dev); 2332 } 2333 2334 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 2) && 2335 !amdgpu_sriov_vf(adev)) { 2336 bool need_to_reset_gpu = false; 2337 2338 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2339 struct amdgpu_hive_info *hive; 2340 2341 hive = amdgpu_get_xgmi_hive(adev); 2342 if (hive->device_remove_count == 0) 2343 need_to_reset_gpu = true; 2344 hive->device_remove_count++; 2345 amdgpu_put_xgmi_hive(hive); 2346 } else { 2347 need_to_reset_gpu = true; 2348 } 2349 2350 /* Workaround for ASICs need to reset SMU. 2351 * Called only when the first device is removed. 2352 */ 2353 if (need_to_reset_gpu) { 2354 struct amdgpu_reset_context reset_context; 2355 2356 adev->shutdown = true; 2357 memset(&reset_context, 0, sizeof(reset_context)); 2358 reset_context.method = AMD_RESET_METHOD_NONE; 2359 reset_context.reset_req_dev = adev; 2360 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2361 set_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context.flags); 2362 amdgpu_device_gpu_recover(adev, NULL, &reset_context); 2363 } 2364 } 2365 2366 amdgpu_driver_unload_kms(dev); 2367 2368 /* 2369 * Flush any in flight DMA operations from device. 2370 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2371 * StatusTransactions Pending bit. 2372 */ 2373 pci_disable_device(pdev); 2374 pci_wait_for_pending_transaction(pdev); 2375 } 2376 2377 static void 2378 amdgpu_pci_shutdown(struct pci_dev *pdev) 2379 { 2380 struct drm_device *dev = pci_get_drvdata(pdev); 2381 struct amdgpu_device *adev = drm_to_adev(dev); 2382 2383 if (amdgpu_ras_intr_triggered()) 2384 return; 2385 2386 /* if we are running in a VM, make sure the device 2387 * torn down properly on reboot/shutdown. 2388 * unfortunately we can't detect certain 2389 * hypervisors so just do this all the time. 2390 */ 2391 if (!amdgpu_passthrough(adev)) 2392 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2393 amdgpu_device_ip_suspend(adev); 2394 adev->mp1_state = PP_MP1_STATE_NONE; 2395 } 2396 2397 /** 2398 * amdgpu_drv_delayed_reset_work_handler - work handler for reset 2399 * 2400 * @work: work_struct. 2401 */ 2402 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) 2403 { 2404 struct list_head device_list; 2405 struct amdgpu_device *adev; 2406 int i, r; 2407 struct amdgpu_reset_context reset_context; 2408 2409 memset(&reset_context, 0, sizeof(reset_context)); 2410 2411 mutex_lock(&mgpu_info.mutex); 2412 if (mgpu_info.pending_reset == true) { 2413 mutex_unlock(&mgpu_info.mutex); 2414 return; 2415 } 2416 mgpu_info.pending_reset = true; 2417 mutex_unlock(&mgpu_info.mutex); 2418 2419 /* Use a common context, just need to make sure full reset is done */ 2420 reset_context.method = AMD_RESET_METHOD_NONE; 2421 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2422 2423 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2424 adev = mgpu_info.gpu_ins[i].adev; 2425 reset_context.reset_req_dev = adev; 2426 r = amdgpu_device_pre_asic_reset(adev, &reset_context); 2427 if (r) { 2428 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", 2429 r, adev_to_drm(adev)->unique); 2430 } 2431 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) 2432 r = -EALREADY; 2433 } 2434 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2435 adev = mgpu_info.gpu_ins[i].adev; 2436 flush_work(&adev->xgmi_reset_work); 2437 adev->gmc.xgmi.pending_reset = false; 2438 } 2439 2440 /* reset function will rebuild the xgmi hive info , clear it now */ 2441 for (i = 0; i < mgpu_info.num_dgpu; i++) 2442 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); 2443 2444 INIT_LIST_HEAD(&device_list); 2445 2446 for (i = 0; i < mgpu_info.num_dgpu; i++) 2447 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); 2448 2449 /* unregister the GPU first, reset function will add them back */ 2450 list_for_each_entry(adev, &device_list, reset_list) 2451 amdgpu_unregister_gpu_instance(adev); 2452 2453 /* Use a common context, just need to make sure full reset is done */ 2454 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); 2455 r = amdgpu_do_asic_reset(&device_list, &reset_context); 2456 2457 if (r) { 2458 DRM_ERROR("reinit gpus failure"); 2459 return; 2460 } 2461 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2462 adev = mgpu_info.gpu_ins[i].adev; 2463 if (!adev->kfd.init_complete) 2464 amdgpu_amdkfd_device_init(adev); 2465 amdgpu_ttm_set_buffer_funcs_status(adev, true); 2466 } 2467 } 2468 2469 static int amdgpu_pmops_prepare(struct device *dev) 2470 { 2471 struct drm_device *drm_dev = dev_get_drvdata(dev); 2472 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2473 2474 /* Return a positive number here so 2475 * DPM_FLAG_SMART_SUSPEND works properly 2476 */ 2477 if (amdgpu_device_supports_boco(drm_dev) && 2478 pm_runtime_suspended(dev)) 2479 return 1; 2480 2481 /* if we will not support s3 or s2i for the device 2482 * then skip suspend 2483 */ 2484 if (!amdgpu_acpi_is_s0ix_active(adev) && 2485 !amdgpu_acpi_is_s3_active(adev)) 2486 return 1; 2487 2488 return amdgpu_device_prepare(drm_dev); 2489 } 2490 2491 static void amdgpu_pmops_complete(struct device *dev) 2492 { 2493 /* nothing to do */ 2494 } 2495 2496 static int amdgpu_pmops_suspend(struct device *dev) 2497 { 2498 struct drm_device *drm_dev = dev_get_drvdata(dev); 2499 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2500 2501 if (amdgpu_acpi_is_s0ix_active(adev)) 2502 adev->in_s0ix = true; 2503 else if (amdgpu_acpi_is_s3_active(adev)) 2504 adev->in_s3 = true; 2505 if (!adev->in_s0ix && !adev->in_s3) 2506 return 0; 2507 return amdgpu_device_suspend(drm_dev, true); 2508 } 2509 2510 static int amdgpu_pmops_suspend_noirq(struct device *dev) 2511 { 2512 struct drm_device *drm_dev = dev_get_drvdata(dev); 2513 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2514 2515 if (amdgpu_acpi_should_gpu_reset(adev)) 2516 return amdgpu_asic_reset(adev); 2517 2518 return 0; 2519 } 2520 2521 static int amdgpu_pmops_resume(struct device *dev) 2522 { 2523 struct drm_device *drm_dev = dev_get_drvdata(dev); 2524 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2525 int r; 2526 2527 if (!adev->in_s0ix && !adev->in_s3) 2528 return 0; 2529 2530 /* Avoids registers access if device is physically gone */ 2531 if (!pci_device_is_present(adev->pdev)) 2532 adev->no_hw_access = true; 2533 2534 r = amdgpu_device_resume(drm_dev, true); 2535 if (amdgpu_acpi_is_s0ix_active(adev)) 2536 adev->in_s0ix = false; 2537 else 2538 adev->in_s3 = false; 2539 return r; 2540 } 2541 2542 static int amdgpu_pmops_freeze(struct device *dev) 2543 { 2544 struct drm_device *drm_dev = dev_get_drvdata(dev); 2545 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2546 int r; 2547 2548 adev->in_s4 = true; 2549 r = amdgpu_device_suspend(drm_dev, true); 2550 adev->in_s4 = false; 2551 if (r) 2552 return r; 2553 2554 if (amdgpu_acpi_should_gpu_reset(adev)) 2555 return amdgpu_asic_reset(adev); 2556 return 0; 2557 } 2558 2559 static int amdgpu_pmops_thaw(struct device *dev) 2560 { 2561 struct drm_device *drm_dev = dev_get_drvdata(dev); 2562 2563 return amdgpu_device_resume(drm_dev, true); 2564 } 2565 2566 static int amdgpu_pmops_poweroff(struct device *dev) 2567 { 2568 struct drm_device *drm_dev = dev_get_drvdata(dev); 2569 2570 return amdgpu_device_suspend(drm_dev, true); 2571 } 2572 2573 static int amdgpu_pmops_restore(struct device *dev) 2574 { 2575 struct drm_device *drm_dev = dev_get_drvdata(dev); 2576 2577 return amdgpu_device_resume(drm_dev, true); 2578 } 2579 2580 static int amdgpu_runtime_idle_check_display(struct device *dev) 2581 { 2582 struct pci_dev *pdev = to_pci_dev(dev); 2583 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2584 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2585 2586 if (adev->mode_info.num_crtc) { 2587 struct drm_connector *list_connector; 2588 struct drm_connector_list_iter iter; 2589 int ret = 0; 2590 2591 if (amdgpu_runtime_pm != -2) { 2592 /* XXX: Return busy if any displays are connected to avoid 2593 * possible display wakeups after runtime resume due to 2594 * hotplug events in case any displays were connected while 2595 * the GPU was in suspend. Remove this once that is fixed. 2596 */ 2597 mutex_lock(&drm_dev->mode_config.mutex); 2598 drm_connector_list_iter_begin(drm_dev, &iter); 2599 drm_for_each_connector_iter(list_connector, &iter) { 2600 if (list_connector->status == connector_status_connected) { 2601 ret = -EBUSY; 2602 break; 2603 } 2604 } 2605 drm_connector_list_iter_end(&iter); 2606 mutex_unlock(&drm_dev->mode_config.mutex); 2607 2608 if (ret) 2609 return ret; 2610 } 2611 2612 if (adev->dc_enabled) { 2613 struct drm_crtc *crtc; 2614 2615 drm_for_each_crtc(crtc, drm_dev) { 2616 drm_modeset_lock(&crtc->mutex, NULL); 2617 if (crtc->state->active) 2618 ret = -EBUSY; 2619 drm_modeset_unlock(&crtc->mutex); 2620 if (ret < 0) 2621 break; 2622 } 2623 } else { 2624 mutex_lock(&drm_dev->mode_config.mutex); 2625 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2626 2627 drm_connector_list_iter_begin(drm_dev, &iter); 2628 drm_for_each_connector_iter(list_connector, &iter) { 2629 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2630 ret = -EBUSY; 2631 break; 2632 } 2633 } 2634 2635 drm_connector_list_iter_end(&iter); 2636 2637 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2638 mutex_unlock(&drm_dev->mode_config.mutex); 2639 } 2640 if (ret) 2641 return ret; 2642 } 2643 2644 return 0; 2645 } 2646 2647 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2648 { 2649 struct pci_dev *pdev = to_pci_dev(dev); 2650 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2651 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2652 int ret, i; 2653 2654 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2655 pm_runtime_forbid(dev); 2656 return -EBUSY; 2657 } 2658 2659 ret = amdgpu_runtime_idle_check_display(dev); 2660 if (ret) 2661 return ret; 2662 2663 /* wait for all rings to drain before suspending */ 2664 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2665 struct amdgpu_ring *ring = adev->rings[i]; 2666 2667 if (ring && ring->sched.ready) { 2668 ret = amdgpu_fence_wait_empty(ring); 2669 if (ret) 2670 return -EBUSY; 2671 } 2672 } 2673 2674 adev->in_runpm = true; 2675 if (amdgpu_device_supports_px(drm_dev)) 2676 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2677 2678 /* 2679 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2680 * proper cleanups and put itself into a state ready for PNP. That 2681 * can address some random resuming failure observed on BOCO capable 2682 * platforms. 2683 * TODO: this may be also needed for PX capable platform. 2684 */ 2685 if (amdgpu_device_supports_boco(drm_dev)) 2686 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2687 2688 ret = amdgpu_device_prepare(drm_dev); 2689 if (ret) 2690 return ret; 2691 ret = amdgpu_device_suspend(drm_dev, false); 2692 if (ret) { 2693 adev->in_runpm = false; 2694 if (amdgpu_device_supports_boco(drm_dev)) 2695 adev->mp1_state = PP_MP1_STATE_NONE; 2696 return ret; 2697 } 2698 2699 if (amdgpu_device_supports_boco(drm_dev)) 2700 adev->mp1_state = PP_MP1_STATE_NONE; 2701 2702 if (amdgpu_device_supports_px(drm_dev)) { 2703 /* Only need to handle PCI state in the driver for ATPX 2704 * PCI core handles it for _PR3. 2705 */ 2706 amdgpu_device_cache_pci_state(pdev); 2707 pci_disable_device(pdev); 2708 pci_ignore_hotplug(pdev); 2709 pci_set_power_state(pdev, PCI_D3cold); 2710 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2711 } else if (amdgpu_device_supports_boco(drm_dev)) { 2712 /* nothing to do */ 2713 } else if (amdgpu_device_supports_baco(drm_dev)) { 2714 amdgpu_device_baco_enter(drm_dev); 2715 } 2716 2717 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n"); 2718 2719 return 0; 2720 } 2721 2722 static int amdgpu_pmops_runtime_resume(struct device *dev) 2723 { 2724 struct pci_dev *pdev = to_pci_dev(dev); 2725 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2726 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2727 int ret; 2728 2729 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) 2730 return -EINVAL; 2731 2732 /* Avoids registers access if device is physically gone */ 2733 if (!pci_device_is_present(adev->pdev)) 2734 adev->no_hw_access = true; 2735 2736 if (amdgpu_device_supports_px(drm_dev)) { 2737 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2738 2739 /* Only need to handle PCI state in the driver for ATPX 2740 * PCI core handles it for _PR3. 2741 */ 2742 pci_set_power_state(pdev, PCI_D0); 2743 amdgpu_device_load_pci_state(pdev); 2744 ret = pci_enable_device(pdev); 2745 if (ret) 2746 return ret; 2747 pci_set_master(pdev); 2748 } else if (amdgpu_device_supports_boco(drm_dev)) { 2749 /* Only need to handle PCI state in the driver for ATPX 2750 * PCI core handles it for _PR3. 2751 */ 2752 pci_set_master(pdev); 2753 } else if (amdgpu_device_supports_baco(drm_dev)) { 2754 amdgpu_device_baco_exit(drm_dev); 2755 } 2756 ret = amdgpu_device_resume(drm_dev, false); 2757 if (ret) { 2758 if (amdgpu_device_supports_px(drm_dev)) 2759 pci_disable_device(pdev); 2760 return ret; 2761 } 2762 2763 if (amdgpu_device_supports_px(drm_dev)) 2764 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2765 adev->in_runpm = false; 2766 return 0; 2767 } 2768 2769 static int amdgpu_pmops_runtime_idle(struct device *dev) 2770 { 2771 struct drm_device *drm_dev = dev_get_drvdata(dev); 2772 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2773 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 2774 int ret = 1; 2775 2776 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2777 pm_runtime_forbid(dev); 2778 return -EBUSY; 2779 } 2780 2781 ret = amdgpu_runtime_idle_check_display(dev); 2782 2783 pm_runtime_mark_last_busy(dev); 2784 pm_runtime_autosuspend(dev); 2785 return ret; 2786 } 2787 2788 long amdgpu_drm_ioctl(struct file *filp, 2789 unsigned int cmd, unsigned long arg) 2790 { 2791 struct drm_file *file_priv = filp->private_data; 2792 struct drm_device *dev; 2793 long ret; 2794 2795 dev = file_priv->minor->dev; 2796 ret = pm_runtime_get_sync(dev->dev); 2797 if (ret < 0) 2798 goto out; 2799 2800 ret = drm_ioctl(filp, cmd, arg); 2801 2802 pm_runtime_mark_last_busy(dev->dev); 2803 out: 2804 pm_runtime_put_autosuspend(dev->dev); 2805 return ret; 2806 } 2807 2808 static const struct dev_pm_ops amdgpu_pm_ops = { 2809 .prepare = amdgpu_pmops_prepare, 2810 .complete = amdgpu_pmops_complete, 2811 .suspend = amdgpu_pmops_suspend, 2812 .suspend_noirq = amdgpu_pmops_suspend_noirq, 2813 .resume = amdgpu_pmops_resume, 2814 .freeze = amdgpu_pmops_freeze, 2815 .thaw = amdgpu_pmops_thaw, 2816 .poweroff = amdgpu_pmops_poweroff, 2817 .restore = amdgpu_pmops_restore, 2818 .runtime_suspend = amdgpu_pmops_runtime_suspend, 2819 .runtime_resume = amdgpu_pmops_runtime_resume, 2820 .runtime_idle = amdgpu_pmops_runtime_idle, 2821 }; 2822 2823 static int amdgpu_flush(struct file *f, fl_owner_t id) 2824 { 2825 struct drm_file *file_priv = f->private_data; 2826 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2827 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2828 2829 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 2830 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 2831 2832 return timeout >= 0 ? 0 : timeout; 2833 } 2834 2835 static const struct file_operations amdgpu_driver_kms_fops = { 2836 .owner = THIS_MODULE, 2837 .open = drm_open, 2838 .flush = amdgpu_flush, 2839 .release = drm_release, 2840 .unlocked_ioctl = amdgpu_drm_ioctl, 2841 .mmap = drm_gem_mmap, 2842 .poll = drm_poll, 2843 .read = drm_read, 2844 #ifdef CONFIG_COMPAT 2845 .compat_ioctl = amdgpu_kms_compat_ioctl, 2846 #endif 2847 #ifdef CONFIG_PROC_FS 2848 .show_fdinfo = drm_show_fdinfo, 2849 #endif 2850 }; 2851 2852 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 2853 { 2854 struct drm_file *file; 2855 2856 if (!filp) 2857 return -EINVAL; 2858 2859 if (filp->f_op != &amdgpu_driver_kms_fops) 2860 return -EINVAL; 2861 2862 file = filp->private_data; 2863 *fpriv = file->driver_priv; 2864 return 0; 2865 } 2866 2867 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 2868 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2869 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2870 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2871 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 2872 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2873 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2874 /* KMS */ 2875 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2876 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2877 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2878 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2879 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2880 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2881 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2882 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2883 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2884 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2885 }; 2886 2887 static const struct drm_driver amdgpu_kms_driver = { 2888 .driver_features = 2889 DRIVER_ATOMIC | 2890 DRIVER_GEM | 2891 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 2892 DRIVER_SYNCOBJ_TIMELINE, 2893 .open = amdgpu_driver_open_kms, 2894 .postclose = amdgpu_driver_postclose_kms, 2895 .lastclose = amdgpu_driver_lastclose_kms, 2896 .ioctls = amdgpu_ioctls_kms, 2897 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2898 .dumb_create = amdgpu_mode_dumb_create, 2899 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2900 .fops = &amdgpu_driver_kms_fops, 2901 .release = &amdgpu_driver_release_kms, 2902 #ifdef CONFIG_PROC_FS 2903 .show_fdinfo = amdgpu_show_fdinfo, 2904 #endif 2905 2906 .gem_prime_import = amdgpu_gem_prime_import, 2907 2908 .name = DRIVER_NAME, 2909 .desc = DRIVER_DESC, 2910 .date = DRIVER_DATE, 2911 .major = KMS_DRIVER_MAJOR, 2912 .minor = KMS_DRIVER_MINOR, 2913 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2914 }; 2915 2916 const struct drm_driver amdgpu_partition_driver = { 2917 .driver_features = 2918 DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ | 2919 DRIVER_SYNCOBJ_TIMELINE, 2920 .open = amdgpu_driver_open_kms, 2921 .postclose = amdgpu_driver_postclose_kms, 2922 .lastclose = amdgpu_driver_lastclose_kms, 2923 .ioctls = amdgpu_ioctls_kms, 2924 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2925 .dumb_create = amdgpu_mode_dumb_create, 2926 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2927 .fops = &amdgpu_driver_kms_fops, 2928 .release = &amdgpu_driver_release_kms, 2929 2930 .gem_prime_import = amdgpu_gem_prime_import, 2931 2932 .name = DRIVER_NAME, 2933 .desc = DRIVER_DESC, 2934 .date = DRIVER_DATE, 2935 .major = KMS_DRIVER_MAJOR, 2936 .minor = KMS_DRIVER_MINOR, 2937 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2938 }; 2939 2940 static struct pci_error_handlers amdgpu_pci_err_handler = { 2941 .error_detected = amdgpu_pci_error_detected, 2942 .mmio_enabled = amdgpu_pci_mmio_enabled, 2943 .slot_reset = amdgpu_pci_slot_reset, 2944 .resume = amdgpu_pci_resume, 2945 }; 2946 2947 static const struct attribute_group *amdgpu_sysfs_groups[] = { 2948 &amdgpu_vram_mgr_attr_group, 2949 &amdgpu_gtt_mgr_attr_group, 2950 &amdgpu_flash_attr_group, 2951 NULL, 2952 }; 2953 2954 static struct pci_driver amdgpu_kms_pci_driver = { 2955 .name = DRIVER_NAME, 2956 .id_table = pciidlist, 2957 .probe = amdgpu_pci_probe, 2958 .remove = amdgpu_pci_remove, 2959 .shutdown = amdgpu_pci_shutdown, 2960 .driver.pm = &amdgpu_pm_ops, 2961 .err_handler = &amdgpu_pci_err_handler, 2962 .dev_groups = amdgpu_sysfs_groups, 2963 }; 2964 2965 static int __init amdgpu_init(void) 2966 { 2967 int r; 2968 2969 if (drm_firmware_drivers_only()) 2970 return -EINVAL; 2971 2972 r = amdgpu_sync_init(); 2973 if (r) 2974 goto error_sync; 2975 2976 r = amdgpu_fence_slab_init(); 2977 if (r) 2978 goto error_fence; 2979 2980 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 2981 amdgpu_register_atpx_handler(); 2982 amdgpu_acpi_detect(); 2983 2984 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 2985 amdgpu_amdkfd_init(); 2986 2987 /* let modprobe override vga console setting */ 2988 return pci_register_driver(&amdgpu_kms_pci_driver); 2989 2990 error_fence: 2991 amdgpu_sync_fini(); 2992 2993 error_sync: 2994 return r; 2995 } 2996 2997 static void __exit amdgpu_exit(void) 2998 { 2999 amdgpu_amdkfd_fini(); 3000 pci_unregister_driver(&amdgpu_kms_pci_driver); 3001 amdgpu_unregister_atpx_handler(); 3002 amdgpu_acpi_release(); 3003 amdgpu_sync_fini(); 3004 amdgpu_fence_slab_fini(); 3005 mmu_notifier_synchronize(); 3006 amdgpu_xcp_drv_release(); 3007 } 3008 3009 module_init(amdgpu_init); 3010 module_exit(amdgpu_exit); 3011 3012 MODULE_AUTHOR(DRIVER_AUTHOR); 3013 MODULE_DESCRIPTION(DRIVER_DESC); 3014 MODULE_LICENSE("GPL and additional rights"); 3015