1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_drv.h> 27 #include <drm/drm_fbdev_generic.h> 28 #include <drm/drm_gem.h> 29 #include <drm/drm_managed.h> 30 #include <drm/drm_pciids.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/drm_vblank.h> 33 34 #include <linux/cc_platform.h> 35 #include <linux/dynamic_debug.h> 36 #include <linux/module.h> 37 #include <linux/mmu_notifier.h> 38 #include <linux/pm_runtime.h> 39 #include <linux/suspend.h> 40 #include <linux/vga_switcheroo.h> 41 42 #include "amdgpu.h" 43 #include "amdgpu_amdkfd.h" 44 #include "amdgpu_dma_buf.h" 45 #include "amdgpu_drv.h" 46 #include "amdgpu_fdinfo.h" 47 #include "amdgpu_irq.h" 48 #include "amdgpu_psp.h" 49 #include "amdgpu_ras.h" 50 #include "amdgpu_reset.h" 51 #include "amdgpu_sched.h" 52 #include "amdgpu_xgmi.h" 53 #include "../amdxcp/amdgpu_xcp_drv.h" 54 55 /* 56 * KMS wrapper. 57 * - 3.0.0 - initial driver 58 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 59 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 60 * at the end of IBs. 61 * - 3.3.0 - Add VM support for UVD on supported hardware. 62 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 63 * - 3.5.0 - Add support for new UVD_NO_OP register. 64 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 65 * - 3.7.0 - Add support for VCE clock list packet 66 * - 3.8.0 - Add support raster config init in the kernel 67 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 68 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 69 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 70 * - 3.12.0 - Add query for double offchip LDS buffers 71 * - 3.13.0 - Add PRT support 72 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 73 * - 3.15.0 - Export more gpu info for gfx9 74 * - 3.16.0 - Add reserved vmid support 75 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 76 * - 3.18.0 - Export gpu always on cu bitmap 77 * - 3.19.0 - Add support for UVD MJPEG decode 78 * - 3.20.0 - Add support for local BOs 79 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 80 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 81 * - 3.23.0 - Add query for VRAM lost counter 82 * - 3.24.0 - Add high priority compute support for gfx9 83 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 84 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 85 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation. 86 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 87 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 88 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 89 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 90 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 91 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 92 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 93 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 94 * - 3.36.0 - Allow reading more status registers on si/cik 95 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 96 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 97 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 98 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 99 * - 3.41.0 - Add video codec query 100 * - 3.42.0 - Add 16bpc fixed point display support 101 * - 3.43.0 - Add device hot plug/unplug support 102 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 103 * - 3.45.0 - Add context ioctl stable pstate interface 104 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm 105 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags 106 * - 3.48.0 - Add IP discovery version info to HW INFO 107 * - 3.49.0 - Add gang submit into CS IOCTL 108 * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock 109 * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock 110 * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl 111 * 3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields: 112 * tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size, 113 * gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi 114 * 3.53.0 - Support for GFX11 CP GFX shadowing 115 * 3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support 116 * - 3.55.0 - Add AMDGPU_INFO_GPUVM_FAULT query 117 * - 3.56.0 - Update IB start address and size alignment for decode and encode 118 * - 3.57.0 - Compute tunneling on GFX10+ 119 */ 120 #define KMS_DRIVER_MAJOR 3 121 #define KMS_DRIVER_MINOR 57 122 #define KMS_DRIVER_PATCHLEVEL 0 123 124 /* 125 * amdgpu.debug module options. Are all disabled by default 126 */ 127 enum AMDGPU_DEBUG_MASK { 128 AMDGPU_DEBUG_VM = BIT(0), 129 AMDGPU_DEBUG_LARGEBAR = BIT(1), 130 AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY = BIT(2), 131 AMDGPU_DEBUG_USE_VRAM_FW_BUF = BIT(3), 132 }; 133 134 unsigned int amdgpu_vram_limit = UINT_MAX; 135 int amdgpu_vis_vram_limit; 136 int amdgpu_gart_size = -1; /* auto */ 137 int amdgpu_gtt_size = -1; /* auto */ 138 int amdgpu_moverate = -1; /* auto */ 139 int amdgpu_audio = -1; 140 int amdgpu_disp_priority; 141 int amdgpu_hw_i2c; 142 int amdgpu_pcie_gen2 = -1; 143 int amdgpu_msi = -1; 144 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 145 int amdgpu_dpm = -1; 146 int amdgpu_fw_load_type = -1; 147 int amdgpu_aspm = -1; 148 int amdgpu_runtime_pm = -1; 149 uint amdgpu_ip_block_mask = 0xffffffff; 150 int amdgpu_bapm = -1; 151 int amdgpu_deep_color; 152 int amdgpu_vm_size = -1; 153 int amdgpu_vm_fragment_size = -1; 154 int amdgpu_vm_block_size = -1; 155 int amdgpu_vm_fault_stop; 156 int amdgpu_vm_update_mode = -1; 157 int amdgpu_exp_hw_support; 158 int amdgpu_dc = -1; 159 int amdgpu_sched_jobs = 32; 160 int amdgpu_sched_hw_submission = 2; 161 uint amdgpu_pcie_gen_cap; 162 uint amdgpu_pcie_lane_cap; 163 u64 amdgpu_cg_mask = 0xffffffffffffffff; 164 uint amdgpu_pg_mask = 0xffffffff; 165 uint amdgpu_sdma_phase_quantum = 32; 166 char *amdgpu_disable_cu; 167 char *amdgpu_virtual_display; 168 bool enforce_isolation; 169 /* 170 * OverDrive(bit 14) disabled by default 171 * GFX DCS(bit 19) disabled by default 172 */ 173 uint amdgpu_pp_feature_mask = 0xfff7bfff; 174 uint amdgpu_force_long_training; 175 int amdgpu_lbpw = -1; 176 int amdgpu_compute_multipipe = -1; 177 int amdgpu_gpu_recovery = -1; /* auto */ 178 int amdgpu_emu_mode; 179 uint amdgpu_smu_memory_pool_size; 180 int amdgpu_smu_pptable_id = -1; 181 /* 182 * FBC (bit 0) disabled by default 183 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 184 * - With this, for multiple monitors in sync(e.g. with the same model), 185 * mclk switching will be allowed. And the mclk will be not foced to the 186 * highest. That helps saving some idle power. 187 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 188 * PSR (bit 3) disabled by default 189 * EDP NO POWER SEQUENCING (bit 4) disabled by default 190 */ 191 uint amdgpu_dc_feature_mask = 2; 192 uint amdgpu_dc_debug_mask; 193 uint amdgpu_dc_visual_confirm; 194 int amdgpu_async_gfx_ring = 1; 195 int amdgpu_mcbp = -1; 196 int amdgpu_discovery = -1; 197 int amdgpu_mes; 198 int amdgpu_mes_log_enable = 0; 199 int amdgpu_mes_kiq; 200 int amdgpu_uni_mes; 201 int amdgpu_noretry = -1; 202 int amdgpu_force_asic_type = -1; 203 int amdgpu_tmz = -1; /* auto */ 204 uint amdgpu_freesync_vid_mode; 205 int amdgpu_reset_method = -1; /* auto */ 206 int amdgpu_num_kcq = -1; 207 int amdgpu_smartshift_bias; 208 int amdgpu_use_xgmi_p2p = 1; 209 int amdgpu_vcnfw_log; 210 int amdgpu_sg_display = -1; /* auto */ 211 int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE; 212 int amdgpu_umsch_mm; 213 int amdgpu_seamless = -1; /* auto */ 214 uint amdgpu_debug_mask; 215 int amdgpu_agp = -1; /* auto */ 216 int amdgpu_wbrf = -1; 217 int amdgpu_damage_clips = -1; /* auto */ 218 219 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 220 221 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 222 "DRM_UT_CORE", 223 "DRM_UT_DRIVER", 224 "DRM_UT_KMS", 225 "DRM_UT_PRIME", 226 "DRM_UT_ATOMIC", 227 "DRM_UT_VBL", 228 "DRM_UT_STATE", 229 "DRM_UT_LEASE", 230 "DRM_UT_DP", 231 "DRM_UT_DRMRES"); 232 233 struct amdgpu_mgpu_info mgpu_info = { 234 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 235 .delayed_reset_work = __DELAYED_WORK_INITIALIZER( 236 mgpu_info.delayed_reset_work, 237 amdgpu_drv_delayed_reset_work_handler, 0), 238 }; 239 int amdgpu_ras_enable = -1; 240 uint amdgpu_ras_mask = 0xffffffff; 241 int amdgpu_bad_page_threshold = -1; 242 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 243 .timeout_fatal_disable = false, 244 .period = 0x0, /* default to 0x0 (timeout disable) */ 245 }; 246 247 /** 248 * DOC: vramlimit (int) 249 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 250 */ 251 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 252 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 253 254 /** 255 * DOC: vis_vramlimit (int) 256 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 257 */ 258 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 259 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 260 261 /** 262 * DOC: gartsize (uint) 263 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing. 264 * The default is -1 (The size depends on asic). 265 */ 266 MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)"); 267 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 268 269 /** 270 * DOC: gttsize (int) 271 * Restrict the size of GTT domain (for userspace use) in MiB for testing. 272 * The default is -1 (Use 1/2 RAM, minimum value is 3GB). 273 */ 274 MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)"); 275 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 276 277 /** 278 * DOC: moverate (int) 279 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 280 */ 281 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 282 module_param_named(moverate, amdgpu_moverate, int, 0600); 283 284 /** 285 * DOC: audio (int) 286 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 287 */ 288 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 289 module_param_named(audio, amdgpu_audio, int, 0444); 290 291 /** 292 * DOC: disp_priority (int) 293 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 294 */ 295 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 296 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 297 298 /** 299 * DOC: hw_i2c (int) 300 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 301 */ 302 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 303 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 304 305 /** 306 * DOC: pcie_gen2 (int) 307 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 308 */ 309 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 310 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 311 312 /** 313 * DOC: msi (int) 314 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 315 */ 316 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 317 module_param_named(msi, amdgpu_msi, int, 0444); 318 319 /** 320 * DOC: lockup_timeout (string) 321 * Set GPU scheduler timeout value in ms. 322 * 323 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 324 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 325 * to the default timeout. 326 * 327 * - With one value specified, the setting will apply to all non-compute jobs. 328 * - With multiple values specified, the first one will be for GFX. 329 * The second one is for Compute. The third and fourth ones are 330 * for SDMA and Video. 331 * 332 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 333 * jobs is 10000. The timeout for compute is 60000. 334 */ 335 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 336 "for passthrough or sriov, 10000 for all jobs. 0: keep default value. negative: infinity timeout), format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 337 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 338 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 339 340 /** 341 * DOC: dpm (int) 342 * Override for dynamic power management setting 343 * (0 = disable, 1 = enable) 344 * The default is -1 (auto). 345 */ 346 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 347 module_param_named(dpm, amdgpu_dpm, int, 0444); 348 349 /** 350 * DOC: fw_load_type (int) 351 * Set different firmware loading type for debugging, if supported. 352 * Set to 0 to force direct loading if supported by the ASIC. Set 353 * to -1 to select the default loading mode for the ASIC, as defined 354 * by the driver. The default is -1 (auto). 355 */ 356 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); 357 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 358 359 /** 360 * DOC: aspm (int) 361 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 362 */ 363 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 364 module_param_named(aspm, amdgpu_aspm, int, 0444); 365 366 /** 367 * DOC: runpm (int) 368 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 369 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 370 * Setting the value to 0 disables this functionality. 371 * Setting the value to -2 is auto enabled with power down when displays are attached. 372 */ 373 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto, -2 = auto with displays)"); 374 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 375 376 /** 377 * DOC: ip_block_mask (uint) 378 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 379 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 380 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 381 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 382 */ 383 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 384 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 385 386 /** 387 * DOC: bapm (int) 388 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 389 * The default -1 (auto, enabled) 390 */ 391 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 392 module_param_named(bapm, amdgpu_bapm, int, 0444); 393 394 /** 395 * DOC: deep_color (int) 396 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 397 */ 398 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 399 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 400 401 /** 402 * DOC: vm_size (int) 403 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 404 */ 405 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 406 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 407 408 /** 409 * DOC: vm_fragment_size (int) 410 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 411 */ 412 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 413 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 414 415 /** 416 * DOC: vm_block_size (int) 417 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 418 */ 419 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 420 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 421 422 /** 423 * DOC: vm_fault_stop (int) 424 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 425 */ 426 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 427 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 428 429 /** 430 * DOC: vm_update_mode (int) 431 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 432 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 433 */ 434 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 435 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 436 437 /** 438 * DOC: exp_hw_support (int) 439 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 440 */ 441 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 442 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 443 444 /** 445 * DOC: dc (int) 446 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 447 */ 448 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 449 module_param_named(dc, amdgpu_dc, int, 0444); 450 451 /** 452 * DOC: sched_jobs (int) 453 * Override the max number of jobs supported in the sw queue. The default is 32. 454 */ 455 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 456 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 457 458 /** 459 * DOC: sched_hw_submission (int) 460 * Override the max number of HW submissions. The default is 2. 461 */ 462 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 463 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 464 465 /** 466 * DOC: ppfeaturemask (hexint) 467 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 468 * The default is the current set of stable power features. 469 */ 470 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 471 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 472 473 /** 474 * DOC: forcelongtraining (uint) 475 * Force long memory training in resume. 476 * The default is zero, indicates short training in resume. 477 */ 478 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 479 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 480 481 /** 482 * DOC: pcie_gen_cap (uint) 483 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 484 * The default is 0 (automatic for each asic). 485 */ 486 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 487 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 488 489 /** 490 * DOC: pcie_lane_cap (uint) 491 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 492 * The default is 0 (automatic for each asic). 493 */ 494 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 495 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 496 497 /** 498 * DOC: cg_mask (ullong) 499 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 500 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 501 */ 502 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 503 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 504 505 /** 506 * DOC: pg_mask (uint) 507 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 508 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 509 */ 510 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 511 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 512 513 /** 514 * DOC: sdma_phase_quantum (uint) 515 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 516 */ 517 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 518 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 519 520 /** 521 * DOC: disable_cu (charp) 522 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 523 */ 524 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 525 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 526 527 /** 528 * DOC: virtual_display (charp) 529 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 530 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 531 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 532 * device at 26:00.0. The default is NULL. 533 */ 534 MODULE_PARM_DESC(virtual_display, 535 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 536 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 537 538 /** 539 * DOC: lbpw (int) 540 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 541 */ 542 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 543 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 544 545 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 546 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 547 548 /** 549 * DOC: gpu_recovery (int) 550 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 551 */ 552 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 553 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 554 555 /** 556 * DOC: emu_mode (int) 557 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 558 */ 559 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 560 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 561 562 /** 563 * DOC: ras_enable (int) 564 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 565 */ 566 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 567 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 568 569 /** 570 * DOC: ras_mask (uint) 571 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 572 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 573 */ 574 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 575 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 576 577 /** 578 * DOC: timeout_fatal_disable (bool) 579 * Disable Watchdog timeout fatal error event 580 */ 581 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 582 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 583 584 /** 585 * DOC: timeout_period (uint) 586 * Modify the watchdog timeout max_cycles as (1 << period) 587 */ 588 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 589 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 590 591 /** 592 * DOC: si_support (int) 593 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 594 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 595 * otherwise using amdgpu driver. 596 */ 597 #ifdef CONFIG_DRM_AMDGPU_SI 598 599 #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) 600 int amdgpu_si_support; 601 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 602 #else 603 int amdgpu_si_support = 1; 604 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 605 #endif 606 607 module_param_named(si_support, amdgpu_si_support, int, 0444); 608 #endif 609 610 /** 611 * DOC: cik_support (int) 612 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 613 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 614 * otherwise using amdgpu driver. 615 */ 616 #ifdef CONFIG_DRM_AMDGPU_CIK 617 618 #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) 619 int amdgpu_cik_support; 620 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 621 #else 622 int amdgpu_cik_support = 1; 623 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 624 #endif 625 626 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 627 #endif 628 629 /** 630 * DOC: smu_memory_pool_size (uint) 631 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 632 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 633 */ 634 MODULE_PARM_DESC(smu_memory_pool_size, 635 "reserve gtt for smu debug usage, 0 = disable,0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 636 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 637 638 /** 639 * DOC: async_gfx_ring (int) 640 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 641 */ 642 MODULE_PARM_DESC(async_gfx_ring, 643 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 644 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 645 646 /** 647 * DOC: mcbp (int) 648 * It is used to enable mid command buffer preemption. (0 = disabled, 1 = enabled, -1 auto (default)) 649 */ 650 MODULE_PARM_DESC(mcbp, 651 "Enable Mid-command buffer preemption (0 = disabled, 1 = enabled), -1 = auto (default)"); 652 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 653 654 /** 655 * DOC: discovery (int) 656 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 657 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 658 */ 659 MODULE_PARM_DESC(discovery, 660 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 661 module_param_named(discovery, amdgpu_discovery, int, 0444); 662 663 /** 664 * DOC: mes (int) 665 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 666 * (0 = disabled (default), 1 = enabled) 667 */ 668 MODULE_PARM_DESC(mes, 669 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 670 module_param_named(mes, amdgpu_mes, int, 0444); 671 672 /** 673 * DOC: mes_log_enable (int) 674 * Enable Micro Engine Scheduler log. This is used to enable/disable MES internal log. 675 * (0 = disabled (default), 1 = enabled) 676 */ 677 MODULE_PARM_DESC(mes_log_enable, 678 "Enable Micro Engine Scheduler log (0 = disabled (default), 1 = enabled)"); 679 module_param_named(mes_log_enable, amdgpu_mes_log_enable, int, 0444); 680 681 /** 682 * DOC: mes_kiq (int) 683 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq. 684 * (0 = disabled (default), 1 = enabled) 685 */ 686 MODULE_PARM_DESC(mes_kiq, 687 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)"); 688 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444); 689 690 /** 691 * DOC: uni_mes (int) 692 * Enable Unified Micro Engine Scheduler. This is a new engine pipe for unified scheduler. 693 * (0 = disabled (default), 1 = enabled) 694 */ 695 MODULE_PARM_DESC(uni_mes, 696 "Enable Unified Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 697 module_param_named(uni_mes, amdgpu_uni_mes, int, 0444); 698 699 /** 700 * DOC: noretry (int) 701 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 702 * do not support per-process XNACK this also disables retry page faults. 703 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 704 */ 705 MODULE_PARM_DESC(noretry, 706 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 707 module_param_named(noretry, amdgpu_noretry, int, 0644); 708 709 /** 710 * DOC: force_asic_type (int) 711 * A non negative value used to specify the asic type for all supported GPUs. 712 */ 713 MODULE_PARM_DESC(force_asic_type, 714 "A non negative value used to specify the asic type for all supported GPUs"); 715 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 716 717 /** 718 * DOC: use_xgmi_p2p (int) 719 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 720 */ 721 MODULE_PARM_DESC(use_xgmi_p2p, 722 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 723 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 724 725 726 #ifdef CONFIG_HSA_AMD 727 /** 728 * DOC: sched_policy (int) 729 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 730 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 731 * assigns queues to HQDs. 732 */ 733 int sched_policy = KFD_SCHED_POLICY_HWS; 734 module_param(sched_policy, int, 0444); 735 MODULE_PARM_DESC(sched_policy, 736 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 737 738 /** 739 * DOC: hws_max_conc_proc (int) 740 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 741 * number of VMIDs assigned to the HWS, which is also the default. 742 */ 743 int hws_max_conc_proc = -1; 744 module_param(hws_max_conc_proc, int, 0444); 745 MODULE_PARM_DESC(hws_max_conc_proc, 746 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 747 748 /** 749 * DOC: cwsr_enable (int) 750 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 751 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 752 * disables it. 753 */ 754 int cwsr_enable = 1; 755 module_param(cwsr_enable, int, 0444); 756 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 757 758 /** 759 * DOC: max_num_of_queues_per_device (int) 760 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 761 * is 4096. 762 */ 763 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 764 module_param(max_num_of_queues_per_device, int, 0444); 765 MODULE_PARM_DESC(max_num_of_queues_per_device, 766 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 767 768 /** 769 * DOC: send_sigterm (int) 770 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 771 * but just print errors on dmesg. Setting 1 enables sending sigterm. 772 */ 773 int send_sigterm; 774 module_param(send_sigterm, int, 0444); 775 MODULE_PARM_DESC(send_sigterm, 776 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 777 778 /** 779 * DOC: halt_if_hws_hang (int) 780 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 781 * Setting 1 enables halt on hang. 782 */ 783 int halt_if_hws_hang; 784 module_param(halt_if_hws_hang, int, 0644); 785 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 786 787 /** 788 * DOC: hws_gws_support(bool) 789 * Assume that HWS supports GWS barriers regardless of what firmware version 790 * check says. Default value: false (rely on MEC2 firmware version check). 791 */ 792 bool hws_gws_support; 793 module_param(hws_gws_support, bool, 0444); 794 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 795 796 /** 797 * DOC: queue_preemption_timeout_ms (int) 798 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 799 */ 800 int queue_preemption_timeout_ms = 9000; 801 module_param(queue_preemption_timeout_ms, int, 0644); 802 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 803 804 /** 805 * DOC: debug_evictions(bool) 806 * Enable extra debug messages to help determine the cause of evictions 807 */ 808 bool debug_evictions; 809 module_param(debug_evictions, bool, 0644); 810 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 811 812 /** 813 * DOC: no_system_mem_limit(bool) 814 * Disable system memory limit, to support multiple process shared memory 815 */ 816 bool no_system_mem_limit; 817 module_param(no_system_mem_limit, bool, 0644); 818 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 819 820 /** 821 * DOC: no_queue_eviction_on_vm_fault (int) 822 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 823 */ 824 int amdgpu_no_queue_eviction_on_vm_fault; 825 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 826 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 827 #endif 828 829 /** 830 * DOC: mtype_local (int) 831 */ 832 int amdgpu_mtype_local; 833 MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (0 = MTYPE_RW (default), 1 = MTYPE_NC, 2 = MTYPE_CC)"); 834 module_param_named(mtype_local, amdgpu_mtype_local, int, 0444); 835 836 /** 837 * DOC: pcie_p2p (bool) 838 * Enable PCIe P2P (requires large-BAR). Default value: true (on) 839 */ 840 #ifdef CONFIG_HSA_AMD_P2P 841 bool pcie_p2p = true; 842 module_param(pcie_p2p, bool, 0444); 843 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); 844 #endif 845 846 /** 847 * DOC: dcfeaturemask (uint) 848 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 849 * The default is the current set of stable display features. 850 */ 851 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 852 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 853 854 /** 855 * DOC: dcdebugmask (uint) 856 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 857 */ 858 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 859 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 860 861 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)"); 862 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444); 863 864 /** 865 * DOC: abmlevel (uint) 866 * Override the default ABM (Adaptive Backlight Management) level used for DC 867 * enabled hardware. Requires DMCU to be supported and loaded. 868 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 869 * default. Values 1-4 control the maximum allowable brightness reduction via 870 * the ABM algorithm, with 1 being the least reduction and 4 being the most 871 * reduction. 872 * 873 * Defaults to -1, or disabled. Userspace can only override this level after 874 * boot if it's set to auto. 875 */ 876 int amdgpu_dm_abm_level = -1; 877 MODULE_PARM_DESC(abmlevel, 878 "ABM level (0 = off, 1-4 = backlight reduction level, -1 auto (default))"); 879 module_param_named(abmlevel, amdgpu_dm_abm_level, int, 0444); 880 881 int amdgpu_backlight = -1; 882 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 883 module_param_named(backlight, amdgpu_backlight, bint, 0444); 884 885 /** 886 * DOC: damageclips (int) 887 * Enable or disable damage clips support. If damage clips support is disabled, 888 * we will force full frame updates, irrespective of what user space sends to 889 * us. 890 * 891 * Defaults to -1 (where it is enabled unless a PSR-SU display is detected). 892 */ 893 MODULE_PARM_DESC(damageclips, 894 "Damage clips support (0 = disable, 1 = enable, -1 auto (default))"); 895 module_param_named(damageclips, amdgpu_damage_clips, int, 0444); 896 897 /** 898 * DOC: tmz (int) 899 * Trusted Memory Zone (TMZ) is a method to protect data being written 900 * to or read from memory. 901 * 902 * The default value: 0 (off). TODO: change to auto till it is completed. 903 */ 904 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 905 module_param_named(tmz, amdgpu_tmz, int, 0444); 906 907 /** 908 * DOC: freesync_video (uint) 909 * Enable the optimization to adjust front porch timing to achieve seamless 910 * mode change experience when setting a freesync supported mode for which full 911 * modeset is not needed. 912 * 913 * The Display Core will add a set of modes derived from the base FreeSync 914 * video mode into the corresponding connector's mode list based on commonly 915 * used refresh rates and VRR range of the connected display, when users enable 916 * this feature. From the userspace perspective, they can see a seamless mode 917 * change experience when the change between different refresh rates under the 918 * same resolution. Additionally, userspace applications such as Video playback 919 * can read this modeset list and change the refresh rate based on the video 920 * frame rate. Finally, the userspace can also derive an appropriate mode for a 921 * particular refresh rate based on the FreeSync Mode and add it to the 922 * connector's mode list. 923 * 924 * Note: This is an experimental feature. 925 * 926 * The default value: 0 (off). 927 */ 928 MODULE_PARM_DESC( 929 freesync_video, 930 "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)"); 931 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); 932 933 /** 934 * DOC: reset_method (int) 935 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 936 */ 937 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 938 module_param_named(reset_method, amdgpu_reset_method, int, 0644); 939 940 /** 941 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 942 * threshold value of faulty pages detected by RAS ECC, which may 943 * result in the GPU entering bad status when the number of total 944 * faulty pages by ECC exceeds the threshold value. 945 */ 946 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = driver sets threshold)"); 947 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 948 949 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 950 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 951 952 /** 953 * DOC: vcnfw_log (int) 954 * Enable vcnfw log output for debugging, the default is disabled. 955 */ 956 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 957 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 958 959 /** 960 * DOC: sg_display (int) 961 * Disable S/G (scatter/gather) display (i.e., display from system memory). 962 * This option is only relevant on APUs. Set this option to 0 to disable 963 * S/G display if you experience flickering or other issues under memory 964 * pressure and report the issue. 965 */ 966 MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)"); 967 module_param_named(sg_display, amdgpu_sg_display, int, 0444); 968 969 /** 970 * DOC: umsch_mm (int) 971 * Enable Multi Media User Mode Scheduler. This is a HW scheduling engine for VCN and VPE. 972 * (0 = disabled (default), 1 = enabled) 973 */ 974 MODULE_PARM_DESC(umsch_mm, 975 "Enable Multi Media User Mode Scheduler (0 = disabled (default), 1 = enabled)"); 976 module_param_named(umsch_mm, amdgpu_umsch_mm, int, 0444); 977 978 /** 979 * DOC: smu_pptable_id (int) 980 * Used to override pptable id. id = 0 use VBIOS pptable. 981 * id > 0 use the soft pptable with specicfied id. 982 */ 983 MODULE_PARM_DESC(smu_pptable_id, 984 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 985 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 986 987 /** 988 * DOC: partition_mode (int) 989 * Used to override the default SPX mode. 990 */ 991 MODULE_PARM_DESC( 992 user_partt_mode, 993 "specify partition mode to be used (-2 = AMDGPU_AUTO_COMPUTE_PARTITION_MODE(default value) \ 994 0 = AMDGPU_SPX_PARTITION_MODE, \ 995 1 = AMDGPU_DPX_PARTITION_MODE, \ 996 2 = AMDGPU_TPX_PARTITION_MODE, \ 997 3 = AMDGPU_QPX_PARTITION_MODE, \ 998 4 = AMDGPU_CPX_PARTITION_MODE)"); 999 module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint, 0444); 1000 1001 1002 /** 1003 * DOC: enforce_isolation (bool) 1004 * enforce process isolation between graphics and compute via using the same reserved vmid. 1005 */ 1006 module_param(enforce_isolation, bool, 0444); 1007 MODULE_PARM_DESC(enforce_isolation, "enforce process isolation between graphics and compute . enforce_isolation = on"); 1008 1009 /** 1010 * DOC: seamless (int) 1011 * Seamless boot will keep the image on the screen during the boot process. 1012 */ 1013 MODULE_PARM_DESC(seamless, "Seamless boot (-1 = auto (default), 0 = disable, 1 = enable)"); 1014 module_param_named(seamless, amdgpu_seamless, int, 0444); 1015 1016 /** 1017 * DOC: debug_mask (uint) 1018 * Debug options for amdgpu, work as a binary mask with the following options: 1019 * 1020 * - 0x1: Debug VM handling 1021 * - 0x2: Enable simulating large-bar capability on non-large bar system. This 1022 * limits the VRAM size reported to ROCm applications to the visible 1023 * size, usually 256MB. 1024 * - 0x4: Disable GPU soft recovery, always do a full reset 1025 */ 1026 MODULE_PARM_DESC(debug_mask, "debug options for amdgpu, disabled by default"); 1027 module_param_named(debug_mask, amdgpu_debug_mask, uint, 0444); 1028 1029 /** 1030 * DOC: agp (int) 1031 * Enable the AGP aperture. This provides an aperture in the GPU's internal 1032 * address space for direct access to system memory. Note that these accesses 1033 * are non-snooped, so they are only used for access to uncached memory. 1034 */ 1035 MODULE_PARM_DESC(agp, "AGP (-1 = auto (default), 0 = disable, 1 = enable)"); 1036 module_param_named(agp, amdgpu_agp, int, 0444); 1037 1038 /** 1039 * DOC: wbrf (int) 1040 * Enable Wifi RFI interference mitigation feature. 1041 * Due to electrical and mechanical constraints there may be likely interference of 1042 * relatively high-powered harmonics of the (G-)DDR memory clocks with local radio 1043 * module frequency bands used by Wifi 6/6e/7. To mitigate the possible RFI interference, 1044 * with this feature enabled, PMFW will use either “shadowed P-State” or “P-State” based 1045 * on active list of frequencies in-use (to be avoided) as part of initial setting or 1046 * P-state transition. However, there may be potential performance impact with this 1047 * feature enabled. 1048 * (0 = disabled, 1 = enabled, -1 = auto (default setting, will be enabled if supported)) 1049 */ 1050 MODULE_PARM_DESC(wbrf, 1051 "Enable Wifi RFI interference mitigation (0 = disabled, 1 = enabled, -1 = auto(default)"); 1052 module_param_named(wbrf, amdgpu_wbrf, int, 0444); 1053 1054 /* These devices are not supported by amdgpu. 1055 * They are supported by the mach64, r128, radeon drivers 1056 */ 1057 static const u16 amdgpu_unsupported_pciidlist[] = { 1058 /* mach64 */ 1059 0x4354, 1060 0x4358, 1061 0x4554, 1062 0x4742, 1063 0x4744, 1064 0x4749, 1065 0x474C, 1066 0x474D, 1067 0x474E, 1068 0x474F, 1069 0x4750, 1070 0x4751, 1071 0x4752, 1072 0x4753, 1073 0x4754, 1074 0x4755, 1075 0x4756, 1076 0x4757, 1077 0x4758, 1078 0x4759, 1079 0x475A, 1080 0x4C42, 1081 0x4C44, 1082 0x4C47, 1083 0x4C49, 1084 0x4C4D, 1085 0x4C4E, 1086 0x4C50, 1087 0x4C51, 1088 0x4C52, 1089 0x4C53, 1090 0x5654, 1091 0x5655, 1092 0x5656, 1093 /* r128 */ 1094 0x4c45, 1095 0x4c46, 1096 0x4d46, 1097 0x4d4c, 1098 0x5041, 1099 0x5042, 1100 0x5043, 1101 0x5044, 1102 0x5045, 1103 0x5046, 1104 0x5047, 1105 0x5048, 1106 0x5049, 1107 0x504A, 1108 0x504B, 1109 0x504C, 1110 0x504D, 1111 0x504E, 1112 0x504F, 1113 0x5050, 1114 0x5051, 1115 0x5052, 1116 0x5053, 1117 0x5054, 1118 0x5055, 1119 0x5056, 1120 0x5057, 1121 0x5058, 1122 0x5245, 1123 0x5246, 1124 0x5247, 1125 0x524b, 1126 0x524c, 1127 0x534d, 1128 0x5446, 1129 0x544C, 1130 0x5452, 1131 /* radeon */ 1132 0x3150, 1133 0x3151, 1134 0x3152, 1135 0x3154, 1136 0x3155, 1137 0x3E50, 1138 0x3E54, 1139 0x4136, 1140 0x4137, 1141 0x4144, 1142 0x4145, 1143 0x4146, 1144 0x4147, 1145 0x4148, 1146 0x4149, 1147 0x414A, 1148 0x414B, 1149 0x4150, 1150 0x4151, 1151 0x4152, 1152 0x4153, 1153 0x4154, 1154 0x4155, 1155 0x4156, 1156 0x4237, 1157 0x4242, 1158 0x4336, 1159 0x4337, 1160 0x4437, 1161 0x4966, 1162 0x4967, 1163 0x4A48, 1164 0x4A49, 1165 0x4A4A, 1166 0x4A4B, 1167 0x4A4C, 1168 0x4A4D, 1169 0x4A4E, 1170 0x4A4F, 1171 0x4A50, 1172 0x4A54, 1173 0x4B48, 1174 0x4B49, 1175 0x4B4A, 1176 0x4B4B, 1177 0x4B4C, 1178 0x4C57, 1179 0x4C58, 1180 0x4C59, 1181 0x4C5A, 1182 0x4C64, 1183 0x4C66, 1184 0x4C67, 1185 0x4E44, 1186 0x4E45, 1187 0x4E46, 1188 0x4E47, 1189 0x4E48, 1190 0x4E49, 1191 0x4E4A, 1192 0x4E4B, 1193 0x4E50, 1194 0x4E51, 1195 0x4E52, 1196 0x4E53, 1197 0x4E54, 1198 0x4E56, 1199 0x5144, 1200 0x5145, 1201 0x5146, 1202 0x5147, 1203 0x5148, 1204 0x514C, 1205 0x514D, 1206 0x5157, 1207 0x5158, 1208 0x5159, 1209 0x515A, 1210 0x515E, 1211 0x5460, 1212 0x5462, 1213 0x5464, 1214 0x5548, 1215 0x5549, 1216 0x554A, 1217 0x554B, 1218 0x554C, 1219 0x554D, 1220 0x554E, 1221 0x554F, 1222 0x5550, 1223 0x5551, 1224 0x5552, 1225 0x5554, 1226 0x564A, 1227 0x564B, 1228 0x564F, 1229 0x5652, 1230 0x5653, 1231 0x5657, 1232 0x5834, 1233 0x5835, 1234 0x5954, 1235 0x5955, 1236 0x5974, 1237 0x5975, 1238 0x5960, 1239 0x5961, 1240 0x5962, 1241 0x5964, 1242 0x5965, 1243 0x5969, 1244 0x5a41, 1245 0x5a42, 1246 0x5a61, 1247 0x5a62, 1248 0x5b60, 1249 0x5b62, 1250 0x5b63, 1251 0x5b64, 1252 0x5b65, 1253 0x5c61, 1254 0x5c63, 1255 0x5d48, 1256 0x5d49, 1257 0x5d4a, 1258 0x5d4c, 1259 0x5d4d, 1260 0x5d4e, 1261 0x5d4f, 1262 0x5d50, 1263 0x5d52, 1264 0x5d57, 1265 0x5e48, 1266 0x5e4a, 1267 0x5e4b, 1268 0x5e4c, 1269 0x5e4d, 1270 0x5e4f, 1271 0x6700, 1272 0x6701, 1273 0x6702, 1274 0x6703, 1275 0x6704, 1276 0x6705, 1277 0x6706, 1278 0x6707, 1279 0x6708, 1280 0x6709, 1281 0x6718, 1282 0x6719, 1283 0x671c, 1284 0x671d, 1285 0x671f, 1286 0x6720, 1287 0x6721, 1288 0x6722, 1289 0x6723, 1290 0x6724, 1291 0x6725, 1292 0x6726, 1293 0x6727, 1294 0x6728, 1295 0x6729, 1296 0x6738, 1297 0x6739, 1298 0x673e, 1299 0x6740, 1300 0x6741, 1301 0x6742, 1302 0x6743, 1303 0x6744, 1304 0x6745, 1305 0x6746, 1306 0x6747, 1307 0x6748, 1308 0x6749, 1309 0x674A, 1310 0x6750, 1311 0x6751, 1312 0x6758, 1313 0x6759, 1314 0x675B, 1315 0x675D, 1316 0x675F, 1317 0x6760, 1318 0x6761, 1319 0x6762, 1320 0x6763, 1321 0x6764, 1322 0x6765, 1323 0x6766, 1324 0x6767, 1325 0x6768, 1326 0x6770, 1327 0x6771, 1328 0x6772, 1329 0x6778, 1330 0x6779, 1331 0x677B, 1332 0x6840, 1333 0x6841, 1334 0x6842, 1335 0x6843, 1336 0x6849, 1337 0x684C, 1338 0x6850, 1339 0x6858, 1340 0x6859, 1341 0x6880, 1342 0x6888, 1343 0x6889, 1344 0x688A, 1345 0x688C, 1346 0x688D, 1347 0x6898, 1348 0x6899, 1349 0x689b, 1350 0x689c, 1351 0x689d, 1352 0x689e, 1353 0x68a0, 1354 0x68a1, 1355 0x68a8, 1356 0x68a9, 1357 0x68b0, 1358 0x68b8, 1359 0x68b9, 1360 0x68ba, 1361 0x68be, 1362 0x68bf, 1363 0x68c0, 1364 0x68c1, 1365 0x68c7, 1366 0x68c8, 1367 0x68c9, 1368 0x68d8, 1369 0x68d9, 1370 0x68da, 1371 0x68de, 1372 0x68e0, 1373 0x68e1, 1374 0x68e4, 1375 0x68e5, 1376 0x68e8, 1377 0x68e9, 1378 0x68f1, 1379 0x68f2, 1380 0x68f8, 1381 0x68f9, 1382 0x68fa, 1383 0x68fe, 1384 0x7100, 1385 0x7101, 1386 0x7102, 1387 0x7103, 1388 0x7104, 1389 0x7105, 1390 0x7106, 1391 0x7108, 1392 0x7109, 1393 0x710A, 1394 0x710B, 1395 0x710C, 1396 0x710E, 1397 0x710F, 1398 0x7140, 1399 0x7141, 1400 0x7142, 1401 0x7143, 1402 0x7144, 1403 0x7145, 1404 0x7146, 1405 0x7147, 1406 0x7149, 1407 0x714A, 1408 0x714B, 1409 0x714C, 1410 0x714D, 1411 0x714E, 1412 0x714F, 1413 0x7151, 1414 0x7152, 1415 0x7153, 1416 0x715E, 1417 0x715F, 1418 0x7180, 1419 0x7181, 1420 0x7183, 1421 0x7186, 1422 0x7187, 1423 0x7188, 1424 0x718A, 1425 0x718B, 1426 0x718C, 1427 0x718D, 1428 0x718F, 1429 0x7193, 1430 0x7196, 1431 0x719B, 1432 0x719F, 1433 0x71C0, 1434 0x71C1, 1435 0x71C2, 1436 0x71C3, 1437 0x71C4, 1438 0x71C5, 1439 0x71C6, 1440 0x71C7, 1441 0x71CD, 1442 0x71CE, 1443 0x71D2, 1444 0x71D4, 1445 0x71D5, 1446 0x71D6, 1447 0x71DA, 1448 0x71DE, 1449 0x7200, 1450 0x7210, 1451 0x7211, 1452 0x7240, 1453 0x7243, 1454 0x7244, 1455 0x7245, 1456 0x7246, 1457 0x7247, 1458 0x7248, 1459 0x7249, 1460 0x724A, 1461 0x724B, 1462 0x724C, 1463 0x724D, 1464 0x724E, 1465 0x724F, 1466 0x7280, 1467 0x7281, 1468 0x7283, 1469 0x7284, 1470 0x7287, 1471 0x7288, 1472 0x7289, 1473 0x728B, 1474 0x728C, 1475 0x7290, 1476 0x7291, 1477 0x7293, 1478 0x7297, 1479 0x7834, 1480 0x7835, 1481 0x791e, 1482 0x791f, 1483 0x793f, 1484 0x7941, 1485 0x7942, 1486 0x796c, 1487 0x796d, 1488 0x796e, 1489 0x796f, 1490 0x9400, 1491 0x9401, 1492 0x9402, 1493 0x9403, 1494 0x9405, 1495 0x940A, 1496 0x940B, 1497 0x940F, 1498 0x94A0, 1499 0x94A1, 1500 0x94A3, 1501 0x94B1, 1502 0x94B3, 1503 0x94B4, 1504 0x94B5, 1505 0x94B9, 1506 0x9440, 1507 0x9441, 1508 0x9442, 1509 0x9443, 1510 0x9444, 1511 0x9446, 1512 0x944A, 1513 0x944B, 1514 0x944C, 1515 0x944E, 1516 0x9450, 1517 0x9452, 1518 0x9456, 1519 0x945A, 1520 0x945B, 1521 0x945E, 1522 0x9460, 1523 0x9462, 1524 0x946A, 1525 0x946B, 1526 0x947A, 1527 0x947B, 1528 0x9480, 1529 0x9487, 1530 0x9488, 1531 0x9489, 1532 0x948A, 1533 0x948F, 1534 0x9490, 1535 0x9491, 1536 0x9495, 1537 0x9498, 1538 0x949C, 1539 0x949E, 1540 0x949F, 1541 0x94C0, 1542 0x94C1, 1543 0x94C3, 1544 0x94C4, 1545 0x94C5, 1546 0x94C6, 1547 0x94C7, 1548 0x94C8, 1549 0x94C9, 1550 0x94CB, 1551 0x94CC, 1552 0x94CD, 1553 0x9500, 1554 0x9501, 1555 0x9504, 1556 0x9505, 1557 0x9506, 1558 0x9507, 1559 0x9508, 1560 0x9509, 1561 0x950F, 1562 0x9511, 1563 0x9515, 1564 0x9517, 1565 0x9519, 1566 0x9540, 1567 0x9541, 1568 0x9542, 1569 0x954E, 1570 0x954F, 1571 0x9552, 1572 0x9553, 1573 0x9555, 1574 0x9557, 1575 0x955f, 1576 0x9580, 1577 0x9581, 1578 0x9583, 1579 0x9586, 1580 0x9587, 1581 0x9588, 1582 0x9589, 1583 0x958A, 1584 0x958B, 1585 0x958C, 1586 0x958D, 1587 0x958E, 1588 0x958F, 1589 0x9590, 1590 0x9591, 1591 0x9593, 1592 0x9595, 1593 0x9596, 1594 0x9597, 1595 0x9598, 1596 0x9599, 1597 0x959B, 1598 0x95C0, 1599 0x95C2, 1600 0x95C4, 1601 0x95C5, 1602 0x95C6, 1603 0x95C7, 1604 0x95C9, 1605 0x95CC, 1606 0x95CD, 1607 0x95CE, 1608 0x95CF, 1609 0x9610, 1610 0x9611, 1611 0x9612, 1612 0x9613, 1613 0x9614, 1614 0x9615, 1615 0x9616, 1616 0x9640, 1617 0x9641, 1618 0x9642, 1619 0x9643, 1620 0x9644, 1621 0x9645, 1622 0x9647, 1623 0x9648, 1624 0x9649, 1625 0x964a, 1626 0x964b, 1627 0x964c, 1628 0x964e, 1629 0x964f, 1630 0x9710, 1631 0x9711, 1632 0x9712, 1633 0x9713, 1634 0x9714, 1635 0x9715, 1636 0x9802, 1637 0x9803, 1638 0x9804, 1639 0x9805, 1640 0x9806, 1641 0x9807, 1642 0x9808, 1643 0x9809, 1644 0x980A, 1645 0x9900, 1646 0x9901, 1647 0x9903, 1648 0x9904, 1649 0x9905, 1650 0x9906, 1651 0x9907, 1652 0x9908, 1653 0x9909, 1654 0x990A, 1655 0x990B, 1656 0x990C, 1657 0x990D, 1658 0x990E, 1659 0x990F, 1660 0x9910, 1661 0x9913, 1662 0x9917, 1663 0x9918, 1664 0x9919, 1665 0x9990, 1666 0x9991, 1667 0x9992, 1668 0x9993, 1669 0x9994, 1670 0x9995, 1671 0x9996, 1672 0x9997, 1673 0x9998, 1674 0x9999, 1675 0x999A, 1676 0x999B, 1677 0x999C, 1678 0x999D, 1679 0x99A0, 1680 0x99A2, 1681 0x99A4, 1682 /* radeon secondary ids */ 1683 0x3171, 1684 0x3e70, 1685 0x4164, 1686 0x4165, 1687 0x4166, 1688 0x4168, 1689 0x4170, 1690 0x4171, 1691 0x4172, 1692 0x4173, 1693 0x496e, 1694 0x4a69, 1695 0x4a6a, 1696 0x4a6b, 1697 0x4a70, 1698 0x4a74, 1699 0x4b69, 1700 0x4b6b, 1701 0x4b6c, 1702 0x4c6e, 1703 0x4e64, 1704 0x4e65, 1705 0x4e66, 1706 0x4e67, 1707 0x4e68, 1708 0x4e69, 1709 0x4e6a, 1710 0x4e71, 1711 0x4f73, 1712 0x5569, 1713 0x556b, 1714 0x556d, 1715 0x556f, 1716 0x5571, 1717 0x5854, 1718 0x5874, 1719 0x5940, 1720 0x5941, 1721 0x5b70, 1722 0x5b72, 1723 0x5b73, 1724 0x5b74, 1725 0x5b75, 1726 0x5d44, 1727 0x5d45, 1728 0x5d6d, 1729 0x5d6f, 1730 0x5d72, 1731 0x5d77, 1732 0x5e6b, 1733 0x5e6d, 1734 0x7120, 1735 0x7124, 1736 0x7129, 1737 0x712e, 1738 0x712f, 1739 0x7162, 1740 0x7163, 1741 0x7166, 1742 0x7167, 1743 0x7172, 1744 0x7173, 1745 0x71a0, 1746 0x71a1, 1747 0x71a3, 1748 0x71a7, 1749 0x71bb, 1750 0x71e0, 1751 0x71e1, 1752 0x71e2, 1753 0x71e6, 1754 0x71e7, 1755 0x71f2, 1756 0x7269, 1757 0x726b, 1758 0x726e, 1759 0x72a0, 1760 0x72a8, 1761 0x72b1, 1762 0x72b3, 1763 0x793f, 1764 }; 1765 1766 static const struct pci_device_id pciidlist[] = { 1767 #ifdef CONFIG_DRM_AMDGPU_SI 1768 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1769 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1770 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1771 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1772 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1773 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1774 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1775 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1776 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1777 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1778 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1779 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1780 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1781 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1782 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1783 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1784 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1785 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1786 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1787 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1788 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1789 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1790 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1791 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1792 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1793 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1794 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1795 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1796 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1797 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1798 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1799 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1800 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1801 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1802 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1803 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1804 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1805 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1806 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1807 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1808 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1809 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1810 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1811 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1812 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1813 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1814 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1815 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1816 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1817 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1818 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1819 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1820 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1821 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1822 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1823 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1824 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1825 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1826 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1827 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1828 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1829 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1830 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1831 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1832 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1833 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1834 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1835 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1836 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1837 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1838 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1839 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1840 #endif 1841 #ifdef CONFIG_DRM_AMDGPU_CIK 1842 /* Kaveri */ 1843 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1844 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1845 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1846 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1847 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1848 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1849 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1850 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1851 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1852 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1853 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1854 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1855 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1856 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1857 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1858 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1859 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1860 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1861 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1862 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1863 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1864 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1865 /* Bonaire */ 1866 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1867 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1868 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1869 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1870 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1871 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1872 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1873 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1874 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1875 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1876 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1877 /* Hawaii */ 1878 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1879 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1880 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1881 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1882 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1883 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1884 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1885 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1886 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1887 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1888 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1889 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1890 /* Kabini */ 1891 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1892 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1893 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1894 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1895 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1896 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1897 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1898 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1899 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1900 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1901 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1902 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1903 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1904 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1905 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1906 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1907 /* mullins */ 1908 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1909 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1910 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1911 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1912 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1913 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1914 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1915 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1916 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1917 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1918 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1919 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1920 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1921 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1922 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1923 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1924 #endif 1925 /* topaz */ 1926 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1927 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1928 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1929 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1930 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1931 /* tonga */ 1932 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1933 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1934 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1935 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1936 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1937 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1938 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1939 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1940 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1941 /* fiji */ 1942 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1943 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1944 /* carrizo */ 1945 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1946 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1947 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1948 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1949 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1950 /* stoney */ 1951 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1952 /* Polaris11 */ 1953 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1954 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1955 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1956 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1957 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1958 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1959 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1960 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1961 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1962 /* Polaris10 */ 1963 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1964 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1965 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1966 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1967 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1968 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1969 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1970 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1971 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1972 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1973 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1974 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1975 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1976 /* Polaris12 */ 1977 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1978 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1979 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1980 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1981 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1982 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1983 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1984 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1985 /* VEGAM */ 1986 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1987 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1988 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1989 /* Vega 10 */ 1990 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1991 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1992 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1993 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1994 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1995 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1996 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1997 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1998 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1999 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2000 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2001 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2002 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2003 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2004 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2005 /* Vega 12 */ 2006 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2007 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2008 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2009 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2010 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2011 /* Vega 20 */ 2012 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2013 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2014 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2015 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2016 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2017 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2018 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2019 /* Raven */ 2020 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 2021 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 2022 /* Arcturus */ 2023 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2024 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2025 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2026 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2027 /* Navi10 */ 2028 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2029 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2030 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2031 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2032 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2033 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2034 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2035 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2036 /* Navi14 */ 2037 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2038 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2039 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2040 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2041 2042 /* Renoir */ 2043 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2044 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2045 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2046 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2047 2048 /* Navi12 */ 2049 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 2050 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 2051 2052 /* Sienna_Cichlid */ 2053 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2054 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2055 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2056 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2057 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2058 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2059 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2060 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2061 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2062 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2063 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2064 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2065 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2066 2067 /* Yellow Carp */ 2068 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 2069 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 2070 2071 /* Navy_Flounder */ 2072 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2073 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2074 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2075 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2076 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2077 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2078 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2079 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2080 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2081 2082 /* DIMGREY_CAVEFISH */ 2083 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2084 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2085 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2086 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2087 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2088 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2089 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2090 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2091 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2092 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2093 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2094 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2095 2096 /* Aldebaran */ 2097 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2098 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2099 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2100 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2101 2102 /* CYAN_SKILLFISH */ 2103 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2104 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2105 2106 /* BEIGE_GOBY */ 2107 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2108 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2109 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2110 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2111 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2112 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2113 2114 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2115 .class = PCI_CLASS_DISPLAY_VGA << 8, 2116 .class_mask = 0xffffff, 2117 .driver_data = CHIP_IP_DISCOVERY }, 2118 2119 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2120 .class = PCI_CLASS_DISPLAY_OTHER << 8, 2121 .class_mask = 0xffffff, 2122 .driver_data = CHIP_IP_DISCOVERY }, 2123 2124 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2125 .class = PCI_CLASS_ACCELERATOR_PROCESSING << 8, 2126 .class_mask = 0xffffff, 2127 .driver_data = CHIP_IP_DISCOVERY }, 2128 2129 {0, 0, 0} 2130 }; 2131 2132 MODULE_DEVICE_TABLE(pci, pciidlist); 2133 2134 static const struct amdgpu_asic_type_quirk asic_type_quirks[] = { 2135 /* differentiate between P10 and P11 asics with the same DID */ 2136 {0x67FF, 0xE3, CHIP_POLARIS10}, 2137 {0x67FF, 0xE7, CHIP_POLARIS10}, 2138 {0x67FF, 0xF3, CHIP_POLARIS10}, 2139 {0x67FF, 0xF7, CHIP_POLARIS10}, 2140 }; 2141 2142 static const struct drm_driver amdgpu_kms_driver; 2143 2144 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 2145 { 2146 struct pci_dev *p = NULL; 2147 int i; 2148 2149 /* 0 - GPU 2150 * 1 - audio 2151 * 2 - USB 2152 * 3 - UCSI 2153 */ 2154 for (i = 1; i < 4; i++) { 2155 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 2156 adev->pdev->bus->number, i); 2157 if (p) { 2158 pm_runtime_get_sync(&p->dev); 2159 pm_runtime_mark_last_busy(&p->dev); 2160 pm_runtime_put_autosuspend(&p->dev); 2161 pci_dev_put(p); 2162 } 2163 } 2164 } 2165 2166 static void amdgpu_init_debug_options(struct amdgpu_device *adev) 2167 { 2168 if (amdgpu_debug_mask & AMDGPU_DEBUG_VM) { 2169 pr_info("debug: VM handling debug enabled\n"); 2170 adev->debug_vm = true; 2171 } 2172 2173 if (amdgpu_debug_mask & AMDGPU_DEBUG_LARGEBAR) { 2174 pr_info("debug: enabled simulating large-bar capability on non-large bar system\n"); 2175 adev->debug_largebar = true; 2176 } 2177 2178 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY) { 2179 pr_info("debug: soft reset for GPU recovery disabled\n"); 2180 adev->debug_disable_soft_recovery = true; 2181 } 2182 2183 if (amdgpu_debug_mask & AMDGPU_DEBUG_USE_VRAM_FW_BUF) { 2184 pr_info("debug: place fw in vram for frontdoor loading\n"); 2185 adev->debug_use_vram_fw_buf = true; 2186 } 2187 } 2188 2189 static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long flags) 2190 { 2191 int i; 2192 2193 for (i = 0; i < ARRAY_SIZE(asic_type_quirks); i++) { 2194 if (pdev->device == asic_type_quirks[i].device && 2195 pdev->revision == asic_type_quirks[i].revision) { 2196 flags &= ~AMD_ASIC_MASK; 2197 flags |= asic_type_quirks[i].type; 2198 break; 2199 } 2200 } 2201 2202 return flags; 2203 } 2204 2205 static int amdgpu_pci_probe(struct pci_dev *pdev, 2206 const struct pci_device_id *ent) 2207 { 2208 struct drm_device *ddev; 2209 struct amdgpu_device *adev; 2210 unsigned long flags = ent->driver_data; 2211 int ret, retry = 0, i; 2212 bool supports_atomic = false; 2213 2214 /* skip devices which are owned by radeon */ 2215 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2216 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2217 return -ENODEV; 2218 } 2219 2220 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) 2221 amdgpu_aspm = 0; 2222 2223 if (amdgpu_virtual_display || 2224 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 2225 supports_atomic = true; 2226 2227 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2228 DRM_INFO("This hardware requires experimental hardware support.\n" 2229 "See modparam exp_hw_support\n"); 2230 return -ENODEV; 2231 } 2232 2233 flags = amdgpu_fix_asic_type(pdev, flags); 2234 2235 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2236 * however, SME requires an indirect IOMMU mapping because the encryption 2237 * bit is beyond the DMA mask of the chip. 2238 */ 2239 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2240 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2241 dev_info(&pdev->dev, 2242 "SME is not compatible with RAVEN\n"); 2243 return -ENOTSUPP; 2244 } 2245 2246 #ifdef CONFIG_DRM_AMDGPU_SI 2247 if (!amdgpu_si_support) { 2248 switch (flags & AMD_ASIC_MASK) { 2249 case CHIP_TAHITI: 2250 case CHIP_PITCAIRN: 2251 case CHIP_VERDE: 2252 case CHIP_OLAND: 2253 case CHIP_HAINAN: 2254 dev_info(&pdev->dev, 2255 "SI support provided by radeon.\n"); 2256 dev_info(&pdev->dev, 2257 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 2258 ); 2259 return -ENODEV; 2260 } 2261 } 2262 #endif 2263 #ifdef CONFIG_DRM_AMDGPU_CIK 2264 if (!amdgpu_cik_support) { 2265 switch (flags & AMD_ASIC_MASK) { 2266 case CHIP_KAVERI: 2267 case CHIP_BONAIRE: 2268 case CHIP_HAWAII: 2269 case CHIP_KABINI: 2270 case CHIP_MULLINS: 2271 dev_info(&pdev->dev, 2272 "CIK support provided by radeon.\n"); 2273 dev_info(&pdev->dev, 2274 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 2275 ); 2276 return -ENODEV; 2277 } 2278 } 2279 #endif 2280 2281 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2282 if (IS_ERR(adev)) 2283 return PTR_ERR(adev); 2284 2285 adev->dev = &pdev->dev; 2286 adev->pdev = pdev; 2287 ddev = adev_to_drm(adev); 2288 2289 if (!supports_atomic) 2290 ddev->driver_features &= ~DRIVER_ATOMIC; 2291 2292 ret = pci_enable_device(pdev); 2293 if (ret) 2294 return ret; 2295 2296 pci_set_drvdata(pdev, ddev); 2297 2298 amdgpu_init_debug_options(adev); 2299 2300 ret = amdgpu_driver_load_kms(adev, flags); 2301 if (ret) 2302 goto err_pci; 2303 2304 retry_init: 2305 ret = drm_dev_register(ddev, flags); 2306 if (ret == -EAGAIN && ++retry <= 3) { 2307 DRM_INFO("retry init %d\n", retry); 2308 /* Don't request EX mode too frequently which is attacking */ 2309 msleep(5000); 2310 goto retry_init; 2311 } else if (ret) { 2312 goto err_pci; 2313 } 2314 2315 ret = amdgpu_xcp_dev_register(adev, ent); 2316 if (ret) 2317 goto err_pci; 2318 2319 ret = amdgpu_amdkfd_drm_client_create(adev); 2320 if (ret) 2321 goto err_pci; 2322 2323 /* 2324 * 1. don't init fbdev on hw without DCE 2325 * 2. don't init fbdev if there are no connectors 2326 */ 2327 if (adev->mode_info.mode_config_initialized && 2328 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2329 /* select 8 bpp console on low vram cards */ 2330 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2331 drm_fbdev_generic_setup(adev_to_drm(adev), 8); 2332 else 2333 drm_fbdev_generic_setup(adev_to_drm(adev), 32); 2334 } 2335 2336 ret = amdgpu_debugfs_init(adev); 2337 if (ret) 2338 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2339 2340 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2341 /* only need to skip on ATPX */ 2342 if (amdgpu_device_supports_px(ddev)) 2343 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2344 /* we want direct complete for BOCO */ 2345 if (amdgpu_device_supports_boco(ddev)) 2346 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2347 DPM_FLAG_SMART_SUSPEND | 2348 DPM_FLAG_MAY_SKIP_RESUME); 2349 pm_runtime_use_autosuspend(ddev->dev); 2350 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2351 2352 pm_runtime_allow(ddev->dev); 2353 2354 pm_runtime_mark_last_busy(ddev->dev); 2355 pm_runtime_put_autosuspend(ddev->dev); 2356 2357 pci_wake_from_d3(pdev, TRUE); 2358 2359 /* 2360 * For runpm implemented via BACO, PMFW will handle the 2361 * timing for BACO in and out: 2362 * - put ASIC into BACO state only when both video and 2363 * audio functions are in D3 state. 2364 * - pull ASIC out of BACO state when either video or 2365 * audio function is in D0 state. 2366 * Also, at startup, PMFW assumes both functions are in 2367 * D0 state. 2368 * 2369 * So if snd driver was loaded prior to amdgpu driver 2370 * and audio function was put into D3 state, there will 2371 * be no PMFW-aware D-state transition(D0->D3) on runpm 2372 * suspend. Thus the BACO will be not correctly kicked in. 2373 * 2374 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2375 * into D0 state. Then there will be a PMFW-aware D-state 2376 * transition(D0->D3) on runpm suspend. 2377 */ 2378 if (amdgpu_device_supports_baco(ddev) && 2379 !(adev->flags & AMD_IS_APU) && 2380 (adev->asic_type >= CHIP_NAVI10)) 2381 amdgpu_get_secondary_funcs(adev); 2382 } 2383 2384 return 0; 2385 2386 err_pci: 2387 pci_disable_device(pdev); 2388 return ret; 2389 } 2390 2391 static void 2392 amdgpu_pci_remove(struct pci_dev *pdev) 2393 { 2394 struct drm_device *dev = pci_get_drvdata(pdev); 2395 struct amdgpu_device *adev = drm_to_adev(dev); 2396 2397 amdgpu_xcp_dev_unplug(adev); 2398 drm_dev_unplug(dev); 2399 2400 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2401 pm_runtime_get_sync(dev->dev); 2402 pm_runtime_forbid(dev->dev); 2403 } 2404 2405 amdgpu_driver_unload_kms(dev); 2406 2407 /* 2408 * Flush any in flight DMA operations from device. 2409 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2410 * StatusTransactions Pending bit. 2411 */ 2412 pci_disable_device(pdev); 2413 pci_wait_for_pending_transaction(pdev); 2414 } 2415 2416 static void 2417 amdgpu_pci_shutdown(struct pci_dev *pdev) 2418 { 2419 struct drm_device *dev = pci_get_drvdata(pdev); 2420 struct amdgpu_device *adev = drm_to_adev(dev); 2421 2422 if (amdgpu_ras_intr_triggered()) 2423 return; 2424 2425 /* if we are running in a VM, make sure the device 2426 * torn down properly on reboot/shutdown. 2427 * unfortunately we can't detect certain 2428 * hypervisors so just do this all the time. 2429 */ 2430 if (!amdgpu_passthrough(adev)) 2431 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2432 amdgpu_device_ip_suspend(adev); 2433 adev->mp1_state = PP_MP1_STATE_NONE; 2434 } 2435 2436 /** 2437 * amdgpu_drv_delayed_reset_work_handler - work handler for reset 2438 * 2439 * @work: work_struct. 2440 */ 2441 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) 2442 { 2443 struct list_head device_list; 2444 struct amdgpu_device *adev; 2445 int i, r; 2446 struct amdgpu_reset_context reset_context; 2447 2448 memset(&reset_context, 0, sizeof(reset_context)); 2449 2450 mutex_lock(&mgpu_info.mutex); 2451 if (mgpu_info.pending_reset == true) { 2452 mutex_unlock(&mgpu_info.mutex); 2453 return; 2454 } 2455 mgpu_info.pending_reset = true; 2456 mutex_unlock(&mgpu_info.mutex); 2457 2458 /* Use a common context, just need to make sure full reset is done */ 2459 reset_context.method = AMD_RESET_METHOD_NONE; 2460 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2461 2462 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2463 adev = mgpu_info.gpu_ins[i].adev; 2464 reset_context.reset_req_dev = adev; 2465 r = amdgpu_device_pre_asic_reset(adev, &reset_context); 2466 if (r) { 2467 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", 2468 r, adev_to_drm(adev)->unique); 2469 } 2470 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) 2471 r = -EALREADY; 2472 } 2473 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2474 adev = mgpu_info.gpu_ins[i].adev; 2475 flush_work(&adev->xgmi_reset_work); 2476 adev->gmc.xgmi.pending_reset = false; 2477 } 2478 2479 /* reset function will rebuild the xgmi hive info , clear it now */ 2480 for (i = 0; i < mgpu_info.num_dgpu; i++) 2481 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); 2482 2483 INIT_LIST_HEAD(&device_list); 2484 2485 for (i = 0; i < mgpu_info.num_dgpu; i++) 2486 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); 2487 2488 /* unregister the GPU first, reset function will add them back */ 2489 list_for_each_entry(adev, &device_list, reset_list) 2490 amdgpu_unregister_gpu_instance(adev); 2491 2492 /* Use a common context, just need to make sure full reset is done */ 2493 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); 2494 set_bit(AMDGPU_SKIP_COREDUMP, &reset_context.flags); 2495 r = amdgpu_do_asic_reset(&device_list, &reset_context); 2496 2497 if (r) { 2498 DRM_ERROR("reinit gpus failure"); 2499 return; 2500 } 2501 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2502 adev = mgpu_info.gpu_ins[i].adev; 2503 if (!adev->kfd.init_complete) { 2504 kgd2kfd_init_zone_device(adev); 2505 amdgpu_amdkfd_device_init(adev); 2506 amdgpu_amdkfd_drm_client_create(adev); 2507 } 2508 amdgpu_ttm_set_buffer_funcs_status(adev, true); 2509 } 2510 } 2511 2512 static int amdgpu_pmops_prepare(struct device *dev) 2513 { 2514 struct drm_device *drm_dev = dev_get_drvdata(dev); 2515 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2516 2517 /* Return a positive number here so 2518 * DPM_FLAG_SMART_SUSPEND works properly 2519 */ 2520 if (amdgpu_device_supports_boco(drm_dev) && 2521 pm_runtime_suspended(dev)) 2522 return 1; 2523 2524 /* if we will not support s3 or s2i for the device 2525 * then skip suspend 2526 */ 2527 if (!amdgpu_acpi_is_s0ix_active(adev) && 2528 !amdgpu_acpi_is_s3_active(adev)) 2529 return 1; 2530 2531 return amdgpu_device_prepare(drm_dev); 2532 } 2533 2534 static void amdgpu_pmops_complete(struct device *dev) 2535 { 2536 /* nothing to do */ 2537 } 2538 2539 static int amdgpu_pmops_suspend(struct device *dev) 2540 { 2541 struct drm_device *drm_dev = dev_get_drvdata(dev); 2542 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2543 2544 adev->suspend_complete = false; 2545 if (amdgpu_acpi_is_s0ix_active(adev)) 2546 adev->in_s0ix = true; 2547 else if (amdgpu_acpi_is_s3_active(adev)) 2548 adev->in_s3 = true; 2549 if (!adev->in_s0ix && !adev->in_s3) 2550 return 0; 2551 return amdgpu_device_suspend(drm_dev, true); 2552 } 2553 2554 static int amdgpu_pmops_suspend_noirq(struct device *dev) 2555 { 2556 struct drm_device *drm_dev = dev_get_drvdata(dev); 2557 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2558 2559 adev->suspend_complete = true; 2560 if (amdgpu_acpi_should_gpu_reset(adev)) 2561 return amdgpu_asic_reset(adev); 2562 2563 return 0; 2564 } 2565 2566 static int amdgpu_pmops_resume(struct device *dev) 2567 { 2568 struct drm_device *drm_dev = dev_get_drvdata(dev); 2569 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2570 int r; 2571 2572 if (!adev->in_s0ix && !adev->in_s3) 2573 return 0; 2574 2575 /* Avoids registers access if device is physically gone */ 2576 if (!pci_device_is_present(adev->pdev)) 2577 adev->no_hw_access = true; 2578 2579 r = amdgpu_device_resume(drm_dev, true); 2580 if (amdgpu_acpi_is_s0ix_active(adev)) 2581 adev->in_s0ix = false; 2582 else 2583 adev->in_s3 = false; 2584 return r; 2585 } 2586 2587 static int amdgpu_pmops_freeze(struct device *dev) 2588 { 2589 struct drm_device *drm_dev = dev_get_drvdata(dev); 2590 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2591 int r; 2592 2593 adev->in_s4 = true; 2594 r = amdgpu_device_suspend(drm_dev, true); 2595 adev->in_s4 = false; 2596 if (r) 2597 return r; 2598 2599 if (amdgpu_acpi_should_gpu_reset(adev)) 2600 return amdgpu_asic_reset(adev); 2601 return 0; 2602 } 2603 2604 static int amdgpu_pmops_thaw(struct device *dev) 2605 { 2606 struct drm_device *drm_dev = dev_get_drvdata(dev); 2607 2608 return amdgpu_device_resume(drm_dev, true); 2609 } 2610 2611 static int amdgpu_pmops_poweroff(struct device *dev) 2612 { 2613 struct drm_device *drm_dev = dev_get_drvdata(dev); 2614 2615 return amdgpu_device_suspend(drm_dev, true); 2616 } 2617 2618 static int amdgpu_pmops_restore(struct device *dev) 2619 { 2620 struct drm_device *drm_dev = dev_get_drvdata(dev); 2621 2622 return amdgpu_device_resume(drm_dev, true); 2623 } 2624 2625 static int amdgpu_runtime_idle_check_display(struct device *dev) 2626 { 2627 struct pci_dev *pdev = to_pci_dev(dev); 2628 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2629 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2630 2631 if (adev->mode_info.num_crtc) { 2632 struct drm_connector *list_connector; 2633 struct drm_connector_list_iter iter; 2634 int ret = 0; 2635 2636 if (amdgpu_runtime_pm != -2) { 2637 /* XXX: Return busy if any displays are connected to avoid 2638 * possible display wakeups after runtime resume due to 2639 * hotplug events in case any displays were connected while 2640 * the GPU was in suspend. Remove this once that is fixed. 2641 */ 2642 mutex_lock(&drm_dev->mode_config.mutex); 2643 drm_connector_list_iter_begin(drm_dev, &iter); 2644 drm_for_each_connector_iter(list_connector, &iter) { 2645 if (list_connector->status == connector_status_connected) { 2646 ret = -EBUSY; 2647 break; 2648 } 2649 } 2650 drm_connector_list_iter_end(&iter); 2651 mutex_unlock(&drm_dev->mode_config.mutex); 2652 2653 if (ret) 2654 return ret; 2655 } 2656 2657 if (adev->dc_enabled) { 2658 struct drm_crtc *crtc; 2659 2660 drm_for_each_crtc(crtc, drm_dev) { 2661 drm_modeset_lock(&crtc->mutex, NULL); 2662 if (crtc->state->active) 2663 ret = -EBUSY; 2664 drm_modeset_unlock(&crtc->mutex); 2665 if (ret < 0) 2666 break; 2667 } 2668 } else { 2669 mutex_lock(&drm_dev->mode_config.mutex); 2670 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2671 2672 drm_connector_list_iter_begin(drm_dev, &iter); 2673 drm_for_each_connector_iter(list_connector, &iter) { 2674 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2675 ret = -EBUSY; 2676 break; 2677 } 2678 } 2679 2680 drm_connector_list_iter_end(&iter); 2681 2682 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2683 mutex_unlock(&drm_dev->mode_config.mutex); 2684 } 2685 if (ret) 2686 return ret; 2687 } 2688 2689 return 0; 2690 } 2691 2692 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2693 { 2694 struct pci_dev *pdev = to_pci_dev(dev); 2695 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2696 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2697 int ret, i; 2698 2699 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2700 pm_runtime_forbid(dev); 2701 return -EBUSY; 2702 } 2703 2704 ret = amdgpu_runtime_idle_check_display(dev); 2705 if (ret) 2706 return ret; 2707 2708 /* wait for all rings to drain before suspending */ 2709 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2710 struct amdgpu_ring *ring = adev->rings[i]; 2711 2712 if (ring && ring->sched.ready) { 2713 ret = amdgpu_fence_wait_empty(ring); 2714 if (ret) 2715 return -EBUSY; 2716 } 2717 } 2718 2719 adev->in_runpm = true; 2720 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2721 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2722 2723 /* 2724 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2725 * proper cleanups and put itself into a state ready for PNP. That 2726 * can address some random resuming failure observed on BOCO capable 2727 * platforms. 2728 * TODO: this may be also needed for PX capable platform. 2729 */ 2730 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2731 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2732 2733 ret = amdgpu_device_prepare(drm_dev); 2734 if (ret) 2735 return ret; 2736 ret = amdgpu_device_suspend(drm_dev, false); 2737 if (ret) { 2738 adev->in_runpm = false; 2739 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2740 adev->mp1_state = PP_MP1_STATE_NONE; 2741 return ret; 2742 } 2743 2744 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2745 adev->mp1_state = PP_MP1_STATE_NONE; 2746 2747 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) { 2748 /* Only need to handle PCI state in the driver for ATPX 2749 * PCI core handles it for _PR3. 2750 */ 2751 amdgpu_device_cache_pci_state(pdev); 2752 pci_disable_device(pdev); 2753 pci_ignore_hotplug(pdev); 2754 pci_set_power_state(pdev, PCI_D3cold); 2755 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2756 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) { 2757 /* nothing to do */ 2758 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2759 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) { 2760 amdgpu_device_baco_enter(drm_dev); 2761 } 2762 2763 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n"); 2764 2765 return 0; 2766 } 2767 2768 static int amdgpu_pmops_runtime_resume(struct device *dev) 2769 { 2770 struct pci_dev *pdev = to_pci_dev(dev); 2771 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2772 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2773 int ret; 2774 2775 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) 2776 return -EINVAL; 2777 2778 /* Avoids registers access if device is physically gone */ 2779 if (!pci_device_is_present(adev->pdev)) 2780 adev->no_hw_access = true; 2781 2782 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) { 2783 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2784 2785 /* Only need to handle PCI state in the driver for ATPX 2786 * PCI core handles it for _PR3. 2787 */ 2788 pci_set_power_state(pdev, PCI_D0); 2789 amdgpu_device_load_pci_state(pdev); 2790 ret = pci_enable_device(pdev); 2791 if (ret) 2792 return ret; 2793 pci_set_master(pdev); 2794 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) { 2795 /* Only need to handle PCI state in the driver for ATPX 2796 * PCI core handles it for _PR3. 2797 */ 2798 pci_set_master(pdev); 2799 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2800 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) { 2801 amdgpu_device_baco_exit(drm_dev); 2802 } 2803 ret = amdgpu_device_resume(drm_dev, false); 2804 if (ret) { 2805 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2806 pci_disable_device(pdev); 2807 return ret; 2808 } 2809 2810 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2811 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2812 adev->in_runpm = false; 2813 return 0; 2814 } 2815 2816 static int amdgpu_pmops_runtime_idle(struct device *dev) 2817 { 2818 struct drm_device *drm_dev = dev_get_drvdata(dev); 2819 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2820 int ret; 2821 2822 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2823 pm_runtime_forbid(dev); 2824 return -EBUSY; 2825 } 2826 2827 ret = amdgpu_runtime_idle_check_display(dev); 2828 2829 pm_runtime_mark_last_busy(dev); 2830 pm_runtime_autosuspend(dev); 2831 return ret; 2832 } 2833 2834 long amdgpu_drm_ioctl(struct file *filp, 2835 unsigned int cmd, unsigned long arg) 2836 { 2837 struct drm_file *file_priv = filp->private_data; 2838 struct drm_device *dev; 2839 long ret; 2840 2841 dev = file_priv->minor->dev; 2842 ret = pm_runtime_get_sync(dev->dev); 2843 if (ret < 0) 2844 goto out; 2845 2846 ret = drm_ioctl(filp, cmd, arg); 2847 2848 pm_runtime_mark_last_busy(dev->dev); 2849 out: 2850 pm_runtime_put_autosuspend(dev->dev); 2851 return ret; 2852 } 2853 2854 static const struct dev_pm_ops amdgpu_pm_ops = { 2855 .prepare = amdgpu_pmops_prepare, 2856 .complete = amdgpu_pmops_complete, 2857 .suspend = amdgpu_pmops_suspend, 2858 .suspend_noirq = amdgpu_pmops_suspend_noirq, 2859 .resume = amdgpu_pmops_resume, 2860 .freeze = amdgpu_pmops_freeze, 2861 .thaw = amdgpu_pmops_thaw, 2862 .poweroff = amdgpu_pmops_poweroff, 2863 .restore = amdgpu_pmops_restore, 2864 .runtime_suspend = amdgpu_pmops_runtime_suspend, 2865 .runtime_resume = amdgpu_pmops_runtime_resume, 2866 .runtime_idle = amdgpu_pmops_runtime_idle, 2867 }; 2868 2869 static int amdgpu_flush(struct file *f, fl_owner_t id) 2870 { 2871 struct drm_file *file_priv = f->private_data; 2872 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2873 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2874 2875 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 2876 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 2877 2878 return timeout >= 0 ? 0 : timeout; 2879 } 2880 2881 static const struct file_operations amdgpu_driver_kms_fops = { 2882 .owner = THIS_MODULE, 2883 .open = drm_open, 2884 .flush = amdgpu_flush, 2885 .release = drm_release, 2886 .unlocked_ioctl = amdgpu_drm_ioctl, 2887 .mmap = drm_gem_mmap, 2888 .poll = drm_poll, 2889 .read = drm_read, 2890 #ifdef CONFIG_COMPAT 2891 .compat_ioctl = amdgpu_kms_compat_ioctl, 2892 #endif 2893 #ifdef CONFIG_PROC_FS 2894 .show_fdinfo = drm_show_fdinfo, 2895 #endif 2896 }; 2897 2898 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 2899 { 2900 struct drm_file *file; 2901 2902 if (!filp) 2903 return -EINVAL; 2904 2905 if (filp->f_op != &amdgpu_driver_kms_fops) 2906 return -EINVAL; 2907 2908 file = filp->private_data; 2909 *fpriv = file->driver_priv; 2910 return 0; 2911 } 2912 2913 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 2914 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2915 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2916 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2917 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 2918 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2919 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2920 /* KMS */ 2921 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2922 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2923 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2924 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2925 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2926 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2927 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2928 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2929 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2930 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2931 }; 2932 2933 static const struct drm_driver amdgpu_kms_driver = { 2934 .driver_features = 2935 DRIVER_ATOMIC | 2936 DRIVER_GEM | 2937 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 2938 DRIVER_SYNCOBJ_TIMELINE, 2939 .open = amdgpu_driver_open_kms, 2940 .postclose = amdgpu_driver_postclose_kms, 2941 .lastclose = amdgpu_driver_lastclose_kms, 2942 .ioctls = amdgpu_ioctls_kms, 2943 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2944 .dumb_create = amdgpu_mode_dumb_create, 2945 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2946 .fops = &amdgpu_driver_kms_fops, 2947 .release = &amdgpu_driver_release_kms, 2948 #ifdef CONFIG_PROC_FS 2949 .show_fdinfo = amdgpu_show_fdinfo, 2950 #endif 2951 2952 .gem_prime_import = amdgpu_gem_prime_import, 2953 2954 .name = DRIVER_NAME, 2955 .desc = DRIVER_DESC, 2956 .date = DRIVER_DATE, 2957 .major = KMS_DRIVER_MAJOR, 2958 .minor = KMS_DRIVER_MINOR, 2959 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2960 }; 2961 2962 const struct drm_driver amdgpu_partition_driver = { 2963 .driver_features = 2964 DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ | 2965 DRIVER_SYNCOBJ_TIMELINE, 2966 .open = amdgpu_driver_open_kms, 2967 .postclose = amdgpu_driver_postclose_kms, 2968 .lastclose = amdgpu_driver_lastclose_kms, 2969 .ioctls = amdgpu_ioctls_kms, 2970 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2971 .dumb_create = amdgpu_mode_dumb_create, 2972 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2973 .fops = &amdgpu_driver_kms_fops, 2974 .release = &amdgpu_driver_release_kms, 2975 2976 .gem_prime_import = amdgpu_gem_prime_import, 2977 2978 .name = DRIVER_NAME, 2979 .desc = DRIVER_DESC, 2980 .date = DRIVER_DATE, 2981 .major = KMS_DRIVER_MAJOR, 2982 .minor = KMS_DRIVER_MINOR, 2983 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2984 }; 2985 2986 static struct pci_error_handlers amdgpu_pci_err_handler = { 2987 .error_detected = amdgpu_pci_error_detected, 2988 .mmio_enabled = amdgpu_pci_mmio_enabled, 2989 .slot_reset = amdgpu_pci_slot_reset, 2990 .resume = amdgpu_pci_resume, 2991 }; 2992 2993 static const struct attribute_group *amdgpu_sysfs_groups[] = { 2994 &amdgpu_vram_mgr_attr_group, 2995 &amdgpu_gtt_mgr_attr_group, 2996 &amdgpu_flash_attr_group, 2997 NULL, 2998 }; 2999 3000 static struct pci_driver amdgpu_kms_pci_driver = { 3001 .name = DRIVER_NAME, 3002 .id_table = pciidlist, 3003 .probe = amdgpu_pci_probe, 3004 .remove = amdgpu_pci_remove, 3005 .shutdown = amdgpu_pci_shutdown, 3006 .driver.pm = &amdgpu_pm_ops, 3007 .err_handler = &amdgpu_pci_err_handler, 3008 .dev_groups = amdgpu_sysfs_groups, 3009 }; 3010 3011 static int __init amdgpu_init(void) 3012 { 3013 int r; 3014 3015 if (drm_firmware_drivers_only()) 3016 return -EINVAL; 3017 3018 r = amdgpu_sync_init(); 3019 if (r) 3020 goto error_sync; 3021 3022 r = amdgpu_fence_slab_init(); 3023 if (r) 3024 goto error_fence; 3025 3026 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 3027 amdgpu_register_atpx_handler(); 3028 amdgpu_acpi_detect(); 3029 3030 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 3031 amdgpu_amdkfd_init(); 3032 3033 /* let modprobe override vga console setting */ 3034 return pci_register_driver(&amdgpu_kms_pci_driver); 3035 3036 error_fence: 3037 amdgpu_sync_fini(); 3038 3039 error_sync: 3040 return r; 3041 } 3042 3043 static void __exit amdgpu_exit(void) 3044 { 3045 amdgpu_amdkfd_fini(); 3046 pci_unregister_driver(&amdgpu_kms_pci_driver); 3047 amdgpu_unregister_atpx_handler(); 3048 amdgpu_acpi_release(); 3049 amdgpu_sync_fini(); 3050 amdgpu_fence_slab_fini(); 3051 mmu_notifier_synchronize(); 3052 amdgpu_xcp_drv_release(); 3053 } 3054 3055 module_init(amdgpu_init); 3056 module_exit(amdgpu_exit); 3057 3058 MODULE_AUTHOR(DRIVER_AUTHOR); 3059 MODULE_DESCRIPTION(DRIVER_DESC); 3060 MODULE_LICENSE("GPL and additional rights"); 3061