1 /** 2 * \file amdgpu_drv.c 3 * AMD Amdgpu driver 4 * 5 * \author Gareth Hughes <gareth@valinux.com> 6 */ 7 8 /* 9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 10 * All Rights Reserved. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a 13 * copy of this software and associated documentation files (the "Software"), 14 * to deal in the Software without restriction, including without limitation 15 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 16 * and/or sell copies of the Software, and to permit persons to whom the 17 * Software is furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice (including the next 20 * paragraph) shall be included in all copies or substantial portions of the 21 * Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 29 * OTHER DEALINGS IN THE SOFTWARE. 30 */ 31 32 #include <drm/drmP.h> 33 #include <drm/amdgpu_drm.h> 34 #include <drm/drm_gem.h> 35 #include "amdgpu_drv.h" 36 37 #include <drm/drm_pciids.h> 38 #include <linux/console.h> 39 #include <linux/module.h> 40 #include <linux/pm_runtime.h> 41 #include <linux/vga_switcheroo.h> 42 #include "drm_crtc_helper.h" 43 44 #include "amdgpu.h" 45 #include "amdgpu_irq.h" 46 47 #include "amdgpu_amdkfd.h" 48 49 /* 50 * KMS wrapper. 51 * - 3.0.0 - initial driver 52 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 53 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 54 * at the end of IBs. 55 */ 56 #define KMS_DRIVER_MAJOR 3 57 #define KMS_DRIVER_MINOR 2 58 #define KMS_DRIVER_PATCHLEVEL 0 59 60 int amdgpu_vram_limit = 0; 61 int amdgpu_gart_size = -1; /* auto */ 62 int amdgpu_benchmarking = 0; 63 int amdgpu_testing = 0; 64 int amdgpu_audio = -1; 65 int amdgpu_disp_priority = 0; 66 int amdgpu_hw_i2c = 0; 67 int amdgpu_pcie_gen2 = -1; 68 int amdgpu_msi = -1; 69 int amdgpu_lockup_timeout = 0; 70 int amdgpu_dpm = -1; 71 int amdgpu_smc_load_fw = 1; 72 int amdgpu_aspm = -1; 73 int amdgpu_runtime_pm = -1; 74 unsigned amdgpu_ip_block_mask = 0xffffffff; 75 int amdgpu_bapm = -1; 76 int amdgpu_deep_color = 0; 77 int amdgpu_vm_size = 64; 78 int amdgpu_vm_block_size = -1; 79 int amdgpu_vm_fault_stop = 0; 80 int amdgpu_vm_debug = 0; 81 int amdgpu_exp_hw_support = 0; 82 int amdgpu_sched_jobs = 32; 83 int amdgpu_sched_hw_submission = 2; 84 int amdgpu_powerplay = -1; 85 unsigned amdgpu_pcie_gen_cap = 0; 86 unsigned amdgpu_pcie_lane_cap = 0; 87 88 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 89 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 90 91 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)"); 92 module_param_named(gartsize, amdgpu_gart_size, int, 0600); 93 94 MODULE_PARM_DESC(benchmark, "Run benchmark"); 95 module_param_named(benchmark, amdgpu_benchmarking, int, 0444); 96 97 MODULE_PARM_DESC(test, "Run tests"); 98 module_param_named(test, amdgpu_testing, int, 0444); 99 100 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 101 module_param_named(audio, amdgpu_audio, int, 0444); 102 103 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 104 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 105 106 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 107 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 108 109 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 110 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 111 112 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 113 module_param_named(msi, amdgpu_msi, int, 0444); 114 115 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 0 = disable)"); 116 module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444); 117 118 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 119 module_param_named(dpm, amdgpu_dpm, int, 0444); 120 121 MODULE_PARM_DESC(smc_load_fw, "SMC firmware loading(1 = enable, 0 = disable)"); 122 module_param_named(smc_load_fw, amdgpu_smc_load_fw, int, 0444); 123 124 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 125 module_param_named(aspm, amdgpu_aspm, int, 0444); 126 127 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 128 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 129 130 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 131 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 132 133 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 134 module_param_named(bapm, amdgpu_bapm, int, 0444); 135 136 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 137 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 138 139 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 140 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 141 142 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 143 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 144 145 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 146 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 147 148 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 149 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 150 151 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 152 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 153 154 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 155 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 156 157 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 158 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 159 160 #ifdef CONFIG_DRM_AMD_POWERPLAY 161 MODULE_PARM_DESC(powerplay, "Powerplay component (1 = enable, 0 = disable, -1 = auto (default))"); 162 module_param_named(powerplay, amdgpu_powerplay, int, 0444); 163 #endif 164 165 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 166 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 167 168 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 169 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 170 171 static const struct pci_device_id pciidlist[] = { 172 #ifdef CONFIG_DRM_AMDGPU_CIK 173 /* Kaveri */ 174 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 175 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 176 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 177 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 178 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 179 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 180 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 181 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 182 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 183 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 184 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 185 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 186 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 187 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 188 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 189 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 190 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 191 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 192 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 193 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 194 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 195 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 196 /* Bonaire */ 197 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 198 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 199 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 200 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 201 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 202 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 203 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 204 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 205 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 206 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 207 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 208 /* Hawaii */ 209 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 210 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 211 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 212 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 213 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 214 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 215 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 216 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 217 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 218 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 219 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 220 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 221 /* Kabini */ 222 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 223 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 224 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 225 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 226 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 227 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 228 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 229 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 230 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 231 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 232 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 233 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 234 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 235 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 236 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 237 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 238 /* mullins */ 239 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 240 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 241 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 242 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 243 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 244 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 245 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 246 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 247 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 248 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 249 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 250 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 251 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 252 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 253 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 254 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 255 #endif 256 /* topaz */ 257 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 258 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 259 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 260 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 261 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 262 /* tonga */ 263 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 264 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 265 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 266 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 267 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 268 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 269 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 270 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 271 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 272 /* fiji */ 273 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 274 /* carrizo */ 275 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 276 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 277 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 278 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 279 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 280 /* stoney */ 281 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 282 /* Polaris11 */ 283 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 284 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 285 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 286 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 287 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 288 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 289 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 290 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 291 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 292 /* Polaris10 */ 293 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 294 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 295 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 296 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 297 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 298 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 299 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 300 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 301 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 302 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 303 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 304 305 {0, 0, 0} 306 }; 307 308 MODULE_DEVICE_TABLE(pci, pciidlist); 309 310 static struct drm_driver kms_driver; 311 312 static int amdgpu_kick_out_firmware_fb(struct pci_dev *pdev) 313 { 314 struct apertures_struct *ap; 315 bool primary = false; 316 317 ap = alloc_apertures(1); 318 if (!ap) 319 return -ENOMEM; 320 321 ap->ranges[0].base = pci_resource_start(pdev, 0); 322 ap->ranges[0].size = pci_resource_len(pdev, 0); 323 324 #ifdef CONFIG_X86 325 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; 326 #endif 327 remove_conflicting_framebuffers(ap, "amdgpudrmfb", primary); 328 kfree(ap); 329 330 return 0; 331 } 332 333 static int amdgpu_pci_probe(struct pci_dev *pdev, 334 const struct pci_device_id *ent) 335 { 336 unsigned long flags = ent->driver_data; 337 int ret; 338 339 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 340 DRM_INFO("This hardware requires experimental hardware support.\n" 341 "See modparam exp_hw_support\n"); 342 return -ENODEV; 343 } 344 345 /* 346 * Initialize amdkfd before starting radeon. If it was not loaded yet, 347 * defer radeon probing 348 */ 349 ret = amdgpu_amdkfd_init(); 350 if (ret == -EPROBE_DEFER) 351 return ret; 352 353 /* Get rid of things like offb */ 354 ret = amdgpu_kick_out_firmware_fb(pdev); 355 if (ret) 356 return ret; 357 358 return drm_get_pci_dev(pdev, ent, &kms_driver); 359 } 360 361 static void 362 amdgpu_pci_remove(struct pci_dev *pdev) 363 { 364 struct drm_device *dev = pci_get_drvdata(pdev); 365 366 drm_put_dev(dev); 367 } 368 369 static int amdgpu_pmops_suspend(struct device *dev) 370 { 371 struct pci_dev *pdev = to_pci_dev(dev); 372 struct drm_device *drm_dev = pci_get_drvdata(pdev); 373 return amdgpu_suspend_kms(drm_dev, true, true); 374 } 375 376 static int amdgpu_pmops_resume(struct device *dev) 377 { 378 struct pci_dev *pdev = to_pci_dev(dev); 379 struct drm_device *drm_dev = pci_get_drvdata(pdev); 380 return amdgpu_resume_kms(drm_dev, true, true); 381 } 382 383 static int amdgpu_pmops_freeze(struct device *dev) 384 { 385 struct pci_dev *pdev = to_pci_dev(dev); 386 struct drm_device *drm_dev = pci_get_drvdata(pdev); 387 return amdgpu_suspend_kms(drm_dev, false, true); 388 } 389 390 static int amdgpu_pmops_thaw(struct device *dev) 391 { 392 struct pci_dev *pdev = to_pci_dev(dev); 393 struct drm_device *drm_dev = pci_get_drvdata(pdev); 394 return amdgpu_resume_kms(drm_dev, false, true); 395 } 396 397 static int amdgpu_pmops_runtime_suspend(struct device *dev) 398 { 399 struct pci_dev *pdev = to_pci_dev(dev); 400 struct drm_device *drm_dev = pci_get_drvdata(pdev); 401 int ret; 402 403 if (!amdgpu_device_is_px(drm_dev)) { 404 pm_runtime_forbid(dev); 405 return -EBUSY; 406 } 407 408 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 409 drm_kms_helper_poll_disable(drm_dev); 410 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF); 411 412 ret = amdgpu_suspend_kms(drm_dev, false, false); 413 pci_save_state(pdev); 414 pci_disable_device(pdev); 415 pci_ignore_hotplug(pdev); 416 pci_set_power_state(pdev, PCI_D3cold); 417 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 418 419 return 0; 420 } 421 422 static int amdgpu_pmops_runtime_resume(struct device *dev) 423 { 424 struct pci_dev *pdev = to_pci_dev(dev); 425 struct drm_device *drm_dev = pci_get_drvdata(pdev); 426 int ret; 427 428 if (!amdgpu_device_is_px(drm_dev)) 429 return -EINVAL; 430 431 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 432 433 pci_set_power_state(pdev, PCI_D0); 434 pci_restore_state(pdev); 435 ret = pci_enable_device(pdev); 436 if (ret) 437 return ret; 438 pci_set_master(pdev); 439 440 ret = amdgpu_resume_kms(drm_dev, false, false); 441 drm_kms_helper_poll_enable(drm_dev); 442 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON); 443 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 444 return 0; 445 } 446 447 static int amdgpu_pmops_runtime_idle(struct device *dev) 448 { 449 struct pci_dev *pdev = to_pci_dev(dev); 450 struct drm_device *drm_dev = pci_get_drvdata(pdev); 451 struct drm_crtc *crtc; 452 453 if (!amdgpu_device_is_px(drm_dev)) { 454 pm_runtime_forbid(dev); 455 return -EBUSY; 456 } 457 458 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 459 if (crtc->enabled) { 460 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 461 return -EBUSY; 462 } 463 } 464 465 pm_runtime_mark_last_busy(dev); 466 pm_runtime_autosuspend(dev); 467 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 468 return 1; 469 } 470 471 long amdgpu_drm_ioctl(struct file *filp, 472 unsigned int cmd, unsigned long arg) 473 { 474 struct drm_file *file_priv = filp->private_data; 475 struct drm_device *dev; 476 long ret; 477 dev = file_priv->minor->dev; 478 ret = pm_runtime_get_sync(dev->dev); 479 if (ret < 0) 480 return ret; 481 482 ret = drm_ioctl(filp, cmd, arg); 483 484 pm_runtime_mark_last_busy(dev->dev); 485 pm_runtime_put_autosuspend(dev->dev); 486 return ret; 487 } 488 489 static const struct dev_pm_ops amdgpu_pm_ops = { 490 .suspend = amdgpu_pmops_suspend, 491 .resume = amdgpu_pmops_resume, 492 .freeze = amdgpu_pmops_freeze, 493 .thaw = amdgpu_pmops_thaw, 494 .poweroff = amdgpu_pmops_freeze, 495 .restore = amdgpu_pmops_resume, 496 .runtime_suspend = amdgpu_pmops_runtime_suspend, 497 .runtime_resume = amdgpu_pmops_runtime_resume, 498 .runtime_idle = amdgpu_pmops_runtime_idle, 499 }; 500 501 static const struct file_operations amdgpu_driver_kms_fops = { 502 .owner = THIS_MODULE, 503 .open = drm_open, 504 .release = drm_release, 505 .unlocked_ioctl = amdgpu_drm_ioctl, 506 .mmap = amdgpu_mmap, 507 .poll = drm_poll, 508 .read = drm_read, 509 #ifdef CONFIG_COMPAT 510 .compat_ioctl = amdgpu_kms_compat_ioctl, 511 #endif 512 }; 513 514 static struct drm_driver kms_driver = { 515 .driver_features = 516 DRIVER_USE_AGP | 517 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | 518 DRIVER_PRIME | DRIVER_RENDER, 519 .dev_priv_size = 0, 520 .load = amdgpu_driver_load_kms, 521 .open = amdgpu_driver_open_kms, 522 .preclose = amdgpu_driver_preclose_kms, 523 .postclose = amdgpu_driver_postclose_kms, 524 .lastclose = amdgpu_driver_lastclose_kms, 525 .set_busid = drm_pci_set_busid, 526 .unload = amdgpu_driver_unload_kms, 527 .get_vblank_counter = amdgpu_get_vblank_counter_kms, 528 .enable_vblank = amdgpu_enable_vblank_kms, 529 .disable_vblank = amdgpu_disable_vblank_kms, 530 .get_vblank_timestamp = amdgpu_get_vblank_timestamp_kms, 531 .get_scanout_position = amdgpu_get_crtc_scanoutpos, 532 #if defined(CONFIG_DEBUG_FS) 533 .debugfs_init = amdgpu_debugfs_init, 534 .debugfs_cleanup = amdgpu_debugfs_cleanup, 535 #endif 536 .irq_preinstall = amdgpu_irq_preinstall, 537 .irq_postinstall = amdgpu_irq_postinstall, 538 .irq_uninstall = amdgpu_irq_uninstall, 539 .irq_handler = amdgpu_irq_handler, 540 .ioctls = amdgpu_ioctls_kms, 541 .gem_free_object_unlocked = amdgpu_gem_object_free, 542 .gem_open_object = amdgpu_gem_object_open, 543 .gem_close_object = amdgpu_gem_object_close, 544 .dumb_create = amdgpu_mode_dumb_create, 545 .dumb_map_offset = amdgpu_mode_dumb_mmap, 546 .dumb_destroy = drm_gem_dumb_destroy, 547 .fops = &amdgpu_driver_kms_fops, 548 549 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 550 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 551 .gem_prime_export = amdgpu_gem_prime_export, 552 .gem_prime_import = drm_gem_prime_import, 553 .gem_prime_pin = amdgpu_gem_prime_pin, 554 .gem_prime_unpin = amdgpu_gem_prime_unpin, 555 .gem_prime_res_obj = amdgpu_gem_prime_res_obj, 556 .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table, 557 .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table, 558 .gem_prime_vmap = amdgpu_gem_prime_vmap, 559 .gem_prime_vunmap = amdgpu_gem_prime_vunmap, 560 561 .name = DRIVER_NAME, 562 .desc = DRIVER_DESC, 563 .date = DRIVER_DATE, 564 .major = KMS_DRIVER_MAJOR, 565 .minor = KMS_DRIVER_MINOR, 566 .patchlevel = KMS_DRIVER_PATCHLEVEL, 567 }; 568 569 static struct drm_driver *driver; 570 static struct pci_driver *pdriver; 571 572 static struct pci_driver amdgpu_kms_pci_driver = { 573 .name = DRIVER_NAME, 574 .id_table = pciidlist, 575 .probe = amdgpu_pci_probe, 576 .remove = amdgpu_pci_remove, 577 .driver.pm = &amdgpu_pm_ops, 578 }; 579 580 581 582 static int __init amdgpu_init(void) 583 { 584 amdgpu_sync_init(); 585 amdgpu_fence_slab_init(); 586 if (vgacon_text_force()) { 587 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); 588 return -EINVAL; 589 } 590 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 591 driver = &kms_driver; 592 pdriver = &amdgpu_kms_pci_driver; 593 driver->driver_features |= DRIVER_MODESET; 594 driver->num_ioctls = amdgpu_max_kms_ioctl; 595 amdgpu_register_atpx_handler(); 596 /* let modprobe override vga console setting */ 597 return drm_pci_init(driver, pdriver); 598 } 599 600 static void __exit amdgpu_exit(void) 601 { 602 amdgpu_amdkfd_fini(); 603 drm_pci_exit(driver, pdriver); 604 amdgpu_unregister_atpx_handler(); 605 amdgpu_sync_fini(); 606 amdgpu_fence_slab_fini(); 607 } 608 609 module_init(amdgpu_init); 610 module_exit(amdgpu_exit); 611 612 MODULE_AUTHOR(DRIVER_AUTHOR); 613 MODULE_DESCRIPTION(DRIVER_DESC); 614 MODULE_LICENSE("GPL and additional rights"); 615