1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/clients/drm_client_setup.h> 27 #include <drm/drm_drv.h> 28 #include <drm/drm_fbdev_ttm.h> 29 #include <drm/drm_gem.h> 30 #include <drm/drm_managed.h> 31 #include <drm/drm_pciids.h> 32 #include <drm/drm_probe_helper.h> 33 #include <drm/drm_vblank.h> 34 35 #include <linux/cc_platform.h> 36 #include <linux/dynamic_debug.h> 37 #include <linux/module.h> 38 #include <linux/mmu_notifier.h> 39 #include <linux/pm_runtime.h> 40 #include <linux/suspend.h> 41 #include <linux/vga_switcheroo.h> 42 43 #include "amdgpu.h" 44 #include "amdgpu_amdkfd.h" 45 #include "amdgpu_dma_buf.h" 46 #include "amdgpu_drv.h" 47 #include "amdgpu_fdinfo.h" 48 #include "amdgpu_irq.h" 49 #include "amdgpu_psp.h" 50 #include "amdgpu_ras.h" 51 #include "amdgpu_reset.h" 52 #include "amdgpu_sched.h" 53 #include "amdgpu_xgmi.h" 54 #include "amdgpu_userq.h" 55 #include "amdgpu_userq_fence.h" 56 #include "../amdxcp/amdgpu_xcp_drv.h" 57 58 /* 59 * KMS wrapper. 60 * - 3.0.0 - initial driver 61 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 62 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 63 * at the end of IBs. 64 * - 3.3.0 - Add VM support for UVD on supported hardware. 65 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 66 * - 3.5.0 - Add support for new UVD_NO_OP register. 67 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 68 * - 3.7.0 - Add support for VCE clock list packet 69 * - 3.8.0 - Add support raster config init in the kernel 70 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 71 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 72 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 73 * - 3.12.0 - Add query for double offchip LDS buffers 74 * - 3.13.0 - Add PRT support 75 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 76 * - 3.15.0 - Export more gpu info for gfx9 77 * - 3.16.0 - Add reserved vmid support 78 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 79 * - 3.18.0 - Export gpu always on cu bitmap 80 * - 3.19.0 - Add support for UVD MJPEG decode 81 * - 3.20.0 - Add support for local BOs 82 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 83 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 84 * - 3.23.0 - Add query for VRAM lost counter 85 * - 3.24.0 - Add high priority compute support for gfx9 86 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 87 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 88 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation. 89 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 90 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 91 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 92 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 93 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 94 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 95 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 96 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 97 * - 3.36.0 - Allow reading more status registers on si/cik 98 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 99 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 100 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 101 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 102 * - 3.41.0 - Add video codec query 103 * - 3.42.0 - Add 16bpc fixed point display support 104 * - 3.43.0 - Add device hot plug/unplug support 105 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 106 * - 3.45.0 - Add context ioctl stable pstate interface 107 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm 108 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags 109 * - 3.48.0 - Add IP discovery version info to HW INFO 110 * - 3.49.0 - Add gang submit into CS IOCTL 111 * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock 112 * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock 113 * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl 114 * 3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields: 115 * tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size, 116 * gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi 117 * 3.53.0 - Support for GFX11 CP GFX shadowing 118 * 3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support 119 * - 3.55.0 - Add AMDGPU_INFO_GPUVM_FAULT query 120 * - 3.56.0 - Update IB start address and size alignment for decode and encode 121 * - 3.57.0 - Compute tunneling on GFX10+ 122 * - 3.58.0 - Add GFX12 DCC support 123 * - 3.59.0 - Cleared VRAM 124 * - 3.60.0 - Add AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE (Vulkan requirement) 125 * - 3.61.0 - Contains fix for RV/PCO compute queues 126 * - 3.62.0 - Add AMDGPU_IDS_FLAGS_MODE_PF, AMDGPU_IDS_FLAGS_MODE_VF & AMDGPU_IDS_FLAGS_MODE_PT 127 * - 3.63.0 - GFX12 display DCC supports 256B max compressed block size 128 * - 3.64.0 - Userq IP support query 129 */ 130 #define KMS_DRIVER_MAJOR 3 131 #define KMS_DRIVER_MINOR 64 132 #define KMS_DRIVER_PATCHLEVEL 0 133 134 /* 135 * amdgpu.debug module options. Are all disabled by default 136 */ 137 enum AMDGPU_DEBUG_MASK { 138 AMDGPU_DEBUG_VM = BIT(0), 139 AMDGPU_DEBUG_LARGEBAR = BIT(1), 140 AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY = BIT(2), 141 AMDGPU_DEBUG_USE_VRAM_FW_BUF = BIT(3), 142 AMDGPU_DEBUG_ENABLE_RAS_ACA = BIT(4), 143 AMDGPU_DEBUG_ENABLE_EXP_RESETS = BIT(5), 144 AMDGPU_DEBUG_DISABLE_GPU_RING_RESET = BIT(6), 145 AMDGPU_DEBUG_SMU_POOL = BIT(7), 146 AMDGPU_DEBUG_VM_USERPTR = BIT(8), 147 AMDGPU_DEBUG_DISABLE_RAS_CE_LOG = BIT(9) 148 }; 149 150 unsigned int amdgpu_vram_limit = UINT_MAX; 151 int amdgpu_vis_vram_limit; 152 int amdgpu_gart_size = -1; /* auto */ 153 int amdgpu_gtt_size = -1; /* auto */ 154 int amdgpu_moverate = -1; /* auto */ 155 int amdgpu_audio = -1; 156 int amdgpu_disp_priority; 157 int amdgpu_hw_i2c; 158 int amdgpu_pcie_gen2 = -1; 159 int amdgpu_msi = -1; 160 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 161 int amdgpu_dpm = -1; 162 int amdgpu_fw_load_type = -1; 163 int amdgpu_aspm = -1; 164 int amdgpu_runtime_pm = -1; 165 uint amdgpu_ip_block_mask = 0xffffffff; 166 int amdgpu_bapm = -1; 167 int amdgpu_deep_color; 168 int amdgpu_vm_size = -1; 169 int amdgpu_vm_fragment_size = -1; 170 int amdgpu_vm_block_size = -1; 171 int amdgpu_vm_fault_stop; 172 int amdgpu_vm_update_mode = -1; 173 int amdgpu_exp_hw_support; 174 int amdgpu_dc = -1; 175 int amdgpu_sched_jobs = 32; 176 int amdgpu_sched_hw_submission = 2; 177 uint amdgpu_pcie_gen_cap; 178 uint amdgpu_pcie_lane_cap; 179 u64 amdgpu_cg_mask = 0xffffffffffffffff; 180 uint amdgpu_pg_mask = 0xffffffff; 181 uint amdgpu_sdma_phase_quantum = 32; 182 char *amdgpu_disable_cu; 183 char *amdgpu_virtual_display; 184 int amdgpu_enforce_isolation = -1; 185 int amdgpu_modeset = -1; 186 187 /* Specifies the default granularity for SVM, used in buffer 188 * migration and restoration of backing memory when handling 189 * recoverable page faults. 190 * 191 * The value is given as log(numPages(buffer)); for a 2 MiB 192 * buffer it computes to be 9 193 */ 194 uint amdgpu_svm_default_granularity = 9; 195 196 /* 197 * OverDrive(bit 14) disabled by default 198 * GFX DCS(bit 19) disabled by default 199 */ 200 uint amdgpu_pp_feature_mask = 0xfff7bfff; 201 uint amdgpu_force_long_training; 202 int amdgpu_lbpw = -1; 203 int amdgpu_compute_multipipe = -1; 204 int amdgpu_gpu_recovery = -1; /* auto */ 205 int amdgpu_emu_mode; 206 uint amdgpu_smu_memory_pool_size; 207 int amdgpu_smu_pptable_id = -1; 208 /* 209 * FBC (bit 0) disabled by default 210 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 211 * - With this, for multiple monitors in sync(e.g. with the same model), 212 * mclk switching will be allowed. And the mclk will be not foced to the 213 * highest. That helps saving some idle power. 214 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 215 * PSR (bit 3) disabled by default 216 * EDP NO POWER SEQUENCING (bit 4) disabled by default 217 */ 218 uint amdgpu_dc_feature_mask = 2; 219 uint amdgpu_dc_debug_mask; 220 uint amdgpu_dc_visual_confirm; 221 int amdgpu_async_gfx_ring = 1; 222 int amdgpu_mcbp = -1; 223 int amdgpu_discovery = -1; 224 int amdgpu_mes; 225 int amdgpu_mes_log_enable = 0; 226 int amdgpu_mes_kiq; 227 int amdgpu_uni_mes = 1; 228 int amdgpu_noretry = -1; 229 int amdgpu_force_asic_type = -1; 230 int amdgpu_tmz = -1; /* auto */ 231 uint amdgpu_freesync_vid_mode; 232 int amdgpu_reset_method = -1; /* auto */ 233 int amdgpu_num_kcq = -1; 234 int amdgpu_smartshift_bias; 235 int amdgpu_use_xgmi_p2p = 1; 236 int amdgpu_vcnfw_log; 237 int amdgpu_sg_display = -1; /* auto */ 238 int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE; 239 int amdgpu_umsch_mm; 240 int amdgpu_seamless = -1; /* auto */ 241 uint amdgpu_debug_mask; 242 int amdgpu_agp = -1; /* auto */ 243 int amdgpu_wbrf = -1; 244 int amdgpu_damage_clips = -1; /* auto */ 245 int amdgpu_umsch_mm_fwlog; 246 int amdgpu_rebar = -1; /* auto */ 247 int amdgpu_user_queue = -1; 248 249 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 250 "DRM_UT_CORE", 251 "DRM_UT_DRIVER", 252 "DRM_UT_KMS", 253 "DRM_UT_PRIME", 254 "DRM_UT_ATOMIC", 255 "DRM_UT_VBL", 256 "DRM_UT_STATE", 257 "DRM_UT_LEASE", 258 "DRM_UT_DP", 259 "DRM_UT_DRMRES"); 260 261 struct amdgpu_mgpu_info mgpu_info = { 262 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 263 }; 264 int amdgpu_ras_enable = -1; 265 uint amdgpu_ras_mask = 0xffffffff; 266 int amdgpu_bad_page_threshold = -1; 267 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 268 .timeout_fatal_disable = false, 269 .period = 0x0, /* default to 0x0 (timeout disable) */ 270 }; 271 272 /** 273 * DOC: vramlimit (int) 274 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 275 */ 276 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 277 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 278 279 /** 280 * DOC: vis_vramlimit (int) 281 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 282 */ 283 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 284 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 285 286 /** 287 * DOC: gartsize (uint) 288 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing. 289 * The default is -1 (The size depends on asic). 290 */ 291 MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)"); 292 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 293 294 /** 295 * DOC: gttsize (int) 296 * Restrict the size of GTT domain (for userspace use) in MiB for testing. 297 * The default is -1 (Use value specified by TTM). 298 * This parameter is deprecated and will be removed in the future. 299 */ 300 MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)"); 301 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 302 303 /** 304 * DOC: moverate (int) 305 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 306 */ 307 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 308 module_param_named(moverate, amdgpu_moverate, int, 0600); 309 310 /** 311 * DOC: audio (int) 312 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 313 */ 314 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 315 module_param_named(audio, amdgpu_audio, int, 0444); 316 317 /** 318 * DOC: disp_priority (int) 319 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 320 */ 321 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 322 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 323 324 /** 325 * DOC: hw_i2c (int) 326 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 327 */ 328 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 329 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 330 331 /** 332 * DOC: pcie_gen2 (int) 333 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 334 */ 335 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 336 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 337 338 /** 339 * DOC: msi (int) 340 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 341 */ 342 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 343 module_param_named(msi, amdgpu_msi, int, 0444); 344 345 /** 346 * DOC: svm_default_granularity (uint) 347 * Used in buffer migration and handling of recoverable page faults 348 */ 349 MODULE_PARM_DESC(svm_default_granularity, "SVM's default granularity in log(2^Pages), default 9 = 2^9 = 2 MiB"); 350 module_param_named(svm_default_granularity, amdgpu_svm_default_granularity, uint, 0644); 351 352 /** 353 * DOC: lockup_timeout (string) 354 * Set GPU scheduler timeout value in ms. 355 * 356 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 357 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 358 * to the default timeout. 359 * 360 * - With one value specified, the setting will apply to all non-compute jobs. 361 * - With multiple values specified, the first one will be for GFX. 362 * The second one is for Compute. The third and fourth ones are 363 * for SDMA and Video. 364 * 365 * By default(with no lockup_timeout settings), the timeout for all jobs is 10000. 366 */ 367 MODULE_PARM_DESC(lockup_timeout, 368 "GPU lockup timeout in ms (default: 10000 for all jobs. " 369 "0: keep default value. negative: infinity timeout), format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 370 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 371 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 372 373 /** 374 * DOC: dpm (int) 375 * Override for dynamic power management setting 376 * (0 = disable, 1 = enable) 377 * The default is -1 (auto). 378 */ 379 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 380 module_param_named(dpm, amdgpu_dpm, int, 0444); 381 382 /** 383 * DOC: fw_load_type (int) 384 * Set different firmware loading type for debugging, if supported. 385 * Set to 0 to force direct loading if supported by the ASIC. Set 386 * to -1 to select the default loading mode for the ASIC, as defined 387 * by the driver. The default is -1 (auto). 388 */ 389 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); 390 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 391 392 /** 393 * DOC: aspm (int) 394 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 395 */ 396 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 397 module_param_named(aspm, amdgpu_aspm, int, 0444); 398 399 /** 400 * DOC: runpm (int) 401 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 402 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 403 * Setting the value to 0 disables this functionality. 404 * Setting the value to -2 is auto enabled with power down when displays are attached. 405 */ 406 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto, -2 = auto with displays)"); 407 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 408 409 /** 410 * DOC: ip_block_mask (uint) 411 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 412 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 413 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 414 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 415 */ 416 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 417 module_param_named_unsafe(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 418 419 /** 420 * DOC: bapm (int) 421 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 422 * The default -1 (auto, enabled) 423 */ 424 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 425 module_param_named(bapm, amdgpu_bapm, int, 0444); 426 427 /** 428 * DOC: deep_color (int) 429 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 430 */ 431 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 432 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 433 434 /** 435 * DOC: vm_size (int) 436 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 437 */ 438 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 439 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 440 441 /** 442 * DOC: vm_fragment_size (int) 443 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 444 */ 445 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 446 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 447 448 /** 449 * DOC: vm_block_size (int) 450 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 451 */ 452 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 453 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 454 455 /** 456 * DOC: vm_fault_stop (int) 457 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 458 */ 459 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 460 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 461 462 /** 463 * DOC: vm_update_mode (int) 464 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 465 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 466 */ 467 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 468 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 469 470 /** 471 * DOC: exp_hw_support (int) 472 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 473 */ 474 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 475 module_param_named_unsafe(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 476 477 /** 478 * DOC: dc (int) 479 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 480 */ 481 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 482 module_param_named(dc, amdgpu_dc, int, 0444); 483 484 /** 485 * DOC: sched_jobs (int) 486 * Override the max number of jobs supported in the sw queue. The default is 32. 487 */ 488 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 489 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 490 491 /** 492 * DOC: sched_hw_submission (int) 493 * Override the max number of HW submissions. The default is 2. 494 */ 495 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 496 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 497 498 /** 499 * DOC: ppfeaturemask (hexint) 500 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 501 * The default is the current set of stable power features. 502 */ 503 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 504 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 505 506 /** 507 * DOC: forcelongtraining (uint) 508 * Force long memory training in resume. 509 * The default is zero, indicates short training in resume. 510 */ 511 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 512 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 513 514 /** 515 * DOC: pcie_gen_cap (uint) 516 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 517 * The default is 0 (automatic for each asic). 518 */ 519 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 520 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 521 522 /** 523 * DOC: pcie_lane_cap (uint) 524 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 525 * The default is 0 (automatic for each asic). 526 */ 527 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 528 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 529 530 /** 531 * DOC: cg_mask (ullong) 532 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 533 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 534 */ 535 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 536 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 537 538 /** 539 * DOC: pg_mask (uint) 540 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 541 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 542 */ 543 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 544 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 545 546 /** 547 * DOC: sdma_phase_quantum (uint) 548 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 549 */ 550 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 551 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 552 553 /** 554 * DOC: disable_cu (charp) 555 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 556 */ 557 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 558 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 559 560 /** 561 * DOC: virtual_display (charp) 562 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 563 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 564 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 565 * device at 26:00.0. The default is NULL. 566 */ 567 MODULE_PARM_DESC(virtual_display, 568 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 569 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 570 571 /** 572 * DOC: lbpw (int) 573 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 574 */ 575 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 576 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 577 578 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 579 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 580 581 /** 582 * DOC: gpu_recovery (int) 583 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 584 */ 585 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 586 module_param_named_unsafe(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 587 588 /** 589 * DOC: emu_mode (int) 590 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 591 */ 592 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 593 module_param_named_unsafe(emu_mode, amdgpu_emu_mode, int, 0444); 594 595 /** 596 * DOC: ras_enable (int) 597 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 598 */ 599 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 600 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 601 602 /** 603 * DOC: ras_mask (uint) 604 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 605 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 606 */ 607 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 608 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 609 610 /** 611 * DOC: timeout_fatal_disable (bool) 612 * Disable Watchdog timeout fatal error event 613 */ 614 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 615 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 616 617 /** 618 * DOC: timeout_period (uint) 619 * Modify the watchdog timeout max_cycles as (1 << period) 620 */ 621 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 622 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 623 624 /** 625 * DOC: si_support (int) 626 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 627 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 628 * otherwise using amdgpu driver. 629 */ 630 #ifdef CONFIG_DRM_AMDGPU_SI 631 632 #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) 633 int amdgpu_si_support; 634 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 635 #else 636 int amdgpu_si_support = 1; 637 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 638 #endif 639 640 module_param_named(si_support, amdgpu_si_support, int, 0444); 641 #endif 642 643 /** 644 * DOC: cik_support (int) 645 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 646 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 647 * otherwise using amdgpu driver. 648 */ 649 #ifdef CONFIG_DRM_AMDGPU_CIK 650 651 #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) 652 int amdgpu_cik_support; 653 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 654 #else 655 int amdgpu_cik_support = 1; 656 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 657 #endif 658 659 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 660 #endif 661 662 /** 663 * DOC: smu_memory_pool_size (uint) 664 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 665 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 666 */ 667 MODULE_PARM_DESC(smu_memory_pool_size, 668 "reserve gtt for smu debug usage, 0 = disable,0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 669 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 670 671 /** 672 * DOC: async_gfx_ring (int) 673 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 674 */ 675 MODULE_PARM_DESC(async_gfx_ring, 676 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 677 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 678 679 /** 680 * DOC: mcbp (int) 681 * It is used to enable mid command buffer preemption. (0 = disabled, 1 = enabled, -1 auto (default)) 682 */ 683 MODULE_PARM_DESC(mcbp, 684 "Enable Mid-command buffer preemption (0 = disabled, 1 = enabled), -1 = auto (default)"); 685 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 686 687 /** 688 * DOC: discovery (int) 689 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 690 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 691 */ 692 MODULE_PARM_DESC(discovery, 693 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 694 module_param_named(discovery, amdgpu_discovery, int, 0444); 695 696 /** 697 * DOC: mes (int) 698 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 699 * (0 = disabled (default), 1 = enabled) 700 */ 701 MODULE_PARM_DESC(mes, 702 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 703 module_param_named(mes, amdgpu_mes, int, 0444); 704 705 /** 706 * DOC: mes_log_enable (int) 707 * Enable Micro Engine Scheduler log. This is used to enable/disable MES internal log. 708 * (0 = disabled (default), 1 = enabled) 709 */ 710 MODULE_PARM_DESC(mes_log_enable, 711 "Enable Micro Engine Scheduler log (0 = disabled (default), 1 = enabled)"); 712 module_param_named(mes_log_enable, amdgpu_mes_log_enable, int, 0444); 713 714 /** 715 * DOC: mes_kiq (int) 716 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq. 717 * (0 = disabled (default), 1 = enabled) 718 */ 719 MODULE_PARM_DESC(mes_kiq, 720 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)"); 721 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444); 722 723 /** 724 * DOC: uni_mes (int) 725 * Enable Unified Micro Engine Scheduler. This is a new engine pipe for unified scheduler. 726 * (0 = disabled (default), 1 = enabled) 727 */ 728 MODULE_PARM_DESC(uni_mes, 729 "Enable Unified Micro Engine Scheduler (0 = disabled, 1 = enabled(default)"); 730 module_param_named(uni_mes, amdgpu_uni_mes, int, 0444); 731 732 /** 733 * DOC: noretry (int) 734 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 735 * do not support per-process XNACK this also disables retry page faults. 736 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 737 */ 738 MODULE_PARM_DESC(noretry, 739 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 740 module_param_named(noretry, amdgpu_noretry, int, 0644); 741 742 /** 743 * DOC: force_asic_type (int) 744 * A non negative value used to specify the asic type for all supported GPUs. 745 */ 746 MODULE_PARM_DESC(force_asic_type, 747 "A non negative value used to specify the asic type for all supported GPUs"); 748 module_param_named_unsafe(force_asic_type, amdgpu_force_asic_type, int, 0444); 749 750 /** 751 * DOC: use_xgmi_p2p (int) 752 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 753 */ 754 MODULE_PARM_DESC(use_xgmi_p2p, 755 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 756 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 757 758 759 #ifdef CONFIG_HSA_AMD 760 /** 761 * DOC: sched_policy (int) 762 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 763 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 764 * assigns queues to HQDs. 765 */ 766 int sched_policy = KFD_SCHED_POLICY_HWS; 767 module_param_unsafe(sched_policy, int, 0444); 768 MODULE_PARM_DESC(sched_policy, 769 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 770 771 /** 772 * DOC: hws_max_conc_proc (int) 773 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 774 * number of VMIDs assigned to the HWS, which is also the default. 775 */ 776 int hws_max_conc_proc = -1; 777 module_param(hws_max_conc_proc, int, 0444); 778 MODULE_PARM_DESC(hws_max_conc_proc, 779 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 780 781 /** 782 * DOC: cwsr_enable (int) 783 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 784 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 785 * disables it. 786 */ 787 int cwsr_enable = 1; 788 module_param(cwsr_enable, int, 0444); 789 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 790 791 /** 792 * DOC: max_num_of_queues_per_device (int) 793 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 794 * is 4096. 795 */ 796 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 797 module_param(max_num_of_queues_per_device, int, 0444); 798 MODULE_PARM_DESC(max_num_of_queues_per_device, 799 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 800 801 /** 802 * DOC: send_sigterm (int) 803 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 804 * but just print errors on dmesg. Setting 1 enables sending sigterm. 805 */ 806 int send_sigterm; 807 module_param(send_sigterm, int, 0444); 808 MODULE_PARM_DESC(send_sigterm, 809 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 810 811 /** 812 * DOC: halt_if_hws_hang (int) 813 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 814 * Setting 1 enables halt on hang. 815 */ 816 int halt_if_hws_hang; 817 module_param_unsafe(halt_if_hws_hang, int, 0644); 818 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 819 820 /** 821 * DOC: hws_gws_support(bool) 822 * Assume that HWS supports GWS barriers regardless of what firmware version 823 * check says. Default value: false (rely on MEC2 firmware version check). 824 */ 825 bool hws_gws_support; 826 module_param_unsafe(hws_gws_support, bool, 0444); 827 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 828 829 /** 830 * DOC: queue_preemption_timeout_ms (int) 831 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 832 */ 833 int queue_preemption_timeout_ms = 9000; 834 module_param(queue_preemption_timeout_ms, int, 0644); 835 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 836 837 /** 838 * DOC: debug_evictions(bool) 839 * Enable extra debug messages to help determine the cause of evictions 840 */ 841 bool debug_evictions; 842 module_param(debug_evictions, bool, 0644); 843 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 844 845 /** 846 * DOC: no_system_mem_limit(bool) 847 * Disable system memory limit, to support multiple process shared memory 848 */ 849 bool no_system_mem_limit; 850 module_param(no_system_mem_limit, bool, 0644); 851 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 852 853 /** 854 * DOC: no_queue_eviction_on_vm_fault (int) 855 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 856 */ 857 int amdgpu_no_queue_eviction_on_vm_fault; 858 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 859 module_param_named_unsafe(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 860 #endif 861 862 /** 863 * DOC: mtype_local (int) 864 */ 865 int amdgpu_mtype_local; 866 MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (0 = MTYPE_RW (default), 1 = MTYPE_NC, 2 = MTYPE_CC)"); 867 module_param_named_unsafe(mtype_local, amdgpu_mtype_local, int, 0444); 868 869 /** 870 * DOC: pcie_p2p (bool) 871 * Enable PCIe P2P (requires large-BAR). Default value: true (on) 872 */ 873 #ifdef CONFIG_HSA_AMD_P2P 874 bool pcie_p2p = true; 875 module_param(pcie_p2p, bool, 0444); 876 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); 877 #endif 878 879 /** 880 * DOC: dcfeaturemask (uint) 881 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 882 * The default is the current set of stable display features. 883 */ 884 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 885 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 886 887 /** 888 * DOC: dcdebugmask (uint) 889 * Display debug options. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 890 */ 891 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 892 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 893 894 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)"); 895 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444); 896 897 /** 898 * DOC: abmlevel (uint) 899 * Override the default ABM (Adaptive Backlight Management) level used for DC 900 * enabled hardware. Requires DMCU to be supported and loaded. 901 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 902 * default. Values 1-4 control the maximum allowable brightness reduction via 903 * the ABM algorithm, with 1 being the least reduction and 4 being the most 904 * reduction. 905 * 906 * Defaults to -1, or auto. Userspace can only override this level after 907 * boot if it's set to auto. 908 */ 909 int amdgpu_dm_abm_level = -1; 910 MODULE_PARM_DESC(abmlevel, 911 "ABM level (0 = off, 1-4 = backlight reduction level, -1 auto (default))"); 912 module_param_named(abmlevel, amdgpu_dm_abm_level, int, 0444); 913 914 int amdgpu_backlight = -1; 915 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 916 module_param_named(backlight, amdgpu_backlight, bint, 0444); 917 918 /** 919 * DOC: damageclips (int) 920 * Enable or disable damage clips support. If damage clips support is disabled, 921 * we will force full frame updates, irrespective of what user space sends to 922 * us. 923 * 924 * Defaults to -1 (where it is enabled unless a PSR-SU display is detected). 925 */ 926 MODULE_PARM_DESC(damageclips, 927 "Damage clips support (0 = disable, 1 = enable, -1 auto (default))"); 928 module_param_named(damageclips, amdgpu_damage_clips, int, 0444); 929 930 /** 931 * DOC: tmz (int) 932 * Trusted Memory Zone (TMZ) is a method to protect data being written 933 * to or read from memory. 934 * 935 * The default value: 0 (off). TODO: change to auto till it is completed. 936 */ 937 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 938 module_param_named(tmz, amdgpu_tmz, int, 0444); 939 940 /** 941 * DOC: freesync_video (uint) 942 * Enable the optimization to adjust front porch timing to achieve seamless 943 * mode change experience when setting a freesync supported mode for which full 944 * modeset is not needed. 945 * 946 * The Display Core will add a set of modes derived from the base FreeSync 947 * video mode into the corresponding connector's mode list based on commonly 948 * used refresh rates and VRR range of the connected display, when users enable 949 * this feature. From the userspace perspective, they can see a seamless mode 950 * change experience when the change between different refresh rates under the 951 * same resolution. Additionally, userspace applications such as Video playback 952 * can read this modeset list and change the refresh rate based on the video 953 * frame rate. Finally, the userspace can also derive an appropriate mode for a 954 * particular refresh rate based on the FreeSync Mode and add it to the 955 * connector's mode list. 956 * 957 * Note: This is an experimental feature. 958 * 959 * The default value: 0 (off). 960 */ 961 MODULE_PARM_DESC( 962 freesync_video, 963 "Adds additional modes via VRR for refresh changes without a full modeset (0 = off (default), 1 = on)"); 964 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); 965 966 /** 967 * DOC: reset_method (int) 968 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 969 */ 970 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 971 module_param_named_unsafe(reset_method, amdgpu_reset_method, int, 0644); 972 973 /** 974 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 975 * threshold value of faulty pages detected by RAS ECC, which may 976 * result in the GPU entering bad status when the number of total 977 * faulty pages by ECC exceeds the threshold value. 978 */ 979 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = threshold determined by a formula, 0 < threshold < max records, user-defined threshold)"); 980 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 981 982 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 983 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 984 985 /** 986 * DOC: vcnfw_log (int) 987 * Enable vcnfw log output for debugging, the default is disabled. 988 */ 989 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 990 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 991 992 /** 993 * DOC: sg_display (int) 994 * Disable S/G (scatter/gather) display (i.e., display from system memory). 995 * This option is only relevant on APUs. Set this option to 0 to disable 996 * S/G display if you experience flickering or other issues under memory 997 * pressure and report the issue. 998 */ 999 MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)"); 1000 module_param_named(sg_display, amdgpu_sg_display, int, 0444); 1001 1002 /** 1003 * DOC: umsch_mm (int) 1004 * Enable Multi Media User Mode Scheduler. This is a HW scheduling engine for VCN and VPE. 1005 * (0 = disabled (default), 1 = enabled) 1006 */ 1007 MODULE_PARM_DESC(umsch_mm, 1008 "Enable Multi Media User Mode Scheduler (0 = disabled (default), 1 = enabled)"); 1009 module_param_named(umsch_mm, amdgpu_umsch_mm, int, 0444); 1010 1011 /** 1012 * DOC: umsch_mm_fwlog (int) 1013 * Enable umschfw log output for debugging, the default is disabled. 1014 */ 1015 MODULE_PARM_DESC(umsch_mm_fwlog, "Enable umschfw log(0 = disable (default value), 1 = enable)"); 1016 module_param_named(umsch_mm_fwlog, amdgpu_umsch_mm_fwlog, int, 0444); 1017 1018 /** 1019 * DOC: smu_pptable_id (int) 1020 * Used to override pptable id. id = 0 use VBIOS pptable. 1021 * id > 0 use the soft pptable with specicfied id. 1022 */ 1023 MODULE_PARM_DESC(smu_pptable_id, 1024 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 1025 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 1026 1027 /** 1028 * DOC: partition_mode (int) 1029 * Used to override the default SPX mode. 1030 */ 1031 MODULE_PARM_DESC( 1032 user_partt_mode, 1033 "specify partition mode to be used (-2 = AMDGPU_AUTO_COMPUTE_PARTITION_MODE(default value) \ 1034 0 = AMDGPU_SPX_PARTITION_MODE, \ 1035 1 = AMDGPU_DPX_PARTITION_MODE, \ 1036 2 = AMDGPU_TPX_PARTITION_MODE, \ 1037 3 = AMDGPU_QPX_PARTITION_MODE, \ 1038 4 = AMDGPU_CPX_PARTITION_MODE)"); 1039 module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint, 0444); 1040 1041 1042 /** 1043 * DOC: enforce_isolation (int) 1044 * enforce process isolation between graphics and compute. 1045 * (-1 = auto, 0 = disable, 1 = enable, 2 = enable legacy mode, 3 = enable without cleaner shader) 1046 */ 1047 module_param_named(enforce_isolation, amdgpu_enforce_isolation, int, 0444); 1048 MODULE_PARM_DESC(enforce_isolation, 1049 "enforce process isolation between graphics and compute. (-1 = auto, 0 = disable, 1 = enable, 2 = enable legacy mode, 3 = enable without cleaner shader)"); 1050 1051 /** 1052 * DOC: modeset (int) 1053 * Override nomodeset (1 = override, -1 = auto). The default is -1 (auto). 1054 */ 1055 MODULE_PARM_DESC(modeset, "Override nomodeset (1 = enable, -1 = auto)"); 1056 module_param_named(modeset, amdgpu_modeset, int, 0444); 1057 1058 /** 1059 * DOC: seamless (int) 1060 * Seamless boot will keep the image on the screen during the boot process. 1061 */ 1062 MODULE_PARM_DESC(seamless, "Seamless boot (-1 = auto (default), 0 = disable, 1 = enable)"); 1063 module_param_named(seamless, amdgpu_seamless, int, 0444); 1064 1065 /** 1066 * DOC: debug_mask (uint) 1067 * Debug options for amdgpu, work as a binary mask with the following options: 1068 * 1069 * - 0x1: Debug VM handling 1070 * - 0x2: Enable simulating large-bar capability on non-large bar system. This 1071 * limits the VRAM size reported to ROCm applications to the visible 1072 * size, usually 256MB. 1073 * - 0x4: Disable GPU soft recovery, always do a full reset 1074 * - 0x8: Use VRAM for firmware loading 1075 * - 0x10: Enable ACA based RAS logging 1076 * - 0x20: Enable experimental resets 1077 * - 0x40: Disable ring resets 1078 * - 0x80: Use VRAM for SMU pool 1079 */ 1080 MODULE_PARM_DESC(debug_mask, "debug options for amdgpu, disabled by default"); 1081 module_param_named_unsafe(debug_mask, amdgpu_debug_mask, uint, 0444); 1082 1083 /** 1084 * DOC: agp (int) 1085 * Enable the AGP aperture. This provides an aperture in the GPU's internal 1086 * address space for direct access to system memory. Note that these accesses 1087 * are non-snooped, so they are only used for access to uncached memory. 1088 */ 1089 MODULE_PARM_DESC(agp, "AGP (-1 = auto (default), 0 = disable, 1 = enable)"); 1090 module_param_named(agp, amdgpu_agp, int, 0444); 1091 1092 /** 1093 * DOC: wbrf (int) 1094 * Enable Wifi RFI interference mitigation feature. 1095 * Due to electrical and mechanical constraints there may be likely interference of 1096 * relatively high-powered harmonics of the (G-)DDR memory clocks with local radio 1097 * module frequency bands used by Wifi 6/6e/7. To mitigate the possible RFI interference, 1098 * with this feature enabled, PMFW will use either “shadowed P-State” or “P-State” based 1099 * on active list of frequencies in-use (to be avoided) as part of initial setting or 1100 * P-state transition. However, there may be potential performance impact with this 1101 * feature enabled. 1102 * (0 = disabled, 1 = enabled, -1 = auto (default setting, will be enabled if supported)) 1103 */ 1104 MODULE_PARM_DESC(wbrf, 1105 "Enable Wifi RFI interference mitigation (0 = disabled, 1 = enabled, -1 = auto(default)"); 1106 module_param_named(wbrf, amdgpu_wbrf, int, 0444); 1107 1108 /** 1109 * DOC: rebar (int) 1110 * Allow BAR resizing. Disable this to prevent the driver from attempting 1111 * to resize the BAR if the GPU supports it and there is available MMIO space. 1112 * Note that this just prevents the driver from resizing the BAR. The BIOS 1113 * may have already resized the BAR at boot time. 1114 */ 1115 MODULE_PARM_DESC(rebar, "Resizable BAR (-1 = auto (default), 0 = disable, 1 = enable)"); 1116 module_param_named(rebar, amdgpu_rebar, int, 0444); 1117 1118 /** 1119 * DOC: user_queue (int) 1120 * Enable user queues on systems that support user queues. Possible values: 1121 * 1122 * - -1 = auto (ASIC specific default) 1123 * - 0 = user queues disabled 1124 * - 1 = user queues enabled and kernel queues enabled (if supported) 1125 * - 2 = user queues enabled and kernel queues disabled 1126 */ 1127 MODULE_PARM_DESC(user_queue, "Enable user queues (-1 = auto (default), 0 = disable, 1 = enable, 2 = enable UQs and disable KQs)"); 1128 module_param_named(user_queue, amdgpu_user_queue, int, 0444); 1129 1130 /* These devices are not supported by amdgpu. 1131 * They are supported by the mach64, r128, radeon drivers 1132 */ 1133 static const u16 amdgpu_unsupported_pciidlist[] = { 1134 /* mach64 */ 1135 0x4354, 1136 0x4358, 1137 0x4554, 1138 0x4742, 1139 0x4744, 1140 0x4749, 1141 0x474C, 1142 0x474D, 1143 0x474E, 1144 0x474F, 1145 0x4750, 1146 0x4751, 1147 0x4752, 1148 0x4753, 1149 0x4754, 1150 0x4755, 1151 0x4756, 1152 0x4757, 1153 0x4758, 1154 0x4759, 1155 0x475A, 1156 0x4C42, 1157 0x4C44, 1158 0x4C47, 1159 0x4C49, 1160 0x4C4D, 1161 0x4C4E, 1162 0x4C50, 1163 0x4C51, 1164 0x4C52, 1165 0x4C53, 1166 0x5654, 1167 0x5655, 1168 0x5656, 1169 /* r128 */ 1170 0x4c45, 1171 0x4c46, 1172 0x4d46, 1173 0x4d4c, 1174 0x5041, 1175 0x5042, 1176 0x5043, 1177 0x5044, 1178 0x5045, 1179 0x5046, 1180 0x5047, 1181 0x5048, 1182 0x5049, 1183 0x504A, 1184 0x504B, 1185 0x504C, 1186 0x504D, 1187 0x504E, 1188 0x504F, 1189 0x5050, 1190 0x5051, 1191 0x5052, 1192 0x5053, 1193 0x5054, 1194 0x5055, 1195 0x5056, 1196 0x5057, 1197 0x5058, 1198 0x5245, 1199 0x5246, 1200 0x5247, 1201 0x524b, 1202 0x524c, 1203 0x534d, 1204 0x5446, 1205 0x544C, 1206 0x5452, 1207 /* radeon */ 1208 0x3150, 1209 0x3151, 1210 0x3152, 1211 0x3154, 1212 0x3155, 1213 0x3E50, 1214 0x3E54, 1215 0x4136, 1216 0x4137, 1217 0x4144, 1218 0x4145, 1219 0x4146, 1220 0x4147, 1221 0x4148, 1222 0x4149, 1223 0x414A, 1224 0x414B, 1225 0x4150, 1226 0x4151, 1227 0x4152, 1228 0x4153, 1229 0x4154, 1230 0x4155, 1231 0x4156, 1232 0x4237, 1233 0x4242, 1234 0x4336, 1235 0x4337, 1236 0x4437, 1237 0x4966, 1238 0x4967, 1239 0x4A48, 1240 0x4A49, 1241 0x4A4A, 1242 0x4A4B, 1243 0x4A4C, 1244 0x4A4D, 1245 0x4A4E, 1246 0x4A4F, 1247 0x4A50, 1248 0x4A54, 1249 0x4B48, 1250 0x4B49, 1251 0x4B4A, 1252 0x4B4B, 1253 0x4B4C, 1254 0x4C57, 1255 0x4C58, 1256 0x4C59, 1257 0x4C5A, 1258 0x4C64, 1259 0x4C66, 1260 0x4C67, 1261 0x4E44, 1262 0x4E45, 1263 0x4E46, 1264 0x4E47, 1265 0x4E48, 1266 0x4E49, 1267 0x4E4A, 1268 0x4E4B, 1269 0x4E50, 1270 0x4E51, 1271 0x4E52, 1272 0x4E53, 1273 0x4E54, 1274 0x4E56, 1275 0x5144, 1276 0x5145, 1277 0x5146, 1278 0x5147, 1279 0x5148, 1280 0x514C, 1281 0x514D, 1282 0x5157, 1283 0x5158, 1284 0x5159, 1285 0x515A, 1286 0x515E, 1287 0x5460, 1288 0x5462, 1289 0x5464, 1290 0x5548, 1291 0x5549, 1292 0x554A, 1293 0x554B, 1294 0x554C, 1295 0x554D, 1296 0x554E, 1297 0x554F, 1298 0x5550, 1299 0x5551, 1300 0x5552, 1301 0x5554, 1302 0x564A, 1303 0x564B, 1304 0x564F, 1305 0x5652, 1306 0x5653, 1307 0x5657, 1308 0x5834, 1309 0x5835, 1310 0x5954, 1311 0x5955, 1312 0x5974, 1313 0x5975, 1314 0x5960, 1315 0x5961, 1316 0x5962, 1317 0x5964, 1318 0x5965, 1319 0x5969, 1320 0x5a41, 1321 0x5a42, 1322 0x5a61, 1323 0x5a62, 1324 0x5b60, 1325 0x5b62, 1326 0x5b63, 1327 0x5b64, 1328 0x5b65, 1329 0x5c61, 1330 0x5c63, 1331 0x5d48, 1332 0x5d49, 1333 0x5d4a, 1334 0x5d4c, 1335 0x5d4d, 1336 0x5d4e, 1337 0x5d4f, 1338 0x5d50, 1339 0x5d52, 1340 0x5d57, 1341 0x5e48, 1342 0x5e4a, 1343 0x5e4b, 1344 0x5e4c, 1345 0x5e4d, 1346 0x5e4f, 1347 0x6700, 1348 0x6701, 1349 0x6702, 1350 0x6703, 1351 0x6704, 1352 0x6705, 1353 0x6706, 1354 0x6707, 1355 0x6708, 1356 0x6709, 1357 0x6718, 1358 0x6719, 1359 0x671c, 1360 0x671d, 1361 0x671f, 1362 0x6720, 1363 0x6721, 1364 0x6722, 1365 0x6723, 1366 0x6724, 1367 0x6725, 1368 0x6726, 1369 0x6727, 1370 0x6728, 1371 0x6729, 1372 0x6738, 1373 0x6739, 1374 0x673e, 1375 0x6740, 1376 0x6741, 1377 0x6742, 1378 0x6743, 1379 0x6744, 1380 0x6745, 1381 0x6746, 1382 0x6747, 1383 0x6748, 1384 0x6749, 1385 0x674A, 1386 0x6750, 1387 0x6751, 1388 0x6758, 1389 0x6759, 1390 0x675B, 1391 0x675D, 1392 0x675F, 1393 0x6760, 1394 0x6761, 1395 0x6762, 1396 0x6763, 1397 0x6764, 1398 0x6765, 1399 0x6766, 1400 0x6767, 1401 0x6768, 1402 0x6770, 1403 0x6771, 1404 0x6772, 1405 0x6778, 1406 0x6779, 1407 0x677B, 1408 0x6840, 1409 0x6841, 1410 0x6842, 1411 0x6843, 1412 0x6849, 1413 0x684C, 1414 0x6850, 1415 0x6858, 1416 0x6859, 1417 0x6880, 1418 0x6888, 1419 0x6889, 1420 0x688A, 1421 0x688C, 1422 0x688D, 1423 0x6898, 1424 0x6899, 1425 0x689b, 1426 0x689c, 1427 0x689d, 1428 0x689e, 1429 0x68a0, 1430 0x68a1, 1431 0x68a8, 1432 0x68a9, 1433 0x68b0, 1434 0x68b8, 1435 0x68b9, 1436 0x68ba, 1437 0x68be, 1438 0x68bf, 1439 0x68c0, 1440 0x68c1, 1441 0x68c7, 1442 0x68c8, 1443 0x68c9, 1444 0x68d8, 1445 0x68d9, 1446 0x68da, 1447 0x68de, 1448 0x68e0, 1449 0x68e1, 1450 0x68e4, 1451 0x68e5, 1452 0x68e8, 1453 0x68e9, 1454 0x68f1, 1455 0x68f2, 1456 0x68f8, 1457 0x68f9, 1458 0x68fa, 1459 0x68fe, 1460 0x7100, 1461 0x7101, 1462 0x7102, 1463 0x7103, 1464 0x7104, 1465 0x7105, 1466 0x7106, 1467 0x7108, 1468 0x7109, 1469 0x710A, 1470 0x710B, 1471 0x710C, 1472 0x710E, 1473 0x710F, 1474 0x7140, 1475 0x7141, 1476 0x7142, 1477 0x7143, 1478 0x7144, 1479 0x7145, 1480 0x7146, 1481 0x7147, 1482 0x7149, 1483 0x714A, 1484 0x714B, 1485 0x714C, 1486 0x714D, 1487 0x714E, 1488 0x714F, 1489 0x7151, 1490 0x7152, 1491 0x7153, 1492 0x715E, 1493 0x715F, 1494 0x7180, 1495 0x7181, 1496 0x7183, 1497 0x7186, 1498 0x7187, 1499 0x7188, 1500 0x718A, 1501 0x718B, 1502 0x718C, 1503 0x718D, 1504 0x718F, 1505 0x7193, 1506 0x7196, 1507 0x719B, 1508 0x719F, 1509 0x71C0, 1510 0x71C1, 1511 0x71C2, 1512 0x71C3, 1513 0x71C4, 1514 0x71C5, 1515 0x71C6, 1516 0x71C7, 1517 0x71CD, 1518 0x71CE, 1519 0x71D2, 1520 0x71D4, 1521 0x71D5, 1522 0x71D6, 1523 0x71DA, 1524 0x71DE, 1525 0x7200, 1526 0x7210, 1527 0x7211, 1528 0x7240, 1529 0x7243, 1530 0x7244, 1531 0x7245, 1532 0x7246, 1533 0x7247, 1534 0x7248, 1535 0x7249, 1536 0x724A, 1537 0x724B, 1538 0x724C, 1539 0x724D, 1540 0x724E, 1541 0x724F, 1542 0x7280, 1543 0x7281, 1544 0x7283, 1545 0x7284, 1546 0x7287, 1547 0x7288, 1548 0x7289, 1549 0x728B, 1550 0x728C, 1551 0x7290, 1552 0x7291, 1553 0x7293, 1554 0x7297, 1555 0x7834, 1556 0x7835, 1557 0x791e, 1558 0x791f, 1559 0x793f, 1560 0x7941, 1561 0x7942, 1562 0x796c, 1563 0x796d, 1564 0x796e, 1565 0x796f, 1566 0x9400, 1567 0x9401, 1568 0x9402, 1569 0x9403, 1570 0x9405, 1571 0x940A, 1572 0x940B, 1573 0x940F, 1574 0x94A0, 1575 0x94A1, 1576 0x94A3, 1577 0x94B1, 1578 0x94B3, 1579 0x94B4, 1580 0x94B5, 1581 0x94B9, 1582 0x9440, 1583 0x9441, 1584 0x9442, 1585 0x9443, 1586 0x9444, 1587 0x9446, 1588 0x944A, 1589 0x944B, 1590 0x944C, 1591 0x944E, 1592 0x9450, 1593 0x9452, 1594 0x9456, 1595 0x945A, 1596 0x945B, 1597 0x945E, 1598 0x9460, 1599 0x9462, 1600 0x946A, 1601 0x946B, 1602 0x947A, 1603 0x947B, 1604 0x9480, 1605 0x9487, 1606 0x9488, 1607 0x9489, 1608 0x948A, 1609 0x948F, 1610 0x9490, 1611 0x9491, 1612 0x9495, 1613 0x9498, 1614 0x949C, 1615 0x949E, 1616 0x949F, 1617 0x94C0, 1618 0x94C1, 1619 0x94C3, 1620 0x94C4, 1621 0x94C5, 1622 0x94C6, 1623 0x94C7, 1624 0x94C8, 1625 0x94C9, 1626 0x94CB, 1627 0x94CC, 1628 0x94CD, 1629 0x9500, 1630 0x9501, 1631 0x9504, 1632 0x9505, 1633 0x9506, 1634 0x9507, 1635 0x9508, 1636 0x9509, 1637 0x950F, 1638 0x9511, 1639 0x9515, 1640 0x9517, 1641 0x9519, 1642 0x9540, 1643 0x9541, 1644 0x9542, 1645 0x954E, 1646 0x954F, 1647 0x9552, 1648 0x9553, 1649 0x9555, 1650 0x9557, 1651 0x955f, 1652 0x9580, 1653 0x9581, 1654 0x9583, 1655 0x9586, 1656 0x9587, 1657 0x9588, 1658 0x9589, 1659 0x958A, 1660 0x958B, 1661 0x958C, 1662 0x958D, 1663 0x958E, 1664 0x958F, 1665 0x9590, 1666 0x9591, 1667 0x9593, 1668 0x9595, 1669 0x9596, 1670 0x9597, 1671 0x9598, 1672 0x9599, 1673 0x959B, 1674 0x95C0, 1675 0x95C2, 1676 0x95C4, 1677 0x95C5, 1678 0x95C6, 1679 0x95C7, 1680 0x95C9, 1681 0x95CC, 1682 0x95CD, 1683 0x95CE, 1684 0x95CF, 1685 0x9610, 1686 0x9611, 1687 0x9612, 1688 0x9613, 1689 0x9614, 1690 0x9615, 1691 0x9616, 1692 0x9640, 1693 0x9641, 1694 0x9642, 1695 0x9643, 1696 0x9644, 1697 0x9645, 1698 0x9647, 1699 0x9648, 1700 0x9649, 1701 0x964a, 1702 0x964b, 1703 0x964c, 1704 0x964e, 1705 0x964f, 1706 0x9710, 1707 0x9711, 1708 0x9712, 1709 0x9713, 1710 0x9714, 1711 0x9715, 1712 0x9802, 1713 0x9803, 1714 0x9804, 1715 0x9805, 1716 0x9806, 1717 0x9807, 1718 0x9808, 1719 0x9809, 1720 0x980A, 1721 0x9900, 1722 0x9901, 1723 0x9903, 1724 0x9904, 1725 0x9905, 1726 0x9906, 1727 0x9907, 1728 0x9908, 1729 0x9909, 1730 0x990A, 1731 0x990B, 1732 0x990C, 1733 0x990D, 1734 0x990E, 1735 0x990F, 1736 0x9910, 1737 0x9913, 1738 0x9917, 1739 0x9918, 1740 0x9919, 1741 0x9990, 1742 0x9991, 1743 0x9992, 1744 0x9993, 1745 0x9994, 1746 0x9995, 1747 0x9996, 1748 0x9997, 1749 0x9998, 1750 0x9999, 1751 0x999A, 1752 0x999B, 1753 0x999C, 1754 0x999D, 1755 0x99A0, 1756 0x99A2, 1757 0x99A4, 1758 /* radeon secondary ids */ 1759 0x3171, 1760 0x3e70, 1761 0x4164, 1762 0x4165, 1763 0x4166, 1764 0x4168, 1765 0x4170, 1766 0x4171, 1767 0x4172, 1768 0x4173, 1769 0x496e, 1770 0x4a69, 1771 0x4a6a, 1772 0x4a6b, 1773 0x4a70, 1774 0x4a74, 1775 0x4b69, 1776 0x4b6b, 1777 0x4b6c, 1778 0x4c6e, 1779 0x4e64, 1780 0x4e65, 1781 0x4e66, 1782 0x4e67, 1783 0x4e68, 1784 0x4e69, 1785 0x4e6a, 1786 0x4e71, 1787 0x4f73, 1788 0x5569, 1789 0x556b, 1790 0x556d, 1791 0x556f, 1792 0x5571, 1793 0x5854, 1794 0x5874, 1795 0x5940, 1796 0x5941, 1797 0x5b70, 1798 0x5b72, 1799 0x5b73, 1800 0x5b74, 1801 0x5b75, 1802 0x5d44, 1803 0x5d45, 1804 0x5d6d, 1805 0x5d6f, 1806 0x5d72, 1807 0x5d77, 1808 0x5e6b, 1809 0x5e6d, 1810 0x7120, 1811 0x7124, 1812 0x7129, 1813 0x712e, 1814 0x712f, 1815 0x7162, 1816 0x7163, 1817 0x7166, 1818 0x7167, 1819 0x7172, 1820 0x7173, 1821 0x71a0, 1822 0x71a1, 1823 0x71a3, 1824 0x71a7, 1825 0x71bb, 1826 0x71e0, 1827 0x71e1, 1828 0x71e2, 1829 0x71e6, 1830 0x71e7, 1831 0x71f2, 1832 0x7269, 1833 0x726b, 1834 0x726e, 1835 0x72a0, 1836 0x72a8, 1837 0x72b1, 1838 0x72b3, 1839 0x793f, 1840 }; 1841 1842 static const struct pci_device_id pciidlist[] = { 1843 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1844 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1845 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1846 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1847 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1848 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1849 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1850 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1851 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1852 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1853 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1854 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1855 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1856 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1857 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1858 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1859 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1860 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1861 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1862 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1863 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1864 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1865 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1866 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1867 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1868 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1869 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1870 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1871 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1872 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1873 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1874 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1875 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1876 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1877 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1878 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1879 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1880 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1881 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1882 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1883 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1884 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1885 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1886 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1887 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1888 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1889 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1890 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1891 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1892 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1893 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1894 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1895 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1896 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1897 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1898 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1899 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1900 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1901 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1902 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1903 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1904 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1905 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1906 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1907 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1908 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1909 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1910 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1911 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1912 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1913 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1914 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1915 /* Kaveri */ 1916 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1917 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1918 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1919 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1920 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1921 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1922 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1923 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1924 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1925 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1926 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1927 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1928 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1929 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1930 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1931 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1932 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1933 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1934 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1935 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1936 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1937 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1938 /* Bonaire */ 1939 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1940 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1941 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1942 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1943 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1944 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1945 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1946 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1947 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1948 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1949 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1950 /* Hawaii */ 1951 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1952 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1953 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1954 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1955 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1956 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1957 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1958 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1959 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1960 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1961 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1962 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1963 /* Kabini */ 1964 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1965 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1966 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1967 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1968 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1969 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1970 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1971 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1972 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1973 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1974 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1975 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1976 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1977 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1978 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1979 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1980 /* mullins */ 1981 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1982 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1983 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1984 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1985 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1986 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1987 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1988 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1989 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1990 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1991 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1992 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1993 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1994 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1995 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1996 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1997 /* topaz */ 1998 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1999 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 2000 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 2001 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 2002 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 2003 /* tonga */ 2004 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2005 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2006 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2007 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2008 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2009 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2010 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2011 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2012 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2013 /* fiji */ 2014 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 2015 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 2016 /* carrizo */ 2017 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 2018 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 2019 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 2020 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 2021 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 2022 /* stoney */ 2023 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 2024 /* Polaris11 */ 2025 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2026 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2027 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2028 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2029 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2030 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2031 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2032 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2033 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2034 /* Polaris10 */ 2035 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2036 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2037 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2038 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2039 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2040 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2041 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2042 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2043 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2044 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2045 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2046 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2047 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2048 /* Polaris12 */ 2049 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2050 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2051 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2052 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2053 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2054 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2055 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2056 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2057 /* VEGAM */ 2058 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 2059 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 2060 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 2061 /* Vega 10 */ 2062 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2063 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2064 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2065 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2066 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2067 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2068 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2069 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2070 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2071 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2072 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2073 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2074 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2075 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2076 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2077 /* Vega 12 */ 2078 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2079 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2080 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2081 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2082 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2083 /* Vega 20 */ 2084 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2085 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2086 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2087 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2088 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2089 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2090 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2091 /* Raven */ 2092 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 2093 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 2094 /* Arcturus */ 2095 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2096 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2097 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2098 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2099 /* Navi10 */ 2100 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2101 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2102 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2103 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2104 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2105 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2106 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2107 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2108 /* Navi14 */ 2109 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2110 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2111 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2112 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2113 2114 /* Renoir */ 2115 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2116 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2117 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2118 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2119 2120 /* Navi12 */ 2121 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 2122 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 2123 2124 /* Sienna_Cichlid */ 2125 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2126 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2127 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2128 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2129 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2130 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2131 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2132 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2133 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2134 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2135 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2136 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2137 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2138 2139 /* Yellow Carp */ 2140 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 2141 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 2142 2143 /* Navy_Flounder */ 2144 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2145 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2146 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2147 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2148 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2149 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2150 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2151 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2152 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2153 2154 /* DIMGREY_CAVEFISH */ 2155 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2156 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2157 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2158 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2159 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2160 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2161 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2162 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2163 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2164 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2165 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2166 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2167 2168 /* Aldebaran */ 2169 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2170 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2171 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2172 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2173 2174 /* CYAN_SKILLFISH */ 2175 {0x1002, 0x13DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2176 {0x1002, 0x13F9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2177 {0x1002, 0x13FA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2178 {0x1002, 0x13FB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2179 {0x1002, 0x13FC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2180 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2181 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2182 2183 /* BEIGE_GOBY */ 2184 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2185 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2186 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2187 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2188 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2189 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2190 2191 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2192 .class = PCI_CLASS_DISPLAY_VGA << 8, 2193 .class_mask = 0xffffff, 2194 .driver_data = CHIP_IP_DISCOVERY }, 2195 2196 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2197 .class = PCI_CLASS_DISPLAY_OTHER << 8, 2198 .class_mask = 0xffffff, 2199 .driver_data = CHIP_IP_DISCOVERY }, 2200 2201 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2202 .class = PCI_CLASS_ACCELERATOR_PROCESSING << 8, 2203 .class_mask = 0xffffff, 2204 .driver_data = CHIP_IP_DISCOVERY }, 2205 2206 {0, 0, 0} 2207 }; 2208 2209 MODULE_DEVICE_TABLE(pci, pciidlist); 2210 2211 static const struct amdgpu_asic_type_quirk asic_type_quirks[] = { 2212 /* differentiate between P10 and P11 asics with the same DID */ 2213 {0x67FF, 0xE3, CHIP_POLARIS10}, 2214 {0x67FF, 0xE7, CHIP_POLARIS10}, 2215 {0x67FF, 0xF3, CHIP_POLARIS10}, 2216 {0x67FF, 0xF7, CHIP_POLARIS10}, 2217 }; 2218 2219 static const struct drm_driver amdgpu_kms_driver; 2220 2221 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 2222 { 2223 struct pci_dev *p = NULL; 2224 int i; 2225 2226 /* 0 - GPU 2227 * 1 - audio 2228 * 2 - USB 2229 * 3 - UCSI 2230 */ 2231 for (i = 1; i < 4; i++) { 2232 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 2233 adev->pdev->bus->number, i); 2234 if (p) { 2235 pm_runtime_get_sync(&p->dev); 2236 pm_runtime_mark_last_busy(&p->dev); 2237 pm_runtime_put_autosuspend(&p->dev); 2238 pci_dev_put(p); 2239 } 2240 } 2241 } 2242 2243 static void amdgpu_init_debug_options(struct amdgpu_device *adev) 2244 { 2245 if (amdgpu_debug_mask & AMDGPU_DEBUG_VM) { 2246 pr_info("debug: VM handling debug enabled\n"); 2247 adev->debug_vm = true; 2248 } 2249 2250 if (amdgpu_debug_mask & AMDGPU_DEBUG_LARGEBAR) { 2251 pr_info("debug: enabled simulating large-bar capability on non-large bar system\n"); 2252 adev->debug_largebar = true; 2253 } 2254 2255 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY) { 2256 pr_info("debug: soft reset for GPU recovery disabled\n"); 2257 adev->debug_disable_soft_recovery = true; 2258 } 2259 2260 if (amdgpu_debug_mask & AMDGPU_DEBUG_USE_VRAM_FW_BUF) { 2261 pr_info("debug: place fw in vram for frontdoor loading\n"); 2262 adev->debug_use_vram_fw_buf = true; 2263 } 2264 2265 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_RAS_ACA) { 2266 pr_info("debug: enable RAS ACA\n"); 2267 adev->debug_enable_ras_aca = true; 2268 } 2269 2270 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_EXP_RESETS) { 2271 pr_info("debug: enable experimental reset features\n"); 2272 adev->debug_exp_resets = true; 2273 } 2274 2275 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_RING_RESET) { 2276 pr_info("debug: ring reset disabled\n"); 2277 adev->debug_disable_gpu_ring_reset = true; 2278 } 2279 if (amdgpu_debug_mask & AMDGPU_DEBUG_SMU_POOL) { 2280 pr_info("debug: use vram for smu pool\n"); 2281 adev->pm.smu_debug_mask |= SMU_DEBUG_POOL_USE_VRAM; 2282 } 2283 if (amdgpu_debug_mask & AMDGPU_DEBUG_VM_USERPTR) { 2284 pr_info("debug: VM mode debug for userptr is enabled\n"); 2285 adev->debug_vm_userptr = true; 2286 } 2287 2288 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_RAS_CE_LOG) { 2289 pr_info("debug: disable kernel logs of correctable errors\n"); 2290 adev->debug_disable_ce_logs = true; 2291 } 2292 } 2293 2294 static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long flags) 2295 { 2296 int i; 2297 2298 for (i = 0; i < ARRAY_SIZE(asic_type_quirks); i++) { 2299 if (pdev->device == asic_type_quirks[i].device && 2300 pdev->revision == asic_type_quirks[i].revision) { 2301 flags &= ~AMD_ASIC_MASK; 2302 flags |= asic_type_quirks[i].type; 2303 break; 2304 } 2305 } 2306 2307 return flags; 2308 } 2309 2310 static int amdgpu_pci_probe(struct pci_dev *pdev, 2311 const struct pci_device_id *ent) 2312 { 2313 struct drm_device *ddev; 2314 struct amdgpu_device *adev; 2315 unsigned long flags = ent->driver_data; 2316 int ret, retry = 0, i; 2317 bool supports_atomic = false; 2318 2319 if ((pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA || 2320 (pdev->class >> 8) == PCI_CLASS_DISPLAY_OTHER) { 2321 if (drm_firmware_drivers_only() && amdgpu_modeset == -1) 2322 return -EINVAL; 2323 } 2324 2325 /* skip devices which are owned by radeon */ 2326 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2327 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2328 return -ENODEV; 2329 } 2330 2331 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) 2332 amdgpu_aspm = 0; 2333 2334 if (amdgpu_virtual_display || 2335 amdgpu_device_asic_has_dc_support(pdev, flags & AMD_ASIC_MASK)) 2336 supports_atomic = true; 2337 2338 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2339 DRM_INFO("This hardware requires experimental hardware support.\n" 2340 "See modparam exp_hw_support\n"); 2341 return -ENODEV; 2342 } 2343 2344 flags = amdgpu_fix_asic_type(pdev, flags); 2345 2346 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2347 * however, SME requires an indirect IOMMU mapping because the encryption 2348 * bit is beyond the DMA mask of the chip. 2349 */ 2350 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2351 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2352 dev_info(&pdev->dev, 2353 "SME is not compatible with RAVEN\n"); 2354 return -ENOTSUPP; 2355 } 2356 2357 switch (flags & AMD_ASIC_MASK) { 2358 case CHIP_TAHITI: 2359 case CHIP_PITCAIRN: 2360 case CHIP_VERDE: 2361 case CHIP_OLAND: 2362 case CHIP_HAINAN: 2363 #ifdef CONFIG_DRM_AMDGPU_SI 2364 if (!amdgpu_si_support) { 2365 dev_info(&pdev->dev, 2366 "SI support provided by radeon.\n"); 2367 dev_info(&pdev->dev, 2368 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 2369 ); 2370 return -ENODEV; 2371 } 2372 break; 2373 #else 2374 dev_info(&pdev->dev, "amdgpu is built without SI support.\n"); 2375 return -ENODEV; 2376 #endif 2377 case CHIP_KAVERI: 2378 case CHIP_BONAIRE: 2379 case CHIP_HAWAII: 2380 case CHIP_KABINI: 2381 case CHIP_MULLINS: 2382 #ifdef CONFIG_DRM_AMDGPU_CIK 2383 if (!amdgpu_cik_support) { 2384 dev_info(&pdev->dev, 2385 "CIK support provided by radeon.\n"); 2386 dev_info(&pdev->dev, 2387 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 2388 ); 2389 return -ENODEV; 2390 } 2391 break; 2392 #else 2393 dev_info(&pdev->dev, "amdgpu is built without CIK support.\n"); 2394 return -ENODEV; 2395 #endif 2396 default: 2397 break; 2398 } 2399 2400 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2401 if (IS_ERR(adev)) 2402 return PTR_ERR(adev); 2403 2404 adev->dev = &pdev->dev; 2405 adev->pdev = pdev; 2406 ddev = adev_to_drm(adev); 2407 2408 if (!supports_atomic) 2409 ddev->driver_features &= ~DRIVER_ATOMIC; 2410 2411 ret = pci_enable_device(pdev); 2412 if (ret) 2413 return ret; 2414 2415 pci_set_drvdata(pdev, ddev); 2416 2417 amdgpu_init_debug_options(adev); 2418 2419 ret = amdgpu_driver_load_kms(adev, flags); 2420 if (ret) 2421 goto err_pci; 2422 2423 retry_init: 2424 ret = drm_dev_register(ddev, flags); 2425 if (ret == -EAGAIN && ++retry <= 3) { 2426 DRM_INFO("retry init %d\n", retry); 2427 /* Don't request EX mode too frequently which is attacking */ 2428 msleep(5000); 2429 goto retry_init; 2430 } else if (ret) { 2431 goto err_pci; 2432 } 2433 2434 ret = amdgpu_xcp_dev_register(adev, ent); 2435 if (ret) 2436 goto err_pci; 2437 2438 ret = amdgpu_amdkfd_drm_client_create(adev); 2439 if (ret) 2440 goto err_pci; 2441 2442 /* 2443 * 1. don't init fbdev on hw without DCE 2444 * 2. don't init fbdev if there are no connectors 2445 */ 2446 if (adev->mode_info.mode_config_initialized && 2447 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2448 const struct drm_format_info *format; 2449 2450 /* select 8 bpp console on low vram cards */ 2451 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2452 format = drm_format_info(DRM_FORMAT_C8); 2453 else 2454 format = NULL; 2455 2456 drm_client_setup(adev_to_drm(adev), format); 2457 } 2458 2459 ret = amdgpu_debugfs_init(adev); 2460 if (ret) 2461 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2462 2463 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2464 /* only need to skip on ATPX */ 2465 if (amdgpu_device_supports_px(adev)) 2466 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2467 /* we want direct complete for BOCO */ 2468 if (amdgpu_device_supports_boco(adev)) 2469 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2470 DPM_FLAG_SMART_SUSPEND | 2471 DPM_FLAG_MAY_SKIP_RESUME); 2472 pm_runtime_use_autosuspend(ddev->dev); 2473 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2474 2475 pm_runtime_allow(ddev->dev); 2476 2477 pm_runtime_mark_last_busy(ddev->dev); 2478 pm_runtime_put_autosuspend(ddev->dev); 2479 2480 pci_wake_from_d3(pdev, TRUE); 2481 2482 /* 2483 * For runpm implemented via BACO, PMFW will handle the 2484 * timing for BACO in and out: 2485 * - put ASIC into BACO state only when both video and 2486 * audio functions are in D3 state. 2487 * - pull ASIC out of BACO state when either video or 2488 * audio function is in D0 state. 2489 * Also, at startup, PMFW assumes both functions are in 2490 * D0 state. 2491 * 2492 * So if snd driver was loaded prior to amdgpu driver 2493 * and audio function was put into D3 state, there will 2494 * be no PMFW-aware D-state transition(D0->D3) on runpm 2495 * suspend. Thus the BACO will be not correctly kicked in. 2496 * 2497 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2498 * into D0 state. Then there will be a PMFW-aware D-state 2499 * transition(D0->D3) on runpm suspend. 2500 */ 2501 if (amdgpu_device_supports_baco(adev) && 2502 !(adev->flags & AMD_IS_APU) && 2503 adev->asic_type >= CHIP_NAVI10) 2504 amdgpu_get_secondary_funcs(adev); 2505 } 2506 2507 return 0; 2508 2509 err_pci: 2510 pci_disable_device(pdev); 2511 return ret; 2512 } 2513 2514 static void 2515 amdgpu_pci_remove(struct pci_dev *pdev) 2516 { 2517 struct drm_device *dev = pci_get_drvdata(pdev); 2518 struct amdgpu_device *adev = drm_to_adev(dev); 2519 2520 amdgpu_ras_eeprom_check_and_recover(adev); 2521 amdgpu_xcp_dev_unplug(adev); 2522 amdgpu_gmc_prepare_nps_mode_change(adev); 2523 drm_dev_unplug(dev); 2524 2525 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2526 pm_runtime_get_sync(dev->dev); 2527 pm_runtime_forbid(dev->dev); 2528 } 2529 2530 amdgpu_driver_unload_kms(dev); 2531 2532 /* 2533 * Flush any in flight DMA operations from device. 2534 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2535 * StatusTransactions Pending bit. 2536 */ 2537 pci_disable_device(pdev); 2538 pci_wait_for_pending_transaction(pdev); 2539 } 2540 2541 static void 2542 amdgpu_pci_shutdown(struct pci_dev *pdev) 2543 { 2544 struct drm_device *dev = pci_get_drvdata(pdev); 2545 struct amdgpu_device *adev = drm_to_adev(dev); 2546 2547 if (amdgpu_ras_intr_triggered()) 2548 return; 2549 2550 /* device maybe not resumed here, return immediately in this case */ 2551 if (adev->in_s4 && adev->in_suspend) 2552 return; 2553 2554 /* if we are running in a VM, make sure the device 2555 * torn down properly on reboot/shutdown. 2556 * unfortunately we can't detect certain 2557 * hypervisors so just do this all the time. 2558 */ 2559 if (!amdgpu_passthrough(adev)) 2560 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2561 amdgpu_device_ip_suspend(adev); 2562 adev->mp1_state = PP_MP1_STATE_NONE; 2563 } 2564 2565 static int amdgpu_pmops_prepare(struct device *dev) 2566 { 2567 struct drm_device *drm_dev = dev_get_drvdata(dev); 2568 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2569 2570 /* device maybe not resumed here, return immediately in this case */ 2571 if (adev->in_s4 && adev->in_suspend) 2572 return 0; 2573 2574 /* Return a positive number here so 2575 * DPM_FLAG_SMART_SUSPEND works properly 2576 */ 2577 if (amdgpu_device_supports_boco(adev) && pm_runtime_suspended(dev)) 2578 return 1; 2579 2580 /* if we will not support s3 or s2i for the device 2581 * then skip suspend 2582 */ 2583 if (!amdgpu_acpi_is_s0ix_active(adev) && 2584 !amdgpu_acpi_is_s3_active(adev)) 2585 return 1; 2586 2587 return amdgpu_device_prepare(drm_dev); 2588 } 2589 2590 static void amdgpu_pmops_complete(struct device *dev) 2591 { 2592 amdgpu_device_complete(dev_get_drvdata(dev)); 2593 } 2594 2595 static int amdgpu_pmops_suspend(struct device *dev) 2596 { 2597 struct drm_device *drm_dev = dev_get_drvdata(dev); 2598 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2599 2600 if (amdgpu_acpi_is_s0ix_active(adev)) 2601 adev->in_s0ix = true; 2602 else if (amdgpu_acpi_is_s3_active(adev)) 2603 adev->in_s3 = true; 2604 if (!adev->in_s0ix && !adev->in_s3) { 2605 #if IS_ENABLED(CONFIG_SUSPEND) 2606 /* don't allow going deep first time followed by s2idle the next time */ 2607 if (adev->last_suspend_state != PM_SUSPEND_ON && 2608 adev->last_suspend_state != pm_suspend_target_state) { 2609 drm_err_once(drm_dev, "Unsupported suspend state %d\n", 2610 pm_suspend_target_state); 2611 return -EINVAL; 2612 } 2613 #endif 2614 return 0; 2615 } 2616 2617 #if IS_ENABLED(CONFIG_SUSPEND) 2618 /* cache the state last used for suspend */ 2619 adev->last_suspend_state = pm_suspend_target_state; 2620 #endif 2621 2622 return amdgpu_device_suspend(drm_dev, true); 2623 } 2624 2625 static int amdgpu_pmops_suspend_noirq(struct device *dev) 2626 { 2627 struct drm_device *drm_dev = dev_get_drvdata(dev); 2628 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2629 2630 if (amdgpu_acpi_should_gpu_reset(adev)) 2631 return amdgpu_asic_reset(adev); 2632 2633 return 0; 2634 } 2635 2636 static int amdgpu_pmops_resume(struct device *dev) 2637 { 2638 struct drm_device *drm_dev = dev_get_drvdata(dev); 2639 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2640 int r; 2641 2642 if (!adev->in_s0ix && !adev->in_s3) 2643 return 0; 2644 2645 /* Avoids registers access if device is physically gone */ 2646 if (!pci_device_is_present(adev->pdev)) 2647 adev->no_hw_access = true; 2648 2649 r = amdgpu_device_resume(drm_dev, true); 2650 if (amdgpu_acpi_is_s0ix_active(adev)) 2651 adev->in_s0ix = false; 2652 else 2653 adev->in_s3 = false; 2654 return r; 2655 } 2656 2657 static int amdgpu_pmops_freeze(struct device *dev) 2658 { 2659 struct drm_device *drm_dev = dev_get_drvdata(dev); 2660 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2661 int r; 2662 2663 r = amdgpu_device_suspend(drm_dev, true); 2664 if (r) 2665 return r; 2666 2667 if (amdgpu_acpi_should_gpu_reset(adev)) 2668 return amdgpu_asic_reset(adev); 2669 return 0; 2670 } 2671 2672 static int amdgpu_pmops_thaw(struct device *dev) 2673 { 2674 struct drm_device *drm_dev = dev_get_drvdata(dev); 2675 2676 /* do not resume device if it's normal hibernation */ 2677 if (!pm_hibernate_is_recovering() && !pm_hibernation_mode_is_suspend()) 2678 return 0; 2679 2680 return amdgpu_device_resume(drm_dev, true); 2681 } 2682 2683 static int amdgpu_pmops_poweroff(struct device *dev) 2684 { 2685 struct drm_device *drm_dev = dev_get_drvdata(dev); 2686 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2687 2688 /* device maybe not resumed here, return immediately in this case */ 2689 if (adev->in_s4 && adev->in_suspend) 2690 return 0; 2691 2692 return amdgpu_device_suspend(drm_dev, true); 2693 } 2694 2695 static int amdgpu_pmops_restore(struct device *dev) 2696 { 2697 struct drm_device *drm_dev = dev_get_drvdata(dev); 2698 2699 return amdgpu_device_resume(drm_dev, true); 2700 } 2701 2702 static int amdgpu_runtime_idle_check_display(struct device *dev) 2703 { 2704 struct pci_dev *pdev = to_pci_dev(dev); 2705 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2706 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2707 2708 if (adev->mode_info.num_crtc) { 2709 struct drm_connector *list_connector; 2710 struct drm_connector_list_iter iter; 2711 int ret = 0; 2712 2713 if (amdgpu_runtime_pm != -2) { 2714 /* XXX: Return busy if any displays are connected to avoid 2715 * possible display wakeups after runtime resume due to 2716 * hotplug events in case any displays were connected while 2717 * the GPU was in suspend. Remove this once that is fixed. 2718 */ 2719 mutex_lock(&drm_dev->mode_config.mutex); 2720 drm_connector_list_iter_begin(drm_dev, &iter); 2721 drm_for_each_connector_iter(list_connector, &iter) { 2722 if (list_connector->status == connector_status_connected) { 2723 ret = -EBUSY; 2724 break; 2725 } 2726 } 2727 drm_connector_list_iter_end(&iter); 2728 mutex_unlock(&drm_dev->mode_config.mutex); 2729 2730 if (ret) 2731 return ret; 2732 } 2733 2734 if (adev->dc_enabled) { 2735 struct drm_crtc *crtc; 2736 2737 drm_for_each_crtc(crtc, drm_dev) { 2738 drm_modeset_lock(&crtc->mutex, NULL); 2739 if (crtc->state->active) 2740 ret = -EBUSY; 2741 drm_modeset_unlock(&crtc->mutex); 2742 if (ret < 0) 2743 break; 2744 } 2745 } else { 2746 mutex_lock(&drm_dev->mode_config.mutex); 2747 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2748 2749 drm_connector_list_iter_begin(drm_dev, &iter); 2750 drm_for_each_connector_iter(list_connector, &iter) { 2751 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2752 ret = -EBUSY; 2753 break; 2754 } 2755 } 2756 2757 drm_connector_list_iter_end(&iter); 2758 2759 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2760 mutex_unlock(&drm_dev->mode_config.mutex); 2761 } 2762 if (ret) 2763 return ret; 2764 } 2765 2766 return 0; 2767 } 2768 2769 static int amdgpu_runtime_idle_check_userq(struct device *dev) 2770 { 2771 struct pci_dev *pdev = to_pci_dev(dev); 2772 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2773 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2774 struct amdgpu_usermode_queue *queue; 2775 struct amdgpu_userq_mgr *uqm, *tmp; 2776 int queue_id; 2777 int ret = 0; 2778 2779 mutex_lock(&adev->userq_mutex); 2780 list_for_each_entry_safe(uqm, tmp, &adev->userq_mgr_list, list) { 2781 idr_for_each_entry(&uqm->userq_idr, queue, queue_id) { 2782 ret = -EBUSY; 2783 goto done; 2784 } 2785 } 2786 done: 2787 mutex_unlock(&adev->userq_mutex); 2788 2789 return ret; 2790 } 2791 2792 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2793 { 2794 struct pci_dev *pdev = to_pci_dev(dev); 2795 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2796 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2797 int ret, i; 2798 2799 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2800 pm_runtime_forbid(dev); 2801 return -EBUSY; 2802 } 2803 2804 ret = amdgpu_runtime_idle_check_display(dev); 2805 if (ret) 2806 return ret; 2807 ret = amdgpu_runtime_idle_check_userq(dev); 2808 if (ret) 2809 return ret; 2810 2811 /* wait for all rings to drain before suspending */ 2812 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2813 struct amdgpu_ring *ring = adev->rings[i]; 2814 2815 if (ring && ring->sched.ready) { 2816 ret = amdgpu_fence_wait_empty(ring); 2817 if (ret) 2818 return -EBUSY; 2819 } 2820 } 2821 2822 adev->in_runpm = true; 2823 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2824 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2825 2826 /* 2827 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2828 * proper cleanups and put itself into a state ready for PNP. That 2829 * can address some random resuming failure observed on BOCO capable 2830 * platforms. 2831 * TODO: this may be also needed for PX capable platform. 2832 */ 2833 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2834 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2835 2836 ret = amdgpu_device_prepare(drm_dev); 2837 if (ret) 2838 return ret; 2839 ret = amdgpu_device_suspend(drm_dev, false); 2840 if (ret) { 2841 adev->in_runpm = false; 2842 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2843 adev->mp1_state = PP_MP1_STATE_NONE; 2844 return ret; 2845 } 2846 2847 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2848 adev->mp1_state = PP_MP1_STATE_NONE; 2849 2850 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) { 2851 /* Only need to handle PCI state in the driver for ATPX 2852 * PCI core handles it for _PR3. 2853 */ 2854 amdgpu_device_cache_pci_state(pdev); 2855 pci_disable_device(pdev); 2856 pci_ignore_hotplug(pdev); 2857 pci_set_power_state(pdev, PCI_D3cold); 2858 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2859 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) { 2860 /* nothing to do */ 2861 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2862 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) { 2863 amdgpu_device_baco_enter(adev); 2864 } 2865 2866 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n"); 2867 2868 return 0; 2869 } 2870 2871 static int amdgpu_pmops_runtime_resume(struct device *dev) 2872 { 2873 struct pci_dev *pdev = to_pci_dev(dev); 2874 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2875 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2876 int ret; 2877 2878 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) 2879 return -EINVAL; 2880 2881 /* Avoids registers access if device is physically gone */ 2882 if (!pci_device_is_present(adev->pdev)) 2883 adev->no_hw_access = true; 2884 2885 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) { 2886 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2887 2888 /* Only need to handle PCI state in the driver for ATPX 2889 * PCI core handles it for _PR3. 2890 */ 2891 pci_set_power_state(pdev, PCI_D0); 2892 amdgpu_device_load_pci_state(pdev); 2893 ret = pci_enable_device(pdev); 2894 if (ret) 2895 return ret; 2896 pci_set_master(pdev); 2897 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) { 2898 /* Only need to handle PCI state in the driver for ATPX 2899 * PCI core handles it for _PR3. 2900 */ 2901 pci_set_master(pdev); 2902 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2903 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) { 2904 amdgpu_device_baco_exit(adev); 2905 } 2906 ret = amdgpu_device_resume(drm_dev, false); 2907 if (ret) { 2908 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2909 pci_disable_device(pdev); 2910 return ret; 2911 } 2912 2913 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2914 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2915 adev->in_runpm = false; 2916 return 0; 2917 } 2918 2919 static int amdgpu_pmops_runtime_idle(struct device *dev) 2920 { 2921 struct drm_device *drm_dev = dev_get_drvdata(dev); 2922 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2923 int ret; 2924 2925 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2926 pm_runtime_forbid(dev); 2927 return -EBUSY; 2928 } 2929 2930 ret = amdgpu_runtime_idle_check_display(dev); 2931 if (ret) 2932 goto done; 2933 2934 ret = amdgpu_runtime_idle_check_userq(dev); 2935 done: 2936 pm_runtime_mark_last_busy(dev); 2937 pm_runtime_autosuspend(dev); 2938 return ret; 2939 } 2940 2941 static int amdgpu_drm_release(struct inode *inode, struct file *filp) 2942 { 2943 struct drm_file *file_priv = filp->private_data; 2944 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2945 struct drm_device *dev = file_priv->minor->dev; 2946 int idx; 2947 2948 if (fpriv && drm_dev_enter(dev, &idx)) { 2949 fpriv->evf_mgr.fd_closing = true; 2950 amdgpu_eviction_fence_destroy(&fpriv->evf_mgr); 2951 amdgpu_userq_mgr_fini(&fpriv->userq_mgr); 2952 drm_dev_exit(idx); 2953 } 2954 2955 return drm_release(inode, filp); 2956 } 2957 2958 long amdgpu_drm_ioctl(struct file *filp, 2959 unsigned int cmd, unsigned long arg) 2960 { 2961 struct drm_file *file_priv = filp->private_data; 2962 struct drm_device *dev; 2963 long ret; 2964 2965 dev = file_priv->minor->dev; 2966 ret = pm_runtime_get_sync(dev->dev); 2967 if (ret < 0) 2968 goto out; 2969 2970 ret = drm_ioctl(filp, cmd, arg); 2971 2972 pm_runtime_mark_last_busy(dev->dev); 2973 out: 2974 pm_runtime_put_autosuspend(dev->dev); 2975 return ret; 2976 } 2977 2978 static const struct dev_pm_ops amdgpu_pm_ops = { 2979 .prepare = pm_sleep_ptr(amdgpu_pmops_prepare), 2980 .complete = pm_sleep_ptr(amdgpu_pmops_complete), 2981 .suspend = pm_sleep_ptr(amdgpu_pmops_suspend), 2982 .suspend_noirq = pm_sleep_ptr(amdgpu_pmops_suspend_noirq), 2983 .resume = pm_sleep_ptr(amdgpu_pmops_resume), 2984 .freeze = pm_sleep_ptr(amdgpu_pmops_freeze), 2985 .thaw = pm_sleep_ptr(amdgpu_pmops_thaw), 2986 .poweroff = pm_sleep_ptr(amdgpu_pmops_poweroff), 2987 .restore = pm_sleep_ptr(amdgpu_pmops_restore), 2988 .runtime_suspend = amdgpu_pmops_runtime_suspend, 2989 .runtime_resume = amdgpu_pmops_runtime_resume, 2990 .runtime_idle = amdgpu_pmops_runtime_idle, 2991 }; 2992 2993 static int amdgpu_flush(struct file *f, fl_owner_t id) 2994 { 2995 struct drm_file *file_priv = f->private_data; 2996 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2997 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2998 2999 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 3000 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 3001 3002 return timeout >= 0 ? 0 : timeout; 3003 } 3004 3005 static const struct file_operations amdgpu_driver_kms_fops = { 3006 .owner = THIS_MODULE, 3007 .open = drm_open, 3008 .flush = amdgpu_flush, 3009 .release = amdgpu_drm_release, 3010 .unlocked_ioctl = amdgpu_drm_ioctl, 3011 .mmap = drm_gem_mmap, 3012 .poll = drm_poll, 3013 .read = drm_read, 3014 #ifdef CONFIG_COMPAT 3015 .compat_ioctl = amdgpu_kms_compat_ioctl, 3016 #endif 3017 #ifdef CONFIG_PROC_FS 3018 .show_fdinfo = drm_show_fdinfo, 3019 #endif 3020 .fop_flags = FOP_UNSIGNED_OFFSET, 3021 }; 3022 3023 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 3024 { 3025 struct drm_file *file; 3026 3027 if (!filp) 3028 return -EINVAL; 3029 3030 if (filp->f_op != &amdgpu_driver_kms_fops) 3031 return -EINVAL; 3032 3033 file = filp->private_data; 3034 *fpriv = file->driver_priv; 3035 return 0; 3036 } 3037 3038 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 3039 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3040 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3041 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3042 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 3043 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3044 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3045 /* KMS */ 3046 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3047 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3048 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3049 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3050 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3051 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3052 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3053 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3054 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3055 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3056 DRM_IOCTL_DEF_DRV(AMDGPU_USERQ, amdgpu_userq_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3057 DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_SIGNAL, amdgpu_userq_signal_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3058 DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_WAIT, amdgpu_userq_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3059 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_LIST_HANDLES, amdgpu_gem_list_handles_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3060 }; 3061 3062 static const struct drm_driver amdgpu_kms_driver = { 3063 .driver_features = 3064 DRIVER_ATOMIC | 3065 DRIVER_GEM | 3066 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 3067 DRIVER_SYNCOBJ_TIMELINE, 3068 .open = amdgpu_driver_open_kms, 3069 .postclose = amdgpu_driver_postclose_kms, 3070 .ioctls = amdgpu_ioctls_kms, 3071 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 3072 .dumb_create = amdgpu_mode_dumb_create, 3073 .dumb_map_offset = amdgpu_mode_dumb_mmap, 3074 DRM_FBDEV_TTM_DRIVER_OPS, 3075 .fops = &amdgpu_driver_kms_fops, 3076 .release = &amdgpu_driver_release_kms, 3077 #ifdef CONFIG_PROC_FS 3078 .show_fdinfo = amdgpu_show_fdinfo, 3079 #endif 3080 3081 .gem_prime_import = amdgpu_gem_prime_import, 3082 3083 .name = DRIVER_NAME, 3084 .desc = DRIVER_DESC, 3085 .major = KMS_DRIVER_MAJOR, 3086 .minor = KMS_DRIVER_MINOR, 3087 .patchlevel = KMS_DRIVER_PATCHLEVEL, 3088 }; 3089 3090 const struct drm_driver amdgpu_partition_driver = { 3091 .driver_features = 3092 DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ | 3093 DRIVER_SYNCOBJ_TIMELINE, 3094 .open = amdgpu_driver_open_kms, 3095 .postclose = amdgpu_driver_postclose_kms, 3096 .ioctls = amdgpu_ioctls_kms, 3097 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 3098 .dumb_create = amdgpu_mode_dumb_create, 3099 .dumb_map_offset = amdgpu_mode_dumb_mmap, 3100 DRM_FBDEV_TTM_DRIVER_OPS, 3101 .fops = &amdgpu_driver_kms_fops, 3102 .release = &amdgpu_driver_release_kms, 3103 3104 .gem_prime_import = amdgpu_gem_prime_import, 3105 3106 .name = DRIVER_NAME, 3107 .desc = DRIVER_DESC, 3108 .major = KMS_DRIVER_MAJOR, 3109 .minor = KMS_DRIVER_MINOR, 3110 .patchlevel = KMS_DRIVER_PATCHLEVEL, 3111 }; 3112 3113 static struct pci_error_handlers amdgpu_pci_err_handler = { 3114 .error_detected = amdgpu_pci_error_detected, 3115 .mmio_enabled = amdgpu_pci_mmio_enabled, 3116 .slot_reset = amdgpu_pci_slot_reset, 3117 .resume = amdgpu_pci_resume, 3118 }; 3119 3120 static const struct attribute_group *amdgpu_sysfs_groups[] = { 3121 &amdgpu_vram_mgr_attr_group, 3122 &amdgpu_gtt_mgr_attr_group, 3123 &amdgpu_flash_attr_group, 3124 NULL, 3125 }; 3126 3127 static struct pci_driver amdgpu_kms_pci_driver = { 3128 .name = DRIVER_NAME, 3129 .id_table = pciidlist, 3130 .probe = amdgpu_pci_probe, 3131 .remove = amdgpu_pci_remove, 3132 .shutdown = amdgpu_pci_shutdown, 3133 .driver.pm = pm_ptr(&amdgpu_pm_ops), 3134 .err_handler = &amdgpu_pci_err_handler, 3135 .dev_groups = amdgpu_sysfs_groups, 3136 }; 3137 3138 static int __init amdgpu_init(void) 3139 { 3140 int r; 3141 3142 r = amdgpu_sync_init(); 3143 if (r) 3144 goto error_sync; 3145 3146 r = amdgpu_userq_fence_slab_init(); 3147 if (r) 3148 goto error_fence; 3149 3150 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 3151 amdgpu_register_atpx_handler(); 3152 amdgpu_acpi_detect(); 3153 3154 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 3155 amdgpu_amdkfd_init(); 3156 3157 if (amdgpu_pp_feature_mask & PP_OVERDRIVE_MASK) { 3158 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 3159 pr_crit("Overdrive is enabled, please disable it before " 3160 "reporting any bugs unrelated to overdrive.\n"); 3161 } 3162 3163 /* let modprobe override vga console setting */ 3164 return pci_register_driver(&amdgpu_kms_pci_driver); 3165 3166 error_fence: 3167 amdgpu_sync_fini(); 3168 3169 error_sync: 3170 return r; 3171 } 3172 3173 static void __exit amdgpu_exit(void) 3174 { 3175 amdgpu_amdkfd_fini(); 3176 pci_unregister_driver(&amdgpu_kms_pci_driver); 3177 amdgpu_unregister_atpx_handler(); 3178 amdgpu_acpi_release(); 3179 amdgpu_sync_fini(); 3180 amdgpu_userq_fence_slab_fini(); 3181 mmu_notifier_synchronize(); 3182 amdgpu_xcp_drv_release(); 3183 } 3184 3185 module_init(amdgpu_init); 3186 module_exit(amdgpu_exit); 3187 3188 MODULE_AUTHOR(DRIVER_AUTHOR); 3189 MODULE_DESCRIPTION(DRIVER_DESC); 3190 MODULE_LICENSE("GPL and additional rights"); 3191