1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_aperture.h> 27 #include <drm/drm_drv.h> 28 #include <drm/drm_gem.h> 29 #include <drm/drm_vblank.h> 30 #include <drm/drm_managed.h> 31 #include "amdgpu_drv.h" 32 33 #include <drm/drm_pciids.h> 34 #include <linux/console.h> 35 #include <linux/module.h> 36 #include <linux/pm_runtime.h> 37 #include <linux/vga_switcheroo.h> 38 #include <drm/drm_probe_helper.h> 39 #include <linux/mmu_notifier.h> 40 #include <linux/suspend.h> 41 42 #include "amdgpu.h" 43 #include "amdgpu_irq.h" 44 #include "amdgpu_dma_buf.h" 45 #include "amdgpu_sched.h" 46 #include "amdgpu_fdinfo.h" 47 #include "amdgpu_amdkfd.h" 48 49 #include "amdgpu_ras.h" 50 #include "amdgpu_xgmi.h" 51 #include "amdgpu_reset.h" 52 53 /* 54 * KMS wrapper. 55 * - 3.0.0 - initial driver 56 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 57 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 58 * at the end of IBs. 59 * - 3.3.0 - Add VM support for UVD on supported hardware. 60 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 61 * - 3.5.0 - Add support for new UVD_NO_OP register. 62 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 63 * - 3.7.0 - Add support for VCE clock list packet 64 * - 3.8.0 - Add support raster config init in the kernel 65 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 66 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 67 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 68 * - 3.12.0 - Add query for double offchip LDS buffers 69 * - 3.13.0 - Add PRT support 70 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 71 * - 3.15.0 - Export more gpu info for gfx9 72 * - 3.16.0 - Add reserved vmid support 73 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 74 * - 3.18.0 - Export gpu always on cu bitmap 75 * - 3.19.0 - Add support for UVD MJPEG decode 76 * - 3.20.0 - Add support for local BOs 77 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 78 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 79 * - 3.23.0 - Add query for VRAM lost counter 80 * - 3.24.0 - Add high priority compute support for gfx9 81 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 82 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 83 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation. 84 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 85 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 86 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 87 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 88 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 89 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 90 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 91 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 92 * - 3.36.0 - Allow reading more status registers on si/cik 93 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 94 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 95 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 96 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 97 * - 3.41.0 - Add video codec query 98 * - 3.42.0 - Add 16bpc fixed point display support 99 */ 100 #define KMS_DRIVER_MAJOR 3 101 #define KMS_DRIVER_MINOR 42 102 #define KMS_DRIVER_PATCHLEVEL 0 103 104 int amdgpu_vram_limit; 105 int amdgpu_vis_vram_limit; 106 int amdgpu_gart_size = -1; /* auto */ 107 int amdgpu_gtt_size = -1; /* auto */ 108 int amdgpu_moverate = -1; /* auto */ 109 int amdgpu_benchmarking; 110 int amdgpu_testing; 111 int amdgpu_audio = -1; 112 int amdgpu_disp_priority; 113 int amdgpu_hw_i2c; 114 int amdgpu_pcie_gen2 = -1; 115 int amdgpu_msi = -1; 116 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 117 int amdgpu_dpm = -1; 118 int amdgpu_fw_load_type = -1; 119 int amdgpu_aspm = -1; 120 int amdgpu_runtime_pm = -1; 121 uint amdgpu_ip_block_mask = 0xffffffff; 122 int amdgpu_bapm = -1; 123 int amdgpu_deep_color; 124 int amdgpu_vm_size = -1; 125 int amdgpu_vm_fragment_size = -1; 126 int amdgpu_vm_block_size = -1; 127 int amdgpu_vm_fault_stop; 128 int amdgpu_vm_debug; 129 int amdgpu_vm_update_mode = -1; 130 int amdgpu_exp_hw_support; 131 int amdgpu_dc = -1; 132 int amdgpu_sched_jobs = 32; 133 int amdgpu_sched_hw_submission = 2; 134 uint amdgpu_pcie_gen_cap; 135 uint amdgpu_pcie_lane_cap; 136 uint amdgpu_cg_mask = 0xffffffff; 137 uint amdgpu_pg_mask = 0xffffffff; 138 uint amdgpu_sdma_phase_quantum = 32; 139 char *amdgpu_disable_cu = NULL; 140 char *amdgpu_virtual_display = NULL; 141 142 /* 143 * OverDrive(bit 14) disabled by default 144 * GFX DCS(bit 19) disabled by default 145 */ 146 uint amdgpu_pp_feature_mask = 0xfff7bfff; 147 uint amdgpu_force_long_training; 148 int amdgpu_job_hang_limit; 149 int amdgpu_lbpw = -1; 150 int amdgpu_compute_multipipe = -1; 151 int amdgpu_gpu_recovery = -1; /* auto */ 152 int amdgpu_emu_mode; 153 uint amdgpu_smu_memory_pool_size; 154 int amdgpu_smu_pptable_id = -1; 155 /* 156 * FBC (bit 0) disabled by default 157 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 158 * - With this, for multiple monitors in sync(e.g. with the same model), 159 * mclk switching will be allowed. And the mclk will be not foced to the 160 * highest. That helps saving some idle power. 161 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 162 * PSR (bit 3) disabled by default 163 */ 164 uint amdgpu_dc_feature_mask = 2; 165 uint amdgpu_dc_debug_mask; 166 int amdgpu_async_gfx_ring = 1; 167 int amdgpu_mcbp; 168 int amdgpu_discovery = -1; 169 int amdgpu_mes; 170 int amdgpu_noretry = -1; 171 int amdgpu_force_asic_type = -1; 172 int amdgpu_tmz = -1; /* auto */ 173 uint amdgpu_freesync_vid_mode; 174 int amdgpu_reset_method = -1; /* auto */ 175 int amdgpu_num_kcq = -1; 176 int amdgpu_smartshift_bias; 177 178 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 179 180 struct amdgpu_mgpu_info mgpu_info = { 181 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 182 .delayed_reset_work = __DELAYED_WORK_INITIALIZER( 183 mgpu_info.delayed_reset_work, 184 amdgpu_drv_delayed_reset_work_handler, 0), 185 }; 186 int amdgpu_ras_enable = -1; 187 uint amdgpu_ras_mask = 0xffffffff; 188 int amdgpu_bad_page_threshold = -1; 189 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 190 .timeout_fatal_disable = false, 191 .period = 0x0, /* default to 0x0 (timeout disable) */ 192 }; 193 194 /** 195 * DOC: vramlimit (int) 196 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 197 */ 198 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 199 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 200 201 /** 202 * DOC: vis_vramlimit (int) 203 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 204 */ 205 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 206 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 207 208 /** 209 * DOC: gartsize (uint) 210 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic). 211 */ 212 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); 213 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 214 215 /** 216 * DOC: gttsize (int) 217 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM, 218 * otherwise 3/4 RAM size). 219 */ 220 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); 221 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 222 223 /** 224 * DOC: moverate (int) 225 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 226 */ 227 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 228 module_param_named(moverate, amdgpu_moverate, int, 0600); 229 230 /** 231 * DOC: benchmark (int) 232 * Run benchmarks. The default is 0 (Skip benchmarks). 233 */ 234 MODULE_PARM_DESC(benchmark, "Run benchmark"); 235 module_param_named(benchmark, amdgpu_benchmarking, int, 0444); 236 237 /** 238 * DOC: test (int) 239 * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test). 240 */ 241 MODULE_PARM_DESC(test, "Run tests"); 242 module_param_named(test, amdgpu_testing, int, 0444); 243 244 /** 245 * DOC: audio (int) 246 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 247 */ 248 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 249 module_param_named(audio, amdgpu_audio, int, 0444); 250 251 /** 252 * DOC: disp_priority (int) 253 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 254 */ 255 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 256 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 257 258 /** 259 * DOC: hw_i2c (int) 260 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 261 */ 262 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 263 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 264 265 /** 266 * DOC: pcie_gen2 (int) 267 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 268 */ 269 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 270 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 271 272 /** 273 * DOC: msi (int) 274 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 275 */ 276 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 277 module_param_named(msi, amdgpu_msi, int, 0444); 278 279 /** 280 * DOC: lockup_timeout (string) 281 * Set GPU scheduler timeout value in ms. 282 * 283 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 284 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 285 * to the default timeout. 286 * 287 * - With one value specified, the setting will apply to all non-compute jobs. 288 * - With multiple values specified, the first one will be for GFX. 289 * The second one is for Compute. The third and fourth ones are 290 * for SDMA and Video. 291 * 292 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 293 * jobs is 10000. The timeout for compute is 60000. 294 */ 295 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 296 "for passthrough or sriov, 10000 for all jobs." 297 " 0: keep default value. negative: infinity timeout), " 298 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 299 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 300 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 301 302 /** 303 * DOC: dpm (int) 304 * Override for dynamic power management setting 305 * (0 = disable, 1 = enable) 306 * The default is -1 (auto). 307 */ 308 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 309 module_param_named(dpm, amdgpu_dpm, int, 0444); 310 311 /** 312 * DOC: fw_load_type (int) 313 * Set different firmware loading type for debugging (0 = direct, 1 = SMU, 2 = PSP). The default is -1 (auto). 314 */ 315 MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)"); 316 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 317 318 /** 319 * DOC: aspm (int) 320 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 321 */ 322 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 323 module_param_named(aspm, amdgpu_aspm, int, 0444); 324 325 /** 326 * DOC: runpm (int) 327 * Override for runtime power management control for dGPUs in PX/HG laptops. The amdgpu driver can dynamically power down 328 * the dGPU on PX/HG laptops when it is idle. The default is -1 (auto enable). Setting the value to 0 disables this functionality. 329 */ 330 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = PX only default)"); 331 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 332 333 /** 334 * DOC: ip_block_mask (uint) 335 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 336 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 337 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 338 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 339 */ 340 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 341 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 342 343 /** 344 * DOC: bapm (int) 345 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 346 * The default -1 (auto, enabled) 347 */ 348 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 349 module_param_named(bapm, amdgpu_bapm, int, 0444); 350 351 /** 352 * DOC: deep_color (int) 353 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 354 */ 355 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 356 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 357 358 /** 359 * DOC: vm_size (int) 360 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 361 */ 362 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 363 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 364 365 /** 366 * DOC: vm_fragment_size (int) 367 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 368 */ 369 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 370 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 371 372 /** 373 * DOC: vm_block_size (int) 374 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 375 */ 376 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 377 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 378 379 /** 380 * DOC: vm_fault_stop (int) 381 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 382 */ 383 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 384 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 385 386 /** 387 * DOC: vm_debug (int) 388 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 389 */ 390 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 391 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 392 393 /** 394 * DOC: vm_update_mode (int) 395 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 396 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 397 */ 398 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 399 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 400 401 /** 402 * DOC: exp_hw_support (int) 403 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 404 */ 405 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 406 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 407 408 /** 409 * DOC: dc (int) 410 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 411 */ 412 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 413 module_param_named(dc, amdgpu_dc, int, 0444); 414 415 /** 416 * DOC: sched_jobs (int) 417 * Override the max number of jobs supported in the sw queue. The default is 32. 418 */ 419 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 420 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 421 422 /** 423 * DOC: sched_hw_submission (int) 424 * Override the max number of HW submissions. The default is 2. 425 */ 426 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 427 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 428 429 /** 430 * DOC: ppfeaturemask (hexint) 431 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 432 * The default is the current set of stable power features. 433 */ 434 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 435 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 436 437 /** 438 * DOC: forcelongtraining (uint) 439 * Force long memory training in resume. 440 * The default is zero, indicates short training in resume. 441 */ 442 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 443 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 444 445 /** 446 * DOC: pcie_gen_cap (uint) 447 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 448 * The default is 0 (automatic for each asic). 449 */ 450 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 451 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 452 453 /** 454 * DOC: pcie_lane_cap (uint) 455 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 456 * The default is 0 (automatic for each asic). 457 */ 458 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 459 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 460 461 /** 462 * DOC: cg_mask (uint) 463 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 464 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 465 */ 466 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 467 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); 468 469 /** 470 * DOC: pg_mask (uint) 471 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 472 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 473 */ 474 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 475 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 476 477 /** 478 * DOC: sdma_phase_quantum (uint) 479 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 480 */ 481 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 482 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 483 484 /** 485 * DOC: disable_cu (charp) 486 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 487 */ 488 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 489 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 490 491 /** 492 * DOC: virtual_display (charp) 493 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 494 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 495 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 496 * device at 26:00.0. The default is NULL. 497 */ 498 MODULE_PARM_DESC(virtual_display, 499 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 500 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 501 502 /** 503 * DOC: job_hang_limit (int) 504 * Set how much time allow a job hang and not drop it. The default is 0. 505 */ 506 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 507 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 508 509 /** 510 * DOC: lbpw (int) 511 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 512 */ 513 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 514 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 515 516 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 517 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 518 519 /** 520 * DOC: gpu_recovery (int) 521 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 522 */ 523 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (2 = advanced tdr mode, 1 = enable, 0 = disable, -1 = auto)"); 524 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 525 526 /** 527 * DOC: emu_mode (int) 528 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 529 */ 530 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 531 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 532 533 /** 534 * DOC: ras_enable (int) 535 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 536 */ 537 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 538 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 539 540 /** 541 * DOC: ras_mask (uint) 542 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 543 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 544 */ 545 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 546 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 547 548 /** 549 * DOC: timeout_fatal_disable (bool) 550 * Disable Watchdog timeout fatal error event 551 */ 552 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 553 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 554 555 /** 556 * DOC: timeout_period (uint) 557 * Modify the watchdog timeout max_cycles as (1 << period) 558 */ 559 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 560 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 561 562 /** 563 * DOC: si_support (int) 564 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 565 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 566 * otherwise using amdgpu driver. 567 */ 568 #ifdef CONFIG_DRM_AMDGPU_SI 569 570 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 571 int amdgpu_si_support = 0; 572 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 573 #else 574 int amdgpu_si_support = 1; 575 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 576 #endif 577 578 module_param_named(si_support, amdgpu_si_support, int, 0444); 579 #endif 580 581 /** 582 * DOC: cik_support (int) 583 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 584 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 585 * otherwise using amdgpu driver. 586 */ 587 #ifdef CONFIG_DRM_AMDGPU_CIK 588 589 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 590 int amdgpu_cik_support = 0; 591 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 592 #else 593 int amdgpu_cik_support = 1; 594 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 595 #endif 596 597 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 598 #endif 599 600 /** 601 * DOC: smu_memory_pool_size (uint) 602 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 603 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 604 */ 605 MODULE_PARM_DESC(smu_memory_pool_size, 606 "reserve gtt for smu debug usage, 0 = disable," 607 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 608 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 609 610 /** 611 * DOC: async_gfx_ring (int) 612 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 613 */ 614 MODULE_PARM_DESC(async_gfx_ring, 615 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 616 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 617 618 /** 619 * DOC: mcbp (int) 620 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled) 621 */ 622 MODULE_PARM_DESC(mcbp, 623 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); 624 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 625 626 /** 627 * DOC: discovery (int) 628 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 629 * (-1 = auto (default), 0 = disabled, 1 = enabled) 630 */ 631 MODULE_PARM_DESC(discovery, 632 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 633 module_param_named(discovery, amdgpu_discovery, int, 0444); 634 635 /** 636 * DOC: mes (int) 637 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 638 * (0 = disabled (default), 1 = enabled) 639 */ 640 MODULE_PARM_DESC(mes, 641 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 642 module_param_named(mes, amdgpu_mes, int, 0444); 643 644 /** 645 * DOC: noretry (int) 646 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 647 * do not support per-process XNACK this also disables retry page faults. 648 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 649 */ 650 MODULE_PARM_DESC(noretry, 651 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 652 module_param_named(noretry, amdgpu_noretry, int, 0644); 653 654 /** 655 * DOC: force_asic_type (int) 656 * A non negative value used to specify the asic type for all supported GPUs. 657 */ 658 MODULE_PARM_DESC(force_asic_type, 659 "A non negative value used to specify the asic type for all supported GPUs"); 660 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 661 662 663 664 #ifdef CONFIG_HSA_AMD 665 /** 666 * DOC: sched_policy (int) 667 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 668 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 669 * assigns queues to HQDs. 670 */ 671 int sched_policy = KFD_SCHED_POLICY_HWS; 672 module_param(sched_policy, int, 0444); 673 MODULE_PARM_DESC(sched_policy, 674 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 675 676 /** 677 * DOC: hws_max_conc_proc (int) 678 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 679 * number of VMIDs assigned to the HWS, which is also the default. 680 */ 681 int hws_max_conc_proc = 8; 682 module_param(hws_max_conc_proc, int, 0444); 683 MODULE_PARM_DESC(hws_max_conc_proc, 684 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 685 686 /** 687 * DOC: cwsr_enable (int) 688 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 689 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 690 * disables it. 691 */ 692 int cwsr_enable = 1; 693 module_param(cwsr_enable, int, 0444); 694 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 695 696 /** 697 * DOC: max_num_of_queues_per_device (int) 698 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 699 * is 4096. 700 */ 701 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 702 module_param(max_num_of_queues_per_device, int, 0444); 703 MODULE_PARM_DESC(max_num_of_queues_per_device, 704 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 705 706 /** 707 * DOC: send_sigterm (int) 708 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 709 * but just print errors on dmesg. Setting 1 enables sending sigterm. 710 */ 711 int send_sigterm; 712 module_param(send_sigterm, int, 0444); 713 MODULE_PARM_DESC(send_sigterm, 714 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 715 716 /** 717 * DOC: debug_largebar (int) 718 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 719 * system. This limits the VRAM size reported to ROCm applications to the visible 720 * size, usually 256MB. 721 * Default value is 0, diabled. 722 */ 723 int debug_largebar; 724 module_param(debug_largebar, int, 0444); 725 MODULE_PARM_DESC(debug_largebar, 726 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 727 728 /** 729 * DOC: ignore_crat (int) 730 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 731 * table to get information about AMD APUs. This option can serve as a workaround on 732 * systems with a broken CRAT table. 733 * 734 * Default is auto (according to asic type, iommu_v2, and crat table, to decide 735 * whehter use CRAT) 736 */ 737 int ignore_crat; 738 module_param(ignore_crat, int, 0444); 739 MODULE_PARM_DESC(ignore_crat, 740 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)"); 741 742 /** 743 * DOC: halt_if_hws_hang (int) 744 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 745 * Setting 1 enables halt on hang. 746 */ 747 int halt_if_hws_hang; 748 module_param(halt_if_hws_hang, int, 0644); 749 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 750 751 /** 752 * DOC: hws_gws_support(bool) 753 * Assume that HWS supports GWS barriers regardless of what firmware version 754 * check says. Default value: false (rely on MEC2 firmware version check). 755 */ 756 bool hws_gws_support; 757 module_param(hws_gws_support, bool, 0444); 758 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 759 760 /** 761 * DOC: queue_preemption_timeout_ms (int) 762 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 763 */ 764 int queue_preemption_timeout_ms = 9000; 765 module_param(queue_preemption_timeout_ms, int, 0644); 766 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 767 768 /** 769 * DOC: debug_evictions(bool) 770 * Enable extra debug messages to help determine the cause of evictions 771 */ 772 bool debug_evictions; 773 module_param(debug_evictions, bool, 0644); 774 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 775 776 /** 777 * DOC: no_system_mem_limit(bool) 778 * Disable system memory limit, to support multiple process shared memory 779 */ 780 bool no_system_mem_limit; 781 module_param(no_system_mem_limit, bool, 0644); 782 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 783 784 /** 785 * DOC: no_queue_eviction_on_vm_fault (int) 786 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 787 */ 788 int amdgpu_no_queue_eviction_on_vm_fault = 0; 789 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 790 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 791 #endif 792 793 /** 794 * DOC: dcfeaturemask (uint) 795 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 796 * The default is the current set of stable display features. 797 */ 798 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 799 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 800 801 /** 802 * DOC: dcdebugmask (uint) 803 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 804 */ 805 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 806 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 807 808 /** 809 * DOC: abmlevel (uint) 810 * Override the default ABM (Adaptive Backlight Management) level used for DC 811 * enabled hardware. Requires DMCU to be supported and loaded. 812 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 813 * default. Values 1-4 control the maximum allowable brightness reduction via 814 * the ABM algorithm, with 1 being the least reduction and 4 being the most 815 * reduction. 816 * 817 * Defaults to 0, or disabled. Userspace can still override this level later 818 * after boot. 819 */ 820 uint amdgpu_dm_abm_level; 821 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 822 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 823 824 int amdgpu_backlight = -1; 825 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 826 module_param_named(backlight, amdgpu_backlight, bint, 0444); 827 828 /** 829 * DOC: tmz (int) 830 * Trusted Memory Zone (TMZ) is a method to protect data being written 831 * to or read from memory. 832 * 833 * The default value: 0 (off). TODO: change to auto till it is completed. 834 */ 835 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 836 module_param_named(tmz, amdgpu_tmz, int, 0444); 837 838 /** 839 * DOC: freesync_video (uint) 840 * Enabled the optimization to adjust front porch timing to achieve seamless mode change experience 841 * when setting a freesync supported mode for which full modeset is not needed. 842 * The default value: 0 (off). 843 */ 844 MODULE_PARM_DESC( 845 freesync_video, 846 "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)"); 847 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); 848 849 /** 850 * DOC: reset_method (int) 851 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco, 5 = pci) 852 */ 853 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco, 5 = pci)"); 854 module_param_named(reset_method, amdgpu_reset_method, int, 0444); 855 856 /** 857 * DOC: bad_page_threshold (int) 858 * Bad page threshold is to specify the threshold value of faulty pages 859 * detected by RAS ECC, that may result in GPU entering bad status if total 860 * faulty pages by ECC exceed threshold value and leave it for user's further 861 * check. 862 */ 863 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement)"); 864 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 865 866 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 867 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 868 869 /** 870 * DOC: smu_pptable_id (int) 871 * Used to override pptable id. id = 0 use VBIOS pptable. 872 * id > 0 use the soft pptable with specicfied id. 873 */ 874 MODULE_PARM_DESC(smu_pptable_id, 875 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 876 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 877 878 static const struct pci_device_id pciidlist[] = { 879 #ifdef CONFIG_DRM_AMDGPU_SI 880 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 881 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 882 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 883 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 884 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 885 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 886 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 887 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 888 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 889 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 890 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 891 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 892 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 893 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 894 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 895 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 896 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 897 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 898 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 899 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 900 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 901 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 902 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 903 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 904 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 905 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 906 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 907 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 908 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 909 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 910 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 911 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 912 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 913 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 914 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 915 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 916 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 917 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 918 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 919 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 920 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 921 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 922 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 923 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 924 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 925 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 926 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 927 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 928 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 929 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 930 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 931 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 932 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 933 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 934 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 935 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 936 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 937 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 938 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 939 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 940 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 941 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 942 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 943 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 944 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 945 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 946 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 947 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 948 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 949 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 950 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 951 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 952 #endif 953 #ifdef CONFIG_DRM_AMDGPU_CIK 954 /* Kaveri */ 955 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 956 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 957 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 958 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 959 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 960 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 961 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 962 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 963 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 964 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 965 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 966 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 967 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 968 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 969 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 970 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 971 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 972 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 973 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 974 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 975 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 976 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 977 /* Bonaire */ 978 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 979 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 980 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 981 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 982 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 983 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 984 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 985 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 986 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 987 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 988 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 989 /* Hawaii */ 990 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 991 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 992 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 993 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 994 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 995 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 996 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 997 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 998 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 999 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1000 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1001 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1002 /* Kabini */ 1003 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1004 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1005 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1006 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1007 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1008 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1009 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1010 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1011 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1012 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1013 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1014 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1015 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1016 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1017 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1018 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1019 /* mullins */ 1020 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1021 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1022 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1023 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1024 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1025 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1026 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1027 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1028 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1029 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1030 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1031 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1032 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1033 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1034 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1035 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1036 #endif 1037 /* topaz */ 1038 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1039 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1040 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1041 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1042 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1043 /* tonga */ 1044 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1045 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1046 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1047 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1048 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1049 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1050 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1051 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1052 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1053 /* fiji */ 1054 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1055 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1056 /* carrizo */ 1057 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1058 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1059 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1060 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1061 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1062 /* stoney */ 1063 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1064 /* Polaris11 */ 1065 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1066 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1067 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1068 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1069 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1070 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1071 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1072 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1073 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1074 /* Polaris10 */ 1075 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1076 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1077 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1078 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1079 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1080 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1081 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1082 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1083 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1084 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1085 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1086 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1087 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1088 /* Polaris12 */ 1089 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1090 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1091 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1092 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1093 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1094 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1095 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1096 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1097 /* VEGAM */ 1098 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1099 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1100 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1101 /* Vega 10 */ 1102 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1103 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1104 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1105 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1106 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1107 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1108 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1109 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1110 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1111 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1112 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1113 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1114 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1115 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1116 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1117 /* Vega 12 */ 1118 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1119 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1120 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1121 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1122 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1123 /* Vega 20 */ 1124 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1125 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1126 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1127 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1128 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1129 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1130 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1131 /* Raven */ 1132 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1133 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1134 /* Arcturus */ 1135 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1136 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1137 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1138 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1139 /* Navi10 */ 1140 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1141 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1142 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1143 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1144 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1145 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1146 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1147 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1148 /* Navi14 */ 1149 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1150 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1151 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1152 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1153 1154 /* Renoir */ 1155 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1156 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1157 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1158 1159 /* Navi12 */ 1160 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1161 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1162 1163 /* Sienna_Cichlid */ 1164 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1165 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1166 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1167 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1168 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1169 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1170 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1171 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1172 1173 /* Van Gogh */ 1174 {0x1002, 0x163F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VANGOGH|AMD_IS_APU}, 1175 1176 /* Navy_Flounder */ 1177 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1178 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1179 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1180 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1181 1182 /* DIMGREY_CAVEFISH */ 1183 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1184 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1185 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1186 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1187 1188 /* Aldebaran */ 1189 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT}, 1190 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT}, 1191 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT}, 1192 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT}, 1193 1194 {0, 0, 0} 1195 }; 1196 1197 MODULE_DEVICE_TABLE(pci, pciidlist); 1198 1199 static const struct drm_driver amdgpu_kms_driver; 1200 1201 static int amdgpu_pci_probe(struct pci_dev *pdev, 1202 const struct pci_device_id *ent) 1203 { 1204 struct drm_device *ddev; 1205 struct amdgpu_device *adev; 1206 unsigned long flags = ent->driver_data; 1207 int ret, retry = 0; 1208 bool supports_atomic = false; 1209 1210 if (!amdgpu_virtual_display && 1211 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 1212 supports_atomic = true; 1213 1214 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 1215 DRM_INFO("This hardware requires experimental hardware support.\n" 1216 "See modparam exp_hw_support\n"); 1217 return -ENODEV; 1218 } 1219 1220 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 1221 * however, SME requires an indirect IOMMU mapping because the encryption 1222 * bit is beyond the DMA mask of the chip. 1223 */ 1224 if (mem_encrypt_active() && ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 1225 dev_info(&pdev->dev, 1226 "SME is not compatible with RAVEN\n"); 1227 return -ENOTSUPP; 1228 } 1229 1230 #ifdef CONFIG_DRM_AMDGPU_SI 1231 if (!amdgpu_si_support) { 1232 switch (flags & AMD_ASIC_MASK) { 1233 case CHIP_TAHITI: 1234 case CHIP_PITCAIRN: 1235 case CHIP_VERDE: 1236 case CHIP_OLAND: 1237 case CHIP_HAINAN: 1238 dev_info(&pdev->dev, 1239 "SI support provided by radeon.\n"); 1240 dev_info(&pdev->dev, 1241 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 1242 ); 1243 return -ENODEV; 1244 } 1245 } 1246 #endif 1247 #ifdef CONFIG_DRM_AMDGPU_CIK 1248 if (!amdgpu_cik_support) { 1249 switch (flags & AMD_ASIC_MASK) { 1250 case CHIP_KAVERI: 1251 case CHIP_BONAIRE: 1252 case CHIP_HAWAII: 1253 case CHIP_KABINI: 1254 case CHIP_MULLINS: 1255 dev_info(&pdev->dev, 1256 "CIK support provided by radeon.\n"); 1257 dev_info(&pdev->dev, 1258 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 1259 ); 1260 return -ENODEV; 1261 } 1262 } 1263 #endif 1264 1265 /* Get rid of things like offb */ 1266 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, "amdgpudrmfb"); 1267 if (ret) 1268 return ret; 1269 1270 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 1271 if (IS_ERR(adev)) 1272 return PTR_ERR(adev); 1273 1274 adev->dev = &pdev->dev; 1275 adev->pdev = pdev; 1276 ddev = adev_to_drm(adev); 1277 1278 if (!supports_atomic) 1279 ddev->driver_features &= ~DRIVER_ATOMIC; 1280 1281 ret = pci_enable_device(pdev); 1282 if (ret) 1283 return ret; 1284 1285 pci_set_drvdata(pdev, ddev); 1286 1287 ret = amdgpu_driver_load_kms(adev, ent->driver_data); 1288 if (ret) 1289 goto err_pci; 1290 1291 retry_init: 1292 ret = drm_dev_register(ddev, ent->driver_data); 1293 if (ret == -EAGAIN && ++retry <= 3) { 1294 DRM_INFO("retry init %d\n", retry); 1295 /* Don't request EX mode too frequently which is attacking */ 1296 msleep(5000); 1297 goto retry_init; 1298 } else if (ret) { 1299 goto err_pci; 1300 } 1301 1302 ret = amdgpu_debugfs_init(adev); 1303 if (ret) 1304 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 1305 1306 return 0; 1307 1308 err_pci: 1309 pci_disable_device(pdev); 1310 return ret; 1311 } 1312 1313 static void 1314 amdgpu_pci_remove(struct pci_dev *pdev) 1315 { 1316 struct drm_device *dev = pci_get_drvdata(pdev); 1317 1318 drm_dev_unplug(dev); 1319 amdgpu_driver_unload_kms(dev); 1320 1321 /* 1322 * Flush any in flight DMA operations from device. 1323 * Clear the Bus Master Enable bit and then wait on the PCIe Device 1324 * StatusTransactions Pending bit. 1325 */ 1326 pci_disable_device(pdev); 1327 pci_wait_for_pending_transaction(pdev); 1328 } 1329 1330 static void 1331 amdgpu_pci_shutdown(struct pci_dev *pdev) 1332 { 1333 struct drm_device *dev = pci_get_drvdata(pdev); 1334 struct amdgpu_device *adev = drm_to_adev(dev); 1335 1336 if (amdgpu_ras_intr_triggered()) 1337 return; 1338 1339 /* if we are running in a VM, make sure the device 1340 * torn down properly on reboot/shutdown. 1341 * unfortunately we can't detect certain 1342 * hypervisors so just do this all the time. 1343 */ 1344 if (!amdgpu_passthrough(adev)) 1345 adev->mp1_state = PP_MP1_STATE_UNLOAD; 1346 amdgpu_device_ip_suspend(adev); 1347 adev->mp1_state = PP_MP1_STATE_NONE; 1348 } 1349 1350 /** 1351 * amdgpu_drv_delayed_reset_work_handler - work handler for reset 1352 * 1353 * @work: work_struct. 1354 */ 1355 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) 1356 { 1357 struct list_head device_list; 1358 struct amdgpu_device *adev; 1359 int i, r; 1360 struct amdgpu_reset_context reset_context; 1361 1362 memset(&reset_context, 0, sizeof(reset_context)); 1363 1364 mutex_lock(&mgpu_info.mutex); 1365 if (mgpu_info.pending_reset == true) { 1366 mutex_unlock(&mgpu_info.mutex); 1367 return; 1368 } 1369 mgpu_info.pending_reset = true; 1370 mutex_unlock(&mgpu_info.mutex); 1371 1372 /* Use a common context, just need to make sure full reset is done */ 1373 reset_context.method = AMD_RESET_METHOD_NONE; 1374 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 1375 1376 for (i = 0; i < mgpu_info.num_dgpu; i++) { 1377 adev = mgpu_info.gpu_ins[i].adev; 1378 reset_context.reset_req_dev = adev; 1379 r = amdgpu_device_pre_asic_reset(adev, &reset_context); 1380 if (r) { 1381 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", 1382 r, adev_to_drm(adev)->unique); 1383 } 1384 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) 1385 r = -EALREADY; 1386 } 1387 for (i = 0; i < mgpu_info.num_dgpu; i++) { 1388 adev = mgpu_info.gpu_ins[i].adev; 1389 flush_work(&adev->xgmi_reset_work); 1390 adev->gmc.xgmi.pending_reset = false; 1391 } 1392 1393 /* reset function will rebuild the xgmi hive info , clear it now */ 1394 for (i = 0; i < mgpu_info.num_dgpu; i++) 1395 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); 1396 1397 INIT_LIST_HEAD(&device_list); 1398 1399 for (i = 0; i < mgpu_info.num_dgpu; i++) 1400 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); 1401 1402 /* unregister the GPU first, reset function will add them back */ 1403 list_for_each_entry(adev, &device_list, reset_list) 1404 amdgpu_unregister_gpu_instance(adev); 1405 1406 /* Use a common context, just need to make sure full reset is done */ 1407 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); 1408 r = amdgpu_do_asic_reset(&device_list, &reset_context); 1409 1410 if (r) { 1411 DRM_ERROR("reinit gpus failure"); 1412 return; 1413 } 1414 for (i = 0; i < mgpu_info.num_dgpu; i++) { 1415 adev = mgpu_info.gpu_ins[i].adev; 1416 if (!adev->kfd.init_complete) 1417 amdgpu_amdkfd_device_init(adev); 1418 amdgpu_ttm_set_buffer_funcs_status(adev, true); 1419 } 1420 return; 1421 } 1422 1423 static int amdgpu_pmops_prepare(struct device *dev) 1424 { 1425 struct drm_device *drm_dev = dev_get_drvdata(dev); 1426 1427 /* Return a positive number here so 1428 * DPM_FLAG_SMART_SUSPEND works properly 1429 */ 1430 if (amdgpu_device_supports_boco(drm_dev)) 1431 return pm_runtime_suspended(dev) && 1432 pm_suspend_via_firmware(); 1433 1434 return 0; 1435 } 1436 1437 static void amdgpu_pmops_complete(struct device *dev) 1438 { 1439 /* nothing to do */ 1440 } 1441 1442 static int amdgpu_pmops_suspend(struct device *dev) 1443 { 1444 struct drm_device *drm_dev = dev_get_drvdata(dev); 1445 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1446 int r; 1447 1448 if (amdgpu_acpi_is_s0ix_supported(adev)) 1449 adev->in_s0ix = true; 1450 adev->in_s3 = true; 1451 r = amdgpu_device_suspend(drm_dev, true); 1452 adev->in_s3 = false; 1453 1454 return r; 1455 } 1456 1457 static int amdgpu_pmops_resume(struct device *dev) 1458 { 1459 struct drm_device *drm_dev = dev_get_drvdata(dev); 1460 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1461 int r; 1462 1463 r = amdgpu_device_resume(drm_dev, true); 1464 if (amdgpu_acpi_is_s0ix_supported(adev)) 1465 adev->in_s0ix = false; 1466 return r; 1467 } 1468 1469 static int amdgpu_pmops_freeze(struct device *dev) 1470 { 1471 struct drm_device *drm_dev = dev_get_drvdata(dev); 1472 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1473 int r; 1474 1475 adev->in_s4 = true; 1476 r = amdgpu_device_suspend(drm_dev, true); 1477 adev->in_s4 = false; 1478 if (r) 1479 return r; 1480 return amdgpu_asic_reset(adev); 1481 } 1482 1483 static int amdgpu_pmops_thaw(struct device *dev) 1484 { 1485 struct drm_device *drm_dev = dev_get_drvdata(dev); 1486 1487 return amdgpu_device_resume(drm_dev, true); 1488 } 1489 1490 static int amdgpu_pmops_poweroff(struct device *dev) 1491 { 1492 struct drm_device *drm_dev = dev_get_drvdata(dev); 1493 1494 return amdgpu_device_suspend(drm_dev, true); 1495 } 1496 1497 static int amdgpu_pmops_restore(struct device *dev) 1498 { 1499 struct drm_device *drm_dev = dev_get_drvdata(dev); 1500 1501 return amdgpu_device_resume(drm_dev, true); 1502 } 1503 1504 static int amdgpu_pmops_runtime_suspend(struct device *dev) 1505 { 1506 struct pci_dev *pdev = to_pci_dev(dev); 1507 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1508 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1509 int ret, i; 1510 1511 if (!adev->runpm) { 1512 pm_runtime_forbid(dev); 1513 return -EBUSY; 1514 } 1515 1516 /* wait for all rings to drain before suspending */ 1517 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 1518 struct amdgpu_ring *ring = adev->rings[i]; 1519 if (ring && ring->sched.ready) { 1520 ret = amdgpu_fence_wait_empty(ring); 1521 if (ret) 1522 return -EBUSY; 1523 } 1524 } 1525 1526 adev->in_runpm = true; 1527 if (amdgpu_device_supports_px(drm_dev)) 1528 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1529 1530 ret = amdgpu_device_suspend(drm_dev, false); 1531 if (ret) { 1532 adev->in_runpm = false; 1533 return ret; 1534 } 1535 1536 if (amdgpu_device_supports_px(drm_dev)) { 1537 /* Only need to handle PCI state in the driver for ATPX 1538 * PCI core handles it for _PR3. 1539 */ 1540 amdgpu_device_cache_pci_state(pdev); 1541 pci_disable_device(pdev); 1542 pci_ignore_hotplug(pdev); 1543 pci_set_power_state(pdev, PCI_D3cold); 1544 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 1545 } else if (amdgpu_device_supports_baco(drm_dev)) { 1546 amdgpu_device_baco_enter(drm_dev); 1547 } 1548 1549 return 0; 1550 } 1551 1552 static int amdgpu_pmops_runtime_resume(struct device *dev) 1553 { 1554 struct pci_dev *pdev = to_pci_dev(dev); 1555 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1556 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1557 int ret; 1558 1559 if (!adev->runpm) 1560 return -EINVAL; 1561 1562 /* Avoids registers access if device is physically gone */ 1563 if (!pci_device_is_present(adev->pdev)) 1564 adev->no_hw_access = true; 1565 1566 if (amdgpu_device_supports_px(drm_dev)) { 1567 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1568 1569 /* Only need to handle PCI state in the driver for ATPX 1570 * PCI core handles it for _PR3. 1571 */ 1572 pci_set_power_state(pdev, PCI_D0); 1573 amdgpu_device_load_pci_state(pdev); 1574 ret = pci_enable_device(pdev); 1575 if (ret) 1576 return ret; 1577 pci_set_master(pdev); 1578 } else if (amdgpu_device_supports_boco(drm_dev)) { 1579 /* Only need to handle PCI state in the driver for ATPX 1580 * PCI core handles it for _PR3. 1581 */ 1582 pci_set_master(pdev); 1583 } else if (amdgpu_device_supports_baco(drm_dev)) { 1584 amdgpu_device_baco_exit(drm_dev); 1585 } 1586 ret = amdgpu_device_resume(drm_dev, false); 1587 if (ret) 1588 return ret; 1589 1590 if (amdgpu_device_supports_px(drm_dev)) 1591 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 1592 adev->in_runpm = false; 1593 return 0; 1594 } 1595 1596 static int amdgpu_pmops_runtime_idle(struct device *dev) 1597 { 1598 struct drm_device *drm_dev = dev_get_drvdata(dev); 1599 struct amdgpu_device *adev = drm_to_adev(drm_dev); 1600 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 1601 int ret = 1; 1602 1603 if (!adev->runpm) { 1604 pm_runtime_forbid(dev); 1605 return -EBUSY; 1606 } 1607 1608 if (amdgpu_device_has_dc_support(adev)) { 1609 struct drm_crtc *crtc; 1610 1611 drm_for_each_crtc(crtc, drm_dev) { 1612 drm_modeset_lock(&crtc->mutex, NULL); 1613 if (crtc->state->active) 1614 ret = -EBUSY; 1615 drm_modeset_unlock(&crtc->mutex); 1616 if (ret < 0) 1617 break; 1618 } 1619 1620 } else { 1621 struct drm_connector *list_connector; 1622 struct drm_connector_list_iter iter; 1623 1624 mutex_lock(&drm_dev->mode_config.mutex); 1625 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 1626 1627 drm_connector_list_iter_begin(drm_dev, &iter); 1628 drm_for_each_connector_iter(list_connector, &iter) { 1629 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 1630 ret = -EBUSY; 1631 break; 1632 } 1633 } 1634 1635 drm_connector_list_iter_end(&iter); 1636 1637 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 1638 mutex_unlock(&drm_dev->mode_config.mutex); 1639 } 1640 1641 if (ret == -EBUSY) 1642 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 1643 1644 pm_runtime_mark_last_busy(dev); 1645 pm_runtime_autosuspend(dev); 1646 return ret; 1647 } 1648 1649 long amdgpu_drm_ioctl(struct file *filp, 1650 unsigned int cmd, unsigned long arg) 1651 { 1652 struct drm_file *file_priv = filp->private_data; 1653 struct drm_device *dev; 1654 long ret; 1655 dev = file_priv->minor->dev; 1656 ret = pm_runtime_get_sync(dev->dev); 1657 if (ret < 0) 1658 goto out; 1659 1660 ret = drm_ioctl(filp, cmd, arg); 1661 1662 pm_runtime_mark_last_busy(dev->dev); 1663 out: 1664 pm_runtime_put_autosuspend(dev->dev); 1665 return ret; 1666 } 1667 1668 static const struct dev_pm_ops amdgpu_pm_ops = { 1669 .prepare = amdgpu_pmops_prepare, 1670 .complete = amdgpu_pmops_complete, 1671 .suspend = amdgpu_pmops_suspend, 1672 .resume = amdgpu_pmops_resume, 1673 .freeze = amdgpu_pmops_freeze, 1674 .thaw = amdgpu_pmops_thaw, 1675 .poweroff = amdgpu_pmops_poweroff, 1676 .restore = amdgpu_pmops_restore, 1677 .runtime_suspend = amdgpu_pmops_runtime_suspend, 1678 .runtime_resume = amdgpu_pmops_runtime_resume, 1679 .runtime_idle = amdgpu_pmops_runtime_idle, 1680 }; 1681 1682 static int amdgpu_flush(struct file *f, fl_owner_t id) 1683 { 1684 struct drm_file *file_priv = f->private_data; 1685 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1686 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 1687 1688 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 1689 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 1690 1691 return timeout >= 0 ? 0 : timeout; 1692 } 1693 1694 static const struct file_operations amdgpu_driver_kms_fops = { 1695 .owner = THIS_MODULE, 1696 .open = drm_open, 1697 .flush = amdgpu_flush, 1698 .release = drm_release, 1699 .unlocked_ioctl = amdgpu_drm_ioctl, 1700 .mmap = drm_gem_mmap, 1701 .poll = drm_poll, 1702 .read = drm_read, 1703 #ifdef CONFIG_COMPAT 1704 .compat_ioctl = amdgpu_kms_compat_ioctl, 1705 #endif 1706 #ifdef CONFIG_PROC_FS 1707 .show_fdinfo = amdgpu_show_fdinfo 1708 #endif 1709 }; 1710 1711 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 1712 { 1713 struct drm_file *file; 1714 1715 if (!filp) 1716 return -EINVAL; 1717 1718 if (filp->f_op != &amdgpu_driver_kms_fops) { 1719 return -EINVAL; 1720 } 1721 1722 file = filp->private_data; 1723 *fpriv = file->driver_priv; 1724 return 0; 1725 } 1726 1727 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 1728 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1729 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1730 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1731 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 1732 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1733 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1734 /* KMS */ 1735 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1736 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1737 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1738 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1739 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1740 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1741 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1742 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1743 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1744 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1745 }; 1746 1747 static const struct drm_driver amdgpu_kms_driver = { 1748 .driver_features = 1749 DRIVER_ATOMIC | 1750 DRIVER_GEM | 1751 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 1752 DRIVER_SYNCOBJ_TIMELINE, 1753 .open = amdgpu_driver_open_kms, 1754 .postclose = amdgpu_driver_postclose_kms, 1755 .lastclose = amdgpu_driver_lastclose_kms, 1756 .irq_handler = amdgpu_irq_handler, 1757 .ioctls = amdgpu_ioctls_kms, 1758 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 1759 .dumb_create = amdgpu_mode_dumb_create, 1760 .dumb_map_offset = amdgpu_mode_dumb_mmap, 1761 .fops = &amdgpu_driver_kms_fops, 1762 .release = &amdgpu_driver_release_kms, 1763 1764 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 1765 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 1766 .gem_prime_import = amdgpu_gem_prime_import, 1767 .gem_prime_mmap = drm_gem_prime_mmap, 1768 1769 .name = DRIVER_NAME, 1770 .desc = DRIVER_DESC, 1771 .date = DRIVER_DATE, 1772 .major = KMS_DRIVER_MAJOR, 1773 .minor = KMS_DRIVER_MINOR, 1774 .patchlevel = KMS_DRIVER_PATCHLEVEL, 1775 }; 1776 1777 static struct pci_error_handlers amdgpu_pci_err_handler = { 1778 .error_detected = amdgpu_pci_error_detected, 1779 .mmio_enabled = amdgpu_pci_mmio_enabled, 1780 .slot_reset = amdgpu_pci_slot_reset, 1781 .resume = amdgpu_pci_resume, 1782 }; 1783 1784 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 1785 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 1786 extern const struct attribute_group amdgpu_vbios_version_attr_group; 1787 1788 static const struct attribute_group *amdgpu_sysfs_groups[] = { 1789 &amdgpu_vram_mgr_attr_group, 1790 &amdgpu_gtt_mgr_attr_group, 1791 &amdgpu_vbios_version_attr_group, 1792 NULL, 1793 }; 1794 1795 1796 static struct pci_driver amdgpu_kms_pci_driver = { 1797 .name = DRIVER_NAME, 1798 .id_table = pciidlist, 1799 .probe = amdgpu_pci_probe, 1800 .remove = amdgpu_pci_remove, 1801 .shutdown = amdgpu_pci_shutdown, 1802 .driver.pm = &amdgpu_pm_ops, 1803 .err_handler = &amdgpu_pci_err_handler, 1804 .dev_groups = amdgpu_sysfs_groups, 1805 }; 1806 1807 static int __init amdgpu_init(void) 1808 { 1809 int r; 1810 1811 if (vgacon_text_force()) { 1812 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); 1813 return -EINVAL; 1814 } 1815 1816 r = amdgpu_sync_init(); 1817 if (r) 1818 goto error_sync; 1819 1820 r = amdgpu_fence_slab_init(); 1821 if (r) 1822 goto error_fence; 1823 1824 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 1825 amdgpu_register_atpx_handler(); 1826 amdgpu_acpi_detect(); 1827 1828 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 1829 amdgpu_amdkfd_init(); 1830 1831 /* let modprobe override vga console setting */ 1832 return pci_register_driver(&amdgpu_kms_pci_driver); 1833 1834 error_fence: 1835 amdgpu_sync_fini(); 1836 1837 error_sync: 1838 return r; 1839 } 1840 1841 static void __exit amdgpu_exit(void) 1842 { 1843 amdgpu_amdkfd_fini(); 1844 pci_unregister_driver(&amdgpu_kms_pci_driver); 1845 amdgpu_unregister_atpx_handler(); 1846 amdgpu_sync_fini(); 1847 amdgpu_fence_slab_fini(); 1848 mmu_notifier_synchronize(); 1849 } 1850 1851 module_init(amdgpu_init); 1852 module_exit(amdgpu_exit); 1853 1854 MODULE_AUTHOR(DRIVER_AUTHOR); 1855 MODULE_DESCRIPTION(DRIVER_DESC); 1856 MODULE_LICENSE("GPL and additional rights"); 1857