1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef AMDGPU_DOORBELL_H 25 #define AMDGPU_DOORBELL_H 26 27 /* 28 * GPU doorbell structures, functions & helpers 29 */ 30 struct amdgpu_doorbell { 31 /* doorbell mmio */ 32 resource_size_t base; 33 resource_size_t size; 34 u32 __iomem *ptr; 35 36 /* Number of doorbells reserved for amdgpu kernel driver */ 37 u32 num_kernel_doorbells; 38 }; 39 40 /* Reserved doorbells for amdgpu (including multimedia). 41 * KFD can use all the rest in the 2M doorbell bar. 42 * For asic before vega10, doorbell is 32-bit, so the 43 * index/offset is in dword. For vega10 and after, doorbell 44 * can be 64-bit, so the index defined is in qword. 45 */ 46 struct amdgpu_doorbell_index { 47 uint32_t kiq; 48 uint32_t mec_ring0; 49 uint32_t mec_ring1; 50 uint32_t mec_ring2; 51 uint32_t mec_ring3; 52 uint32_t mec_ring4; 53 uint32_t mec_ring5; 54 uint32_t mec_ring6; 55 uint32_t mec_ring7; 56 uint32_t userqueue_start; 57 uint32_t userqueue_end; 58 uint32_t gfx_ring0; 59 uint32_t gfx_ring1; 60 uint32_t gfx_userqueue_start; 61 uint32_t gfx_userqueue_end; 62 uint32_t sdma_engine[16]; 63 uint32_t mes_ring0; 64 uint32_t mes_ring1; 65 uint32_t ih; 66 union { 67 struct { 68 uint32_t vcn_ring0_1; 69 uint32_t vcn_ring2_3; 70 uint32_t vcn_ring4_5; 71 uint32_t vcn_ring6_7; 72 } vcn; 73 struct { 74 uint32_t uvd_ring0_1; 75 uint32_t uvd_ring2_3; 76 uint32_t uvd_ring4_5; 77 uint32_t uvd_ring6_7; 78 uint32_t vce_ring0_1; 79 uint32_t vce_ring2_3; 80 uint32_t vce_ring4_5; 81 uint32_t vce_ring6_7; 82 } uvd_vce; 83 }; 84 uint32_t first_non_cp; 85 uint32_t last_non_cp; 86 uint32_t max_assignment; 87 /* Per engine SDMA doorbell size in dword */ 88 uint32_t sdma_doorbell_range; 89 /* Per xcc doorbell size for KIQ/KCQ */ 90 uint32_t xcc_doorbell_range; 91 }; 92 93 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT 94 { 95 AMDGPU_DOORBELL_KIQ = 0x000, 96 AMDGPU_DOORBELL_HIQ = 0x001, 97 AMDGPU_DOORBELL_DIQ = 0x002, 98 AMDGPU_DOORBELL_MEC_RING0 = 0x010, 99 AMDGPU_DOORBELL_MEC_RING1 = 0x011, 100 AMDGPU_DOORBELL_MEC_RING2 = 0x012, 101 AMDGPU_DOORBELL_MEC_RING3 = 0x013, 102 AMDGPU_DOORBELL_MEC_RING4 = 0x014, 103 AMDGPU_DOORBELL_MEC_RING5 = 0x015, 104 AMDGPU_DOORBELL_MEC_RING6 = 0x016, 105 AMDGPU_DOORBELL_MEC_RING7 = 0x017, 106 AMDGPU_DOORBELL_GFX_RING0 = 0x020, 107 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, 108 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, 109 AMDGPU_DOORBELL_IH = 0x1E8, 110 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, 111 AMDGPU_DOORBELL_INVALID = 0xFFFF 112 } AMDGPU_DOORBELL_ASSIGNMENT; 113 114 typedef enum _AMDGPU_VEGA20_DOORBELL_ASSIGNMENT 115 { 116 /* Compute + GFX: 0~255 */ 117 AMDGPU_VEGA20_DOORBELL_KIQ = 0x000, 118 AMDGPU_VEGA20_DOORBELL_HIQ = 0x001, 119 AMDGPU_VEGA20_DOORBELL_DIQ = 0x002, 120 AMDGPU_VEGA20_DOORBELL_MEC_RING0 = 0x003, 121 AMDGPU_VEGA20_DOORBELL_MEC_RING1 = 0x004, 122 AMDGPU_VEGA20_DOORBELL_MEC_RING2 = 0x005, 123 AMDGPU_VEGA20_DOORBELL_MEC_RING3 = 0x006, 124 AMDGPU_VEGA20_DOORBELL_MEC_RING4 = 0x007, 125 AMDGPU_VEGA20_DOORBELL_MEC_RING5 = 0x008, 126 AMDGPU_VEGA20_DOORBELL_MEC_RING6 = 0x009, 127 AMDGPU_VEGA20_DOORBELL_MEC_RING7 = 0x00A, 128 AMDGPU_VEGA20_DOORBELL_USERQUEUE_START = 0x00B, 129 AMDGPU_VEGA20_DOORBELL_USERQUEUE_END = 0x08A, 130 AMDGPU_VEGA20_DOORBELL_GFX_RING0 = 0x08B, 131 /* SDMA:256~335*/ 132 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0 = 0x100, 133 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1 = 0x10A, 134 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2 = 0x114, 135 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3 = 0x11E, 136 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4 = 0x128, 137 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5 = 0x132, 138 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6 = 0x13C, 139 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7 = 0x146, 140 /* IH: 376~391 */ 141 AMDGPU_VEGA20_DOORBELL_IH = 0x178, 142 /* MMSCH: 392~407 143 * overlap the doorbell assignment with VCN as they are mutually exclusive 144 * VCN engine's doorbell is 32 bit and two VCN ring share one QWORD 145 */ 146 AMDGPU_VEGA20_DOORBELL64_VCN0_1 = 0x188, /* VNC0 */ 147 AMDGPU_VEGA20_DOORBELL64_VCN2_3 = 0x189, 148 AMDGPU_VEGA20_DOORBELL64_VCN4_5 = 0x18A, 149 AMDGPU_VEGA20_DOORBELL64_VCN6_7 = 0x18B, 150 151 AMDGPU_VEGA20_DOORBELL64_VCN8_9 = 0x18C, /* VNC1 */ 152 AMDGPU_VEGA20_DOORBELL64_VCNa_b = 0x18D, 153 AMDGPU_VEGA20_DOORBELL64_VCNc_d = 0x18E, 154 AMDGPU_VEGA20_DOORBELL64_VCNe_f = 0x18F, 155 156 AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1 = 0x188, 157 AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3 = 0x189, 158 AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5 = 0x18A, 159 AMDGPU_VEGA20_DOORBELL64_UVD_RING6_7 = 0x18B, 160 161 AMDGPU_VEGA20_DOORBELL64_VCE_RING0_1 = 0x18C, 162 AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3 = 0x18D, 163 AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5 = 0x18E, 164 AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7 = 0x18F, 165 166 AMDGPU_VEGA20_DOORBELL64_FIRST_NON_CP = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0, 167 AMDGPU_VEGA20_DOORBELL64_LAST_NON_CP = AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7, 168 169 /* kiq/kcq from second XCD. Max 8 XCDs */ 170 AMDGPU_VEGA20_DOORBELL_XCC1_KIQ_START = 0x190, 171 /* 8 compute rings per GC. Max to 0x1CE */ 172 AMDGPU_VEGA20_DOORBELL_XCC1_MEC_RING0_START = 0x197, 173 174 /* AID1 SDMA: 0x1D0 ~ 0x1F7 */ 175 AMDGPU_VEGA20_DOORBELL_AID1_sDMA_START = 0x1D0, 176 177 AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT = 0x1F7, 178 AMDGPU_VEGA20_DOORBELL_INVALID = 0xFFFF 179 } AMDGPU_VEGA20_DOORBELL_ASSIGNMENT; 180 181 typedef enum _AMDGPU_NAVI10_DOORBELL_ASSIGNMENT 182 { 183 /* Compute + GFX: 0~255 */ 184 AMDGPU_NAVI10_DOORBELL_KIQ = 0x000, 185 AMDGPU_NAVI10_DOORBELL_HIQ = 0x001, 186 AMDGPU_NAVI10_DOORBELL_DIQ = 0x002, 187 AMDGPU_NAVI10_DOORBELL_MEC_RING0 = 0x003, 188 AMDGPU_NAVI10_DOORBELL_MEC_RING1 = 0x004, 189 AMDGPU_NAVI10_DOORBELL_MEC_RING2 = 0x005, 190 AMDGPU_NAVI10_DOORBELL_MEC_RING3 = 0x006, 191 AMDGPU_NAVI10_DOORBELL_MEC_RING4 = 0x007, 192 AMDGPU_NAVI10_DOORBELL_MEC_RING5 = 0x008, 193 AMDGPU_NAVI10_DOORBELL_MEC_RING6 = 0x009, 194 AMDGPU_NAVI10_DOORBELL_MEC_RING7 = 0x00A, 195 AMDGPU_NAVI10_DOORBELL_MES_RING0 = 0x00B, 196 AMDGPU_NAVI10_DOORBELL_MES_RING1 = 0x00C, 197 AMDGPU_NAVI10_DOORBELL_USERQUEUE_START = 0x00D, 198 AMDGPU_NAVI10_DOORBELL_USERQUEUE_END = 0x08A, 199 AMDGPU_NAVI10_DOORBELL_GFX_RING0 = 0x08B, 200 AMDGPU_NAVI10_DOORBELL_GFX_RING1 = 0x08C, 201 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START = 0x08D, 202 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END = 0x0FF, 203 204 /* SDMA:256~335*/ 205 AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0 = 0x100, 206 AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1 = 0x10A, 207 AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2 = 0x114, 208 AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3 = 0x11E, 209 /* IH: 376~391 */ 210 AMDGPU_NAVI10_DOORBELL_IH = 0x178, 211 /* MMSCH: 392~407 212 * overlap the doorbell assignment with VCN as they are mutually exclusive 213 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD 214 */ 215 AMDGPU_NAVI10_DOORBELL64_VCN0_1 = 0x188, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */ 216 AMDGPU_NAVI10_DOORBELL64_VCN2_3 = 0x189, 217 AMDGPU_NAVI10_DOORBELL64_VCN4_5 = 0x18A, 218 AMDGPU_NAVI10_DOORBELL64_VCN6_7 = 0x18B, 219 220 AMDGPU_NAVI10_DOORBELL64_VCN8_9 = 0x18C, 221 AMDGPU_NAVI10_DOORBELL64_VCNa_b = 0x18D, 222 AMDGPU_NAVI10_DOORBELL64_VCNc_d = 0x18E, 223 AMDGPU_NAVI10_DOORBELL64_VCNe_f = 0x18F, 224 225 AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0, 226 AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP = AMDGPU_NAVI10_DOORBELL64_VCNe_f, 227 228 AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT = 0x18F, 229 AMDGPU_NAVI10_DOORBELL_INVALID = 0xFFFF 230 } AMDGPU_NAVI10_DOORBELL_ASSIGNMENT; 231 232 /* 233 * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space 234 */ 235 typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT 236 { 237 /* 238 * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in 239 * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range. 240 * Compute related doorbells are allocated from 0x00 to 0x8a 241 */ 242 243 244 /* kernel scheduling */ 245 AMDGPU_DOORBELL64_KIQ = 0x00, 246 247 /* HSA interface queue and debug queue */ 248 AMDGPU_DOORBELL64_HIQ = 0x01, 249 AMDGPU_DOORBELL64_DIQ = 0x02, 250 251 /* Compute engines */ 252 AMDGPU_DOORBELL64_MEC_RING0 = 0x03, 253 AMDGPU_DOORBELL64_MEC_RING1 = 0x04, 254 AMDGPU_DOORBELL64_MEC_RING2 = 0x05, 255 AMDGPU_DOORBELL64_MEC_RING3 = 0x06, 256 AMDGPU_DOORBELL64_MEC_RING4 = 0x07, 257 AMDGPU_DOORBELL64_MEC_RING5 = 0x08, 258 AMDGPU_DOORBELL64_MEC_RING6 = 0x09, 259 AMDGPU_DOORBELL64_MEC_RING7 = 0x0a, 260 261 /* User queue doorbell range (128 doorbells) */ 262 AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b, 263 AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a, 264 265 /* Graphics engine */ 266 AMDGPU_DOORBELL64_GFX_RING0 = 0x8b, 267 268 /* 269 * Other graphics doorbells can be allocated here: from 0x8c to 0xdf 270 * Graphics voltage island aperture 1 271 * default non-graphics QWORD index is 0xe0 - 0xFF inclusive 272 */ 273 274 /* For vega10 sriov, the sdma doorbell must be fixed as follow 275 * to keep the same setting with host driver, or it will 276 * happen conflicts 277 */ 278 AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0, 279 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1, 280 AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2, 281 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3, 282 283 /* Interrupt handler */ 284 AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */ 285 AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */ 286 AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */ 287 288 /* VCN engine use 32 bits doorbell */ 289 AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */ 290 AMDGPU_DOORBELL64_VCN2_3 = 0xF9, 291 AMDGPU_DOORBELL64_VCN4_5 = 0xFA, 292 AMDGPU_DOORBELL64_VCN6_7 = 0xFB, 293 294 /* overlap the doorbell assignment with VCN as they are mutually exclusive 295 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD 296 */ 297 AMDGPU_DOORBELL64_UVD_RING0_1 = 0xF8, 298 AMDGPU_DOORBELL64_UVD_RING2_3 = 0xF9, 299 AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFA, 300 AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFB, 301 302 AMDGPU_DOORBELL64_VCE_RING0_1 = 0xFC, 303 AMDGPU_DOORBELL64_VCE_RING2_3 = 0xFD, 304 AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE, 305 AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF, 306 307 AMDGPU_DOORBELL64_FIRST_NON_CP = AMDGPU_DOORBELL64_sDMA_ENGINE0, 308 AMDGPU_DOORBELL64_LAST_NON_CP = AMDGPU_DOORBELL64_VCE_RING6_7, 309 310 AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF, 311 AMDGPU_DOORBELL64_INVALID = 0xFFFF 312 } AMDGPU_DOORBELL64_ASSIGNMENT; 313 314 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1 { 315 /* XCC0: 0x00 ~20, XCC1: 20 ~ 2F ... */ 316 317 /* KIQ/HIQ/DIQ */ 318 AMDGPU_DOORBELL_LAYOUT1_KIQ_START = 0x000, 319 AMDGPU_DOORBELL_LAYOUT1_HIQ = 0x001, 320 AMDGPU_DOORBELL_LAYOUT1_DIQ = 0x002, 321 /* Compute: 0x08 ~ 0x20 */ 322 AMDGPU_DOORBELL_LAYOUT1_MEC_RING_START = 0x008, 323 AMDGPU_DOORBELL_LAYOUT1_MEC_RING_END = 0x00F, 324 AMDGPU_DOORBELL_LAYOUT1_USERQUEUE_START = 0x010, 325 AMDGPU_DOORBELL_LAYOUT1_USERQUEUE_END = 0x01F, 326 AMDGPU_DOORBELL_LAYOUT1_XCC_RANGE = 0x020, 327 328 /* SDMA: 0x100 ~ 0x19F */ 329 AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_START = 0x100, 330 AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_END = 0x19F, 331 /* IH: 0x1A0 ~ 0x1AF */ 332 AMDGPU_DOORBELL_LAYOUT1_IH = 0x1A0, 333 /* VCN: 0x1B0 ~ 0x1D4 */ 334 AMDGPU_DOORBELL_LAYOUT1_VCN_START = 0x1B0, 335 AMDGPU_DOORBELL_LAYOUT1_VCN_END = 0x1D4, 336 337 AMDGPU_DOORBELL_LAYOUT1_FIRST_NON_CP = AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_START, 338 AMDGPU_DOORBELL_LAYOUT1_LAST_NON_CP = AMDGPU_DOORBELL_LAYOUT1_VCN_END, 339 340 AMDGPU_DOORBELL_LAYOUT1_MAX_ASSIGNMENT = 0x1D4, 341 AMDGPU_DOORBELL_LAYOUT1_INVALID = 0xFFFF 342 } AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1; 343 344 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); 345 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); 346 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index); 347 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v); 348 349 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) 350 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) 351 #define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index)) 352 #define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v)) 353 354 #endif 355