1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/amdgpu_drm.h> 28 #include "amdgpu.h" 29 #include "amdgpu_i2c.h" 30 #include "atom.h" 31 #include "amdgpu_connectors.h" 32 #include <asm/div64.h> 33 34 #include <linux/pm_runtime.h> 35 #include <drm/drm_crtc_helper.h> 36 #include <drm/drm_edid.h> 37 38 static void amdgpu_flip_wait_fence(struct amdgpu_device *adev, 39 struct fence **f) 40 { 41 struct amdgpu_fence *fence; 42 long r; 43 44 if (*f == NULL) 45 return; 46 47 fence = to_amdgpu_fence(*f); 48 if (fence) { 49 r = fence_wait(&fence->base, false); 50 if (r == -EDEADLK) { 51 up_read(&adev->exclusive_lock); 52 r = amdgpu_gpu_reset(adev); 53 down_read(&adev->exclusive_lock); 54 } 55 } else 56 r = fence_wait(*f, false); 57 58 if (r) 59 DRM_ERROR("failed to wait on page flip fence (%ld)!\n", r); 60 61 /* We continue with the page flip even if we failed to wait on 62 * the fence, otherwise the DRM core and userspace will be 63 * confused about which BO the CRTC is scanning out 64 */ 65 fence_put(*f); 66 *f = NULL; 67 } 68 69 static void amdgpu_flip_work_func(struct work_struct *__work) 70 { 71 struct amdgpu_flip_work *work = 72 container_of(__work, struct amdgpu_flip_work, flip_work); 73 struct amdgpu_device *adev = work->adev; 74 struct amdgpu_crtc *amdgpuCrtc = adev->mode_info.crtcs[work->crtc_id]; 75 76 struct drm_crtc *crtc = &amdgpuCrtc->base; 77 unsigned long flags; 78 unsigned i; 79 80 down_read(&adev->exclusive_lock); 81 amdgpu_flip_wait_fence(adev, &work->excl); 82 for (i = 0; i < work->shared_count; ++i) 83 amdgpu_flip_wait_fence(adev, &work->shared[i]); 84 85 /* We borrow the event spin lock for protecting flip_status */ 86 spin_lock_irqsave(&crtc->dev->event_lock, flags); 87 88 /* do the flip (mmio) */ 89 adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base); 90 /* set the flip status */ 91 amdgpuCrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; 92 93 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 94 up_read(&adev->exclusive_lock); 95 } 96 97 /* 98 * Handle unpin events outside the interrupt handler proper. 99 */ 100 static void amdgpu_unpin_work_func(struct work_struct *__work) 101 { 102 struct amdgpu_flip_work *work = 103 container_of(__work, struct amdgpu_flip_work, unpin_work); 104 int r; 105 106 /* unpin of the old buffer */ 107 r = amdgpu_bo_reserve(work->old_rbo, false); 108 if (likely(r == 0)) { 109 r = amdgpu_bo_unpin(work->old_rbo); 110 if (unlikely(r != 0)) { 111 DRM_ERROR("failed to unpin buffer after flip\n"); 112 } 113 amdgpu_bo_unreserve(work->old_rbo); 114 } else 115 DRM_ERROR("failed to reserve buffer after flip\n"); 116 117 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); 118 kfree(work->shared); 119 kfree(work); 120 } 121 122 int amdgpu_crtc_page_flip(struct drm_crtc *crtc, 123 struct drm_framebuffer *fb, 124 struct drm_pending_vblank_event *event, 125 uint32_t page_flip_flags) 126 { 127 struct drm_device *dev = crtc->dev; 128 struct amdgpu_device *adev = dev->dev_private; 129 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 130 struct amdgpu_framebuffer *old_amdgpu_fb; 131 struct amdgpu_framebuffer *new_amdgpu_fb; 132 struct drm_gem_object *obj; 133 struct amdgpu_flip_work *work; 134 struct amdgpu_bo *new_rbo; 135 unsigned long flags; 136 u64 tiling_flags; 137 u64 base; 138 int i, r; 139 140 work = kzalloc(sizeof *work, GFP_KERNEL); 141 if (work == NULL) 142 return -ENOMEM; 143 144 INIT_WORK(&work->flip_work, amdgpu_flip_work_func); 145 INIT_WORK(&work->unpin_work, amdgpu_unpin_work_func); 146 147 work->event = event; 148 work->adev = adev; 149 work->crtc_id = amdgpu_crtc->crtc_id; 150 151 /* schedule unpin of the old buffer */ 152 old_amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); 153 obj = old_amdgpu_fb->obj; 154 155 /* take a reference to the old object */ 156 drm_gem_object_reference(obj); 157 work->old_rbo = gem_to_amdgpu_bo(obj); 158 159 new_amdgpu_fb = to_amdgpu_framebuffer(fb); 160 obj = new_amdgpu_fb->obj; 161 new_rbo = gem_to_amdgpu_bo(obj); 162 163 /* pin the new buffer */ 164 r = amdgpu_bo_reserve(new_rbo, false); 165 if (unlikely(r != 0)) { 166 DRM_ERROR("failed to reserve new rbo buffer before flip\n"); 167 goto cleanup; 168 } 169 170 r = amdgpu_bo_pin_restricted(new_rbo, AMDGPU_GEM_DOMAIN_VRAM, 0, 0, &base); 171 if (unlikely(r != 0)) { 172 amdgpu_bo_unreserve(new_rbo); 173 r = -EINVAL; 174 DRM_ERROR("failed to pin new rbo buffer before flip\n"); 175 goto cleanup; 176 } 177 178 r = reservation_object_get_fences_rcu(new_rbo->tbo.resv, &work->excl, 179 &work->shared_count, 180 &work->shared); 181 if (unlikely(r != 0)) { 182 amdgpu_bo_unreserve(new_rbo); 183 DRM_ERROR("failed to get fences for buffer\n"); 184 goto cleanup; 185 } 186 187 amdgpu_bo_get_tiling_flags(new_rbo, &tiling_flags); 188 amdgpu_bo_unreserve(new_rbo); 189 190 work->base = base; 191 192 r = drm_vblank_get(crtc->dev, amdgpu_crtc->crtc_id); 193 if (r) { 194 DRM_ERROR("failed to get vblank before flip\n"); 195 goto pflip_cleanup; 196 } 197 198 /* we borrow the event spin lock for protecting flip_wrok */ 199 spin_lock_irqsave(&crtc->dev->event_lock, flags); 200 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) { 201 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); 202 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 203 r = -EBUSY; 204 goto vblank_cleanup; 205 } 206 207 amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING; 208 amdgpu_crtc->pflip_works = work; 209 210 /* update crtc fb */ 211 crtc->primary->fb = fb; 212 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 213 queue_work(amdgpu_crtc->pflip_queue, &work->flip_work); 214 return 0; 215 216 vblank_cleanup: 217 drm_vblank_put(crtc->dev, amdgpu_crtc->crtc_id); 218 219 pflip_cleanup: 220 if (unlikely(amdgpu_bo_reserve(new_rbo, false) != 0)) { 221 DRM_ERROR("failed to reserve new rbo in error path\n"); 222 goto cleanup; 223 } 224 if (unlikely(amdgpu_bo_unpin(new_rbo) != 0)) { 225 DRM_ERROR("failed to unpin new rbo in error path\n"); 226 } 227 amdgpu_bo_unreserve(new_rbo); 228 229 cleanup: 230 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); 231 fence_put(work->excl); 232 for (i = 0; i < work->shared_count; ++i) 233 fence_put(work->shared[i]); 234 kfree(work->shared); 235 kfree(work); 236 237 return r; 238 } 239 240 int amdgpu_crtc_set_config(struct drm_mode_set *set) 241 { 242 struct drm_device *dev; 243 struct amdgpu_device *adev; 244 struct drm_crtc *crtc; 245 bool active = false; 246 int ret; 247 248 if (!set || !set->crtc) 249 return -EINVAL; 250 251 dev = set->crtc->dev; 252 253 ret = pm_runtime_get_sync(dev->dev); 254 if (ret < 0) 255 return ret; 256 257 ret = drm_crtc_helper_set_config(set); 258 259 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 260 if (crtc->enabled) 261 active = true; 262 263 pm_runtime_mark_last_busy(dev->dev); 264 265 adev = dev->dev_private; 266 /* if we have active crtcs and we don't have a power ref, 267 take the current one */ 268 if (active && !adev->have_disp_power_ref) { 269 adev->have_disp_power_ref = true; 270 return ret; 271 } 272 /* if we have no active crtcs, then drop the power ref 273 we got before */ 274 if (!active && adev->have_disp_power_ref) { 275 pm_runtime_put_autosuspend(dev->dev); 276 adev->have_disp_power_ref = false; 277 } 278 279 /* drop the power reference we got coming in here */ 280 pm_runtime_put_autosuspend(dev->dev); 281 return ret; 282 } 283 284 static const char *encoder_names[38] = { 285 "NONE", 286 "INTERNAL_LVDS", 287 "INTERNAL_TMDS1", 288 "INTERNAL_TMDS2", 289 "INTERNAL_DAC1", 290 "INTERNAL_DAC2", 291 "INTERNAL_SDVOA", 292 "INTERNAL_SDVOB", 293 "SI170B", 294 "CH7303", 295 "CH7301", 296 "INTERNAL_DVO1", 297 "EXTERNAL_SDVOA", 298 "EXTERNAL_SDVOB", 299 "TITFP513", 300 "INTERNAL_LVTM1", 301 "VT1623", 302 "HDMI_SI1930", 303 "HDMI_INTERNAL", 304 "INTERNAL_KLDSCP_TMDS1", 305 "INTERNAL_KLDSCP_DVO1", 306 "INTERNAL_KLDSCP_DAC1", 307 "INTERNAL_KLDSCP_DAC2", 308 "SI178", 309 "MVPU_FPGA", 310 "INTERNAL_DDI", 311 "VT1625", 312 "HDMI_SI1932", 313 "DP_AN9801", 314 "DP_DP501", 315 "INTERNAL_UNIPHY", 316 "INTERNAL_KLDSCP_LVTMA", 317 "INTERNAL_UNIPHY1", 318 "INTERNAL_UNIPHY2", 319 "NUTMEG", 320 "TRAVIS", 321 "INTERNAL_VCE", 322 "INTERNAL_UNIPHY3", 323 }; 324 325 static const char *hpd_names[6] = { 326 "HPD1", 327 "HPD2", 328 "HPD3", 329 "HPD4", 330 "HPD5", 331 "HPD6", 332 }; 333 334 void amdgpu_print_display_setup(struct drm_device *dev) 335 { 336 struct drm_connector *connector; 337 struct amdgpu_connector *amdgpu_connector; 338 struct drm_encoder *encoder; 339 struct amdgpu_encoder *amdgpu_encoder; 340 uint32_t devices; 341 int i = 0; 342 343 DRM_INFO("AMDGPU Display Connectors\n"); 344 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 345 amdgpu_connector = to_amdgpu_connector(connector); 346 DRM_INFO("Connector %d:\n", i); 347 DRM_INFO(" %s\n", connector->name); 348 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) 349 DRM_INFO(" %s\n", hpd_names[amdgpu_connector->hpd.hpd]); 350 if (amdgpu_connector->ddc_bus) { 351 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 352 amdgpu_connector->ddc_bus->rec.mask_clk_reg, 353 amdgpu_connector->ddc_bus->rec.mask_data_reg, 354 amdgpu_connector->ddc_bus->rec.a_clk_reg, 355 amdgpu_connector->ddc_bus->rec.a_data_reg, 356 amdgpu_connector->ddc_bus->rec.en_clk_reg, 357 amdgpu_connector->ddc_bus->rec.en_data_reg, 358 amdgpu_connector->ddc_bus->rec.y_clk_reg, 359 amdgpu_connector->ddc_bus->rec.y_data_reg); 360 if (amdgpu_connector->router.ddc_valid) 361 DRM_INFO(" DDC Router 0x%x/0x%x\n", 362 amdgpu_connector->router.ddc_mux_control_pin, 363 amdgpu_connector->router.ddc_mux_state); 364 if (amdgpu_connector->router.cd_valid) 365 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", 366 amdgpu_connector->router.cd_mux_control_pin, 367 amdgpu_connector->router.cd_mux_state); 368 } else { 369 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || 370 connector->connector_type == DRM_MODE_CONNECTOR_DVII || 371 connector->connector_type == DRM_MODE_CONNECTOR_DVID || 372 connector->connector_type == DRM_MODE_CONNECTOR_DVIA || 373 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 374 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) 375 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); 376 } 377 DRM_INFO(" Encoders:\n"); 378 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 379 amdgpu_encoder = to_amdgpu_encoder(encoder); 380 devices = amdgpu_encoder->devices & amdgpu_connector->devices; 381 if (devices) { 382 if (devices & ATOM_DEVICE_CRT1_SUPPORT) 383 DRM_INFO(" CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 384 if (devices & ATOM_DEVICE_CRT2_SUPPORT) 385 DRM_INFO(" CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 386 if (devices & ATOM_DEVICE_LCD1_SUPPORT) 387 DRM_INFO(" LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 388 if (devices & ATOM_DEVICE_DFP1_SUPPORT) 389 DRM_INFO(" DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 390 if (devices & ATOM_DEVICE_DFP2_SUPPORT) 391 DRM_INFO(" DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 392 if (devices & ATOM_DEVICE_DFP3_SUPPORT) 393 DRM_INFO(" DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 394 if (devices & ATOM_DEVICE_DFP4_SUPPORT) 395 DRM_INFO(" DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 396 if (devices & ATOM_DEVICE_DFP5_SUPPORT) 397 DRM_INFO(" DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 398 if (devices & ATOM_DEVICE_DFP6_SUPPORT) 399 DRM_INFO(" DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 400 if (devices & ATOM_DEVICE_TV1_SUPPORT) 401 DRM_INFO(" TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 402 if (devices & ATOM_DEVICE_CV_SUPPORT) 403 DRM_INFO(" CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 404 } 405 } 406 i++; 407 } 408 } 409 410 /** 411 * amdgpu_ddc_probe 412 * 413 */ 414 bool amdgpu_ddc_probe(struct amdgpu_connector *amdgpu_connector, 415 bool use_aux) 416 { 417 u8 out = 0x0; 418 u8 buf[8]; 419 int ret; 420 struct i2c_msg msgs[] = { 421 { 422 .addr = DDC_ADDR, 423 .flags = 0, 424 .len = 1, 425 .buf = &out, 426 }, 427 { 428 .addr = DDC_ADDR, 429 .flags = I2C_M_RD, 430 .len = 8, 431 .buf = buf, 432 } 433 }; 434 435 /* on hw with routers, select right port */ 436 if (amdgpu_connector->router.ddc_valid) 437 amdgpu_i2c_router_select_ddc_port(amdgpu_connector); 438 439 if (use_aux) { 440 ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2); 441 } else { 442 ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2); 443 } 444 445 if (ret != 2) 446 /* Couldn't find an accessible DDC on this connector */ 447 return false; 448 /* Probe also for valid EDID header 449 * EDID header starts with: 450 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00. 451 * Only the first 6 bytes must be valid as 452 * drm_edid_block_valid() can fix the last 2 bytes */ 453 if (drm_edid_header_is_valid(buf) < 6) { 454 /* Couldn't find an accessible EDID on this 455 * connector */ 456 return false; 457 } 458 return true; 459 } 460 461 static void amdgpu_user_framebuffer_destroy(struct drm_framebuffer *fb) 462 { 463 struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb); 464 465 if (amdgpu_fb->obj) { 466 drm_gem_object_unreference_unlocked(amdgpu_fb->obj); 467 } 468 drm_framebuffer_cleanup(fb); 469 kfree(amdgpu_fb); 470 } 471 472 static int amdgpu_user_framebuffer_create_handle(struct drm_framebuffer *fb, 473 struct drm_file *file_priv, 474 unsigned int *handle) 475 { 476 struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb); 477 478 return drm_gem_handle_create(file_priv, amdgpu_fb->obj, handle); 479 } 480 481 static const struct drm_framebuffer_funcs amdgpu_fb_funcs = { 482 .destroy = amdgpu_user_framebuffer_destroy, 483 .create_handle = amdgpu_user_framebuffer_create_handle, 484 }; 485 486 int 487 amdgpu_framebuffer_init(struct drm_device *dev, 488 struct amdgpu_framebuffer *rfb, 489 struct drm_mode_fb_cmd2 *mode_cmd, 490 struct drm_gem_object *obj) 491 { 492 int ret; 493 rfb->obj = obj; 494 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd); 495 ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs); 496 if (ret) { 497 rfb->obj = NULL; 498 return ret; 499 } 500 return 0; 501 } 502 503 static struct drm_framebuffer * 504 amdgpu_user_framebuffer_create(struct drm_device *dev, 505 struct drm_file *file_priv, 506 struct drm_mode_fb_cmd2 *mode_cmd) 507 { 508 struct drm_gem_object *obj; 509 struct amdgpu_framebuffer *amdgpu_fb; 510 int ret; 511 512 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]); 513 if (obj == NULL) { 514 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, " 515 "can't create framebuffer\n", mode_cmd->handles[0]); 516 return ERR_PTR(-ENOENT); 517 } 518 519 amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL); 520 if (amdgpu_fb == NULL) { 521 drm_gem_object_unreference_unlocked(obj); 522 return ERR_PTR(-ENOMEM); 523 } 524 525 ret = amdgpu_framebuffer_init(dev, amdgpu_fb, mode_cmd, obj); 526 if (ret) { 527 kfree(amdgpu_fb); 528 drm_gem_object_unreference_unlocked(obj); 529 return ERR_PTR(ret); 530 } 531 532 return &amdgpu_fb->base; 533 } 534 535 static void amdgpu_output_poll_changed(struct drm_device *dev) 536 { 537 struct amdgpu_device *adev = dev->dev_private; 538 amdgpu_fb_output_poll_changed(adev); 539 } 540 541 const struct drm_mode_config_funcs amdgpu_mode_funcs = { 542 .fb_create = amdgpu_user_framebuffer_create, 543 .output_poll_changed = amdgpu_output_poll_changed 544 }; 545 546 static struct drm_prop_enum_list amdgpu_underscan_enum_list[] = 547 { { UNDERSCAN_OFF, "off" }, 548 { UNDERSCAN_ON, "on" }, 549 { UNDERSCAN_AUTO, "auto" }, 550 }; 551 552 static struct drm_prop_enum_list amdgpu_audio_enum_list[] = 553 { { AMDGPU_AUDIO_DISABLE, "off" }, 554 { AMDGPU_AUDIO_ENABLE, "on" }, 555 { AMDGPU_AUDIO_AUTO, "auto" }, 556 }; 557 558 /* XXX support different dither options? spatial, temporal, both, etc. */ 559 static struct drm_prop_enum_list amdgpu_dither_enum_list[] = 560 { { AMDGPU_FMT_DITHER_DISABLE, "off" }, 561 { AMDGPU_FMT_DITHER_ENABLE, "on" }, 562 }; 563 564 int amdgpu_modeset_create_props(struct amdgpu_device *adev) 565 { 566 int sz; 567 568 if (adev->is_atom_bios) { 569 adev->mode_info.coherent_mode_property = 570 drm_property_create_range(adev->ddev, 0 , "coherent", 0, 1); 571 if (!adev->mode_info.coherent_mode_property) 572 return -ENOMEM; 573 } 574 575 adev->mode_info.load_detect_property = 576 drm_property_create_range(adev->ddev, 0, "load detection", 0, 1); 577 if (!adev->mode_info.load_detect_property) 578 return -ENOMEM; 579 580 drm_mode_create_scaling_mode_property(adev->ddev); 581 582 sz = ARRAY_SIZE(amdgpu_underscan_enum_list); 583 adev->mode_info.underscan_property = 584 drm_property_create_enum(adev->ddev, 0, 585 "underscan", 586 amdgpu_underscan_enum_list, sz); 587 588 adev->mode_info.underscan_hborder_property = 589 drm_property_create_range(adev->ddev, 0, 590 "underscan hborder", 0, 128); 591 if (!adev->mode_info.underscan_hborder_property) 592 return -ENOMEM; 593 594 adev->mode_info.underscan_vborder_property = 595 drm_property_create_range(adev->ddev, 0, 596 "underscan vborder", 0, 128); 597 if (!adev->mode_info.underscan_vborder_property) 598 return -ENOMEM; 599 600 sz = ARRAY_SIZE(amdgpu_audio_enum_list); 601 adev->mode_info.audio_property = 602 drm_property_create_enum(adev->ddev, 0, 603 "audio", 604 amdgpu_audio_enum_list, sz); 605 606 sz = ARRAY_SIZE(amdgpu_dither_enum_list); 607 adev->mode_info.dither_property = 608 drm_property_create_enum(adev->ddev, 0, 609 "dither", 610 amdgpu_dither_enum_list, sz); 611 612 return 0; 613 } 614 615 void amdgpu_update_display_priority(struct amdgpu_device *adev) 616 { 617 /* adjustment options for the display watermarks */ 618 if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2)) 619 adev->mode_info.disp_priority = 0; 620 else 621 adev->mode_info.disp_priority = amdgpu_disp_priority; 622 623 } 624 625 static bool is_hdtv_mode(const struct drm_display_mode *mode) 626 { 627 /* try and guess if this is a tv or a monitor */ 628 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ 629 (mode->vdisplay == 576) || /* 576p */ 630 (mode->vdisplay == 720) || /* 720p */ 631 (mode->vdisplay == 1080)) /* 1080p */ 632 return true; 633 else 634 return false; 635 } 636 637 bool amdgpu_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 638 const struct drm_display_mode *mode, 639 struct drm_display_mode *adjusted_mode) 640 { 641 struct drm_device *dev = crtc->dev; 642 struct drm_encoder *encoder; 643 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 644 struct amdgpu_encoder *amdgpu_encoder; 645 struct drm_connector *connector; 646 struct amdgpu_connector *amdgpu_connector; 647 u32 src_v = 1, dst_v = 1; 648 u32 src_h = 1, dst_h = 1; 649 650 amdgpu_crtc->h_border = 0; 651 amdgpu_crtc->v_border = 0; 652 653 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 654 if (encoder->crtc != crtc) 655 continue; 656 amdgpu_encoder = to_amdgpu_encoder(encoder); 657 connector = amdgpu_get_connector_for_encoder(encoder); 658 amdgpu_connector = to_amdgpu_connector(connector); 659 660 /* set scaling */ 661 if (amdgpu_encoder->rmx_type == RMX_OFF) 662 amdgpu_crtc->rmx_type = RMX_OFF; 663 else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay || 664 mode->vdisplay < amdgpu_encoder->native_mode.vdisplay) 665 amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type; 666 else 667 amdgpu_crtc->rmx_type = RMX_OFF; 668 /* copy native mode */ 669 memcpy(&amdgpu_crtc->native_mode, 670 &amdgpu_encoder->native_mode, 671 sizeof(struct drm_display_mode)); 672 src_v = crtc->mode.vdisplay; 673 dst_v = amdgpu_crtc->native_mode.vdisplay; 674 src_h = crtc->mode.hdisplay; 675 dst_h = amdgpu_crtc->native_mode.hdisplay; 676 677 /* fix up for overscan on hdmi */ 678 if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && 679 ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) || 680 ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) && 681 drm_detect_hdmi_monitor(amdgpu_connector_edid(connector)) && 682 is_hdtv_mode(mode)))) { 683 if (amdgpu_encoder->underscan_hborder != 0) 684 amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder; 685 else 686 amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16; 687 if (amdgpu_encoder->underscan_vborder != 0) 688 amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder; 689 else 690 amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16; 691 amdgpu_crtc->rmx_type = RMX_FULL; 692 src_v = crtc->mode.vdisplay; 693 dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2); 694 src_h = crtc->mode.hdisplay; 695 dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2); 696 } 697 } 698 if (amdgpu_crtc->rmx_type != RMX_OFF) { 699 fixed20_12 a, b; 700 a.full = dfixed_const(src_v); 701 b.full = dfixed_const(dst_v); 702 amdgpu_crtc->vsc.full = dfixed_div(a, b); 703 a.full = dfixed_const(src_h); 704 b.full = dfixed_const(dst_h); 705 amdgpu_crtc->hsc.full = dfixed_div(a, b); 706 } else { 707 amdgpu_crtc->vsc.full = dfixed_const(1); 708 amdgpu_crtc->hsc.full = dfixed_const(1); 709 } 710 return true; 711 } 712 713 /* 714 * Retrieve current video scanout position of crtc on a given gpu, and 715 * an optional accurate timestamp of when query happened. 716 * 717 * \param dev Device to query. 718 * \param crtc Crtc to query. 719 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). 720 * \param *vpos Location where vertical scanout position should be stored. 721 * \param *hpos Location where horizontal scanout position should go. 722 * \param *stime Target location for timestamp taken immediately before 723 * scanout position query. Can be NULL to skip timestamp. 724 * \param *etime Target location for timestamp taken immediately after 725 * scanout position query. Can be NULL to skip timestamp. 726 * 727 * Returns vpos as a positive number while in active scanout area. 728 * Returns vpos as a negative number inside vblank, counting the number 729 * of scanlines to go until end of vblank, e.g., -1 means "one scanline 730 * until start of active scanout / end of vblank." 731 * 732 * \return Flags, or'ed together as follows: 733 * 734 * DRM_SCANOUTPOS_VALID = Query successful. 735 * DRM_SCANOUTPOS_INVBL = Inside vblank. 736 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of 737 * this flag means that returned position may be offset by a constant but 738 * unknown small number of scanlines wrt. real scanout position. 739 * 740 */ 741 int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, int crtc, unsigned int flags, 742 int *vpos, int *hpos, ktime_t *stime, ktime_t *etime) 743 { 744 u32 vbl = 0, position = 0; 745 int vbl_start, vbl_end, vtotal, ret = 0; 746 bool in_vbl = true; 747 748 struct amdgpu_device *adev = dev->dev_private; 749 750 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ 751 752 /* Get optional system timestamp before query. */ 753 if (stime) 754 *stime = ktime_get(); 755 756 if (amdgpu_display_page_flip_get_scanoutpos(adev, crtc, &vbl, &position) == 0) 757 ret |= DRM_SCANOUTPOS_VALID; 758 759 /* Get optional system timestamp after query. */ 760 if (etime) 761 *etime = ktime_get(); 762 763 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ 764 765 /* Decode into vertical and horizontal scanout position. */ 766 *vpos = position & 0x1fff; 767 *hpos = (position >> 16) & 0x1fff; 768 769 /* Valid vblank area boundaries from gpu retrieved? */ 770 if (vbl > 0) { 771 /* Yes: Decode. */ 772 ret |= DRM_SCANOUTPOS_ACCURATE; 773 vbl_start = vbl & 0x1fff; 774 vbl_end = (vbl >> 16) & 0x1fff; 775 } 776 else { 777 /* No: Fake something reasonable which gives at least ok results. */ 778 vbl_start = adev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay; 779 vbl_end = 0; 780 } 781 782 /* Test scanout position against vblank region. */ 783 if ((*vpos < vbl_start) && (*vpos >= vbl_end)) 784 in_vbl = false; 785 786 /* Check if inside vblank area and apply corrective offsets: 787 * vpos will then be >=0 in video scanout area, but negative 788 * within vblank area, counting down the number of lines until 789 * start of scanout. 790 */ 791 792 /* Inside "upper part" of vblank area? Apply corrective offset if so: */ 793 if (in_vbl && (*vpos >= vbl_start)) { 794 vtotal = adev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal; 795 *vpos = *vpos - vtotal; 796 } 797 798 /* Correct for shifted end of vbl at vbl_end. */ 799 *vpos = *vpos - vbl_end; 800 801 /* In vblank? */ 802 if (in_vbl) 803 ret |= DRM_SCANOUTPOS_IN_VBLANK; 804 805 /* Is vpos outside nominal vblank area, but less than 806 * 1/100 of a frame height away from start of vblank? 807 * If so, assume this isn't a massively delayed vblank 808 * interrupt, but a vblank interrupt that fired a few 809 * microseconds before true start of vblank. Compensate 810 * by adding a full frame duration to the final timestamp. 811 * Happens, e.g., on ATI R500, R600. 812 * 813 * We only do this if DRM_CALLED_FROM_VBLIRQ. 814 */ 815 if ((flags & DRM_CALLED_FROM_VBLIRQ) && !in_vbl) { 816 vbl_start = adev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay; 817 vtotal = adev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal; 818 819 if (vbl_start - *vpos < vtotal / 100) { 820 *vpos -= vtotal; 821 822 /* Signal this correction as "applied". */ 823 ret |= 0x8; 824 } 825 } 826 827 return ret; 828 } 829 830 int amdgpu_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc) 831 { 832 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) 833 return AMDGPU_CRTC_IRQ_NONE; 834 835 switch (crtc) { 836 case 0: 837 return AMDGPU_CRTC_IRQ_VBLANK1; 838 case 1: 839 return AMDGPU_CRTC_IRQ_VBLANK2; 840 case 2: 841 return AMDGPU_CRTC_IRQ_VBLANK3; 842 case 3: 843 return AMDGPU_CRTC_IRQ_VBLANK4; 844 case 4: 845 return AMDGPU_CRTC_IRQ_VBLANK5; 846 case 5: 847 return AMDGPU_CRTC_IRQ_VBLANK6; 848 default: 849 return AMDGPU_CRTC_IRQ_NONE; 850 } 851 } 852