1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/amdgpu_drm.h> 28 #include "amdgpu.h" 29 #include "amdgpu_i2c.h" 30 #include "atom.h" 31 #include "amdgpu_connectors.h" 32 #include <asm/div64.h> 33 34 #include <linux/pm_runtime.h> 35 #include <drm/drm_crtc_helper.h> 36 #include <drm/drm_edid.h> 37 38 static void amdgpu_flip_callback(struct dma_fence *f, struct dma_fence_cb *cb) 39 { 40 struct amdgpu_flip_work *work = 41 container_of(cb, struct amdgpu_flip_work, cb); 42 43 dma_fence_put(f); 44 schedule_work(&work->flip_work.work); 45 } 46 47 static bool amdgpu_flip_handle_fence(struct amdgpu_flip_work *work, 48 struct dma_fence **f) 49 { 50 struct dma_fence *fence= *f; 51 52 if (fence == NULL) 53 return false; 54 55 *f = NULL; 56 57 if (!dma_fence_add_callback(fence, &work->cb, amdgpu_flip_callback)) 58 return true; 59 60 dma_fence_put(fence); 61 return false; 62 } 63 64 static void amdgpu_flip_work_func(struct work_struct *__work) 65 { 66 struct delayed_work *delayed_work = 67 container_of(__work, struct delayed_work, work); 68 struct amdgpu_flip_work *work = 69 container_of(delayed_work, struct amdgpu_flip_work, flip_work); 70 struct amdgpu_device *adev = work->adev; 71 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id]; 72 73 struct drm_crtc *crtc = &amdgpu_crtc->base; 74 unsigned long flags; 75 unsigned i; 76 int vpos, hpos; 77 78 if (amdgpu_flip_handle_fence(work, &work->excl)) 79 return; 80 81 for (i = 0; i < work->shared_count; ++i) 82 if (amdgpu_flip_handle_fence(work, &work->shared[i])) 83 return; 84 85 /* Wait until we're out of the vertical blank period before the one 86 * targeted by the flip 87 */ 88 if (amdgpu_crtc->enabled && 89 (amdgpu_get_crtc_scanoutpos(adev->ddev, work->crtc_id, 0, 90 &vpos, &hpos, NULL, NULL, 91 &crtc->hwmode) 92 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 93 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 94 (int)(work->target_vblank - 95 amdgpu_get_vblank_counter_kms(adev->ddev, amdgpu_crtc->crtc_id)) > 0) { 96 schedule_delayed_work(&work->flip_work, usecs_to_jiffies(1000)); 97 return; 98 } 99 100 /* We borrow the event spin lock for protecting flip_status */ 101 spin_lock_irqsave(&crtc->dev->event_lock, flags); 102 103 /* Do the flip (mmio) */ 104 adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async); 105 106 /* Set the flip status */ 107 amdgpu_crtc->pflip_status = AMDGPU_FLIP_SUBMITTED; 108 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 109 110 111 DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n", 112 amdgpu_crtc->crtc_id, amdgpu_crtc, work); 113 114 } 115 116 /* 117 * Handle unpin events outside the interrupt handler proper. 118 */ 119 static void amdgpu_unpin_work_func(struct work_struct *__work) 120 { 121 struct amdgpu_flip_work *work = 122 container_of(__work, struct amdgpu_flip_work, unpin_work); 123 int r; 124 125 /* unpin of the old buffer */ 126 r = amdgpu_bo_reserve(work->old_abo, false); 127 if (likely(r == 0)) { 128 r = amdgpu_bo_unpin(work->old_abo); 129 if (unlikely(r != 0)) { 130 DRM_ERROR("failed to unpin buffer after flip\n"); 131 } 132 amdgpu_bo_unreserve(work->old_abo); 133 } else 134 DRM_ERROR("failed to reserve buffer after flip\n"); 135 136 amdgpu_bo_unref(&work->old_abo); 137 kfree(work->shared); 138 kfree(work); 139 } 140 141 142 static void amdgpu_flip_work_cleanup(struct amdgpu_flip_work *work) 143 { 144 int i; 145 146 amdgpu_bo_unref(&work->old_abo); 147 dma_fence_put(work->excl); 148 for (i = 0; i < work->shared_count; ++i) 149 dma_fence_put(work->shared[i]); 150 kfree(work->shared); 151 kfree(work); 152 } 153 154 static void amdgpu_flip_cleanup_unreserve(struct amdgpu_flip_work *work, 155 struct amdgpu_bo *new_abo) 156 { 157 amdgpu_bo_unreserve(new_abo); 158 amdgpu_flip_work_cleanup(work); 159 } 160 161 static void amdgpu_flip_cleanup_unpin(struct amdgpu_flip_work *work, 162 struct amdgpu_bo *new_abo) 163 { 164 if (unlikely(amdgpu_bo_unpin(new_abo) != 0)) 165 DRM_ERROR("failed to unpin new abo in error path\n"); 166 amdgpu_flip_cleanup_unreserve(work, new_abo); 167 } 168 169 void amdgpu_crtc_cleanup_flip_ctx(struct amdgpu_flip_work *work, 170 struct amdgpu_bo *new_abo) 171 { 172 if (unlikely(amdgpu_bo_reserve(new_abo, false) != 0)) { 173 DRM_ERROR("failed to reserve new abo in error path\n"); 174 amdgpu_flip_work_cleanup(work); 175 return; 176 } 177 amdgpu_flip_cleanup_unpin(work, new_abo); 178 } 179 180 int amdgpu_crtc_prepare_flip(struct drm_crtc *crtc, 181 struct drm_framebuffer *fb, 182 struct drm_pending_vblank_event *event, 183 uint32_t page_flip_flags, 184 uint32_t target, 185 struct amdgpu_flip_work **work_p, 186 struct amdgpu_bo **new_abo_p) 187 { 188 struct drm_device *dev = crtc->dev; 189 struct amdgpu_device *adev = dev->dev_private; 190 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 191 struct amdgpu_framebuffer *old_amdgpu_fb; 192 struct amdgpu_framebuffer *new_amdgpu_fb; 193 struct drm_gem_object *obj; 194 struct amdgpu_flip_work *work; 195 struct amdgpu_bo *new_abo; 196 unsigned long flags; 197 u64 tiling_flags; 198 u64 base; 199 int r; 200 201 work = kzalloc(sizeof *work, GFP_KERNEL); 202 if (work == NULL) 203 return -ENOMEM; 204 205 INIT_DELAYED_WORK(&work->flip_work, amdgpu_flip_work_func); 206 INIT_WORK(&work->unpin_work, amdgpu_unpin_work_func); 207 208 work->event = event; 209 work->adev = adev; 210 work->crtc_id = amdgpu_crtc->crtc_id; 211 work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; 212 213 /* schedule unpin of the old buffer */ 214 old_amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); 215 obj = old_amdgpu_fb->obj; 216 217 /* take a reference to the old object */ 218 work->old_abo = gem_to_amdgpu_bo(obj); 219 amdgpu_bo_ref(work->old_abo); 220 221 new_amdgpu_fb = to_amdgpu_framebuffer(fb); 222 obj = new_amdgpu_fb->obj; 223 new_abo = gem_to_amdgpu_bo(obj); 224 225 /* pin the new buffer */ 226 r = amdgpu_bo_reserve(new_abo, false); 227 if (unlikely(r != 0)) { 228 DRM_ERROR("failed to reserve new abo buffer before flip\n"); 229 goto cleanup; 230 } 231 232 r = amdgpu_bo_pin(new_abo, AMDGPU_GEM_DOMAIN_VRAM, &base); 233 if (unlikely(r != 0)) { 234 DRM_ERROR("failed to pin new abo buffer before flip\n"); 235 goto unreserve; 236 } 237 238 r = reservation_object_get_fences_rcu(new_abo->tbo.resv, &work->excl, 239 &work->shared_count, 240 &work->shared); 241 if (unlikely(r != 0)) { 242 DRM_ERROR("failed to get fences for buffer\n"); 243 goto unpin; 244 } 245 246 amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags); 247 amdgpu_bo_unreserve(new_abo); 248 249 work->base = base; 250 work->target_vblank = target - drm_crtc_vblank_count(crtc) + 251 amdgpu_get_vblank_counter_kms(dev, work->crtc_id); 252 253 /* we borrow the event spin lock for protecting flip_wrok */ 254 spin_lock_irqsave(&crtc->dev->event_lock, flags); 255 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) { 256 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); 257 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 258 r = -EBUSY; 259 goto pflip_cleanup; 260 261 } 262 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 263 264 *work_p = work; 265 *new_abo_p = new_abo; 266 267 return 0; 268 269 pflip_cleanup: 270 amdgpu_crtc_cleanup_flip_ctx(work, new_abo); 271 return r; 272 273 unpin: 274 amdgpu_flip_cleanup_unpin(work, new_abo); 275 return r; 276 277 unreserve: 278 amdgpu_flip_cleanup_unreserve(work, new_abo); 279 return r; 280 281 cleanup: 282 amdgpu_flip_work_cleanup(work); 283 return r; 284 285 } 286 287 void amdgpu_crtc_submit_flip(struct drm_crtc *crtc, 288 struct drm_framebuffer *fb, 289 struct amdgpu_flip_work *work, 290 struct amdgpu_bo *new_abo) 291 { 292 unsigned long flags; 293 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 294 295 spin_lock_irqsave(&crtc->dev->event_lock, flags); 296 amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING; 297 amdgpu_crtc->pflip_works = work; 298 299 /* update crtc fb */ 300 crtc->primary->fb = fb; 301 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 302 303 DRM_DEBUG_DRIVER( 304 "crtc:%d[%p], pflip_stat:AMDGPU_FLIP_PENDING, work: %p,\n", 305 amdgpu_crtc->crtc_id, amdgpu_crtc, work); 306 307 amdgpu_flip_work_func(&work->flip_work.work); 308 } 309 310 int amdgpu_crtc_page_flip_target(struct drm_crtc *crtc, 311 struct drm_framebuffer *fb, 312 struct drm_pending_vblank_event *event, 313 uint32_t page_flip_flags, 314 uint32_t target) 315 { 316 struct amdgpu_bo *new_abo; 317 struct amdgpu_flip_work *work; 318 int r; 319 320 r = amdgpu_crtc_prepare_flip(crtc, 321 fb, 322 event, 323 page_flip_flags, 324 target, 325 &work, 326 &new_abo); 327 if (r) 328 return r; 329 330 amdgpu_crtc_submit_flip(crtc, fb, work, new_abo); 331 332 return 0; 333 } 334 335 int amdgpu_crtc_set_config(struct drm_mode_set *set) 336 { 337 struct drm_device *dev; 338 struct amdgpu_device *adev; 339 struct drm_crtc *crtc; 340 bool active = false; 341 int ret; 342 343 if (!set || !set->crtc) 344 return -EINVAL; 345 346 dev = set->crtc->dev; 347 348 ret = pm_runtime_get_sync(dev->dev); 349 if (ret < 0) 350 return ret; 351 352 ret = drm_crtc_helper_set_config(set); 353 354 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 355 if (crtc->enabled) 356 active = true; 357 358 pm_runtime_mark_last_busy(dev->dev); 359 360 adev = dev->dev_private; 361 /* if we have active crtcs and we don't have a power ref, 362 take the current one */ 363 if (active && !adev->have_disp_power_ref) { 364 adev->have_disp_power_ref = true; 365 return ret; 366 } 367 /* if we have no active crtcs, then drop the power ref 368 we got before */ 369 if (!active && adev->have_disp_power_ref) { 370 pm_runtime_put_autosuspend(dev->dev); 371 adev->have_disp_power_ref = false; 372 } 373 374 /* drop the power reference we got coming in here */ 375 pm_runtime_put_autosuspend(dev->dev); 376 return ret; 377 } 378 379 static const char *encoder_names[41] = { 380 "NONE", 381 "INTERNAL_LVDS", 382 "INTERNAL_TMDS1", 383 "INTERNAL_TMDS2", 384 "INTERNAL_DAC1", 385 "INTERNAL_DAC2", 386 "INTERNAL_SDVOA", 387 "INTERNAL_SDVOB", 388 "SI170B", 389 "CH7303", 390 "CH7301", 391 "INTERNAL_DVO1", 392 "EXTERNAL_SDVOA", 393 "EXTERNAL_SDVOB", 394 "TITFP513", 395 "INTERNAL_LVTM1", 396 "VT1623", 397 "HDMI_SI1930", 398 "HDMI_INTERNAL", 399 "INTERNAL_KLDSCP_TMDS1", 400 "INTERNAL_KLDSCP_DVO1", 401 "INTERNAL_KLDSCP_DAC1", 402 "INTERNAL_KLDSCP_DAC2", 403 "SI178", 404 "MVPU_FPGA", 405 "INTERNAL_DDI", 406 "VT1625", 407 "HDMI_SI1932", 408 "DP_AN9801", 409 "DP_DP501", 410 "INTERNAL_UNIPHY", 411 "INTERNAL_KLDSCP_LVTMA", 412 "INTERNAL_UNIPHY1", 413 "INTERNAL_UNIPHY2", 414 "NUTMEG", 415 "TRAVIS", 416 "INTERNAL_VCE", 417 "INTERNAL_UNIPHY3", 418 "HDMI_ANX9805", 419 "INTERNAL_AMCLK", 420 "VIRTUAL", 421 }; 422 423 static const char *hpd_names[6] = { 424 "HPD1", 425 "HPD2", 426 "HPD3", 427 "HPD4", 428 "HPD5", 429 "HPD6", 430 }; 431 432 void amdgpu_print_display_setup(struct drm_device *dev) 433 { 434 struct drm_connector *connector; 435 struct amdgpu_connector *amdgpu_connector; 436 struct drm_encoder *encoder; 437 struct amdgpu_encoder *amdgpu_encoder; 438 uint32_t devices; 439 int i = 0; 440 441 DRM_INFO("AMDGPU Display Connectors\n"); 442 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 443 amdgpu_connector = to_amdgpu_connector(connector); 444 DRM_INFO("Connector %d:\n", i); 445 DRM_INFO(" %s\n", connector->name); 446 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) 447 DRM_INFO(" %s\n", hpd_names[amdgpu_connector->hpd.hpd]); 448 if (amdgpu_connector->ddc_bus) { 449 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 450 amdgpu_connector->ddc_bus->rec.mask_clk_reg, 451 amdgpu_connector->ddc_bus->rec.mask_data_reg, 452 amdgpu_connector->ddc_bus->rec.a_clk_reg, 453 amdgpu_connector->ddc_bus->rec.a_data_reg, 454 amdgpu_connector->ddc_bus->rec.en_clk_reg, 455 amdgpu_connector->ddc_bus->rec.en_data_reg, 456 amdgpu_connector->ddc_bus->rec.y_clk_reg, 457 amdgpu_connector->ddc_bus->rec.y_data_reg); 458 if (amdgpu_connector->router.ddc_valid) 459 DRM_INFO(" DDC Router 0x%x/0x%x\n", 460 amdgpu_connector->router.ddc_mux_control_pin, 461 amdgpu_connector->router.ddc_mux_state); 462 if (amdgpu_connector->router.cd_valid) 463 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", 464 amdgpu_connector->router.cd_mux_control_pin, 465 amdgpu_connector->router.cd_mux_state); 466 } else { 467 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || 468 connector->connector_type == DRM_MODE_CONNECTOR_DVII || 469 connector->connector_type == DRM_MODE_CONNECTOR_DVID || 470 connector->connector_type == DRM_MODE_CONNECTOR_DVIA || 471 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 472 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) 473 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); 474 } 475 DRM_INFO(" Encoders:\n"); 476 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 477 amdgpu_encoder = to_amdgpu_encoder(encoder); 478 devices = amdgpu_encoder->devices & amdgpu_connector->devices; 479 if (devices) { 480 if (devices & ATOM_DEVICE_CRT1_SUPPORT) 481 DRM_INFO(" CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 482 if (devices & ATOM_DEVICE_CRT2_SUPPORT) 483 DRM_INFO(" CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 484 if (devices & ATOM_DEVICE_LCD1_SUPPORT) 485 DRM_INFO(" LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 486 if (devices & ATOM_DEVICE_DFP1_SUPPORT) 487 DRM_INFO(" DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 488 if (devices & ATOM_DEVICE_DFP2_SUPPORT) 489 DRM_INFO(" DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 490 if (devices & ATOM_DEVICE_DFP3_SUPPORT) 491 DRM_INFO(" DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 492 if (devices & ATOM_DEVICE_DFP4_SUPPORT) 493 DRM_INFO(" DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 494 if (devices & ATOM_DEVICE_DFP5_SUPPORT) 495 DRM_INFO(" DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 496 if (devices & ATOM_DEVICE_DFP6_SUPPORT) 497 DRM_INFO(" DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 498 if (devices & ATOM_DEVICE_TV1_SUPPORT) 499 DRM_INFO(" TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 500 if (devices & ATOM_DEVICE_CV_SUPPORT) 501 DRM_INFO(" CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 502 } 503 } 504 i++; 505 } 506 } 507 508 /** 509 * amdgpu_ddc_probe 510 * 511 */ 512 bool amdgpu_ddc_probe(struct amdgpu_connector *amdgpu_connector, 513 bool use_aux) 514 { 515 u8 out = 0x0; 516 u8 buf[8]; 517 int ret; 518 struct i2c_msg msgs[] = { 519 { 520 .addr = DDC_ADDR, 521 .flags = 0, 522 .len = 1, 523 .buf = &out, 524 }, 525 { 526 .addr = DDC_ADDR, 527 .flags = I2C_M_RD, 528 .len = 8, 529 .buf = buf, 530 } 531 }; 532 533 /* on hw with routers, select right port */ 534 if (amdgpu_connector->router.ddc_valid) 535 amdgpu_i2c_router_select_ddc_port(amdgpu_connector); 536 537 if (use_aux) { 538 ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2); 539 } else { 540 ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2); 541 } 542 543 if (ret != 2) 544 /* Couldn't find an accessible DDC on this connector */ 545 return false; 546 /* Probe also for valid EDID header 547 * EDID header starts with: 548 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00. 549 * Only the first 6 bytes must be valid as 550 * drm_edid_block_valid() can fix the last 2 bytes */ 551 if (drm_edid_header_is_valid(buf) < 6) { 552 /* Couldn't find an accessible EDID on this 553 * connector */ 554 return false; 555 } 556 return true; 557 } 558 559 static void amdgpu_user_framebuffer_destroy(struct drm_framebuffer *fb) 560 { 561 struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb); 562 563 drm_gem_object_unreference_unlocked(amdgpu_fb->obj); 564 drm_framebuffer_cleanup(fb); 565 kfree(amdgpu_fb); 566 } 567 568 static int amdgpu_user_framebuffer_create_handle(struct drm_framebuffer *fb, 569 struct drm_file *file_priv, 570 unsigned int *handle) 571 { 572 struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb); 573 574 return drm_gem_handle_create(file_priv, amdgpu_fb->obj, handle); 575 } 576 577 static const struct drm_framebuffer_funcs amdgpu_fb_funcs = { 578 .destroy = amdgpu_user_framebuffer_destroy, 579 .create_handle = amdgpu_user_framebuffer_create_handle, 580 }; 581 582 int 583 amdgpu_framebuffer_init(struct drm_device *dev, 584 struct amdgpu_framebuffer *rfb, 585 const struct drm_mode_fb_cmd2 *mode_cmd, 586 struct drm_gem_object *obj) 587 { 588 int ret; 589 rfb->obj = obj; 590 drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd); 591 ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs); 592 if (ret) { 593 rfb->obj = NULL; 594 return ret; 595 } 596 return 0; 597 } 598 599 static struct drm_framebuffer * 600 amdgpu_user_framebuffer_create(struct drm_device *dev, 601 struct drm_file *file_priv, 602 const struct drm_mode_fb_cmd2 *mode_cmd) 603 { 604 struct drm_gem_object *obj; 605 struct amdgpu_framebuffer *amdgpu_fb; 606 int ret; 607 608 obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]); 609 if (obj == NULL) { 610 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, " 611 "can't create framebuffer\n", mode_cmd->handles[0]); 612 return ERR_PTR(-ENOENT); 613 } 614 615 amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL); 616 if (amdgpu_fb == NULL) { 617 drm_gem_object_unreference_unlocked(obj); 618 return ERR_PTR(-ENOMEM); 619 } 620 621 ret = amdgpu_framebuffer_init(dev, amdgpu_fb, mode_cmd, obj); 622 if (ret) { 623 kfree(amdgpu_fb); 624 drm_gem_object_unreference_unlocked(obj); 625 return ERR_PTR(ret); 626 } 627 628 return &amdgpu_fb->base; 629 } 630 631 static void amdgpu_output_poll_changed(struct drm_device *dev) 632 { 633 struct amdgpu_device *adev = dev->dev_private; 634 amdgpu_fb_output_poll_changed(adev); 635 } 636 637 const struct drm_mode_config_funcs amdgpu_mode_funcs = { 638 .fb_create = amdgpu_user_framebuffer_create, 639 .output_poll_changed = amdgpu_output_poll_changed 640 }; 641 642 static const struct drm_prop_enum_list amdgpu_underscan_enum_list[] = 643 { { UNDERSCAN_OFF, "off" }, 644 { UNDERSCAN_ON, "on" }, 645 { UNDERSCAN_AUTO, "auto" }, 646 }; 647 648 static const struct drm_prop_enum_list amdgpu_audio_enum_list[] = 649 { { AMDGPU_AUDIO_DISABLE, "off" }, 650 { AMDGPU_AUDIO_ENABLE, "on" }, 651 { AMDGPU_AUDIO_AUTO, "auto" }, 652 }; 653 654 /* XXX support different dither options? spatial, temporal, both, etc. */ 655 static const struct drm_prop_enum_list amdgpu_dither_enum_list[] = 656 { { AMDGPU_FMT_DITHER_DISABLE, "off" }, 657 { AMDGPU_FMT_DITHER_ENABLE, "on" }, 658 }; 659 660 int amdgpu_modeset_create_props(struct amdgpu_device *adev) 661 { 662 int sz; 663 664 adev->mode_info.coherent_mode_property = 665 drm_property_create_range(adev->ddev, 0 , "coherent", 0, 1); 666 if (!adev->mode_info.coherent_mode_property) 667 return -ENOMEM; 668 669 adev->mode_info.load_detect_property = 670 drm_property_create_range(adev->ddev, 0, "load detection", 0, 1); 671 if (!adev->mode_info.load_detect_property) 672 return -ENOMEM; 673 674 drm_mode_create_scaling_mode_property(adev->ddev); 675 676 sz = ARRAY_SIZE(amdgpu_underscan_enum_list); 677 adev->mode_info.underscan_property = 678 drm_property_create_enum(adev->ddev, 0, 679 "underscan", 680 amdgpu_underscan_enum_list, sz); 681 682 adev->mode_info.underscan_hborder_property = 683 drm_property_create_range(adev->ddev, 0, 684 "underscan hborder", 0, 128); 685 if (!adev->mode_info.underscan_hborder_property) 686 return -ENOMEM; 687 688 adev->mode_info.underscan_vborder_property = 689 drm_property_create_range(adev->ddev, 0, 690 "underscan vborder", 0, 128); 691 if (!adev->mode_info.underscan_vborder_property) 692 return -ENOMEM; 693 694 sz = ARRAY_SIZE(amdgpu_audio_enum_list); 695 adev->mode_info.audio_property = 696 drm_property_create_enum(adev->ddev, 0, 697 "audio", 698 amdgpu_audio_enum_list, sz); 699 700 sz = ARRAY_SIZE(amdgpu_dither_enum_list); 701 adev->mode_info.dither_property = 702 drm_property_create_enum(adev->ddev, 0, 703 "dither", 704 amdgpu_dither_enum_list, sz); 705 706 return 0; 707 } 708 709 void amdgpu_update_display_priority(struct amdgpu_device *adev) 710 { 711 /* adjustment options for the display watermarks */ 712 if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2)) 713 adev->mode_info.disp_priority = 0; 714 else 715 adev->mode_info.disp_priority = amdgpu_disp_priority; 716 717 } 718 719 static bool is_hdtv_mode(const struct drm_display_mode *mode) 720 { 721 /* try and guess if this is a tv or a monitor */ 722 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ 723 (mode->vdisplay == 576) || /* 576p */ 724 (mode->vdisplay == 720) || /* 720p */ 725 (mode->vdisplay == 1080)) /* 1080p */ 726 return true; 727 else 728 return false; 729 } 730 731 bool amdgpu_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 732 const struct drm_display_mode *mode, 733 struct drm_display_mode *adjusted_mode) 734 { 735 struct drm_device *dev = crtc->dev; 736 struct drm_encoder *encoder; 737 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 738 struct amdgpu_encoder *amdgpu_encoder; 739 struct drm_connector *connector; 740 struct amdgpu_connector *amdgpu_connector; 741 u32 src_v = 1, dst_v = 1; 742 u32 src_h = 1, dst_h = 1; 743 744 amdgpu_crtc->h_border = 0; 745 amdgpu_crtc->v_border = 0; 746 747 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 748 if (encoder->crtc != crtc) 749 continue; 750 amdgpu_encoder = to_amdgpu_encoder(encoder); 751 connector = amdgpu_get_connector_for_encoder(encoder); 752 amdgpu_connector = to_amdgpu_connector(connector); 753 754 /* set scaling */ 755 if (amdgpu_encoder->rmx_type == RMX_OFF) 756 amdgpu_crtc->rmx_type = RMX_OFF; 757 else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay || 758 mode->vdisplay < amdgpu_encoder->native_mode.vdisplay) 759 amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type; 760 else 761 amdgpu_crtc->rmx_type = RMX_OFF; 762 /* copy native mode */ 763 memcpy(&amdgpu_crtc->native_mode, 764 &amdgpu_encoder->native_mode, 765 sizeof(struct drm_display_mode)); 766 src_v = crtc->mode.vdisplay; 767 dst_v = amdgpu_crtc->native_mode.vdisplay; 768 src_h = crtc->mode.hdisplay; 769 dst_h = amdgpu_crtc->native_mode.hdisplay; 770 771 /* fix up for overscan on hdmi */ 772 if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && 773 ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) || 774 ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) && 775 drm_detect_hdmi_monitor(amdgpu_connector_edid(connector)) && 776 is_hdtv_mode(mode)))) { 777 if (amdgpu_encoder->underscan_hborder != 0) 778 amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder; 779 else 780 amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16; 781 if (amdgpu_encoder->underscan_vborder != 0) 782 amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder; 783 else 784 amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16; 785 amdgpu_crtc->rmx_type = RMX_FULL; 786 src_v = crtc->mode.vdisplay; 787 dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2); 788 src_h = crtc->mode.hdisplay; 789 dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2); 790 } 791 } 792 if (amdgpu_crtc->rmx_type != RMX_OFF) { 793 fixed20_12 a, b; 794 a.full = dfixed_const(src_v); 795 b.full = dfixed_const(dst_v); 796 amdgpu_crtc->vsc.full = dfixed_div(a, b); 797 a.full = dfixed_const(src_h); 798 b.full = dfixed_const(dst_h); 799 amdgpu_crtc->hsc.full = dfixed_div(a, b); 800 } else { 801 amdgpu_crtc->vsc.full = dfixed_const(1); 802 amdgpu_crtc->hsc.full = dfixed_const(1); 803 } 804 return true; 805 } 806 807 /* 808 * Retrieve current video scanout position of crtc on a given gpu, and 809 * an optional accurate timestamp of when query happened. 810 * 811 * \param dev Device to query. 812 * \param pipe Crtc to query. 813 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). 814 * For driver internal use only also supports these flags: 815 * 816 * USE_REAL_VBLANKSTART to use the real start of vblank instead 817 * of a fudged earlier start of vblank. 818 * 819 * GET_DISTANCE_TO_VBLANKSTART to return distance to the 820 * fudged earlier start of vblank in *vpos and the distance 821 * to true start of vblank in *hpos. 822 * 823 * \param *vpos Location where vertical scanout position should be stored. 824 * \param *hpos Location where horizontal scanout position should go. 825 * \param *stime Target location for timestamp taken immediately before 826 * scanout position query. Can be NULL to skip timestamp. 827 * \param *etime Target location for timestamp taken immediately after 828 * scanout position query. Can be NULL to skip timestamp. 829 * 830 * Returns vpos as a positive number while in active scanout area. 831 * Returns vpos as a negative number inside vblank, counting the number 832 * of scanlines to go until end of vblank, e.g., -1 means "one scanline 833 * until start of active scanout / end of vblank." 834 * 835 * \return Flags, or'ed together as follows: 836 * 837 * DRM_SCANOUTPOS_VALID = Query successful. 838 * DRM_SCANOUTPOS_INVBL = Inside vblank. 839 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of 840 * this flag means that returned position may be offset by a constant but 841 * unknown small number of scanlines wrt. real scanout position. 842 * 843 */ 844 int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, 845 unsigned int flags, int *vpos, int *hpos, 846 ktime_t *stime, ktime_t *etime, 847 const struct drm_display_mode *mode) 848 { 849 u32 vbl = 0, position = 0; 850 int vbl_start, vbl_end, vtotal, ret = 0; 851 bool in_vbl = true; 852 853 struct amdgpu_device *adev = dev->dev_private; 854 855 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ 856 857 /* Get optional system timestamp before query. */ 858 if (stime) 859 *stime = ktime_get(); 860 861 if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0) 862 ret |= DRM_SCANOUTPOS_VALID; 863 864 /* Get optional system timestamp after query. */ 865 if (etime) 866 *etime = ktime_get(); 867 868 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ 869 870 /* Decode into vertical and horizontal scanout position. */ 871 *vpos = position & 0x1fff; 872 *hpos = (position >> 16) & 0x1fff; 873 874 /* Valid vblank area boundaries from gpu retrieved? */ 875 if (vbl > 0) { 876 /* Yes: Decode. */ 877 ret |= DRM_SCANOUTPOS_ACCURATE; 878 vbl_start = vbl & 0x1fff; 879 vbl_end = (vbl >> 16) & 0x1fff; 880 } 881 else { 882 /* No: Fake something reasonable which gives at least ok results. */ 883 vbl_start = mode->crtc_vdisplay; 884 vbl_end = 0; 885 } 886 887 /* Called from driver internal vblank counter query code? */ 888 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 889 /* Caller wants distance from real vbl_start in *hpos */ 890 *hpos = *vpos - vbl_start; 891 } 892 893 /* Fudge vblank to start a few scanlines earlier to handle the 894 * problem that vblank irqs fire a few scanlines before start 895 * of vblank. Some driver internal callers need the true vblank 896 * start to be used and signal this via the USE_REAL_VBLANKSTART flag. 897 * 898 * The cause of the "early" vblank irq is that the irq is triggered 899 * by the line buffer logic when the line buffer read position enters 900 * the vblank, whereas our crtc scanout position naturally lags the 901 * line buffer read position. 902 */ 903 if (!(flags & USE_REAL_VBLANKSTART)) 904 vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines; 905 906 /* Test scanout position against vblank region. */ 907 if ((*vpos < vbl_start) && (*vpos >= vbl_end)) 908 in_vbl = false; 909 910 /* In vblank? */ 911 if (in_vbl) 912 ret |= DRM_SCANOUTPOS_IN_VBLANK; 913 914 /* Called from driver internal vblank counter query code? */ 915 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 916 /* Caller wants distance from fudged earlier vbl_start */ 917 *vpos -= vbl_start; 918 return ret; 919 } 920 921 /* Check if inside vblank area and apply corrective offsets: 922 * vpos will then be >=0 in video scanout area, but negative 923 * within vblank area, counting down the number of lines until 924 * start of scanout. 925 */ 926 927 /* Inside "upper part" of vblank area? Apply corrective offset if so: */ 928 if (in_vbl && (*vpos >= vbl_start)) { 929 vtotal = mode->crtc_vtotal; 930 *vpos = *vpos - vtotal; 931 } 932 933 /* Correct for shifted end of vbl at vbl_end. */ 934 *vpos = *vpos - vbl_end; 935 936 return ret; 937 } 938 939 int amdgpu_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc) 940 { 941 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) 942 return AMDGPU_CRTC_IRQ_NONE; 943 944 switch (crtc) { 945 case 0: 946 return AMDGPU_CRTC_IRQ_VBLANK1; 947 case 1: 948 return AMDGPU_CRTC_IRQ_VBLANK2; 949 case 2: 950 return AMDGPU_CRTC_IRQ_VBLANK3; 951 case 3: 952 return AMDGPU_CRTC_IRQ_VBLANK4; 953 case 4: 954 return AMDGPU_CRTC_IRQ_VBLANK5; 955 case 5: 956 return AMDGPU_CRTC_IRQ_VBLANK6; 957 default: 958 return AMDGPU_CRTC_IRQ_NONE; 959 } 960 } 961