1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 27 #include <drm/amdgpu_drm.h> 28 #include "amdgpu.h" 29 #include "amdgpu_i2c.h" 30 #include "atom.h" 31 #include "amdgpu_connectors.h" 32 #include "amdgpu_display.h" 33 #include "soc15_common.h" 34 #include "gc/gc_11_0_0_offset.h" 35 #include "gc/gc_11_0_0_sh_mask.h" 36 #include <asm/div64.h> 37 38 #include <linux/pci.h> 39 #include <linux/pm_runtime.h> 40 #include <drm/drm_crtc_helper.h> 41 #include <drm/drm_damage_helper.h> 42 #include <drm/drm_drv.h> 43 #include <drm/drm_edid.h> 44 #include <drm/drm_gem_framebuffer_helper.h> 45 #include <drm/drm_fb_helper.h> 46 #include <drm/drm_fourcc.h> 47 #include <drm/drm_vblank.h> 48 49 static int amdgpu_display_framebuffer_init(struct drm_device *dev, 50 struct amdgpu_framebuffer *rfb, 51 const struct drm_mode_fb_cmd2 *mode_cmd, 52 struct drm_gem_object *obj); 53 54 static void amdgpu_display_flip_callback(struct dma_fence *f, 55 struct dma_fence_cb *cb) 56 { 57 struct amdgpu_flip_work *work = 58 container_of(cb, struct amdgpu_flip_work, cb); 59 60 dma_fence_put(f); 61 schedule_work(&work->flip_work.work); 62 } 63 64 static bool amdgpu_display_flip_handle_fence(struct amdgpu_flip_work *work, 65 struct dma_fence **f) 66 { 67 struct dma_fence *fence= *f; 68 69 if (fence == NULL) 70 return false; 71 72 *f = NULL; 73 74 if (!dma_fence_add_callback(fence, &work->cb, 75 amdgpu_display_flip_callback)) 76 return true; 77 78 dma_fence_put(fence); 79 return false; 80 } 81 82 static void amdgpu_display_flip_work_func(struct work_struct *__work) 83 { 84 struct delayed_work *delayed_work = 85 container_of(__work, struct delayed_work, work); 86 struct amdgpu_flip_work *work = 87 container_of(delayed_work, struct amdgpu_flip_work, flip_work); 88 struct amdgpu_device *adev = work->adev; 89 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id]; 90 91 struct drm_crtc *crtc = &amdgpu_crtc->base; 92 unsigned long flags; 93 unsigned i; 94 int vpos, hpos; 95 96 for (i = 0; i < work->shared_count; ++i) 97 if (amdgpu_display_flip_handle_fence(work, &work->shared[i])) 98 return; 99 100 /* Wait until we're out of the vertical blank period before the one 101 * targeted by the flip 102 */ 103 if (amdgpu_crtc->enabled && 104 (amdgpu_display_get_crtc_scanoutpos(adev_to_drm(adev), work->crtc_id, 0, 105 &vpos, &hpos, NULL, NULL, 106 &crtc->hwmode) 107 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 108 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 109 (int)(work->target_vblank - 110 amdgpu_get_vblank_counter_kms(crtc)) > 0) { 111 schedule_delayed_work(&work->flip_work, usecs_to_jiffies(1000)); 112 return; 113 } 114 115 /* We borrow the event spin lock for protecting flip_status */ 116 spin_lock_irqsave(&crtc->dev->event_lock, flags); 117 118 /* Do the flip (mmio) */ 119 adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async); 120 121 /* Set the flip status */ 122 amdgpu_crtc->pflip_status = AMDGPU_FLIP_SUBMITTED; 123 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 124 125 126 drm_dbg_vbl(adev_to_drm(adev), 127 "crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n", 128 amdgpu_crtc->crtc_id, amdgpu_crtc, work); 129 130 } 131 132 /* 133 * Handle unpin events outside the interrupt handler proper. 134 */ 135 static void amdgpu_display_unpin_work_func(struct work_struct *__work) 136 { 137 struct amdgpu_flip_work *work = 138 container_of(__work, struct amdgpu_flip_work, unpin_work); 139 int r; 140 141 /* unpin of the old buffer */ 142 r = amdgpu_bo_reserve(work->old_abo, true); 143 if (likely(r == 0)) { 144 amdgpu_bo_unpin(work->old_abo); 145 amdgpu_bo_unreserve(work->old_abo); 146 } else 147 DRM_ERROR("failed to reserve buffer after flip\n"); 148 149 amdgpu_bo_unref(&work->old_abo); 150 kfree(work->shared); 151 kfree(work); 152 } 153 154 int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, 155 struct drm_framebuffer *fb, 156 struct drm_pending_vblank_event *event, 157 uint32_t page_flip_flags, uint32_t target, 158 struct drm_modeset_acquire_ctx *ctx) 159 { 160 struct drm_device *dev = crtc->dev; 161 struct amdgpu_device *adev = drm_to_adev(dev); 162 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 163 struct drm_gem_object *obj; 164 struct amdgpu_flip_work *work; 165 struct amdgpu_bo *new_abo; 166 unsigned long flags; 167 u64 tiling_flags; 168 int i, r; 169 170 work = kzalloc(sizeof *work, GFP_KERNEL); 171 if (work == NULL) 172 return -ENOMEM; 173 174 INIT_DELAYED_WORK(&work->flip_work, amdgpu_display_flip_work_func); 175 INIT_WORK(&work->unpin_work, amdgpu_display_unpin_work_func); 176 177 work->event = event; 178 work->adev = adev; 179 work->crtc_id = amdgpu_crtc->crtc_id; 180 work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; 181 182 /* schedule unpin of the old buffer */ 183 obj = crtc->primary->fb->obj[0]; 184 185 /* take a reference to the old object */ 186 work->old_abo = gem_to_amdgpu_bo(obj); 187 amdgpu_bo_ref(work->old_abo); 188 189 obj = fb->obj[0]; 190 new_abo = gem_to_amdgpu_bo(obj); 191 192 /* pin the new buffer */ 193 r = amdgpu_bo_reserve(new_abo, false); 194 if (unlikely(r != 0)) { 195 DRM_ERROR("failed to reserve new abo buffer before flip\n"); 196 goto cleanup; 197 } 198 199 if (!adev->enable_virtual_display) { 200 r = amdgpu_bo_pin(new_abo, 201 amdgpu_display_supported_domains(adev, new_abo->flags)); 202 if (unlikely(r != 0)) { 203 DRM_ERROR("failed to pin new abo buffer before flip\n"); 204 goto unreserve; 205 } 206 } 207 208 r = amdgpu_ttm_alloc_gart(&new_abo->tbo); 209 if (unlikely(r != 0)) { 210 DRM_ERROR("%p bind failed\n", new_abo); 211 goto unpin; 212 } 213 214 r = dma_resv_get_fences(new_abo->tbo.base.resv, DMA_RESV_USAGE_WRITE, 215 &work->shared_count, 216 &work->shared); 217 if (unlikely(r != 0)) { 218 DRM_ERROR("failed to get fences for buffer\n"); 219 goto unpin; 220 } 221 222 amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags); 223 amdgpu_bo_unreserve(new_abo); 224 225 if (!adev->enable_virtual_display) 226 work->base = amdgpu_bo_gpu_offset(new_abo); 227 work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) + 228 amdgpu_get_vblank_counter_kms(crtc); 229 230 /* we borrow the event spin lock for protecting flip_wrok */ 231 spin_lock_irqsave(&crtc->dev->event_lock, flags); 232 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) { 233 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); 234 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 235 r = -EBUSY; 236 goto pflip_cleanup; 237 } 238 239 amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING; 240 amdgpu_crtc->pflip_works = work; 241 242 243 DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_PENDING, work: %p,\n", 244 amdgpu_crtc->crtc_id, amdgpu_crtc, work); 245 /* update crtc fb */ 246 crtc->primary->fb = fb; 247 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 248 amdgpu_display_flip_work_func(&work->flip_work.work); 249 return 0; 250 251 pflip_cleanup: 252 if (unlikely(amdgpu_bo_reserve(new_abo, false) != 0)) { 253 DRM_ERROR("failed to reserve new abo in error path\n"); 254 goto cleanup; 255 } 256 unpin: 257 if (!adev->enable_virtual_display) 258 amdgpu_bo_unpin(new_abo); 259 260 unreserve: 261 amdgpu_bo_unreserve(new_abo); 262 263 cleanup: 264 amdgpu_bo_unref(&work->old_abo); 265 for (i = 0; i < work->shared_count; ++i) 266 dma_fence_put(work->shared[i]); 267 kfree(work->shared); 268 kfree(work); 269 270 return r; 271 } 272 273 int amdgpu_display_crtc_set_config(struct drm_mode_set *set, 274 struct drm_modeset_acquire_ctx *ctx) 275 { 276 struct drm_device *dev; 277 struct amdgpu_device *adev; 278 struct drm_crtc *crtc; 279 bool active = false; 280 int ret; 281 282 if (!set || !set->crtc) 283 return -EINVAL; 284 285 dev = set->crtc->dev; 286 287 ret = pm_runtime_get_sync(dev->dev); 288 if (ret < 0) 289 goto out; 290 291 ret = drm_crtc_helper_set_config(set, ctx); 292 293 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 294 if (crtc->enabled) 295 active = true; 296 297 pm_runtime_mark_last_busy(dev->dev); 298 299 adev = drm_to_adev(dev); 300 /* if we have active crtcs and we don't have a power ref, 301 take the current one */ 302 if (active && !adev->have_disp_power_ref) { 303 adev->have_disp_power_ref = true; 304 return ret; 305 } 306 /* if we have no active crtcs, then drop the power ref 307 we got before */ 308 if (!active && adev->have_disp_power_ref) { 309 pm_runtime_put_autosuspend(dev->dev); 310 adev->have_disp_power_ref = false; 311 } 312 313 out: 314 /* drop the power reference we got coming in here */ 315 pm_runtime_put_autosuspend(dev->dev); 316 return ret; 317 } 318 319 static const char *encoder_names[41] = { 320 "NONE", 321 "INTERNAL_LVDS", 322 "INTERNAL_TMDS1", 323 "INTERNAL_TMDS2", 324 "INTERNAL_DAC1", 325 "INTERNAL_DAC2", 326 "INTERNAL_SDVOA", 327 "INTERNAL_SDVOB", 328 "SI170B", 329 "CH7303", 330 "CH7301", 331 "INTERNAL_DVO1", 332 "EXTERNAL_SDVOA", 333 "EXTERNAL_SDVOB", 334 "TITFP513", 335 "INTERNAL_LVTM1", 336 "VT1623", 337 "HDMI_SI1930", 338 "HDMI_INTERNAL", 339 "INTERNAL_KLDSCP_TMDS1", 340 "INTERNAL_KLDSCP_DVO1", 341 "INTERNAL_KLDSCP_DAC1", 342 "INTERNAL_KLDSCP_DAC2", 343 "SI178", 344 "MVPU_FPGA", 345 "INTERNAL_DDI", 346 "VT1625", 347 "HDMI_SI1932", 348 "DP_AN9801", 349 "DP_DP501", 350 "INTERNAL_UNIPHY", 351 "INTERNAL_KLDSCP_LVTMA", 352 "INTERNAL_UNIPHY1", 353 "INTERNAL_UNIPHY2", 354 "NUTMEG", 355 "TRAVIS", 356 "INTERNAL_VCE", 357 "INTERNAL_UNIPHY3", 358 "HDMI_ANX9805", 359 "INTERNAL_AMCLK", 360 "VIRTUAL", 361 }; 362 363 static const char *hpd_names[6] = { 364 "HPD1", 365 "HPD2", 366 "HPD3", 367 "HPD4", 368 "HPD5", 369 "HPD6", 370 }; 371 372 void amdgpu_display_print_display_setup(struct drm_device *dev) 373 { 374 struct drm_connector *connector; 375 struct amdgpu_connector *amdgpu_connector; 376 struct drm_encoder *encoder; 377 struct amdgpu_encoder *amdgpu_encoder; 378 struct drm_connector_list_iter iter; 379 uint32_t devices; 380 int i = 0; 381 382 drm_connector_list_iter_begin(dev, &iter); 383 DRM_INFO("AMDGPU Display Connectors\n"); 384 drm_for_each_connector_iter(connector, &iter) { 385 amdgpu_connector = to_amdgpu_connector(connector); 386 DRM_INFO("Connector %d:\n", i); 387 DRM_INFO(" %s\n", connector->name); 388 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) 389 DRM_INFO(" %s\n", hpd_names[amdgpu_connector->hpd.hpd]); 390 if (amdgpu_connector->ddc_bus) { 391 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 392 amdgpu_connector->ddc_bus->rec.mask_clk_reg, 393 amdgpu_connector->ddc_bus->rec.mask_data_reg, 394 amdgpu_connector->ddc_bus->rec.a_clk_reg, 395 amdgpu_connector->ddc_bus->rec.a_data_reg, 396 amdgpu_connector->ddc_bus->rec.en_clk_reg, 397 amdgpu_connector->ddc_bus->rec.en_data_reg, 398 amdgpu_connector->ddc_bus->rec.y_clk_reg, 399 amdgpu_connector->ddc_bus->rec.y_data_reg); 400 if (amdgpu_connector->router.ddc_valid) 401 DRM_INFO(" DDC Router 0x%x/0x%x\n", 402 amdgpu_connector->router.ddc_mux_control_pin, 403 amdgpu_connector->router.ddc_mux_state); 404 if (amdgpu_connector->router.cd_valid) 405 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", 406 amdgpu_connector->router.cd_mux_control_pin, 407 amdgpu_connector->router.cd_mux_state); 408 } else { 409 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || 410 connector->connector_type == DRM_MODE_CONNECTOR_DVII || 411 connector->connector_type == DRM_MODE_CONNECTOR_DVID || 412 connector->connector_type == DRM_MODE_CONNECTOR_DVIA || 413 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 414 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) 415 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); 416 } 417 DRM_INFO(" Encoders:\n"); 418 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 419 amdgpu_encoder = to_amdgpu_encoder(encoder); 420 devices = amdgpu_encoder->devices & amdgpu_connector->devices; 421 if (devices) { 422 if (devices & ATOM_DEVICE_CRT1_SUPPORT) 423 DRM_INFO(" CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 424 if (devices & ATOM_DEVICE_CRT2_SUPPORT) 425 DRM_INFO(" CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 426 if (devices & ATOM_DEVICE_LCD1_SUPPORT) 427 DRM_INFO(" LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 428 if (devices & ATOM_DEVICE_DFP1_SUPPORT) 429 DRM_INFO(" DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 430 if (devices & ATOM_DEVICE_DFP2_SUPPORT) 431 DRM_INFO(" DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 432 if (devices & ATOM_DEVICE_DFP3_SUPPORT) 433 DRM_INFO(" DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 434 if (devices & ATOM_DEVICE_DFP4_SUPPORT) 435 DRM_INFO(" DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 436 if (devices & ATOM_DEVICE_DFP5_SUPPORT) 437 DRM_INFO(" DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 438 if (devices & ATOM_DEVICE_DFP6_SUPPORT) 439 DRM_INFO(" DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 440 if (devices & ATOM_DEVICE_TV1_SUPPORT) 441 DRM_INFO(" TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 442 if (devices & ATOM_DEVICE_CV_SUPPORT) 443 DRM_INFO(" CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 444 } 445 } 446 i++; 447 } 448 drm_connector_list_iter_end(&iter); 449 } 450 451 bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector, 452 bool use_aux) 453 { 454 u8 out = 0x0; 455 u8 buf[8]; 456 int ret; 457 struct i2c_msg msgs[] = { 458 { 459 .addr = DDC_ADDR, 460 .flags = 0, 461 .len = 1, 462 .buf = &out, 463 }, 464 { 465 .addr = DDC_ADDR, 466 .flags = I2C_M_RD, 467 .len = 8, 468 .buf = buf, 469 } 470 }; 471 472 /* on hw with routers, select right port */ 473 if (amdgpu_connector->router.ddc_valid) 474 amdgpu_i2c_router_select_ddc_port(amdgpu_connector); 475 476 if (use_aux) { 477 ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2); 478 } else { 479 ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2); 480 } 481 482 if (ret != 2) 483 /* Couldn't find an accessible DDC on this connector */ 484 return false; 485 /* Probe also for valid EDID header 486 * EDID header starts with: 487 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00. 488 * Only the first 6 bytes must be valid as 489 * drm_edid_block_valid() can fix the last 2 bytes */ 490 if (drm_edid_header_is_valid(buf) < 6) { 491 /* Couldn't find an accessible EDID on this 492 * connector */ 493 return false; 494 } 495 return true; 496 } 497 498 static const struct drm_framebuffer_funcs amdgpu_fb_funcs = { 499 .destroy = drm_gem_fb_destroy, 500 .create_handle = drm_gem_fb_create_handle, 501 }; 502 503 static const struct drm_framebuffer_funcs amdgpu_fb_funcs_atomic = { 504 .destroy = drm_gem_fb_destroy, 505 .create_handle = drm_gem_fb_create_handle, 506 .dirty = drm_atomic_helper_dirtyfb, 507 }; 508 509 uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev, 510 uint64_t bo_flags) 511 { 512 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM; 513 514 #if defined(CONFIG_DRM_AMD_DC) 515 /* 516 * if amdgpu_bo_support_uswc returns false it means that USWC mappings 517 * is not supported for this board. But this mapping is required 518 * to avoid hang caused by placement of scanout BO in GTT on certain 519 * APUs. So force the BO placement to VRAM in case this architecture 520 * will not allow USWC mappings. 521 * Also, don't allow GTT domain if the BO doesn't have USWC flag set. 522 */ 523 if ((bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) && 524 amdgpu_bo_support_uswc(bo_flags) && 525 amdgpu_device_asic_has_dc_support(adev->asic_type) && 526 adev->mode_info.gpu_vm_support) 527 domain |= AMDGPU_GEM_DOMAIN_GTT; 528 #endif 529 530 return domain; 531 } 532 533 static const struct drm_format_info dcc_formats[] = { 534 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, 535 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 536 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, 537 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 538 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, 539 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 540 .has_alpha = true, }, 541 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, 542 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 543 .has_alpha = true, }, 544 { .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 2, 545 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 546 .has_alpha = true, }, 547 { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 2, 548 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 549 { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 2, 550 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 551 { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 2, 552 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 553 .has_alpha = true, }, 554 { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 2, 555 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 556 .has_alpha = true, }, 557 { .format = DRM_FORMAT_RGB565, .depth = 16, .num_planes = 2, 558 .cpp = { 2, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 559 }; 560 561 static const struct drm_format_info dcc_retile_formats[] = { 562 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3, 563 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 564 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3, 565 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 566 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3, 567 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 568 .has_alpha = true, }, 569 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3, 570 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 571 .has_alpha = true, }, 572 { .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 3, 573 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 574 .has_alpha = true, }, 575 { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 3, 576 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 577 { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 3, 578 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 579 { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 3, 580 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 581 .has_alpha = true, }, 582 { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 3, 583 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 584 .has_alpha = true, }, 585 { .format = DRM_FORMAT_RGB565, .depth = 16, .num_planes = 3, 586 .cpp = { 2, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 587 }; 588 589 static const struct drm_format_info * 590 lookup_format_info(const struct drm_format_info formats[], 591 int num_formats, u32 format) 592 { 593 int i; 594 595 for (i = 0; i < num_formats; i++) { 596 if (formats[i].format == format) 597 return &formats[i]; 598 } 599 600 return NULL; 601 } 602 603 const struct drm_format_info * 604 amdgpu_lookup_format_info(u32 format, uint64_t modifier) 605 { 606 if (!IS_AMD_FMT_MOD(modifier)) 607 return NULL; 608 609 if (AMD_FMT_MOD_GET(DCC_RETILE, modifier)) 610 return lookup_format_info(dcc_retile_formats, 611 ARRAY_SIZE(dcc_retile_formats), 612 format); 613 614 if (AMD_FMT_MOD_GET(DCC, modifier)) 615 return lookup_format_info(dcc_formats, ARRAY_SIZE(dcc_formats), 616 format); 617 618 /* returning NULL will cause the default format structs to be used. */ 619 return NULL; 620 } 621 622 623 /* 624 * Tries to extract the renderable DCC offset from the opaque metadata attached 625 * to the buffer. 626 */ 627 static int 628 extract_render_dcc_offset(struct amdgpu_device *adev, 629 struct drm_gem_object *obj, 630 uint64_t *offset) 631 { 632 struct amdgpu_bo *rbo; 633 int r = 0; 634 uint32_t metadata[10]; /* Something that fits a descriptor + header. */ 635 uint32_t size; 636 637 rbo = gem_to_amdgpu_bo(obj); 638 r = amdgpu_bo_reserve(rbo, false); 639 640 if (unlikely(r)) { 641 /* Don't show error message when returning -ERESTARTSYS */ 642 if (r != -ERESTARTSYS) 643 DRM_ERROR("Unable to reserve buffer: %d\n", r); 644 return r; 645 } 646 647 r = amdgpu_bo_get_metadata(rbo, metadata, sizeof(metadata), &size, NULL); 648 amdgpu_bo_unreserve(rbo); 649 650 if (r) 651 return r; 652 653 /* 654 * The first word is the metadata version, and we need space for at least 655 * the version + pci vendor+device id + 8 words for a descriptor. 656 */ 657 if (size < 40 || metadata[0] != 1) 658 return -EINVAL; 659 660 if (adev->family >= AMDGPU_FAMILY_NV) { 661 /* resource word 6/7 META_DATA_ADDRESS{_LO} */ 662 *offset = ((u64)metadata[9] << 16u) | 663 ((metadata[8] & 0xFF000000u) >> 16); 664 } else { 665 /* resource word 5/7 META_DATA_ADDRESS */ 666 *offset = ((u64)metadata[9] << 8u) | 667 ((u64)(metadata[7] & 0x1FE0000u) << 23); 668 } 669 670 return 0; 671 } 672 673 static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb) 674 { 675 struct amdgpu_device *adev = drm_to_adev(afb->base.dev); 676 uint64_t modifier = 0; 677 int num_pipes = 0; 678 int num_pkrs = 0; 679 680 num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs; 681 num_pipes = adev->gfx.config.gb_addr_config_fields.num_pipes; 682 683 if (!afb->tiling_flags || !AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) { 684 modifier = DRM_FORMAT_MOD_LINEAR; 685 } else { 686 int swizzle = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE); 687 bool has_xor = swizzle >= 16; 688 int block_size_bits; 689 int version; 690 int pipe_xor_bits = 0; 691 int bank_xor_bits = 0; 692 int packers = 0; 693 int rb = 0; 694 int pipes = ilog2(num_pipes); 695 uint32_t dcc_offset = AMDGPU_TILING_GET(afb->tiling_flags, DCC_OFFSET_256B); 696 697 switch (swizzle >> 2) { 698 case 0: /* 256B */ 699 block_size_bits = 8; 700 break; 701 case 1: /* 4KiB */ 702 case 5: /* 4KiB _X */ 703 block_size_bits = 12; 704 break; 705 case 2: /* 64KiB */ 706 case 4: /* 64 KiB _T */ 707 case 6: /* 64 KiB _X */ 708 block_size_bits = 16; 709 break; 710 case 7: /* 256 KiB */ 711 block_size_bits = 18; 712 break; 713 default: 714 /* RESERVED or VAR */ 715 return -EINVAL; 716 } 717 718 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0)) 719 version = AMD_FMT_MOD_TILE_VER_GFX11; 720 else if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) 721 version = AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS; 722 else if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 0, 0)) 723 version = AMD_FMT_MOD_TILE_VER_GFX10; 724 else 725 version = AMD_FMT_MOD_TILE_VER_GFX9; 726 727 switch (swizzle & 3) { 728 case 0: /* Z microtiling */ 729 return -EINVAL; 730 case 1: /* S microtiling */ 731 if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0)) { 732 if (!has_xor) 733 version = AMD_FMT_MOD_TILE_VER_GFX9; 734 } 735 break; 736 case 2: 737 if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0)) { 738 if (!has_xor && afb->base.format->cpp[0] != 4) 739 version = AMD_FMT_MOD_TILE_VER_GFX9; 740 } 741 break; 742 case 3: 743 break; 744 } 745 746 if (has_xor) { 747 if (num_pipes == num_pkrs && num_pkrs == 0) { 748 DRM_ERROR("invalid number of pipes and packers\n"); 749 return -EINVAL; 750 } 751 752 switch (version) { 753 case AMD_FMT_MOD_TILE_VER_GFX11: 754 pipe_xor_bits = min(block_size_bits - 8, pipes); 755 packers = ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs); 756 break; 757 case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS: 758 pipe_xor_bits = min(block_size_bits - 8, pipes); 759 packers = min(block_size_bits - 8 - pipe_xor_bits, 760 ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs)); 761 break; 762 case AMD_FMT_MOD_TILE_VER_GFX10: 763 pipe_xor_bits = min(block_size_bits - 8, pipes); 764 break; 765 case AMD_FMT_MOD_TILE_VER_GFX9: 766 rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) + 767 ilog2(adev->gfx.config.gb_addr_config_fields.num_rb_per_se); 768 pipe_xor_bits = min(block_size_bits - 8, pipes + 769 ilog2(adev->gfx.config.gb_addr_config_fields.num_se)); 770 bank_xor_bits = min(block_size_bits - 8 - pipe_xor_bits, 771 ilog2(adev->gfx.config.gb_addr_config_fields.num_banks)); 772 break; 773 } 774 } 775 776 modifier = AMD_FMT_MOD | 777 AMD_FMT_MOD_SET(TILE, AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) | 778 AMD_FMT_MOD_SET(TILE_VERSION, version) | 779 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 780 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) | 781 AMD_FMT_MOD_SET(PACKERS, packers); 782 783 if (dcc_offset != 0) { 784 bool dcc_i64b = AMDGPU_TILING_GET(afb->tiling_flags, DCC_INDEPENDENT_64B) != 0; 785 bool dcc_i128b = version >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS; 786 const struct drm_format_info *format_info; 787 u64 render_dcc_offset; 788 789 /* Enable constant encode on RAVEN2 and later. */ 790 bool dcc_constant_encode = (adev->asic_type > CHIP_RAVEN || 791 (adev->asic_type == CHIP_RAVEN && 792 adev->external_rev_id >= 0x81)) && 793 adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0); 794 795 int max_cblock_size = dcc_i64b ? AMD_FMT_MOD_DCC_BLOCK_64B : 796 dcc_i128b ? AMD_FMT_MOD_DCC_BLOCK_128B : 797 AMD_FMT_MOD_DCC_BLOCK_256B; 798 799 modifier |= AMD_FMT_MOD_SET(DCC, 1) | 800 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, dcc_constant_encode) | 801 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, dcc_i64b) | 802 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, dcc_i128b) | 803 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, max_cblock_size); 804 805 afb->base.offsets[1] = dcc_offset * 256 + afb->base.offsets[0]; 806 afb->base.pitches[1] = 807 AMDGPU_TILING_GET(afb->tiling_flags, DCC_PITCH_MAX) + 1; 808 809 /* 810 * If the userspace driver uses retiling the tiling flags do not contain 811 * info on the renderable DCC buffer. Luckily the opaque metadata contains 812 * the info so we can try to extract it. The kernel does not use this info 813 * but we should convert it to a modifier plane for getfb2, so the 814 * userspace driver that gets it doesn't have to juggle around another DCC 815 * plane internally. 816 */ 817 if (extract_render_dcc_offset(adev, afb->base.obj[0], 818 &render_dcc_offset) == 0 && 819 render_dcc_offset != 0 && 820 render_dcc_offset != afb->base.offsets[1] && 821 render_dcc_offset < UINT_MAX) { 822 uint32_t dcc_block_bits; /* of base surface data */ 823 824 modifier |= AMD_FMT_MOD_SET(DCC_RETILE, 1); 825 afb->base.offsets[2] = render_dcc_offset; 826 827 if (adev->family >= AMDGPU_FAMILY_NV) { 828 int extra_pipe = 0; 829 830 if ((adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) && 831 pipes == packers && pipes > 1) 832 extra_pipe = 1; 833 834 dcc_block_bits = max(20, 16 + pipes + extra_pipe); 835 } else { 836 modifier |= AMD_FMT_MOD_SET(RB, rb) | 837 AMD_FMT_MOD_SET(PIPE, pipes); 838 dcc_block_bits = max(20, 18 + rb); 839 } 840 841 dcc_block_bits -= ilog2(afb->base.format->cpp[0]); 842 afb->base.pitches[2] = ALIGN(afb->base.width, 843 1u << ((dcc_block_bits + 1) / 2)); 844 } 845 format_info = amdgpu_lookup_format_info(afb->base.format->format, 846 modifier); 847 if (!format_info) 848 return -EINVAL; 849 850 afb->base.format = format_info; 851 } 852 } 853 854 afb->base.modifier = modifier; 855 afb->base.flags |= DRM_MODE_FB_MODIFIERS; 856 return 0; 857 } 858 859 /* Mirrors the is_displayable check in radeonsi's gfx6_compute_surface */ 860 static int check_tiling_flags_gfx6(struct amdgpu_framebuffer *afb) 861 { 862 u64 micro_tile_mode; 863 864 /* Zero swizzle mode means linear */ 865 if (AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0) 866 return 0; 867 868 micro_tile_mode = AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE); 869 switch (micro_tile_mode) { 870 case 0: /* DISPLAY */ 871 case 3: /* RENDER */ 872 return 0; 873 default: 874 drm_dbg_kms(afb->base.dev, 875 "Micro tile mode %llu not supported for scanout\n", 876 micro_tile_mode); 877 return -EINVAL; 878 } 879 } 880 881 static void get_block_dimensions(unsigned int block_log2, unsigned int cpp, 882 unsigned int *width, unsigned int *height) 883 { 884 unsigned int cpp_log2 = ilog2(cpp); 885 unsigned int pixel_log2 = block_log2 - cpp_log2; 886 unsigned int width_log2 = (pixel_log2 + 1) / 2; 887 unsigned int height_log2 = pixel_log2 - width_log2; 888 889 *width = 1 << width_log2; 890 *height = 1 << height_log2; 891 } 892 893 static unsigned int get_dcc_block_size(uint64_t modifier, bool rb_aligned, 894 bool pipe_aligned) 895 { 896 unsigned int ver = AMD_FMT_MOD_GET(TILE_VERSION, modifier); 897 898 switch (ver) { 899 case AMD_FMT_MOD_TILE_VER_GFX9: { 900 /* 901 * TODO: for pipe aligned we may need to check the alignment of the 902 * total size of the surface, which may need to be bigger than the 903 * natural alignment due to some HW workarounds 904 */ 905 return max(10 + (rb_aligned ? (int)AMD_FMT_MOD_GET(RB, modifier) : 0), 12); 906 } 907 case AMD_FMT_MOD_TILE_VER_GFX10: 908 case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS: 909 case AMD_FMT_MOD_TILE_VER_GFX11: { 910 int pipes_log2 = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier); 911 912 if (ver >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS && pipes_log2 > 1 && 913 AMD_FMT_MOD_GET(PACKERS, modifier) == pipes_log2) 914 ++pipes_log2; 915 916 return max(8 + (pipe_aligned ? pipes_log2 : 0), 12); 917 } 918 default: 919 return 0; 920 } 921 } 922 923 static int amdgpu_display_verify_plane(struct amdgpu_framebuffer *rfb, int plane, 924 const struct drm_format_info *format, 925 unsigned int block_width, unsigned int block_height, 926 unsigned int block_size_log2) 927 { 928 unsigned int width = rfb->base.width / 929 ((plane && plane < format->num_planes) ? format->hsub : 1); 930 unsigned int height = rfb->base.height / 931 ((plane && plane < format->num_planes) ? format->vsub : 1); 932 unsigned int cpp = plane < format->num_planes ? format->cpp[plane] : 1; 933 unsigned int block_pitch = block_width * cpp; 934 unsigned int min_pitch = ALIGN(width * cpp, block_pitch); 935 unsigned int block_size = 1 << block_size_log2; 936 uint64_t size; 937 938 if (rfb->base.pitches[plane] % block_pitch) { 939 drm_dbg_kms(rfb->base.dev, 940 "pitch %d for plane %d is not a multiple of block pitch %d\n", 941 rfb->base.pitches[plane], plane, block_pitch); 942 return -EINVAL; 943 } 944 if (rfb->base.pitches[plane] < min_pitch) { 945 drm_dbg_kms(rfb->base.dev, 946 "pitch %d for plane %d is less than minimum pitch %d\n", 947 rfb->base.pitches[plane], plane, min_pitch); 948 return -EINVAL; 949 } 950 951 /* Force at least natural alignment. */ 952 if (rfb->base.offsets[plane] % block_size) { 953 drm_dbg_kms(rfb->base.dev, 954 "offset 0x%x for plane %d is not a multiple of block pitch 0x%x\n", 955 rfb->base.offsets[plane], plane, block_size); 956 return -EINVAL; 957 } 958 959 size = rfb->base.offsets[plane] + 960 (uint64_t)rfb->base.pitches[plane] / block_pitch * 961 block_size * DIV_ROUND_UP(height, block_height); 962 963 if (rfb->base.obj[0]->size < size) { 964 drm_dbg_kms(rfb->base.dev, 965 "BO size 0x%zx is less than 0x%llx required for plane %d\n", 966 rfb->base.obj[0]->size, size, plane); 967 return -EINVAL; 968 } 969 970 return 0; 971 } 972 973 974 static int amdgpu_display_verify_sizes(struct amdgpu_framebuffer *rfb) 975 { 976 const struct drm_format_info *format_info = drm_format_info(rfb->base.format->format); 977 uint64_t modifier = rfb->base.modifier; 978 int ret; 979 unsigned int i, block_width, block_height, block_size_log2; 980 981 if (rfb->base.dev->mode_config.fb_modifiers_not_supported) 982 return 0; 983 984 for (i = 0; i < format_info->num_planes; ++i) { 985 if (modifier == DRM_FORMAT_MOD_LINEAR) { 986 block_width = 256 / format_info->cpp[i]; 987 block_height = 1; 988 block_size_log2 = 8; 989 } else { 990 int swizzle = AMD_FMT_MOD_GET(TILE, modifier); 991 992 switch ((swizzle & ~3) + 1) { 993 case DC_SW_256B_S: 994 block_size_log2 = 8; 995 break; 996 case DC_SW_4KB_S: 997 case DC_SW_4KB_S_X: 998 block_size_log2 = 12; 999 break; 1000 case DC_SW_64KB_S: 1001 case DC_SW_64KB_S_T: 1002 case DC_SW_64KB_S_X: 1003 block_size_log2 = 16; 1004 break; 1005 case DC_SW_VAR_S_X: 1006 block_size_log2 = 18; 1007 break; 1008 default: 1009 drm_dbg_kms(rfb->base.dev, 1010 "Swizzle mode with unknown block size: %d\n", swizzle); 1011 return -EINVAL; 1012 } 1013 1014 get_block_dimensions(block_size_log2, format_info->cpp[i], 1015 &block_width, &block_height); 1016 } 1017 1018 ret = amdgpu_display_verify_plane(rfb, i, format_info, 1019 block_width, block_height, block_size_log2); 1020 if (ret) 1021 return ret; 1022 } 1023 1024 if (AMD_FMT_MOD_GET(DCC, modifier)) { 1025 if (AMD_FMT_MOD_GET(DCC_RETILE, modifier)) { 1026 block_size_log2 = get_dcc_block_size(modifier, false, false); 1027 get_block_dimensions(block_size_log2 + 8, format_info->cpp[0], 1028 &block_width, &block_height); 1029 ret = amdgpu_display_verify_plane(rfb, i, format_info, 1030 block_width, block_height, 1031 block_size_log2); 1032 if (ret) 1033 return ret; 1034 1035 ++i; 1036 block_size_log2 = get_dcc_block_size(modifier, true, true); 1037 } else { 1038 bool pipe_aligned = AMD_FMT_MOD_GET(DCC_PIPE_ALIGN, modifier); 1039 1040 block_size_log2 = get_dcc_block_size(modifier, true, pipe_aligned); 1041 } 1042 get_block_dimensions(block_size_log2 + 8, format_info->cpp[0], 1043 &block_width, &block_height); 1044 ret = amdgpu_display_verify_plane(rfb, i, format_info, 1045 block_width, block_height, block_size_log2); 1046 if (ret) 1047 return ret; 1048 } 1049 1050 return 0; 1051 } 1052 1053 static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb, 1054 uint64_t *tiling_flags, bool *tmz_surface) 1055 { 1056 struct amdgpu_bo *rbo; 1057 int r; 1058 1059 if (!amdgpu_fb) { 1060 *tiling_flags = 0; 1061 *tmz_surface = false; 1062 return 0; 1063 } 1064 1065 rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]); 1066 r = amdgpu_bo_reserve(rbo, false); 1067 1068 if (unlikely(r)) { 1069 /* Don't show error message when returning -ERESTARTSYS */ 1070 if (r != -ERESTARTSYS) 1071 DRM_ERROR("Unable to reserve buffer: %d\n", r); 1072 return r; 1073 } 1074 1075 if (tiling_flags) 1076 amdgpu_bo_get_tiling_flags(rbo, tiling_flags); 1077 1078 if (tmz_surface) 1079 *tmz_surface = amdgpu_bo_encrypted(rbo); 1080 1081 amdgpu_bo_unreserve(rbo); 1082 1083 return r; 1084 } 1085 1086 static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev, 1087 struct amdgpu_framebuffer *rfb, 1088 struct drm_file *file_priv, 1089 const struct drm_mode_fb_cmd2 *mode_cmd, 1090 struct drm_gem_object *obj) 1091 { 1092 int ret; 1093 1094 rfb->base.obj[0] = obj; 1095 drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd); 1096 /* Verify that the modifier is supported. */ 1097 if (!drm_any_plane_has_format(dev, mode_cmd->pixel_format, 1098 mode_cmd->modifier[0])) { 1099 drm_dbg_kms(dev, 1100 "unsupported pixel format %p4cc / modifier 0x%llx\n", 1101 &mode_cmd->pixel_format, mode_cmd->modifier[0]); 1102 1103 ret = -EINVAL; 1104 goto err; 1105 } 1106 1107 ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj); 1108 if (ret) 1109 goto err; 1110 1111 if (drm_drv_uses_atomic_modeset(dev)) 1112 ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs_atomic); 1113 else 1114 ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs); 1115 if (ret) 1116 goto err; 1117 1118 return 0; 1119 err: 1120 drm_dbg_kms(dev, "Failed to verify and init gem fb: %d\n", ret); 1121 rfb->base.obj[0] = NULL; 1122 return ret; 1123 } 1124 1125 static int amdgpu_display_framebuffer_init(struct drm_device *dev, 1126 struct amdgpu_framebuffer *rfb, 1127 const struct drm_mode_fb_cmd2 *mode_cmd, 1128 struct drm_gem_object *obj) 1129 { 1130 struct amdgpu_device *adev = drm_to_adev(dev); 1131 int ret, i; 1132 1133 /* 1134 * This needs to happen before modifier conversion as that might change 1135 * the number of planes. 1136 */ 1137 for (i = 1; i < rfb->base.format->num_planes; ++i) { 1138 if (mode_cmd->handles[i] != mode_cmd->handles[0]) { 1139 drm_dbg_kms(dev, "Plane 0 and %d have different BOs: %u vs. %u\n", 1140 i, mode_cmd->handles[0], mode_cmd->handles[i]); 1141 ret = -EINVAL; 1142 return ret; 1143 } 1144 } 1145 1146 ret = amdgpu_display_get_fb_info(rfb, &rfb->tiling_flags, &rfb->tmz_surface); 1147 if (ret) 1148 return ret; 1149 1150 if (dev->mode_config.fb_modifiers_not_supported && !adev->enable_virtual_display) { 1151 drm_WARN_ONCE(dev, adev->family >= AMDGPU_FAMILY_AI, 1152 "GFX9+ requires FB check based on format modifier\n"); 1153 ret = check_tiling_flags_gfx6(rfb); 1154 if (ret) 1155 return ret; 1156 } 1157 1158 if (!dev->mode_config.fb_modifiers_not_supported && 1159 !(rfb->base.flags & DRM_MODE_FB_MODIFIERS)) { 1160 ret = convert_tiling_flags_to_modifier(rfb); 1161 if (ret) { 1162 drm_dbg_kms(dev, "Failed to convert tiling flags 0x%llX to a modifier", 1163 rfb->tiling_flags); 1164 return ret; 1165 } 1166 } 1167 1168 ret = amdgpu_display_verify_sizes(rfb); 1169 if (ret) 1170 return ret; 1171 1172 for (i = 0; i < rfb->base.format->num_planes; ++i) { 1173 drm_gem_object_get(rfb->base.obj[0]); 1174 rfb->base.obj[i] = rfb->base.obj[0]; 1175 } 1176 1177 return 0; 1178 } 1179 1180 struct drm_framebuffer * 1181 amdgpu_display_user_framebuffer_create(struct drm_device *dev, 1182 struct drm_file *file_priv, 1183 const struct drm_mode_fb_cmd2 *mode_cmd) 1184 { 1185 struct amdgpu_framebuffer *amdgpu_fb; 1186 struct drm_gem_object *obj; 1187 struct amdgpu_bo *bo; 1188 uint32_t domains; 1189 int ret; 1190 1191 obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]); 1192 if (obj == NULL) { 1193 drm_dbg_kms(dev, "No GEM object associated to handle 0x%08X, " 1194 "can't create framebuffer\n", mode_cmd->handles[0]); 1195 return ERR_PTR(-ENOENT); 1196 } 1197 1198 /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */ 1199 bo = gem_to_amdgpu_bo(obj); 1200 domains = amdgpu_display_supported_domains(drm_to_adev(dev), bo->flags); 1201 if (obj->import_attach && !(domains & AMDGPU_GEM_DOMAIN_GTT)) { 1202 drm_dbg_kms(dev, "Cannot create framebuffer from imported dma_buf\n"); 1203 drm_gem_object_put(obj); 1204 return ERR_PTR(-EINVAL); 1205 } 1206 1207 amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL); 1208 if (amdgpu_fb == NULL) { 1209 drm_gem_object_put(obj); 1210 return ERR_PTR(-ENOMEM); 1211 } 1212 1213 ret = amdgpu_display_gem_fb_verify_and_init(dev, amdgpu_fb, file_priv, 1214 mode_cmd, obj); 1215 if (ret) { 1216 kfree(amdgpu_fb); 1217 drm_gem_object_put(obj); 1218 return ERR_PTR(ret); 1219 } 1220 1221 drm_gem_object_put(obj); 1222 return &amdgpu_fb->base; 1223 } 1224 1225 const struct drm_mode_config_funcs amdgpu_mode_funcs = { 1226 .fb_create = amdgpu_display_user_framebuffer_create, 1227 .output_poll_changed = drm_fb_helper_output_poll_changed, 1228 }; 1229 1230 static const struct drm_prop_enum_list amdgpu_underscan_enum_list[] = 1231 { { UNDERSCAN_OFF, "off" }, 1232 { UNDERSCAN_ON, "on" }, 1233 { UNDERSCAN_AUTO, "auto" }, 1234 }; 1235 1236 static const struct drm_prop_enum_list amdgpu_audio_enum_list[] = 1237 { { AMDGPU_AUDIO_DISABLE, "off" }, 1238 { AMDGPU_AUDIO_ENABLE, "on" }, 1239 { AMDGPU_AUDIO_AUTO, "auto" }, 1240 }; 1241 1242 /* XXX support different dither options? spatial, temporal, both, etc. */ 1243 static const struct drm_prop_enum_list amdgpu_dither_enum_list[] = 1244 { { AMDGPU_FMT_DITHER_DISABLE, "off" }, 1245 { AMDGPU_FMT_DITHER_ENABLE, "on" }, 1246 }; 1247 1248 int amdgpu_display_modeset_create_props(struct amdgpu_device *adev) 1249 { 1250 int sz; 1251 1252 adev->mode_info.coherent_mode_property = 1253 drm_property_create_range(adev_to_drm(adev), 0, "coherent", 0, 1); 1254 if (!adev->mode_info.coherent_mode_property) 1255 return -ENOMEM; 1256 1257 adev->mode_info.load_detect_property = 1258 drm_property_create_range(adev_to_drm(adev), 0, "load detection", 0, 1); 1259 if (!adev->mode_info.load_detect_property) 1260 return -ENOMEM; 1261 1262 drm_mode_create_scaling_mode_property(adev_to_drm(adev)); 1263 1264 sz = ARRAY_SIZE(amdgpu_underscan_enum_list); 1265 adev->mode_info.underscan_property = 1266 drm_property_create_enum(adev_to_drm(adev), 0, 1267 "underscan", 1268 amdgpu_underscan_enum_list, sz); 1269 1270 adev->mode_info.underscan_hborder_property = 1271 drm_property_create_range(adev_to_drm(adev), 0, 1272 "underscan hborder", 0, 128); 1273 if (!adev->mode_info.underscan_hborder_property) 1274 return -ENOMEM; 1275 1276 adev->mode_info.underscan_vborder_property = 1277 drm_property_create_range(adev_to_drm(adev), 0, 1278 "underscan vborder", 0, 128); 1279 if (!adev->mode_info.underscan_vborder_property) 1280 return -ENOMEM; 1281 1282 sz = ARRAY_SIZE(amdgpu_audio_enum_list); 1283 adev->mode_info.audio_property = 1284 drm_property_create_enum(adev_to_drm(adev), 0, 1285 "audio", 1286 amdgpu_audio_enum_list, sz); 1287 1288 sz = ARRAY_SIZE(amdgpu_dither_enum_list); 1289 adev->mode_info.dither_property = 1290 drm_property_create_enum(adev_to_drm(adev), 0, 1291 "dither", 1292 amdgpu_dither_enum_list, sz); 1293 1294 if (amdgpu_device_has_dc_support(adev)) { 1295 adev->mode_info.abm_level_property = 1296 drm_property_create_range(adev_to_drm(adev), 0, 1297 "abm level", 0, 4); 1298 if (!adev->mode_info.abm_level_property) 1299 return -ENOMEM; 1300 } 1301 1302 return 0; 1303 } 1304 1305 void amdgpu_display_update_priority(struct amdgpu_device *adev) 1306 { 1307 /* adjustment options for the display watermarks */ 1308 if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2)) 1309 adev->mode_info.disp_priority = 0; 1310 else 1311 adev->mode_info.disp_priority = amdgpu_disp_priority; 1312 1313 } 1314 1315 static bool amdgpu_display_is_hdtv_mode(const struct drm_display_mode *mode) 1316 { 1317 /* try and guess if this is a tv or a monitor */ 1318 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ 1319 (mode->vdisplay == 576) || /* 576p */ 1320 (mode->vdisplay == 720) || /* 720p */ 1321 (mode->vdisplay == 1080)) /* 1080p */ 1322 return true; 1323 else 1324 return false; 1325 } 1326 1327 bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 1328 const struct drm_display_mode *mode, 1329 struct drm_display_mode *adjusted_mode) 1330 { 1331 struct drm_device *dev = crtc->dev; 1332 struct drm_encoder *encoder; 1333 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1334 struct amdgpu_encoder *amdgpu_encoder; 1335 struct drm_connector *connector; 1336 u32 src_v = 1, dst_v = 1; 1337 u32 src_h = 1, dst_h = 1; 1338 1339 amdgpu_crtc->h_border = 0; 1340 amdgpu_crtc->v_border = 0; 1341 1342 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1343 if (encoder->crtc != crtc) 1344 continue; 1345 amdgpu_encoder = to_amdgpu_encoder(encoder); 1346 connector = amdgpu_get_connector_for_encoder(encoder); 1347 1348 /* set scaling */ 1349 if (amdgpu_encoder->rmx_type == RMX_OFF) 1350 amdgpu_crtc->rmx_type = RMX_OFF; 1351 else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay || 1352 mode->vdisplay < amdgpu_encoder->native_mode.vdisplay) 1353 amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type; 1354 else 1355 amdgpu_crtc->rmx_type = RMX_OFF; 1356 /* copy native mode */ 1357 memcpy(&amdgpu_crtc->native_mode, 1358 &amdgpu_encoder->native_mode, 1359 sizeof(struct drm_display_mode)); 1360 src_v = crtc->mode.vdisplay; 1361 dst_v = amdgpu_crtc->native_mode.vdisplay; 1362 src_h = crtc->mode.hdisplay; 1363 dst_h = amdgpu_crtc->native_mode.hdisplay; 1364 1365 /* fix up for overscan on hdmi */ 1366 if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && 1367 ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) || 1368 ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) && 1369 connector->display_info.is_hdmi && 1370 amdgpu_display_is_hdtv_mode(mode)))) { 1371 if (amdgpu_encoder->underscan_hborder != 0) 1372 amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder; 1373 else 1374 amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16; 1375 if (amdgpu_encoder->underscan_vborder != 0) 1376 amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder; 1377 else 1378 amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16; 1379 amdgpu_crtc->rmx_type = RMX_FULL; 1380 src_v = crtc->mode.vdisplay; 1381 dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2); 1382 src_h = crtc->mode.hdisplay; 1383 dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2); 1384 } 1385 } 1386 if (amdgpu_crtc->rmx_type != RMX_OFF) { 1387 fixed20_12 a, b; 1388 a.full = dfixed_const(src_v); 1389 b.full = dfixed_const(dst_v); 1390 amdgpu_crtc->vsc.full = dfixed_div(a, b); 1391 a.full = dfixed_const(src_h); 1392 b.full = dfixed_const(dst_h); 1393 amdgpu_crtc->hsc.full = dfixed_div(a, b); 1394 } else { 1395 amdgpu_crtc->vsc.full = dfixed_const(1); 1396 amdgpu_crtc->hsc.full = dfixed_const(1); 1397 } 1398 return true; 1399 } 1400 1401 /* 1402 * Retrieve current video scanout position of crtc on a given gpu, and 1403 * an optional accurate timestamp of when query happened. 1404 * 1405 * \param dev Device to query. 1406 * \param pipe Crtc to query. 1407 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). 1408 * For driver internal use only also supports these flags: 1409 * 1410 * USE_REAL_VBLANKSTART to use the real start of vblank instead 1411 * of a fudged earlier start of vblank. 1412 * 1413 * GET_DISTANCE_TO_VBLANKSTART to return distance to the 1414 * fudged earlier start of vblank in *vpos and the distance 1415 * to true start of vblank in *hpos. 1416 * 1417 * \param *vpos Location where vertical scanout position should be stored. 1418 * \param *hpos Location where horizontal scanout position should go. 1419 * \param *stime Target location for timestamp taken immediately before 1420 * scanout position query. Can be NULL to skip timestamp. 1421 * \param *etime Target location for timestamp taken immediately after 1422 * scanout position query. Can be NULL to skip timestamp. 1423 * 1424 * Returns vpos as a positive number while in active scanout area. 1425 * Returns vpos as a negative number inside vblank, counting the number 1426 * of scanlines to go until end of vblank, e.g., -1 means "one scanline 1427 * until start of active scanout / end of vblank." 1428 * 1429 * \return Flags, or'ed together as follows: 1430 * 1431 * DRM_SCANOUTPOS_VALID = Query successful. 1432 * DRM_SCANOUTPOS_INVBL = Inside vblank. 1433 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of 1434 * this flag means that returned position may be offset by a constant but 1435 * unknown small number of scanlines wrt. real scanout position. 1436 * 1437 */ 1438 int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev, 1439 unsigned int pipe, unsigned int flags, int *vpos, 1440 int *hpos, ktime_t *stime, ktime_t *etime, 1441 const struct drm_display_mode *mode) 1442 { 1443 u32 vbl = 0, position = 0; 1444 int vbl_start, vbl_end, vtotal, ret = 0; 1445 bool in_vbl = true; 1446 1447 struct amdgpu_device *adev = drm_to_adev(dev); 1448 1449 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ 1450 1451 /* Get optional system timestamp before query. */ 1452 if (stime) 1453 *stime = ktime_get(); 1454 1455 if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0) 1456 ret |= DRM_SCANOUTPOS_VALID; 1457 1458 /* Get optional system timestamp after query. */ 1459 if (etime) 1460 *etime = ktime_get(); 1461 1462 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ 1463 1464 /* Decode into vertical and horizontal scanout position. */ 1465 *vpos = position & 0x1fff; 1466 *hpos = (position >> 16) & 0x1fff; 1467 1468 /* Valid vblank area boundaries from gpu retrieved? */ 1469 if (vbl > 0) { 1470 /* Yes: Decode. */ 1471 ret |= DRM_SCANOUTPOS_ACCURATE; 1472 vbl_start = vbl & 0x1fff; 1473 vbl_end = (vbl >> 16) & 0x1fff; 1474 } 1475 else { 1476 /* No: Fake something reasonable which gives at least ok results. */ 1477 vbl_start = mode->crtc_vdisplay; 1478 vbl_end = 0; 1479 } 1480 1481 /* Called from driver internal vblank counter query code? */ 1482 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 1483 /* Caller wants distance from real vbl_start in *hpos */ 1484 *hpos = *vpos - vbl_start; 1485 } 1486 1487 /* Fudge vblank to start a few scanlines earlier to handle the 1488 * problem that vblank irqs fire a few scanlines before start 1489 * of vblank. Some driver internal callers need the true vblank 1490 * start to be used and signal this via the USE_REAL_VBLANKSTART flag. 1491 * 1492 * The cause of the "early" vblank irq is that the irq is triggered 1493 * by the line buffer logic when the line buffer read position enters 1494 * the vblank, whereas our crtc scanout position naturally lags the 1495 * line buffer read position. 1496 */ 1497 if (!(flags & USE_REAL_VBLANKSTART)) 1498 vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines; 1499 1500 /* Test scanout position against vblank region. */ 1501 if ((*vpos < vbl_start) && (*vpos >= vbl_end)) 1502 in_vbl = false; 1503 1504 /* In vblank? */ 1505 if (in_vbl) 1506 ret |= DRM_SCANOUTPOS_IN_VBLANK; 1507 1508 /* Called from driver internal vblank counter query code? */ 1509 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 1510 /* Caller wants distance from fudged earlier vbl_start */ 1511 *vpos -= vbl_start; 1512 return ret; 1513 } 1514 1515 /* Check if inside vblank area and apply corrective offsets: 1516 * vpos will then be >=0 in video scanout area, but negative 1517 * within vblank area, counting down the number of lines until 1518 * start of scanout. 1519 */ 1520 1521 /* Inside "upper part" of vblank area? Apply corrective offset if so: */ 1522 if (in_vbl && (*vpos >= vbl_start)) { 1523 vtotal = mode->crtc_vtotal; 1524 1525 /* With variable refresh rate displays the vpos can exceed 1526 * the vtotal value. Clamp to 0 to return -vbl_end instead 1527 * of guessing the remaining number of lines until scanout. 1528 */ 1529 *vpos = (*vpos < vtotal) ? (*vpos - vtotal) : 0; 1530 } 1531 1532 /* Correct for shifted end of vbl at vbl_end. */ 1533 *vpos = *vpos - vbl_end; 1534 1535 return ret; 1536 } 1537 1538 int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc) 1539 { 1540 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) 1541 return AMDGPU_CRTC_IRQ_NONE; 1542 1543 switch (crtc) { 1544 case 0: 1545 return AMDGPU_CRTC_IRQ_VBLANK1; 1546 case 1: 1547 return AMDGPU_CRTC_IRQ_VBLANK2; 1548 case 2: 1549 return AMDGPU_CRTC_IRQ_VBLANK3; 1550 case 3: 1551 return AMDGPU_CRTC_IRQ_VBLANK4; 1552 case 4: 1553 return AMDGPU_CRTC_IRQ_VBLANK5; 1554 case 5: 1555 return AMDGPU_CRTC_IRQ_VBLANK6; 1556 default: 1557 return AMDGPU_CRTC_IRQ_NONE; 1558 } 1559 } 1560 1561 bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc, 1562 bool in_vblank_irq, int *vpos, 1563 int *hpos, ktime_t *stime, ktime_t *etime, 1564 const struct drm_display_mode *mode) 1565 { 1566 struct drm_device *dev = crtc->dev; 1567 unsigned int pipe = crtc->index; 1568 1569 return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos, 1570 stime, etime, mode); 1571 } 1572 1573 static bool 1574 amdgpu_display_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj) 1575 { 1576 struct drm_device *dev = adev_to_drm(adev); 1577 struct drm_fb_helper *fb_helper = dev->fb_helper; 1578 1579 if (!fb_helper || !fb_helper->buffer) 1580 return false; 1581 1582 if (gem_to_amdgpu_bo(fb_helper->buffer->gem) != robj) 1583 return false; 1584 1585 return true; 1586 } 1587 1588 int amdgpu_display_suspend_helper(struct amdgpu_device *adev) 1589 { 1590 struct drm_device *dev = adev_to_drm(adev); 1591 struct drm_crtc *crtc; 1592 struct drm_connector *connector; 1593 struct drm_connector_list_iter iter; 1594 int r; 1595 1596 /* turn off display hw */ 1597 drm_modeset_lock_all(dev); 1598 drm_connector_list_iter_begin(dev, &iter); 1599 drm_for_each_connector_iter(connector, &iter) 1600 drm_helper_connector_dpms(connector, 1601 DRM_MODE_DPMS_OFF); 1602 drm_connector_list_iter_end(&iter); 1603 drm_modeset_unlock_all(dev); 1604 /* unpin the front buffers and cursors */ 1605 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1606 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1607 struct drm_framebuffer *fb = crtc->primary->fb; 1608 struct amdgpu_bo *robj; 1609 1610 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) { 1611 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); 1612 r = amdgpu_bo_reserve(aobj, true); 1613 if (r == 0) { 1614 amdgpu_bo_unpin(aobj); 1615 amdgpu_bo_unreserve(aobj); 1616 } 1617 } 1618 1619 if (fb == NULL || fb->obj[0] == NULL) { 1620 continue; 1621 } 1622 robj = gem_to_amdgpu_bo(fb->obj[0]); 1623 if (!amdgpu_display_robj_is_fb(adev, robj)) { 1624 r = amdgpu_bo_reserve(robj, true); 1625 if (r == 0) { 1626 amdgpu_bo_unpin(robj); 1627 amdgpu_bo_unreserve(robj); 1628 } 1629 } 1630 } 1631 return 0; 1632 } 1633 1634 int amdgpu_display_resume_helper(struct amdgpu_device *adev) 1635 { 1636 struct drm_device *dev = adev_to_drm(adev); 1637 struct drm_connector *connector; 1638 struct drm_connector_list_iter iter; 1639 struct drm_crtc *crtc; 1640 int r; 1641 1642 /* pin cursors */ 1643 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1644 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1645 1646 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) { 1647 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); 1648 r = amdgpu_bo_reserve(aobj, true); 1649 if (r == 0) { 1650 r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM); 1651 if (r != 0) 1652 dev_err(adev->dev, "Failed to pin cursor BO (%d)\n", r); 1653 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj); 1654 amdgpu_bo_unreserve(aobj); 1655 } 1656 } 1657 } 1658 1659 drm_helper_resume_force_mode(dev); 1660 1661 /* turn on display hw */ 1662 drm_modeset_lock_all(dev); 1663 1664 drm_connector_list_iter_begin(dev, &iter); 1665 drm_for_each_connector_iter(connector, &iter) 1666 drm_helper_connector_dpms(connector, 1667 DRM_MODE_DPMS_ON); 1668 drm_connector_list_iter_end(&iter); 1669 1670 drm_modeset_unlock_all(dev); 1671 1672 return 0; 1673 } 1674 1675