1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_discovery.h" 28 #include "soc15_hw_ip.h" 29 #include "discovery.h" 30 31 #include "soc15.h" 32 #include "gfx_v9_0.h" 33 #include "gmc_v9_0.h" 34 #include "df_v1_7.h" 35 #include "df_v3_6.h" 36 #include "nbio_v6_1.h" 37 #include "nbio_v7_0.h" 38 #include "nbio_v7_4.h" 39 #include "hdp_v4_0.h" 40 #include "vega10_ih.h" 41 #include "vega20_ih.h" 42 #include "sdma_v4_0.h" 43 #include "uvd_v7_0.h" 44 #include "vce_v4_0.h" 45 #include "vcn_v1_0.h" 46 #include "vcn_v2_5.h" 47 #include "jpeg_v2_5.h" 48 #include "smuio_v9_0.h" 49 #include "gmc_v10_0.h" 50 #include "gfxhub_v2_0.h" 51 #include "mmhub_v2_0.h" 52 #include "nbio_v2_3.h" 53 #include "nbio_v7_2.h" 54 #include "hdp_v5_0.h" 55 #include "nv.h" 56 #include "navi10_ih.h" 57 #include "gfx_v10_0.h" 58 #include "sdma_v5_0.h" 59 #include "sdma_v5_2.h" 60 #include "vcn_v2_0.h" 61 #include "jpeg_v2_0.h" 62 #include "vcn_v3_0.h" 63 #include "jpeg_v3_0.h" 64 #include "amdgpu_vkms.h" 65 #include "mes_v10_1.h" 66 #include "smuio_v11_0.h" 67 #include "smuio_v11_0_6.h" 68 #include "smuio_v13_0.h" 69 70 #define FIRMWARE_IP_DISCOVERY "amdgpu/ip_discovery.bin" 71 MODULE_FIRMWARE(FIRMWARE_IP_DISCOVERY); 72 73 #define mmRCC_CONFIG_MEMSIZE 0xde3 74 #define mmMM_INDEX 0x0 75 #define mmMM_INDEX_HI 0x6 76 #define mmMM_DATA 0x1 77 78 static const char *hw_id_names[HW_ID_MAX] = { 79 [MP1_HWID] = "MP1", 80 [MP2_HWID] = "MP2", 81 [THM_HWID] = "THM", 82 [SMUIO_HWID] = "SMUIO", 83 [FUSE_HWID] = "FUSE", 84 [CLKA_HWID] = "CLKA", 85 [PWR_HWID] = "PWR", 86 [GC_HWID] = "GC", 87 [UVD_HWID] = "UVD", 88 [AUDIO_AZ_HWID] = "AUDIO_AZ", 89 [ACP_HWID] = "ACP", 90 [DCI_HWID] = "DCI", 91 [DMU_HWID] = "DMU", 92 [DCO_HWID] = "DCO", 93 [DIO_HWID] = "DIO", 94 [XDMA_HWID] = "XDMA", 95 [DCEAZ_HWID] = "DCEAZ", 96 [DAZ_HWID] = "DAZ", 97 [SDPMUX_HWID] = "SDPMUX", 98 [NTB_HWID] = "NTB", 99 [IOHC_HWID] = "IOHC", 100 [L2IMU_HWID] = "L2IMU", 101 [VCE_HWID] = "VCE", 102 [MMHUB_HWID] = "MMHUB", 103 [ATHUB_HWID] = "ATHUB", 104 [DBGU_NBIO_HWID] = "DBGU_NBIO", 105 [DFX_HWID] = "DFX", 106 [DBGU0_HWID] = "DBGU0", 107 [DBGU1_HWID] = "DBGU1", 108 [OSSSYS_HWID] = "OSSSYS", 109 [HDP_HWID] = "HDP", 110 [SDMA0_HWID] = "SDMA0", 111 [SDMA1_HWID] = "SDMA1", 112 [SDMA2_HWID] = "SDMA2", 113 [SDMA3_HWID] = "SDMA3", 114 [ISP_HWID] = "ISP", 115 [DBGU_IO_HWID] = "DBGU_IO", 116 [DF_HWID] = "DF", 117 [CLKB_HWID] = "CLKB", 118 [FCH_HWID] = "FCH", 119 [DFX_DAP_HWID] = "DFX_DAP", 120 [L1IMU_PCIE_HWID] = "L1IMU_PCIE", 121 [L1IMU_NBIF_HWID] = "L1IMU_NBIF", 122 [L1IMU_IOAGR_HWID] = "L1IMU_IOAGR", 123 [L1IMU3_HWID] = "L1IMU3", 124 [L1IMU4_HWID] = "L1IMU4", 125 [L1IMU5_HWID] = "L1IMU5", 126 [L1IMU6_HWID] = "L1IMU6", 127 [L1IMU7_HWID] = "L1IMU7", 128 [L1IMU8_HWID] = "L1IMU8", 129 [L1IMU9_HWID] = "L1IMU9", 130 [L1IMU10_HWID] = "L1IMU10", 131 [L1IMU11_HWID] = "L1IMU11", 132 [L1IMU12_HWID] = "L1IMU12", 133 [L1IMU13_HWID] = "L1IMU13", 134 [L1IMU14_HWID] = "L1IMU14", 135 [L1IMU15_HWID] = "L1IMU15", 136 [WAFLC_HWID] = "WAFLC", 137 [FCH_USB_PD_HWID] = "FCH_USB_PD", 138 [PCIE_HWID] = "PCIE", 139 [PCS_HWID] = "PCS", 140 [DDCL_HWID] = "DDCL", 141 [SST_HWID] = "SST", 142 [IOAGR_HWID] = "IOAGR", 143 [NBIF_HWID] = "NBIF", 144 [IOAPIC_HWID] = "IOAPIC", 145 [SYSTEMHUB_HWID] = "SYSTEMHUB", 146 [NTBCCP_HWID] = "NTBCCP", 147 [UMC_HWID] = "UMC", 148 [SATA_HWID] = "SATA", 149 [USB_HWID] = "USB", 150 [CCXSEC_HWID] = "CCXSEC", 151 [XGMI_HWID] = "XGMI", 152 [XGBE_HWID] = "XGBE", 153 [MP0_HWID] = "MP0", 154 }; 155 156 static int hw_id_map[MAX_HWIP] = { 157 [GC_HWIP] = GC_HWID, 158 [HDP_HWIP] = HDP_HWID, 159 [SDMA0_HWIP] = SDMA0_HWID, 160 [SDMA1_HWIP] = SDMA1_HWID, 161 [SDMA2_HWIP] = SDMA2_HWID, 162 [SDMA3_HWIP] = SDMA3_HWID, 163 [MMHUB_HWIP] = MMHUB_HWID, 164 [ATHUB_HWIP] = ATHUB_HWID, 165 [NBIO_HWIP] = NBIF_HWID, 166 [MP0_HWIP] = MP0_HWID, 167 [MP1_HWIP] = MP1_HWID, 168 [UVD_HWIP] = UVD_HWID, 169 [VCE_HWIP] = VCE_HWID, 170 [DF_HWIP] = DF_HWID, 171 [DCE_HWIP] = DMU_HWID, 172 [OSSSYS_HWIP] = OSSSYS_HWID, 173 [SMUIO_HWIP] = SMUIO_HWID, 174 [PWR_HWIP] = PWR_HWID, 175 [NBIF_HWIP] = NBIF_HWID, 176 [THM_HWIP] = THM_HWID, 177 [CLK_HWIP] = CLKA_HWID, 178 [UMC_HWIP] = UMC_HWID, 179 [XGMI_HWIP] = XGMI_HWID, 180 [DCI_HWIP] = DCI_HWID, 181 }; 182 183 static int amdgpu_discovery_read_binary_from_vram(struct amdgpu_device *adev, uint8_t *binary) 184 { 185 uint64_t vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20; 186 uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET; 187 188 amdgpu_device_vram_access(adev, pos, (uint32_t *)binary, 189 adev->mman.discovery_tmr_size, false); 190 return 0; 191 } 192 193 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, uint8_t *binary) 194 { 195 const struct firmware *fw; 196 const char *fw_name; 197 int r; 198 199 switch (amdgpu_discovery) { 200 case 2: 201 fw_name = FIRMWARE_IP_DISCOVERY; 202 break; 203 default: 204 dev_warn(adev->dev, "amdgpu_discovery is not set properly\n"); 205 return -EINVAL; 206 } 207 208 r = request_firmware(&fw, fw_name, adev->dev); 209 if (r) { 210 dev_err(adev->dev, "can't load firmware \"%s\"\n", 211 fw_name); 212 return r; 213 } 214 215 memcpy((u8 *)binary, (u8 *)fw->data, adev->mman.discovery_tmr_size); 216 release_firmware(fw); 217 218 return 0; 219 } 220 221 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size) 222 { 223 uint16_t checksum = 0; 224 int i; 225 226 for (i = 0; i < size; i++) 227 checksum += data[i]; 228 229 return checksum; 230 } 231 232 static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size, 233 uint16_t expected) 234 { 235 return !!(amdgpu_discovery_calculate_checksum(data, size) == expected); 236 } 237 238 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary) 239 { 240 struct binary_header *bhdr; 241 bhdr = (struct binary_header *)binary; 242 243 return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE); 244 } 245 246 static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev) 247 { 248 /* 249 * So far, apply this quirk only on those Navy Flounder boards which 250 * have a bad harvest table of VCN config. 251 */ 252 if ((adev->ip_versions[UVD_HWIP][1] == IP_VERSION(3, 0, 1)) && 253 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 2))) { 254 switch (adev->pdev->revision) { 255 case 0xC1: 256 case 0xC2: 257 case 0xC3: 258 case 0xC5: 259 case 0xC7: 260 case 0xCF: 261 case 0xDF: 262 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 263 break; 264 default: 265 break; 266 } 267 } 268 } 269 270 static int amdgpu_discovery_init(struct amdgpu_device *adev) 271 { 272 struct table_info *info; 273 struct binary_header *bhdr; 274 struct ip_discovery_header *ihdr; 275 struct gpu_info_header *ghdr; 276 uint16_t offset; 277 uint16_t size; 278 uint16_t checksum; 279 int r; 280 281 adev->mman.discovery_tmr_size = DISCOVERY_TMR_SIZE; 282 adev->mman.discovery_bin = kzalloc(adev->mman.discovery_tmr_size, GFP_KERNEL); 283 if (!adev->mman.discovery_bin) 284 return -ENOMEM; 285 286 r = amdgpu_discovery_read_binary_from_vram(adev, adev->mman.discovery_bin); 287 if (r) { 288 dev_err(adev->dev, "failed to read ip discovery binary from vram\n"); 289 r = -EINVAL; 290 goto out; 291 } 292 293 if(!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) { 294 dev_warn(adev->dev, "get invalid ip discovery binary signature from vram\n"); 295 /* retry read ip discovery binary from file */ 296 r = amdgpu_discovery_read_binary_from_file(adev, adev->mman.discovery_bin); 297 if (r) { 298 dev_err(adev->dev, "failed to read ip discovery binary from file\n"); 299 r = -EINVAL; 300 goto out; 301 } 302 /* check the ip discovery binary signature */ 303 if(!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) { 304 dev_warn(adev->dev, "get invalid ip discovery binary signature from file\n"); 305 r = -EINVAL; 306 goto out; 307 } 308 } 309 310 bhdr = (struct binary_header *)adev->mman.discovery_bin; 311 312 offset = offsetof(struct binary_header, binary_checksum) + 313 sizeof(bhdr->binary_checksum); 314 size = le16_to_cpu(bhdr->binary_size) - offset; 315 checksum = le16_to_cpu(bhdr->binary_checksum); 316 317 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 318 size, checksum)) { 319 dev_err(adev->dev, "invalid ip discovery binary checksum\n"); 320 r = -EINVAL; 321 goto out; 322 } 323 324 info = &bhdr->table_list[IP_DISCOVERY]; 325 offset = le16_to_cpu(info->offset); 326 checksum = le16_to_cpu(info->checksum); 327 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + offset); 328 329 if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) { 330 dev_err(adev->dev, "invalid ip discovery data table signature\n"); 331 r = -EINVAL; 332 goto out; 333 } 334 335 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 336 le16_to_cpu(ihdr->size), checksum)) { 337 dev_err(adev->dev, "invalid ip discovery data table checksum\n"); 338 r = -EINVAL; 339 goto out; 340 } 341 342 info = &bhdr->table_list[GC]; 343 offset = le16_to_cpu(info->offset); 344 checksum = le16_to_cpu(info->checksum); 345 ghdr = (struct gpu_info_header *)(adev->mman.discovery_bin + offset); 346 347 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 348 le32_to_cpu(ghdr->size), checksum)) { 349 dev_err(adev->dev, "invalid gc data table checksum\n"); 350 r = -EINVAL; 351 goto out; 352 } 353 354 return 0; 355 356 out: 357 kfree(adev->mman.discovery_bin); 358 adev->mman.discovery_bin = NULL; 359 360 return r; 361 } 362 363 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev); 364 365 void amdgpu_discovery_fini(struct amdgpu_device *adev) 366 { 367 amdgpu_discovery_sysfs_fini(adev); 368 kfree(adev->mman.discovery_bin); 369 adev->mman.discovery_bin = NULL; 370 } 371 372 static int amdgpu_discovery_validate_ip(const struct ip *ip) 373 { 374 if (ip->number_instance >= HWIP_MAX_INSTANCE) { 375 DRM_ERROR("Unexpected number_instance (%d) from ip discovery blob\n", 376 ip->number_instance); 377 return -EINVAL; 378 } 379 if (le16_to_cpu(ip->hw_id) >= HW_ID_MAX) { 380 DRM_ERROR("Unexpected hw_id (%d) from ip discovery blob\n", 381 le16_to_cpu(ip->hw_id)); 382 return -EINVAL; 383 } 384 385 return 0; 386 } 387 388 /* ================================================== */ 389 390 struct ip_hw_instance { 391 struct kobject kobj; /* ip_discovery/die/#die/#hw_id/#instance/<attrs...> */ 392 393 int hw_id; 394 u8 num_instance; 395 u8 major, minor, revision; 396 u8 harvest; 397 398 int num_base_addresses; 399 u32 base_addr[]; 400 }; 401 402 struct ip_hw_id { 403 struct kset hw_id_kset; /* ip_discovery/die/#die/#hw_id/, contains ip_hw_instance */ 404 int hw_id; 405 }; 406 407 struct ip_die_entry { 408 struct kset ip_kset; /* ip_discovery/die/#die/, contains ip_hw_id */ 409 u16 num_ips; 410 }; 411 412 /* -------------------------------------------------- */ 413 414 struct ip_hw_instance_attr { 415 struct attribute attr; 416 ssize_t (*show)(struct ip_hw_instance *ip_hw_instance, char *buf); 417 }; 418 419 static ssize_t hw_id_show(struct ip_hw_instance *ip_hw_instance, char *buf) 420 { 421 return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id); 422 } 423 424 static ssize_t num_instance_show(struct ip_hw_instance *ip_hw_instance, char *buf) 425 { 426 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance); 427 } 428 429 static ssize_t major_show(struct ip_hw_instance *ip_hw_instance, char *buf) 430 { 431 return sysfs_emit(buf, "%d\n", ip_hw_instance->major); 432 } 433 434 static ssize_t minor_show(struct ip_hw_instance *ip_hw_instance, char *buf) 435 { 436 return sysfs_emit(buf, "%d\n", ip_hw_instance->minor); 437 } 438 439 static ssize_t revision_show(struct ip_hw_instance *ip_hw_instance, char *buf) 440 { 441 return sysfs_emit(buf, "%d\n", ip_hw_instance->revision); 442 } 443 444 static ssize_t harvest_show(struct ip_hw_instance *ip_hw_instance, char *buf) 445 { 446 return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest); 447 } 448 449 static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, char *buf) 450 { 451 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses); 452 } 453 454 static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf) 455 { 456 ssize_t res, at; 457 int ii; 458 459 for (res = at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) { 460 /* Here we satisfy the condition that, at + size <= PAGE_SIZE. 461 */ 462 if (at + 12 > PAGE_SIZE) 463 break; 464 res = sysfs_emit_at(buf, at, "0x%08X\n", 465 ip_hw_instance->base_addr[ii]); 466 if (res <= 0) 467 break; 468 at += res; 469 } 470 471 return res < 0 ? res : at; 472 } 473 474 static struct ip_hw_instance_attr ip_hw_attr[] = { 475 __ATTR_RO(hw_id), 476 __ATTR_RO(num_instance), 477 __ATTR_RO(major), 478 __ATTR_RO(minor), 479 __ATTR_RO(revision), 480 __ATTR_RO(harvest), 481 __ATTR_RO(num_base_addresses), 482 __ATTR_RO(base_addr), 483 }; 484 485 static struct attribute *ip_hw_instance_attrs[] = { 486 &ip_hw_attr[0].attr, 487 &ip_hw_attr[1].attr, 488 &ip_hw_attr[2].attr, 489 &ip_hw_attr[3].attr, 490 &ip_hw_attr[4].attr, 491 &ip_hw_attr[5].attr, 492 &ip_hw_attr[6].attr, 493 NULL, 494 }; 495 ATTRIBUTE_GROUPS(ip_hw_instance); 496 497 #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj) 498 #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr) 499 500 static ssize_t ip_hw_instance_attr_show(struct kobject *kobj, 501 struct attribute *attr, 502 char *buf) 503 { 504 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 505 struct ip_hw_instance_attr *ip_hw_attr = to_ip_hw_instance_attr(attr); 506 507 if (!ip_hw_attr->show) 508 return -EIO; 509 510 return ip_hw_attr->show(ip_hw_instance, buf); 511 } 512 513 static const struct sysfs_ops ip_hw_instance_sysfs_ops = { 514 .show = ip_hw_instance_attr_show, 515 }; 516 517 static void ip_hw_instance_release(struct kobject *kobj) 518 { 519 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 520 521 kfree(ip_hw_instance); 522 } 523 524 static struct kobj_type ip_hw_instance_ktype = { 525 .release = ip_hw_instance_release, 526 .sysfs_ops = &ip_hw_instance_sysfs_ops, 527 .default_groups = ip_hw_instance_groups, 528 }; 529 530 /* -------------------------------------------------- */ 531 532 #define to_ip_hw_id(x) container_of(to_kset(x), struct ip_hw_id, hw_id_kset) 533 534 static void ip_hw_id_release(struct kobject *kobj) 535 { 536 struct ip_hw_id *ip_hw_id = to_ip_hw_id(kobj); 537 538 if (!list_empty(&ip_hw_id->hw_id_kset.list)) 539 DRM_ERROR("ip_hw_id->hw_id_kset is not empty"); 540 kfree(ip_hw_id); 541 } 542 543 static struct kobj_type ip_hw_id_ktype = { 544 .release = ip_hw_id_release, 545 .sysfs_ops = &kobj_sysfs_ops, 546 }; 547 548 /* -------------------------------------------------- */ 549 550 static void die_kobj_release(struct kobject *kobj); 551 static void ip_disc_release(struct kobject *kobj); 552 553 struct ip_die_entry_attribute { 554 struct attribute attr; 555 ssize_t (*show)(struct ip_die_entry *ip_die_entry, char *buf); 556 }; 557 558 #define to_ip_die_entry_attr(x) container_of(x, struct ip_die_entry_attribute, attr) 559 560 static ssize_t num_ips_show(struct ip_die_entry *ip_die_entry, char *buf) 561 { 562 return sysfs_emit(buf, "%d\n", ip_die_entry->num_ips); 563 } 564 565 /* If there are more ip_die_entry attrs, other than the number of IPs, 566 * we can make this intro an array of attrs, and then initialize 567 * ip_die_entry_attrs in a loop. 568 */ 569 static struct ip_die_entry_attribute num_ips_attr = 570 __ATTR_RO(num_ips); 571 572 static struct attribute *ip_die_entry_attrs[] = { 573 &num_ips_attr.attr, 574 NULL, 575 }; 576 ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */ 577 578 #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset) 579 580 static ssize_t ip_die_entry_attr_show(struct kobject *kobj, 581 struct attribute *attr, 582 char *buf) 583 { 584 struct ip_die_entry_attribute *ip_die_entry_attr = to_ip_die_entry_attr(attr); 585 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 586 587 if (!ip_die_entry_attr->show) 588 return -EIO; 589 590 return ip_die_entry_attr->show(ip_die_entry, buf); 591 } 592 593 static void ip_die_entry_release(struct kobject *kobj) 594 { 595 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 596 597 if (!list_empty(&ip_die_entry->ip_kset.list)) 598 DRM_ERROR("ip_die_entry->ip_kset is not empty"); 599 kfree(ip_die_entry); 600 } 601 602 static const struct sysfs_ops ip_die_entry_sysfs_ops = { 603 .show = ip_die_entry_attr_show, 604 }; 605 606 static struct kobj_type ip_die_entry_ktype = { 607 .release = ip_die_entry_release, 608 .sysfs_ops = &ip_die_entry_sysfs_ops, 609 .default_groups = ip_die_entry_groups, 610 }; 611 612 static struct kobj_type die_kobj_ktype = { 613 .release = die_kobj_release, 614 .sysfs_ops = &kobj_sysfs_ops, 615 }; 616 617 static struct kobj_type ip_discovery_ktype = { 618 .release = ip_disc_release, 619 .sysfs_ops = &kobj_sysfs_ops, 620 }; 621 622 struct ip_discovery_top { 623 struct kobject kobj; /* ip_discovery/ */ 624 struct kset die_kset; /* ip_discovery/die/, contains ip_die_entry */ 625 struct amdgpu_device *adev; 626 }; 627 628 static void die_kobj_release(struct kobject *kobj) 629 { 630 struct ip_discovery_top *ip_top = container_of(to_kset(kobj), 631 struct ip_discovery_top, 632 die_kset); 633 if (!list_empty(&ip_top->die_kset.list)) 634 DRM_ERROR("ip_top->die_kset is not empty"); 635 } 636 637 static void ip_disc_release(struct kobject *kobj) 638 { 639 struct ip_discovery_top *ip_top = container_of(kobj, struct ip_discovery_top, 640 kobj); 641 struct amdgpu_device *adev = ip_top->adev; 642 643 adev->ip_top = NULL; 644 kfree(ip_top); 645 } 646 647 static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev, 648 struct ip_die_entry *ip_die_entry, 649 const size_t _ip_offset, const int num_ips) 650 { 651 int ii, jj, kk, res; 652 653 DRM_DEBUG("num_ips:%d", num_ips); 654 655 /* Find all IPs of a given HW ID, and add their instance to 656 * #die/#hw_id/#instance/<attributes> 657 */ 658 for (ii = 0; ii < HW_ID_MAX; ii++) { 659 struct ip_hw_id *ip_hw_id = NULL; 660 size_t ip_offset = _ip_offset; 661 662 for (jj = 0; jj < num_ips; jj++) { 663 struct ip *ip; 664 struct ip_hw_instance *ip_hw_instance; 665 666 ip = (struct ip *)(adev->mman.discovery_bin + ip_offset); 667 if (amdgpu_discovery_validate_ip(ip) || 668 le16_to_cpu(ip->hw_id) != ii) 669 goto next_ip; 670 671 DRM_DEBUG("match:%d @ ip_offset:%ld", ii, ip_offset); 672 673 /* We have a hw_id match; register the hw 674 * block if not yet registered. 675 */ 676 if (!ip_hw_id) { 677 ip_hw_id = kzalloc(sizeof(*ip_hw_id), GFP_KERNEL); 678 if (!ip_hw_id) 679 return -ENOMEM; 680 ip_hw_id->hw_id = ii; 681 682 kobject_set_name(&ip_hw_id->hw_id_kset.kobj, "%d", ii); 683 ip_hw_id->hw_id_kset.kobj.kset = &ip_die_entry->ip_kset; 684 ip_hw_id->hw_id_kset.kobj.ktype = &ip_hw_id_ktype; 685 res = kset_register(&ip_hw_id->hw_id_kset); 686 if (res) { 687 DRM_ERROR("Couldn't register ip_hw_id kset"); 688 kfree(ip_hw_id); 689 return res; 690 } 691 if (hw_id_names[ii]) { 692 res = sysfs_create_link(&ip_die_entry->ip_kset.kobj, 693 &ip_hw_id->hw_id_kset.kobj, 694 hw_id_names[ii]); 695 if (res) { 696 DRM_ERROR("Couldn't create IP link %s in IP Die:%s\n", 697 hw_id_names[ii], 698 kobject_name(&ip_die_entry->ip_kset.kobj)); 699 } 700 } 701 } 702 703 /* Now register its instance. 704 */ 705 ip_hw_instance = kzalloc(struct_size(ip_hw_instance, 706 base_addr, 707 ip->num_base_address), 708 GFP_KERNEL); 709 if (!ip_hw_instance) { 710 DRM_ERROR("no memory for ip_hw_instance"); 711 return -ENOMEM; 712 } 713 ip_hw_instance->hw_id = le16_to_cpu(ip->hw_id); /* == ii */ 714 ip_hw_instance->num_instance = ip->number_instance; 715 ip_hw_instance->major = ip->major; 716 ip_hw_instance->minor = ip->minor; 717 ip_hw_instance->revision = ip->revision; 718 ip_hw_instance->harvest = ip->harvest; 719 ip_hw_instance->num_base_addresses = ip->num_base_address; 720 721 for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++) 722 ip_hw_instance->base_addr[kk] = ip->base_address[kk]; 723 724 kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype); 725 ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset; 726 res = kobject_add(&ip_hw_instance->kobj, NULL, 727 "%d", ip_hw_instance->num_instance); 728 next_ip: 729 ip_offset += sizeof(*ip) + 4 * (ip->num_base_address - 1); 730 } 731 } 732 733 return 0; 734 } 735 736 static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev) 737 { 738 struct binary_header *bhdr; 739 struct ip_discovery_header *ihdr; 740 struct die_header *dhdr; 741 struct kset *die_kset = &adev->ip_top->die_kset; 742 u16 num_dies, die_offset, num_ips; 743 size_t ip_offset; 744 int ii, res; 745 746 bhdr = (struct binary_header *)adev->mman.discovery_bin; 747 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 748 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 749 num_dies = le16_to_cpu(ihdr->num_dies); 750 751 DRM_DEBUG("number of dies: %d\n", num_dies); 752 753 for (ii = 0; ii < num_dies; ii++) { 754 struct ip_die_entry *ip_die_entry; 755 756 die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset); 757 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 758 num_ips = le16_to_cpu(dhdr->num_ips); 759 ip_offset = die_offset + sizeof(*dhdr); 760 761 /* Add the die to the kset. 762 * 763 * dhdr->die_id == ii, which was checked in 764 * amdgpu_discovery_reg_base_init(). 765 */ 766 767 ip_die_entry = kzalloc(sizeof(*ip_die_entry), GFP_KERNEL); 768 if (!ip_die_entry) 769 return -ENOMEM; 770 771 ip_die_entry->num_ips = num_ips; 772 773 kobject_set_name(&ip_die_entry->ip_kset.kobj, "%d", le16_to_cpu(dhdr->die_id)); 774 ip_die_entry->ip_kset.kobj.kset = die_kset; 775 ip_die_entry->ip_kset.kobj.ktype = &ip_die_entry_ktype; 776 res = kset_register(&ip_die_entry->ip_kset); 777 if (res) { 778 DRM_ERROR("Couldn't register ip_die_entry kset"); 779 kfree(ip_die_entry); 780 return res; 781 } 782 783 amdgpu_discovery_sysfs_ips(adev, ip_die_entry, ip_offset, num_ips); 784 } 785 786 return 0; 787 } 788 789 static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev) 790 { 791 struct kset *die_kset; 792 int res; 793 794 adev->ip_top = kzalloc(sizeof(*adev->ip_top), GFP_KERNEL); 795 if (!adev->ip_top) 796 return -ENOMEM; 797 798 adev->ip_top->adev = adev; 799 800 res = kobject_init_and_add(&adev->ip_top->kobj, &ip_discovery_ktype, 801 &adev->dev->kobj, "ip_discovery"); 802 if (res) { 803 DRM_ERROR("Couldn't init and add ip_discovery/"); 804 goto Err; 805 } 806 807 die_kset = &adev->ip_top->die_kset; 808 kobject_set_name(&die_kset->kobj, "%s", "die"); 809 die_kset->kobj.parent = &adev->ip_top->kobj; 810 die_kset->kobj.ktype = &die_kobj_ktype; 811 res = kset_register(&adev->ip_top->die_kset); 812 if (res) { 813 DRM_ERROR("Couldn't register die_kset"); 814 goto Err; 815 } 816 817 res = amdgpu_discovery_sysfs_recurse(adev); 818 819 return res; 820 Err: 821 kobject_put(&adev->ip_top->kobj); 822 return res; 823 } 824 825 /* -------------------------------------------------- */ 826 827 #define list_to_kobj(el) container_of(el, struct kobject, entry) 828 829 static void amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id *ip_hw_id) 830 { 831 struct list_head *el, *tmp; 832 struct kset *hw_id_kset; 833 834 hw_id_kset = &ip_hw_id->hw_id_kset; 835 spin_lock(&hw_id_kset->list_lock); 836 list_for_each_prev_safe(el, tmp, &hw_id_kset->list) { 837 list_del_init(el); 838 spin_unlock(&hw_id_kset->list_lock); 839 /* kobject is embedded in ip_hw_instance */ 840 kobject_put(list_to_kobj(el)); 841 spin_lock(&hw_id_kset->list_lock); 842 } 843 spin_unlock(&hw_id_kset->list_lock); 844 kobject_put(&ip_hw_id->hw_id_kset.kobj); 845 } 846 847 static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry) 848 { 849 struct list_head *el, *tmp; 850 struct kset *ip_kset; 851 852 ip_kset = &ip_die_entry->ip_kset; 853 spin_lock(&ip_kset->list_lock); 854 list_for_each_prev_safe(el, tmp, &ip_kset->list) { 855 list_del_init(el); 856 spin_unlock(&ip_kset->list_lock); 857 amdgpu_discovery_sysfs_ip_hw_free(to_ip_hw_id(list_to_kobj(el))); 858 spin_lock(&ip_kset->list_lock); 859 } 860 spin_unlock(&ip_kset->list_lock); 861 kobject_put(&ip_die_entry->ip_kset.kobj); 862 } 863 864 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev) 865 { 866 struct list_head *el, *tmp; 867 struct kset *die_kset; 868 869 die_kset = &adev->ip_top->die_kset; 870 spin_lock(&die_kset->list_lock); 871 list_for_each_prev_safe(el, tmp, &die_kset->list) { 872 list_del_init(el); 873 spin_unlock(&die_kset->list_lock); 874 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el))); 875 spin_lock(&die_kset->list_lock); 876 } 877 spin_unlock(&die_kset->list_lock); 878 kobject_put(&adev->ip_top->die_kset.kobj); 879 kobject_put(&adev->ip_top->kobj); 880 } 881 882 /* ================================================== */ 883 884 int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) 885 { 886 struct binary_header *bhdr; 887 struct ip_discovery_header *ihdr; 888 struct die_header *dhdr; 889 struct ip *ip; 890 uint16_t die_offset; 891 uint16_t ip_offset; 892 uint16_t num_dies; 893 uint16_t num_ips; 894 uint8_t num_base_address; 895 int hw_ip; 896 int i, j, k; 897 int r; 898 899 r = amdgpu_discovery_init(adev); 900 if (r) { 901 DRM_ERROR("amdgpu_discovery_init failed\n"); 902 return r; 903 } 904 905 bhdr = (struct binary_header *)adev->mman.discovery_bin; 906 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 907 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 908 num_dies = le16_to_cpu(ihdr->num_dies); 909 910 DRM_DEBUG("number of dies: %d\n", num_dies); 911 912 for (i = 0; i < num_dies; i++) { 913 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 914 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 915 num_ips = le16_to_cpu(dhdr->num_ips); 916 ip_offset = die_offset + sizeof(*dhdr); 917 918 if (le16_to_cpu(dhdr->die_id) != i) { 919 DRM_ERROR("invalid die id %d, expected %d\n", 920 le16_to_cpu(dhdr->die_id), i); 921 return -EINVAL; 922 } 923 924 DRM_DEBUG("number of hardware IPs on die%d: %d\n", 925 le16_to_cpu(dhdr->die_id), num_ips); 926 927 for (j = 0; j < num_ips; j++) { 928 ip = (struct ip *)(adev->mman.discovery_bin + ip_offset); 929 930 if (amdgpu_discovery_validate_ip(ip)) 931 goto next_ip; 932 933 num_base_address = ip->num_base_address; 934 935 DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n", 936 hw_id_names[le16_to_cpu(ip->hw_id)], 937 le16_to_cpu(ip->hw_id), 938 ip->number_instance, 939 ip->major, ip->minor, 940 ip->revision); 941 942 if (le16_to_cpu(ip->hw_id) == VCN_HWID) { 943 /* Bit [5:0]: original revision value 944 * Bit [7:6]: en/decode capability: 945 * 0b00 : VCN function normally 946 * 0b10 : encode is disabled 947 * 0b01 : decode is disabled 948 */ 949 adev->vcn.vcn_config[adev->vcn.num_vcn_inst] = 950 ip->revision & 0xc0; 951 ip->revision &= ~0xc0; 952 adev->vcn.num_vcn_inst++; 953 } 954 if (le16_to_cpu(ip->hw_id) == SDMA0_HWID || 955 le16_to_cpu(ip->hw_id) == SDMA1_HWID || 956 le16_to_cpu(ip->hw_id) == SDMA2_HWID || 957 le16_to_cpu(ip->hw_id) == SDMA3_HWID) 958 adev->sdma.num_instances++; 959 960 for (k = 0; k < num_base_address; k++) { 961 /* 962 * convert the endianness of base addresses in place, 963 * so that we don't need to convert them when accessing adev->reg_offset. 964 */ 965 ip->base_address[k] = le32_to_cpu(ip->base_address[k]); 966 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]); 967 } 968 969 for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) { 970 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id)) { 971 DRM_DEBUG("set register base offset for %s\n", 972 hw_id_names[le16_to_cpu(ip->hw_id)]); 973 adev->reg_offset[hw_ip][ip->number_instance] = 974 ip->base_address; 975 /* Instance support is somewhat inconsistent. 976 * SDMA is a good example. Sienna cichlid has 4 total 977 * SDMA instances, each enumerated separately (HWIDs 978 * 42, 43, 68, 69). Arcturus has 8 total SDMA instances, 979 * but they are enumerated as multiple instances of the 980 * same HWIDs (4x HWID 42, 4x HWID 43). UMC is another 981 * example. On most chips there are multiple instances 982 * with the same HWID. 983 */ 984 adev->ip_versions[hw_ip][ip->number_instance] = 985 IP_VERSION(ip->major, ip->minor, ip->revision); 986 } 987 } 988 989 next_ip: 990 ip_offset += sizeof(*ip) + 4 * (ip->num_base_address - 1); 991 } 992 } 993 994 amdgpu_discovery_sysfs_init(adev); 995 996 return 0; 997 } 998 999 int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, int number_instance, 1000 int *major, int *minor, int *revision) 1001 { 1002 struct binary_header *bhdr; 1003 struct ip_discovery_header *ihdr; 1004 struct die_header *dhdr; 1005 struct ip *ip; 1006 uint16_t die_offset; 1007 uint16_t ip_offset; 1008 uint16_t num_dies; 1009 uint16_t num_ips; 1010 int i, j; 1011 1012 if (!adev->mman.discovery_bin) { 1013 DRM_ERROR("ip discovery uninitialized\n"); 1014 return -EINVAL; 1015 } 1016 1017 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1018 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 1019 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 1020 num_dies = le16_to_cpu(ihdr->num_dies); 1021 1022 for (i = 0; i < num_dies; i++) { 1023 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 1024 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 1025 num_ips = le16_to_cpu(dhdr->num_ips); 1026 ip_offset = die_offset + sizeof(*dhdr); 1027 1028 for (j = 0; j < num_ips; j++) { 1029 ip = (struct ip *)(adev->mman.discovery_bin + ip_offset); 1030 1031 if ((le16_to_cpu(ip->hw_id) == hw_id) && (ip->number_instance == number_instance)) { 1032 if (major) 1033 *major = ip->major; 1034 if (minor) 1035 *minor = ip->minor; 1036 if (revision) 1037 *revision = ip->revision; 1038 return 0; 1039 } 1040 ip_offset += sizeof(*ip) + 4 * (ip->num_base_address - 1); 1041 } 1042 } 1043 1044 return -EINVAL; 1045 } 1046 1047 void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev) 1048 { 1049 struct binary_header *bhdr; 1050 struct harvest_table *harvest_info; 1051 int i, vcn_harvest_count = 0; 1052 1053 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1054 harvest_info = (struct harvest_table *)(adev->mman.discovery_bin + 1055 le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset)); 1056 1057 for (i = 0; i < 32; i++) { 1058 if (le16_to_cpu(harvest_info->list[i].hw_id) == 0) 1059 break; 1060 1061 switch (le16_to_cpu(harvest_info->list[i].hw_id)) { 1062 case VCN_HWID: 1063 vcn_harvest_count++; 1064 if (harvest_info->list[i].number_instance == 0) 1065 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0; 1066 else 1067 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 1068 break; 1069 case DMU_HWID: 1070 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 1071 break; 1072 default: 1073 break; 1074 } 1075 } 1076 1077 amdgpu_discovery_harvest_config_quirk(adev); 1078 1079 if (vcn_harvest_count == adev->vcn.num_vcn_inst) { 1080 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK; 1081 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK; 1082 } 1083 if ((adev->pdev->device == 0x731E && 1084 (adev->pdev->revision == 0xC6 || adev->pdev->revision == 0xC7)) || 1085 (adev->pdev->device == 0x7340 && adev->pdev->revision == 0xC9) || 1086 (adev->pdev->device == 0x7360 && adev->pdev->revision == 0xC7)) { 1087 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK; 1088 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK; 1089 } 1090 } 1091 1092 union gc_info { 1093 struct gc_info_v1_0 v1; 1094 struct gc_info_v2_0 v2; 1095 }; 1096 1097 int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) 1098 { 1099 struct binary_header *bhdr; 1100 union gc_info *gc_info; 1101 1102 if (!adev->mman.discovery_bin) { 1103 DRM_ERROR("ip discovery uninitialized\n"); 1104 return -EINVAL; 1105 } 1106 1107 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1108 gc_info = (union gc_info *)(adev->mman.discovery_bin + 1109 le16_to_cpu(bhdr->table_list[GC].offset)); 1110 switch (gc_info->v1.header.version_major) { 1111 case 1: 1112 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se); 1113 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) + 1114 le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa)); 1115 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1116 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se); 1117 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c); 1118 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs); 1119 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds); 1120 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth); 1121 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth); 1122 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer); 1123 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size); 1124 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd); 1125 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu); 1126 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size); 1127 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) / 1128 le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1129 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc); 1130 break; 1131 case 2: 1132 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se); 1133 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh); 1134 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1135 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se); 1136 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs); 1137 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs); 1138 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds); 1139 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth); 1140 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth); 1141 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer); 1142 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size); 1143 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd); 1144 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu); 1145 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size); 1146 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) / 1147 le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1148 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc); 1149 break; 1150 default: 1151 dev_err(adev->dev, 1152 "Unhandled GC info table %d.%d\n", 1153 gc_info->v1.header.version_major, 1154 gc_info->v1.header.version_minor); 1155 return -EINVAL; 1156 } 1157 return 0; 1158 } 1159 1160 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev) 1161 { 1162 /* what IP to use for this? */ 1163 switch (adev->ip_versions[GC_HWIP][0]) { 1164 case IP_VERSION(9, 0, 1): 1165 case IP_VERSION(9, 1, 0): 1166 case IP_VERSION(9, 2, 1): 1167 case IP_VERSION(9, 2, 2): 1168 case IP_VERSION(9, 3, 0): 1169 case IP_VERSION(9, 4, 0): 1170 case IP_VERSION(9, 4, 1): 1171 case IP_VERSION(9, 4, 2): 1172 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 1173 break; 1174 case IP_VERSION(10, 1, 10): 1175 case IP_VERSION(10, 1, 1): 1176 case IP_VERSION(10, 1, 2): 1177 case IP_VERSION(10, 1, 3): 1178 case IP_VERSION(10, 1, 4): 1179 case IP_VERSION(10, 3, 0): 1180 case IP_VERSION(10, 3, 1): 1181 case IP_VERSION(10, 3, 2): 1182 case IP_VERSION(10, 3, 3): 1183 case IP_VERSION(10, 3, 4): 1184 case IP_VERSION(10, 3, 5): 1185 case IP_VERSION(10, 3, 7): 1186 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 1187 break; 1188 default: 1189 dev_err(adev->dev, 1190 "Failed to add common ip block(GC_HWIP:0x%x)\n", 1191 adev->ip_versions[GC_HWIP][0]); 1192 return -EINVAL; 1193 } 1194 return 0; 1195 } 1196 1197 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev) 1198 { 1199 /* use GC or MMHUB IP version */ 1200 switch (adev->ip_versions[GC_HWIP][0]) { 1201 case IP_VERSION(9, 0, 1): 1202 case IP_VERSION(9, 1, 0): 1203 case IP_VERSION(9, 2, 1): 1204 case IP_VERSION(9, 2, 2): 1205 case IP_VERSION(9, 3, 0): 1206 case IP_VERSION(9, 4, 0): 1207 case IP_VERSION(9, 4, 1): 1208 case IP_VERSION(9, 4, 2): 1209 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 1210 break; 1211 case IP_VERSION(10, 1, 10): 1212 case IP_VERSION(10, 1, 1): 1213 case IP_VERSION(10, 1, 2): 1214 case IP_VERSION(10, 1, 3): 1215 case IP_VERSION(10, 1, 4): 1216 case IP_VERSION(10, 3, 0): 1217 case IP_VERSION(10, 3, 1): 1218 case IP_VERSION(10, 3, 2): 1219 case IP_VERSION(10, 3, 3): 1220 case IP_VERSION(10, 3, 4): 1221 case IP_VERSION(10, 3, 5): 1222 case IP_VERSION(10, 3, 7): 1223 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 1224 break; 1225 default: 1226 dev_err(adev->dev, 1227 "Failed to add gmc ip block(GC_HWIP:0x%x)\n", 1228 adev->ip_versions[GC_HWIP][0]); 1229 return -EINVAL; 1230 } 1231 return 0; 1232 } 1233 1234 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev) 1235 { 1236 switch (adev->ip_versions[OSSSYS_HWIP][0]) { 1237 case IP_VERSION(4, 0, 0): 1238 case IP_VERSION(4, 0, 1): 1239 case IP_VERSION(4, 1, 0): 1240 case IP_VERSION(4, 1, 1): 1241 case IP_VERSION(4, 3, 0): 1242 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 1243 break; 1244 case IP_VERSION(4, 2, 0): 1245 case IP_VERSION(4, 2, 1): 1246 case IP_VERSION(4, 4, 0): 1247 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 1248 break; 1249 case IP_VERSION(5, 0, 0): 1250 case IP_VERSION(5, 0, 1): 1251 case IP_VERSION(5, 0, 2): 1252 case IP_VERSION(5, 0, 3): 1253 case IP_VERSION(5, 2, 0): 1254 case IP_VERSION(5, 2, 1): 1255 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 1256 break; 1257 default: 1258 dev_err(adev->dev, 1259 "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n", 1260 adev->ip_versions[OSSSYS_HWIP][0]); 1261 return -EINVAL; 1262 } 1263 return 0; 1264 } 1265 1266 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev) 1267 { 1268 switch (adev->ip_versions[MP0_HWIP][0]) { 1269 case IP_VERSION(9, 0, 0): 1270 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 1271 break; 1272 case IP_VERSION(10, 0, 0): 1273 case IP_VERSION(10, 0, 1): 1274 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); 1275 break; 1276 case IP_VERSION(11, 0, 0): 1277 case IP_VERSION(11, 0, 2): 1278 case IP_VERSION(11, 0, 4): 1279 case IP_VERSION(11, 0, 5): 1280 case IP_VERSION(11, 0, 9): 1281 case IP_VERSION(11, 0, 7): 1282 case IP_VERSION(11, 0, 11): 1283 case IP_VERSION(11, 0, 12): 1284 case IP_VERSION(11, 0, 13): 1285 case IP_VERSION(11, 5, 0): 1286 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 1287 break; 1288 case IP_VERSION(11, 0, 8): 1289 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block); 1290 break; 1291 case IP_VERSION(11, 0, 3): 1292 case IP_VERSION(12, 0, 1): 1293 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); 1294 break; 1295 case IP_VERSION(13, 0, 1): 1296 case IP_VERSION(13, 0, 2): 1297 case IP_VERSION(13, 0, 3): 1298 case IP_VERSION(13, 0, 8): 1299 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); 1300 break; 1301 default: 1302 dev_err(adev->dev, 1303 "Failed to add psp ip block(MP0_HWIP:0x%x)\n", 1304 adev->ip_versions[MP0_HWIP][0]); 1305 return -EINVAL; 1306 } 1307 return 0; 1308 } 1309 1310 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev) 1311 { 1312 switch (adev->ip_versions[MP1_HWIP][0]) { 1313 case IP_VERSION(9, 0, 0): 1314 case IP_VERSION(10, 0, 0): 1315 case IP_VERSION(10, 0, 1): 1316 case IP_VERSION(11, 0, 2): 1317 if (adev->asic_type == CHIP_ARCTURUS) 1318 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 1319 else 1320 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 1321 break; 1322 case IP_VERSION(11, 0, 0): 1323 case IP_VERSION(11, 0, 5): 1324 case IP_VERSION(11, 0, 9): 1325 case IP_VERSION(11, 0, 7): 1326 case IP_VERSION(11, 0, 8): 1327 case IP_VERSION(11, 0, 11): 1328 case IP_VERSION(11, 0, 12): 1329 case IP_VERSION(11, 0, 13): 1330 case IP_VERSION(11, 5, 0): 1331 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 1332 break; 1333 case IP_VERSION(12, 0, 0): 1334 case IP_VERSION(12, 0, 1): 1335 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); 1336 break; 1337 case IP_VERSION(13, 0, 1): 1338 case IP_VERSION(13, 0, 2): 1339 case IP_VERSION(13, 0, 3): 1340 case IP_VERSION(13, 0, 8): 1341 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); 1342 break; 1343 default: 1344 dev_err(adev->dev, 1345 "Failed to add smu ip block(MP1_HWIP:0x%x)\n", 1346 adev->ip_versions[MP1_HWIP][0]); 1347 return -EINVAL; 1348 } 1349 return 0; 1350 } 1351 1352 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev) 1353 { 1354 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) { 1355 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 1356 return 0; 1357 } 1358 1359 if (!amdgpu_device_has_dc_support(adev)) 1360 return 0; 1361 1362 #if defined(CONFIG_DRM_AMD_DC) 1363 if (adev->ip_versions[DCE_HWIP][0]) { 1364 switch (adev->ip_versions[DCE_HWIP][0]) { 1365 case IP_VERSION(1, 0, 0): 1366 case IP_VERSION(1, 0, 1): 1367 case IP_VERSION(2, 0, 2): 1368 case IP_VERSION(2, 0, 0): 1369 case IP_VERSION(2, 0, 3): 1370 case IP_VERSION(2, 1, 0): 1371 case IP_VERSION(3, 0, 0): 1372 case IP_VERSION(3, 0, 2): 1373 case IP_VERSION(3, 0, 3): 1374 case IP_VERSION(3, 0, 1): 1375 case IP_VERSION(3, 1, 2): 1376 case IP_VERSION(3, 1, 3): 1377 amdgpu_device_ip_block_add(adev, &dm_ip_block); 1378 break; 1379 default: 1380 dev_err(adev->dev, 1381 "Failed to add dm ip block(DCE_HWIP:0x%x)\n", 1382 adev->ip_versions[DCE_HWIP][0]); 1383 return -EINVAL; 1384 } 1385 } else if (adev->ip_versions[DCI_HWIP][0]) { 1386 switch (adev->ip_versions[DCI_HWIP][0]) { 1387 case IP_VERSION(12, 0, 0): 1388 case IP_VERSION(12, 0, 1): 1389 case IP_VERSION(12, 1, 0): 1390 amdgpu_device_ip_block_add(adev, &dm_ip_block); 1391 break; 1392 default: 1393 dev_err(adev->dev, 1394 "Failed to add dm ip block(DCI_HWIP:0x%x)\n", 1395 adev->ip_versions[DCI_HWIP][0]); 1396 return -EINVAL; 1397 } 1398 } 1399 #endif 1400 return 0; 1401 } 1402 1403 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) 1404 { 1405 switch (adev->ip_versions[GC_HWIP][0]) { 1406 case IP_VERSION(9, 0, 1): 1407 case IP_VERSION(9, 1, 0): 1408 case IP_VERSION(9, 2, 1): 1409 case IP_VERSION(9, 2, 2): 1410 case IP_VERSION(9, 3, 0): 1411 case IP_VERSION(9, 4, 0): 1412 case IP_VERSION(9, 4, 1): 1413 case IP_VERSION(9, 4, 2): 1414 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 1415 break; 1416 case IP_VERSION(10, 1, 10): 1417 case IP_VERSION(10, 1, 2): 1418 case IP_VERSION(10, 1, 1): 1419 case IP_VERSION(10, 1, 3): 1420 case IP_VERSION(10, 1, 4): 1421 case IP_VERSION(10, 3, 0): 1422 case IP_VERSION(10, 3, 2): 1423 case IP_VERSION(10, 3, 1): 1424 case IP_VERSION(10, 3, 4): 1425 case IP_VERSION(10, 3, 5): 1426 case IP_VERSION(10, 3, 3): 1427 case IP_VERSION(10, 3, 7): 1428 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 1429 break; 1430 default: 1431 dev_err(adev->dev, 1432 "Failed to add gfx ip block(GC_HWIP:0x%x)\n", 1433 adev->ip_versions[GC_HWIP][0]); 1434 return -EINVAL; 1435 } 1436 return 0; 1437 } 1438 1439 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev) 1440 { 1441 switch (adev->ip_versions[SDMA0_HWIP][0]) { 1442 case IP_VERSION(4, 0, 0): 1443 case IP_VERSION(4, 0, 1): 1444 case IP_VERSION(4, 1, 0): 1445 case IP_VERSION(4, 1, 1): 1446 case IP_VERSION(4, 1, 2): 1447 case IP_VERSION(4, 2, 0): 1448 case IP_VERSION(4, 2, 2): 1449 case IP_VERSION(4, 4, 0): 1450 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 1451 break; 1452 case IP_VERSION(5, 0, 0): 1453 case IP_VERSION(5, 0, 1): 1454 case IP_VERSION(5, 0, 2): 1455 case IP_VERSION(5, 0, 5): 1456 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 1457 break; 1458 case IP_VERSION(5, 2, 0): 1459 case IP_VERSION(5, 2, 2): 1460 case IP_VERSION(5, 2, 4): 1461 case IP_VERSION(5, 2, 5): 1462 case IP_VERSION(5, 2, 3): 1463 case IP_VERSION(5, 2, 1): 1464 case IP_VERSION(5, 2, 7): 1465 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 1466 break; 1467 default: 1468 dev_err(adev->dev, 1469 "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n", 1470 adev->ip_versions[SDMA0_HWIP][0]); 1471 return -EINVAL; 1472 } 1473 return 0; 1474 } 1475 1476 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) 1477 { 1478 if (adev->ip_versions[VCE_HWIP][0]) { 1479 switch (adev->ip_versions[UVD_HWIP][0]) { 1480 case IP_VERSION(7, 0, 0): 1481 case IP_VERSION(7, 2, 0): 1482 /* UVD is not supported on vega20 SR-IOV */ 1483 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 1484 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); 1485 break; 1486 default: 1487 dev_err(adev->dev, 1488 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n", 1489 adev->ip_versions[UVD_HWIP][0]); 1490 return -EINVAL; 1491 } 1492 switch (adev->ip_versions[VCE_HWIP][0]) { 1493 case IP_VERSION(4, 0, 0): 1494 case IP_VERSION(4, 1, 0): 1495 /* VCE is not supported on vega20 SR-IOV */ 1496 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 1497 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); 1498 break; 1499 default: 1500 dev_err(adev->dev, 1501 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n", 1502 adev->ip_versions[VCE_HWIP][0]); 1503 return -EINVAL; 1504 } 1505 } else { 1506 switch (adev->ip_versions[UVD_HWIP][0]) { 1507 case IP_VERSION(1, 0, 0): 1508 case IP_VERSION(1, 0, 1): 1509 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); 1510 break; 1511 case IP_VERSION(2, 0, 0): 1512 case IP_VERSION(2, 0, 2): 1513 case IP_VERSION(2, 2, 0): 1514 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 1515 if (!amdgpu_sriov_vf(adev)) 1516 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 1517 break; 1518 case IP_VERSION(2, 0, 3): 1519 break; 1520 case IP_VERSION(2, 5, 0): 1521 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 1522 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block); 1523 break; 1524 case IP_VERSION(2, 6, 0): 1525 amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block); 1526 amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block); 1527 break; 1528 case IP_VERSION(3, 0, 0): 1529 case IP_VERSION(3, 0, 16): 1530 case IP_VERSION(3, 1, 1): 1531 case IP_VERSION(3, 0, 2): 1532 case IP_VERSION(3, 0, 192): 1533 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 1534 if (!amdgpu_sriov_vf(adev)) 1535 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 1536 break; 1537 case IP_VERSION(3, 0, 33): 1538 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 1539 break; 1540 default: 1541 dev_err(adev->dev, 1542 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n", 1543 adev->ip_versions[UVD_HWIP][0]); 1544 return -EINVAL; 1545 } 1546 } 1547 return 0; 1548 } 1549 1550 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev) 1551 { 1552 switch (adev->ip_versions[GC_HWIP][0]) { 1553 case IP_VERSION(10, 1, 10): 1554 case IP_VERSION(10, 1, 1): 1555 case IP_VERSION(10, 1, 2): 1556 case IP_VERSION(10, 1, 3): 1557 case IP_VERSION(10, 1, 4): 1558 case IP_VERSION(10, 3, 0): 1559 case IP_VERSION(10, 3, 1): 1560 case IP_VERSION(10, 3, 2): 1561 case IP_VERSION(10, 3, 3): 1562 case IP_VERSION(10, 3, 4): 1563 case IP_VERSION(10, 3, 5): 1564 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 1565 break; 1566 default: 1567 break; 1568 } 1569 return 0; 1570 } 1571 1572 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 1573 { 1574 int r; 1575 1576 switch (adev->asic_type) { 1577 case CHIP_VEGA10: 1578 vega10_reg_base_init(adev); 1579 adev->sdma.num_instances = 2; 1580 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0); 1581 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0); 1582 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0); 1583 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0); 1584 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0); 1585 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0); 1586 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 1587 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0); 1588 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0); 1589 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 1590 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 1591 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 1592 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0); 1593 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1); 1594 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 1595 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 1596 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0); 1597 break; 1598 case CHIP_VEGA12: 1599 vega10_reg_base_init(adev); 1600 adev->sdma.num_instances = 2; 1601 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0); 1602 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0); 1603 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1); 1604 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1); 1605 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1); 1606 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1); 1607 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0); 1608 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0); 1609 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0); 1610 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 1611 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 1612 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 1613 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1); 1614 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1); 1615 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 1616 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 1617 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1); 1618 break; 1619 case CHIP_RAVEN: 1620 vega10_reg_base_init(adev); 1621 adev->sdma.num_instances = 1; 1622 adev->vcn.num_vcn_inst = 1; 1623 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { 1624 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0); 1625 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0); 1626 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1); 1627 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1); 1628 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1); 1629 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1); 1630 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1); 1631 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0); 1632 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1); 1633 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1); 1634 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0); 1635 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1); 1636 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2); 1637 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1); 1638 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1); 1639 } else { 1640 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0); 1641 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0); 1642 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0); 1643 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0); 1644 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0); 1645 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 1646 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0); 1647 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0); 1648 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0); 1649 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0); 1650 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0); 1651 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0); 1652 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0); 1653 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0); 1654 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0); 1655 } 1656 break; 1657 case CHIP_VEGA20: 1658 vega20_reg_base_init(adev); 1659 adev->sdma.num_instances = 2; 1660 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0); 1661 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0); 1662 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0); 1663 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0); 1664 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0); 1665 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0); 1666 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0); 1667 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0); 1668 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1); 1669 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2); 1670 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 1671 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2); 1672 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2); 1673 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0); 1674 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0); 1675 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0); 1676 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0); 1677 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0); 1678 break; 1679 case CHIP_ARCTURUS: 1680 arct_reg_base_init(adev); 1681 adev->sdma.num_instances = 8; 1682 adev->vcn.num_vcn_inst = 2; 1683 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1); 1684 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1); 1685 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1); 1686 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1); 1687 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2); 1688 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2); 1689 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2); 1690 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2); 1691 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2); 1692 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2); 1693 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2); 1694 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2); 1695 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1); 1696 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1); 1697 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2); 1698 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4); 1699 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 1700 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3); 1701 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3); 1702 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1); 1703 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0); 1704 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0); 1705 break; 1706 case CHIP_ALDEBARAN: 1707 aldebaran_reg_base_init(adev); 1708 adev->sdma.num_instances = 5; 1709 adev->vcn.num_vcn_inst = 2; 1710 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2); 1711 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2); 1712 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0); 1713 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0); 1714 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0); 1715 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0); 1716 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0); 1717 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0); 1718 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0); 1719 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2); 1720 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4); 1721 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0); 1722 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2); 1723 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2); 1724 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2); 1725 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2); 1726 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2); 1727 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0); 1728 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0); 1729 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0); 1730 break; 1731 default: 1732 r = amdgpu_discovery_reg_base_init(adev); 1733 if (r) 1734 return -EINVAL; 1735 1736 amdgpu_discovery_harvest_ip(adev); 1737 break; 1738 } 1739 1740 switch (adev->ip_versions[GC_HWIP][0]) { 1741 case IP_VERSION(9, 0, 1): 1742 case IP_VERSION(9, 2, 1): 1743 case IP_VERSION(9, 4, 0): 1744 case IP_VERSION(9, 4, 1): 1745 case IP_VERSION(9, 4, 2): 1746 adev->family = AMDGPU_FAMILY_AI; 1747 break; 1748 case IP_VERSION(9, 1, 0): 1749 case IP_VERSION(9, 2, 2): 1750 case IP_VERSION(9, 3, 0): 1751 adev->family = AMDGPU_FAMILY_RV; 1752 break; 1753 case IP_VERSION(10, 1, 10): 1754 case IP_VERSION(10, 1, 1): 1755 case IP_VERSION(10, 1, 2): 1756 case IP_VERSION(10, 1, 3): 1757 case IP_VERSION(10, 1, 4): 1758 case IP_VERSION(10, 3, 0): 1759 case IP_VERSION(10, 3, 2): 1760 case IP_VERSION(10, 3, 4): 1761 case IP_VERSION(10, 3, 5): 1762 adev->family = AMDGPU_FAMILY_NV; 1763 break; 1764 case IP_VERSION(10, 3, 1): 1765 adev->family = AMDGPU_FAMILY_VGH; 1766 break; 1767 case IP_VERSION(10, 3, 3): 1768 adev->family = AMDGPU_FAMILY_YC; 1769 break; 1770 case IP_VERSION(10, 3, 7): 1771 adev->family = AMDGPU_FAMILY_GC_10_3_7; 1772 break; 1773 default: 1774 return -EINVAL; 1775 } 1776 1777 switch (adev->ip_versions[GC_HWIP][0]) { 1778 case IP_VERSION(9, 1, 0): 1779 case IP_VERSION(9, 2, 2): 1780 case IP_VERSION(9, 3, 0): 1781 case IP_VERSION(10, 1, 3): 1782 case IP_VERSION(10, 1, 4): 1783 case IP_VERSION(10, 3, 1): 1784 case IP_VERSION(10, 3, 3): 1785 case IP_VERSION(10, 3, 7): 1786 adev->flags |= AMD_IS_APU; 1787 break; 1788 default: 1789 break; 1790 } 1791 1792 if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(4, 8, 0)) 1793 adev->gmc.xgmi.supported = true; 1794 1795 /* set NBIO version */ 1796 switch (adev->ip_versions[NBIO_HWIP][0]) { 1797 case IP_VERSION(6, 1, 0): 1798 case IP_VERSION(6, 2, 0): 1799 adev->nbio.funcs = &nbio_v6_1_funcs; 1800 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; 1801 break; 1802 case IP_VERSION(7, 0, 0): 1803 case IP_VERSION(7, 0, 1): 1804 case IP_VERSION(2, 5, 0): 1805 adev->nbio.funcs = &nbio_v7_0_funcs; 1806 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; 1807 break; 1808 case IP_VERSION(7, 4, 0): 1809 case IP_VERSION(7, 4, 1): 1810 adev->nbio.funcs = &nbio_v7_4_funcs; 1811 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; 1812 break; 1813 case IP_VERSION(7, 4, 4): 1814 adev->nbio.funcs = &nbio_v7_4_funcs; 1815 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg_ald; 1816 break; 1817 case IP_VERSION(7, 2, 0): 1818 case IP_VERSION(7, 2, 1): 1819 case IP_VERSION(7, 5, 0): 1820 case IP_VERSION(7, 5, 1): 1821 adev->nbio.funcs = &nbio_v7_2_funcs; 1822 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; 1823 break; 1824 case IP_VERSION(2, 1, 1): 1825 case IP_VERSION(2, 3, 0): 1826 case IP_VERSION(2, 3, 1): 1827 case IP_VERSION(2, 3, 2): 1828 adev->nbio.funcs = &nbio_v2_3_funcs; 1829 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 1830 break; 1831 case IP_VERSION(3, 3, 0): 1832 case IP_VERSION(3, 3, 1): 1833 case IP_VERSION(3, 3, 2): 1834 case IP_VERSION(3, 3, 3): 1835 adev->nbio.funcs = &nbio_v2_3_funcs; 1836 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg_sc; 1837 break; 1838 default: 1839 break; 1840 } 1841 1842 switch (adev->ip_versions[HDP_HWIP][0]) { 1843 case IP_VERSION(4, 0, 0): 1844 case IP_VERSION(4, 0, 1): 1845 case IP_VERSION(4, 1, 0): 1846 case IP_VERSION(4, 1, 1): 1847 case IP_VERSION(4, 1, 2): 1848 case IP_VERSION(4, 2, 0): 1849 case IP_VERSION(4, 2, 1): 1850 case IP_VERSION(4, 4, 0): 1851 adev->hdp.funcs = &hdp_v4_0_funcs; 1852 break; 1853 case IP_VERSION(5, 0, 0): 1854 case IP_VERSION(5, 0, 1): 1855 case IP_VERSION(5, 0, 2): 1856 case IP_VERSION(5, 0, 3): 1857 case IP_VERSION(5, 0, 4): 1858 case IP_VERSION(5, 2, 0): 1859 adev->hdp.funcs = &hdp_v5_0_funcs; 1860 break; 1861 default: 1862 break; 1863 } 1864 1865 switch (adev->ip_versions[DF_HWIP][0]) { 1866 case IP_VERSION(3, 6, 0): 1867 case IP_VERSION(3, 6, 1): 1868 case IP_VERSION(3, 6, 2): 1869 adev->df.funcs = &df_v3_6_funcs; 1870 break; 1871 case IP_VERSION(2, 1, 0): 1872 case IP_VERSION(2, 1, 1): 1873 case IP_VERSION(2, 5, 0): 1874 case IP_VERSION(3, 5, 1): 1875 case IP_VERSION(3, 5, 2): 1876 adev->df.funcs = &df_v1_7_funcs; 1877 break; 1878 default: 1879 break; 1880 } 1881 1882 switch (adev->ip_versions[SMUIO_HWIP][0]) { 1883 case IP_VERSION(9, 0, 0): 1884 case IP_VERSION(9, 0, 1): 1885 case IP_VERSION(10, 0, 0): 1886 case IP_VERSION(10, 0, 1): 1887 case IP_VERSION(10, 0, 2): 1888 adev->smuio.funcs = &smuio_v9_0_funcs; 1889 break; 1890 case IP_VERSION(11, 0, 0): 1891 case IP_VERSION(11, 0, 2): 1892 case IP_VERSION(11, 0, 3): 1893 case IP_VERSION(11, 0, 4): 1894 case IP_VERSION(11, 0, 7): 1895 case IP_VERSION(11, 0, 8): 1896 adev->smuio.funcs = &smuio_v11_0_funcs; 1897 break; 1898 case IP_VERSION(11, 0, 6): 1899 case IP_VERSION(11, 0, 10): 1900 case IP_VERSION(11, 0, 11): 1901 case IP_VERSION(11, 5, 0): 1902 case IP_VERSION(13, 0, 1): 1903 case IP_VERSION(13, 0, 9): 1904 adev->smuio.funcs = &smuio_v11_0_6_funcs; 1905 break; 1906 case IP_VERSION(13, 0, 2): 1907 adev->smuio.funcs = &smuio_v13_0_funcs; 1908 break; 1909 default: 1910 break; 1911 } 1912 1913 r = amdgpu_discovery_set_common_ip_blocks(adev); 1914 if (r) 1915 return r; 1916 1917 r = amdgpu_discovery_set_gmc_ip_blocks(adev); 1918 if (r) 1919 return r; 1920 1921 /* For SR-IOV, PSP needs to be initialized before IH */ 1922 if (amdgpu_sriov_vf(adev)) { 1923 r = amdgpu_discovery_set_psp_ip_blocks(adev); 1924 if (r) 1925 return r; 1926 r = amdgpu_discovery_set_ih_ip_blocks(adev); 1927 if (r) 1928 return r; 1929 } else { 1930 r = amdgpu_discovery_set_ih_ip_blocks(adev); 1931 if (r) 1932 return r; 1933 1934 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 1935 r = amdgpu_discovery_set_psp_ip_blocks(adev); 1936 if (r) 1937 return r; 1938 } 1939 } 1940 1941 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 1942 r = amdgpu_discovery_set_smu_ip_blocks(adev); 1943 if (r) 1944 return r; 1945 } 1946 1947 r = amdgpu_discovery_set_display_ip_blocks(adev); 1948 if (r) 1949 return r; 1950 1951 r = amdgpu_discovery_set_gc_ip_blocks(adev); 1952 if (r) 1953 return r; 1954 1955 r = amdgpu_discovery_set_sdma_ip_blocks(adev); 1956 if (r) 1957 return r; 1958 1959 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 1960 !amdgpu_sriov_vf(adev)) { 1961 r = amdgpu_discovery_set_smu_ip_blocks(adev); 1962 if (r) 1963 return r; 1964 } 1965 1966 r = amdgpu_discovery_set_mm_ip_blocks(adev); 1967 if (r) 1968 return r; 1969 1970 if (adev->enable_mes) { 1971 r = amdgpu_discovery_set_mes_ip_blocks(adev); 1972 if (r) 1973 return r; 1974 } 1975 1976 return 0; 1977 } 1978 1979