1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_discovery.h" 28 #include "soc15_hw_ip.h" 29 #include "discovery.h" 30 #include "amdgpu_ras.h" 31 32 #include "soc15.h" 33 #include "gfx_v9_0.h" 34 #include "gfx_v9_4_3.h" 35 #include "gmc_v9_0.h" 36 #include "df_v1_7.h" 37 #include "df_v3_6.h" 38 #include "df_v4_3.h" 39 #include "df_v4_6_2.h" 40 #include "nbio_v6_1.h" 41 #include "nbio_v7_0.h" 42 #include "nbio_v7_4.h" 43 #include "nbio_v7_9.h" 44 #include "nbio_v7_11.h" 45 #include "hdp_v4_0.h" 46 #include "vega10_ih.h" 47 #include "vega20_ih.h" 48 #include "sdma_v4_0.h" 49 #include "sdma_v4_4_2.h" 50 #include "uvd_v7_0.h" 51 #include "vce_v4_0.h" 52 #include "vcn_v1_0.h" 53 #include "vcn_v2_5.h" 54 #include "jpeg_v2_5.h" 55 #include "smuio_v9_0.h" 56 #include "gmc_v10_0.h" 57 #include "gmc_v11_0.h" 58 #include "gfxhub_v2_0.h" 59 #include "mmhub_v2_0.h" 60 #include "nbio_v2_3.h" 61 #include "nbio_v4_3.h" 62 #include "nbio_v7_2.h" 63 #include "nbio_v7_7.h" 64 #include "hdp_v5_0.h" 65 #include "hdp_v5_2.h" 66 #include "hdp_v6_0.h" 67 #include "hdp_v7_0.h" 68 #include "nv.h" 69 #include "soc21.h" 70 #include "navi10_ih.h" 71 #include "ih_v6_0.h" 72 #include "ih_v6_1.h" 73 #include "ih_v7_0.h" 74 #include "gfx_v10_0.h" 75 #include "gfx_v11_0.h" 76 #include "sdma_v5_0.h" 77 #include "sdma_v5_2.h" 78 #include "sdma_v6_0.h" 79 #include "lsdma_v6_0.h" 80 #include "lsdma_v7_0.h" 81 #include "vcn_v2_0.h" 82 #include "jpeg_v2_0.h" 83 #include "vcn_v3_0.h" 84 #include "jpeg_v3_0.h" 85 #include "vcn_v4_0.h" 86 #include "jpeg_v4_0.h" 87 #include "vcn_v4_0_3.h" 88 #include "jpeg_v4_0_3.h" 89 #include "vcn_v4_0_5.h" 90 #include "jpeg_v4_0_5.h" 91 #include "amdgpu_vkms.h" 92 #include "mes_v10_1.h" 93 #include "mes_v11_0.h" 94 #include "smuio_v11_0.h" 95 #include "smuio_v11_0_6.h" 96 #include "smuio_v13_0.h" 97 #include "smuio_v13_0_3.h" 98 #include "smuio_v13_0_6.h" 99 #include "vcn_v5_0_0.h" 100 #include "jpeg_v5_0_0.h" 101 102 #include "amdgpu_vpe.h" 103 104 #define FIRMWARE_IP_DISCOVERY "amdgpu/ip_discovery.bin" 105 MODULE_FIRMWARE(FIRMWARE_IP_DISCOVERY); 106 107 #define mmIP_DISCOVERY_VERSION 0x16A00 108 #define mmRCC_CONFIG_MEMSIZE 0xde3 109 #define mmMP0_SMN_C2PMSG_33 0x16061 110 #define mmMM_INDEX 0x0 111 #define mmMM_INDEX_HI 0x6 112 #define mmMM_DATA 0x1 113 114 static const char *hw_id_names[HW_ID_MAX] = { 115 [MP1_HWID] = "MP1", 116 [MP2_HWID] = "MP2", 117 [THM_HWID] = "THM", 118 [SMUIO_HWID] = "SMUIO", 119 [FUSE_HWID] = "FUSE", 120 [CLKA_HWID] = "CLKA", 121 [PWR_HWID] = "PWR", 122 [GC_HWID] = "GC", 123 [UVD_HWID] = "UVD", 124 [AUDIO_AZ_HWID] = "AUDIO_AZ", 125 [ACP_HWID] = "ACP", 126 [DCI_HWID] = "DCI", 127 [DMU_HWID] = "DMU", 128 [DCO_HWID] = "DCO", 129 [DIO_HWID] = "DIO", 130 [XDMA_HWID] = "XDMA", 131 [DCEAZ_HWID] = "DCEAZ", 132 [DAZ_HWID] = "DAZ", 133 [SDPMUX_HWID] = "SDPMUX", 134 [NTB_HWID] = "NTB", 135 [IOHC_HWID] = "IOHC", 136 [L2IMU_HWID] = "L2IMU", 137 [VCE_HWID] = "VCE", 138 [MMHUB_HWID] = "MMHUB", 139 [ATHUB_HWID] = "ATHUB", 140 [DBGU_NBIO_HWID] = "DBGU_NBIO", 141 [DFX_HWID] = "DFX", 142 [DBGU0_HWID] = "DBGU0", 143 [DBGU1_HWID] = "DBGU1", 144 [OSSSYS_HWID] = "OSSSYS", 145 [HDP_HWID] = "HDP", 146 [SDMA0_HWID] = "SDMA0", 147 [SDMA1_HWID] = "SDMA1", 148 [SDMA2_HWID] = "SDMA2", 149 [SDMA3_HWID] = "SDMA3", 150 [LSDMA_HWID] = "LSDMA", 151 [ISP_HWID] = "ISP", 152 [DBGU_IO_HWID] = "DBGU_IO", 153 [DF_HWID] = "DF", 154 [CLKB_HWID] = "CLKB", 155 [FCH_HWID] = "FCH", 156 [DFX_DAP_HWID] = "DFX_DAP", 157 [L1IMU_PCIE_HWID] = "L1IMU_PCIE", 158 [L1IMU_NBIF_HWID] = "L1IMU_NBIF", 159 [L1IMU_IOAGR_HWID] = "L1IMU_IOAGR", 160 [L1IMU3_HWID] = "L1IMU3", 161 [L1IMU4_HWID] = "L1IMU4", 162 [L1IMU5_HWID] = "L1IMU5", 163 [L1IMU6_HWID] = "L1IMU6", 164 [L1IMU7_HWID] = "L1IMU7", 165 [L1IMU8_HWID] = "L1IMU8", 166 [L1IMU9_HWID] = "L1IMU9", 167 [L1IMU10_HWID] = "L1IMU10", 168 [L1IMU11_HWID] = "L1IMU11", 169 [L1IMU12_HWID] = "L1IMU12", 170 [L1IMU13_HWID] = "L1IMU13", 171 [L1IMU14_HWID] = "L1IMU14", 172 [L1IMU15_HWID] = "L1IMU15", 173 [WAFLC_HWID] = "WAFLC", 174 [FCH_USB_PD_HWID] = "FCH_USB_PD", 175 [PCIE_HWID] = "PCIE", 176 [PCS_HWID] = "PCS", 177 [DDCL_HWID] = "DDCL", 178 [SST_HWID] = "SST", 179 [IOAGR_HWID] = "IOAGR", 180 [NBIF_HWID] = "NBIF", 181 [IOAPIC_HWID] = "IOAPIC", 182 [SYSTEMHUB_HWID] = "SYSTEMHUB", 183 [NTBCCP_HWID] = "NTBCCP", 184 [UMC_HWID] = "UMC", 185 [SATA_HWID] = "SATA", 186 [USB_HWID] = "USB", 187 [CCXSEC_HWID] = "CCXSEC", 188 [XGMI_HWID] = "XGMI", 189 [XGBE_HWID] = "XGBE", 190 [MP0_HWID] = "MP0", 191 [VPE_HWID] = "VPE", 192 }; 193 194 static int hw_id_map[MAX_HWIP] = { 195 [GC_HWIP] = GC_HWID, 196 [HDP_HWIP] = HDP_HWID, 197 [SDMA0_HWIP] = SDMA0_HWID, 198 [SDMA1_HWIP] = SDMA1_HWID, 199 [SDMA2_HWIP] = SDMA2_HWID, 200 [SDMA3_HWIP] = SDMA3_HWID, 201 [LSDMA_HWIP] = LSDMA_HWID, 202 [MMHUB_HWIP] = MMHUB_HWID, 203 [ATHUB_HWIP] = ATHUB_HWID, 204 [NBIO_HWIP] = NBIF_HWID, 205 [MP0_HWIP] = MP0_HWID, 206 [MP1_HWIP] = MP1_HWID, 207 [UVD_HWIP] = UVD_HWID, 208 [VCE_HWIP] = VCE_HWID, 209 [DF_HWIP] = DF_HWID, 210 [DCE_HWIP] = DMU_HWID, 211 [OSSSYS_HWIP] = OSSSYS_HWID, 212 [SMUIO_HWIP] = SMUIO_HWID, 213 [PWR_HWIP] = PWR_HWID, 214 [NBIF_HWIP] = NBIF_HWID, 215 [THM_HWIP] = THM_HWID, 216 [CLK_HWIP] = CLKA_HWID, 217 [UMC_HWIP] = UMC_HWID, 218 [XGMI_HWIP] = XGMI_HWID, 219 [DCI_HWIP] = DCI_HWID, 220 [PCIE_HWIP] = PCIE_HWID, 221 [VPE_HWIP] = VPE_HWID, 222 }; 223 224 static int amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device *adev, uint8_t *binary) 225 { 226 u64 tmr_offset, tmr_size, pos; 227 void *discv_regn; 228 int ret; 229 230 ret = amdgpu_acpi_get_tmr_info(adev, &tmr_offset, &tmr_size); 231 if (ret) 232 return ret; 233 234 pos = tmr_offset + tmr_size - DISCOVERY_TMR_OFFSET; 235 236 /* This region is read-only and reserved from system use */ 237 discv_regn = memremap(pos, adev->mman.discovery_tmr_size, MEMREMAP_WC); 238 if (discv_regn) { 239 memcpy(binary, discv_regn, adev->mman.discovery_tmr_size); 240 memunmap(discv_regn); 241 return 0; 242 } 243 244 return -ENOENT; 245 } 246 247 static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev, 248 uint8_t *binary) 249 { 250 uint64_t vram_size; 251 u32 msg; 252 int i, ret = 0; 253 254 /* It can take up to a second for IFWI init to complete on some dGPUs, 255 * but generally it should be in the 60-100ms range. Normally this starts 256 * as soon as the device gets power so by the time the OS loads this has long 257 * completed. However, when a card is hotplugged via e.g., USB4, we need to 258 * wait for this to complete. Once the C2PMSG is updated, we can 259 * continue. 260 */ 261 if (dev_is_removable(&adev->pdev->dev)) { 262 for (i = 0; i < 1000; i++) { 263 msg = RREG32(mmMP0_SMN_C2PMSG_33); 264 if (msg & 0x80000000) 265 break; 266 msleep(1); 267 } 268 } 269 vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20; 270 271 if (vram_size) { 272 uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET; 273 amdgpu_device_vram_access(adev, pos, (uint32_t *)binary, 274 adev->mman.discovery_tmr_size, false); 275 } else { 276 ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary); 277 } 278 279 return ret; 280 } 281 282 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, uint8_t *binary) 283 { 284 const struct firmware *fw; 285 const char *fw_name; 286 int r; 287 288 switch (amdgpu_discovery) { 289 case 2: 290 fw_name = FIRMWARE_IP_DISCOVERY; 291 break; 292 default: 293 dev_warn(adev->dev, "amdgpu_discovery is not set properly\n"); 294 return -EINVAL; 295 } 296 297 r = request_firmware(&fw, fw_name, adev->dev); 298 if (r) { 299 dev_err(adev->dev, "can't load firmware \"%s\"\n", 300 fw_name); 301 return r; 302 } 303 304 memcpy((u8 *)binary, (u8 *)fw->data, fw->size); 305 release_firmware(fw); 306 307 return 0; 308 } 309 310 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size) 311 { 312 uint16_t checksum = 0; 313 int i; 314 315 for (i = 0; i < size; i++) 316 checksum += data[i]; 317 318 return checksum; 319 } 320 321 static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size, 322 uint16_t expected) 323 { 324 return !!(amdgpu_discovery_calculate_checksum(data, size) == expected); 325 } 326 327 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary) 328 { 329 struct binary_header *bhdr; 330 bhdr = (struct binary_header *)binary; 331 332 return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE); 333 } 334 335 static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev) 336 { 337 /* 338 * So far, apply this quirk only on those Navy Flounder boards which 339 * have a bad harvest table of VCN config. 340 */ 341 if ((amdgpu_ip_version(adev, UVD_HWIP, 1) == IP_VERSION(3, 0, 1)) && 342 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 2))) { 343 switch (adev->pdev->revision) { 344 case 0xC1: 345 case 0xC2: 346 case 0xC3: 347 case 0xC5: 348 case 0xC7: 349 case 0xCF: 350 case 0xDF: 351 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 352 adev->vcn.inst_mask &= ~AMDGPU_VCN_HARVEST_VCN1; 353 break; 354 default: 355 break; 356 } 357 } 358 } 359 360 static int amdgpu_discovery_init(struct amdgpu_device *adev) 361 { 362 struct table_info *info; 363 struct binary_header *bhdr; 364 uint16_t offset; 365 uint16_t size; 366 uint16_t checksum; 367 int r; 368 369 adev->mman.discovery_tmr_size = DISCOVERY_TMR_SIZE; 370 adev->mman.discovery_bin = kzalloc(adev->mman.discovery_tmr_size, GFP_KERNEL); 371 if (!adev->mman.discovery_bin) 372 return -ENOMEM; 373 374 /* Read from file if it is the preferred option */ 375 if (amdgpu_discovery == 2) { 376 dev_info(adev->dev, "use ip discovery information from file"); 377 r = amdgpu_discovery_read_binary_from_file(adev, adev->mman.discovery_bin); 378 379 if (r) { 380 dev_err(adev->dev, "failed to read ip discovery binary from file\n"); 381 r = -EINVAL; 382 goto out; 383 } 384 385 } else { 386 r = amdgpu_discovery_read_binary_from_mem( 387 adev, adev->mman.discovery_bin); 388 if (r) 389 goto out; 390 } 391 392 /* check the ip discovery binary signature */ 393 if (!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) { 394 dev_err(adev->dev, 395 "get invalid ip discovery binary signature\n"); 396 r = -EINVAL; 397 goto out; 398 } 399 400 bhdr = (struct binary_header *)adev->mman.discovery_bin; 401 402 offset = offsetof(struct binary_header, binary_checksum) + 403 sizeof(bhdr->binary_checksum); 404 size = le16_to_cpu(bhdr->binary_size) - offset; 405 checksum = le16_to_cpu(bhdr->binary_checksum); 406 407 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 408 size, checksum)) { 409 dev_err(adev->dev, "invalid ip discovery binary checksum\n"); 410 r = -EINVAL; 411 goto out; 412 } 413 414 info = &bhdr->table_list[IP_DISCOVERY]; 415 offset = le16_to_cpu(info->offset); 416 checksum = le16_to_cpu(info->checksum); 417 418 if (offset) { 419 struct ip_discovery_header *ihdr = 420 (struct ip_discovery_header *)(adev->mman.discovery_bin + offset); 421 if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) { 422 dev_err(adev->dev, "invalid ip discovery data table signature\n"); 423 r = -EINVAL; 424 goto out; 425 } 426 427 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 428 le16_to_cpu(ihdr->size), checksum)) { 429 dev_err(adev->dev, "invalid ip discovery data table checksum\n"); 430 r = -EINVAL; 431 goto out; 432 } 433 } 434 435 info = &bhdr->table_list[GC]; 436 offset = le16_to_cpu(info->offset); 437 checksum = le16_to_cpu(info->checksum); 438 439 if (offset) { 440 struct gpu_info_header *ghdr = 441 (struct gpu_info_header *)(adev->mman.discovery_bin + offset); 442 443 if (le32_to_cpu(ghdr->table_id) != GC_TABLE_ID) { 444 dev_err(adev->dev, "invalid ip discovery gc table id\n"); 445 r = -EINVAL; 446 goto out; 447 } 448 449 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 450 le32_to_cpu(ghdr->size), checksum)) { 451 dev_err(adev->dev, "invalid gc data table checksum\n"); 452 r = -EINVAL; 453 goto out; 454 } 455 } 456 457 info = &bhdr->table_list[HARVEST_INFO]; 458 offset = le16_to_cpu(info->offset); 459 checksum = le16_to_cpu(info->checksum); 460 461 if (offset) { 462 struct harvest_info_header *hhdr = 463 (struct harvest_info_header *)(adev->mman.discovery_bin + offset); 464 465 if (le32_to_cpu(hhdr->signature) != HARVEST_TABLE_SIGNATURE) { 466 dev_err(adev->dev, "invalid ip discovery harvest table signature\n"); 467 r = -EINVAL; 468 goto out; 469 } 470 471 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 472 sizeof(struct harvest_table), checksum)) { 473 dev_err(adev->dev, "invalid harvest data table checksum\n"); 474 r = -EINVAL; 475 goto out; 476 } 477 } 478 479 info = &bhdr->table_list[VCN_INFO]; 480 offset = le16_to_cpu(info->offset); 481 checksum = le16_to_cpu(info->checksum); 482 483 if (offset) { 484 struct vcn_info_header *vhdr = 485 (struct vcn_info_header *)(adev->mman.discovery_bin + offset); 486 487 if (le32_to_cpu(vhdr->table_id) != VCN_INFO_TABLE_ID) { 488 dev_err(adev->dev, "invalid ip discovery vcn table id\n"); 489 r = -EINVAL; 490 goto out; 491 } 492 493 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 494 le32_to_cpu(vhdr->size_bytes), checksum)) { 495 dev_err(adev->dev, "invalid vcn data table checksum\n"); 496 r = -EINVAL; 497 goto out; 498 } 499 } 500 501 info = &bhdr->table_list[MALL_INFO]; 502 offset = le16_to_cpu(info->offset); 503 checksum = le16_to_cpu(info->checksum); 504 505 if (0 && offset) { 506 struct mall_info_header *mhdr = 507 (struct mall_info_header *)(adev->mman.discovery_bin + offset); 508 509 if (le32_to_cpu(mhdr->table_id) != MALL_INFO_TABLE_ID) { 510 dev_err(adev->dev, "invalid ip discovery mall table id\n"); 511 r = -EINVAL; 512 goto out; 513 } 514 515 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 516 le32_to_cpu(mhdr->size_bytes), checksum)) { 517 dev_err(adev->dev, "invalid mall data table checksum\n"); 518 r = -EINVAL; 519 goto out; 520 } 521 } 522 523 return 0; 524 525 out: 526 kfree(adev->mman.discovery_bin); 527 adev->mman.discovery_bin = NULL; 528 if ((amdgpu_discovery != 2) && 529 (RREG32(mmIP_DISCOVERY_VERSION) == 4)) 530 amdgpu_ras_query_boot_status(adev, 4); 531 return r; 532 } 533 534 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev); 535 536 void amdgpu_discovery_fini(struct amdgpu_device *adev) 537 { 538 amdgpu_discovery_sysfs_fini(adev); 539 kfree(adev->mman.discovery_bin); 540 adev->mman.discovery_bin = NULL; 541 } 542 543 static int amdgpu_discovery_validate_ip(const struct ip_v4 *ip) 544 { 545 if (ip->instance_number >= HWIP_MAX_INSTANCE) { 546 DRM_ERROR("Unexpected instance_number (%d) from ip discovery blob\n", 547 ip->instance_number); 548 return -EINVAL; 549 } 550 if (le16_to_cpu(ip->hw_id) >= HW_ID_MAX) { 551 DRM_ERROR("Unexpected hw_id (%d) from ip discovery blob\n", 552 le16_to_cpu(ip->hw_id)); 553 return -EINVAL; 554 } 555 556 return 0; 557 } 558 559 static void amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device *adev, 560 uint32_t *vcn_harvest_count) 561 { 562 struct binary_header *bhdr; 563 struct ip_discovery_header *ihdr; 564 struct die_header *dhdr; 565 struct ip_v4 *ip; 566 uint16_t die_offset, ip_offset, num_dies, num_ips; 567 int i, j; 568 569 bhdr = (struct binary_header *)adev->mman.discovery_bin; 570 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 571 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 572 num_dies = le16_to_cpu(ihdr->num_dies); 573 574 /* scan harvest bit of all IP data structures */ 575 for (i = 0; i < num_dies; i++) { 576 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 577 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 578 num_ips = le16_to_cpu(dhdr->num_ips); 579 ip_offset = die_offset + sizeof(*dhdr); 580 581 for (j = 0; j < num_ips; j++) { 582 ip = (struct ip_v4 *)(adev->mman.discovery_bin + ip_offset); 583 584 if (amdgpu_discovery_validate_ip(ip)) 585 goto next_ip; 586 587 if (le16_to_cpu(ip->variant) == 1) { 588 switch (le16_to_cpu(ip->hw_id)) { 589 case VCN_HWID: 590 (*vcn_harvest_count)++; 591 if (ip->instance_number == 0) { 592 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0; 593 adev->vcn.inst_mask &= 594 ~AMDGPU_VCN_HARVEST_VCN0; 595 adev->jpeg.inst_mask &= 596 ~AMDGPU_VCN_HARVEST_VCN0; 597 } else { 598 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 599 adev->vcn.inst_mask &= 600 ~AMDGPU_VCN_HARVEST_VCN1; 601 adev->jpeg.inst_mask &= 602 ~AMDGPU_VCN_HARVEST_VCN1; 603 } 604 break; 605 case DMU_HWID: 606 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 607 break; 608 default: 609 break; 610 } 611 } 612 next_ip: 613 if (ihdr->base_addr_64_bit) 614 ip_offset += struct_size(ip, base_address_64, ip->num_base_address); 615 else 616 ip_offset += struct_size(ip, base_address, ip->num_base_address); 617 } 618 } 619 } 620 621 static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev, 622 uint32_t *vcn_harvest_count, 623 uint32_t *umc_harvest_count) 624 { 625 struct binary_header *bhdr; 626 struct harvest_table *harvest_info; 627 u16 offset; 628 int i; 629 uint32_t umc_harvest_config = 0; 630 631 bhdr = (struct binary_header *)adev->mman.discovery_bin; 632 offset = le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset); 633 634 if (!offset) { 635 dev_err(adev->dev, "invalid harvest table offset\n"); 636 return; 637 } 638 639 harvest_info = (struct harvest_table *)(adev->mman.discovery_bin + offset); 640 641 for (i = 0; i < 32; i++) { 642 if (le16_to_cpu(harvest_info->list[i].hw_id) == 0) 643 break; 644 645 switch (le16_to_cpu(harvest_info->list[i].hw_id)) { 646 case VCN_HWID: 647 (*vcn_harvest_count)++; 648 adev->vcn.harvest_config |= 649 (1 << harvest_info->list[i].number_instance); 650 adev->jpeg.harvest_config |= 651 (1 << harvest_info->list[i].number_instance); 652 653 adev->vcn.inst_mask &= 654 ~(1U << harvest_info->list[i].number_instance); 655 adev->jpeg.inst_mask &= 656 ~(1U << harvest_info->list[i].number_instance); 657 break; 658 case DMU_HWID: 659 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 660 break; 661 case UMC_HWID: 662 umc_harvest_config |= 663 1 << (le16_to_cpu(harvest_info->list[i].number_instance)); 664 (*umc_harvest_count)++; 665 break; 666 case GC_HWID: 667 adev->gfx.xcc_mask &= 668 ~(1U << harvest_info->list[i].number_instance); 669 break; 670 case SDMA0_HWID: 671 adev->sdma.sdma_mask &= 672 ~(1U << harvest_info->list[i].number_instance); 673 break; 674 default: 675 break; 676 } 677 } 678 679 adev->umc.active_mask = ((1 << adev->umc.node_inst_num) - 1) & 680 ~umc_harvest_config; 681 } 682 683 /* ================================================== */ 684 685 struct ip_hw_instance { 686 struct kobject kobj; /* ip_discovery/die/#die/#hw_id/#instance/<attrs...> */ 687 688 int hw_id; 689 u8 num_instance; 690 u8 major, minor, revision; 691 u8 harvest; 692 693 int num_base_addresses; 694 u32 base_addr[] __counted_by(num_base_addresses); 695 }; 696 697 struct ip_hw_id { 698 struct kset hw_id_kset; /* ip_discovery/die/#die/#hw_id/, contains ip_hw_instance */ 699 int hw_id; 700 }; 701 702 struct ip_die_entry { 703 struct kset ip_kset; /* ip_discovery/die/#die/, contains ip_hw_id */ 704 u16 num_ips; 705 }; 706 707 /* -------------------------------------------------- */ 708 709 struct ip_hw_instance_attr { 710 struct attribute attr; 711 ssize_t (*show)(struct ip_hw_instance *ip_hw_instance, char *buf); 712 }; 713 714 static ssize_t hw_id_show(struct ip_hw_instance *ip_hw_instance, char *buf) 715 { 716 return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id); 717 } 718 719 static ssize_t num_instance_show(struct ip_hw_instance *ip_hw_instance, char *buf) 720 { 721 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance); 722 } 723 724 static ssize_t major_show(struct ip_hw_instance *ip_hw_instance, char *buf) 725 { 726 return sysfs_emit(buf, "%d\n", ip_hw_instance->major); 727 } 728 729 static ssize_t minor_show(struct ip_hw_instance *ip_hw_instance, char *buf) 730 { 731 return sysfs_emit(buf, "%d\n", ip_hw_instance->minor); 732 } 733 734 static ssize_t revision_show(struct ip_hw_instance *ip_hw_instance, char *buf) 735 { 736 return sysfs_emit(buf, "%d\n", ip_hw_instance->revision); 737 } 738 739 static ssize_t harvest_show(struct ip_hw_instance *ip_hw_instance, char *buf) 740 { 741 return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest); 742 } 743 744 static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, char *buf) 745 { 746 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses); 747 } 748 749 static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf) 750 { 751 ssize_t res, at; 752 int ii; 753 754 for (res = at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) { 755 /* Here we satisfy the condition that, at + size <= PAGE_SIZE. 756 */ 757 if (at + 12 > PAGE_SIZE) 758 break; 759 res = sysfs_emit_at(buf, at, "0x%08X\n", 760 ip_hw_instance->base_addr[ii]); 761 if (res <= 0) 762 break; 763 at += res; 764 } 765 766 return res < 0 ? res : at; 767 } 768 769 static struct ip_hw_instance_attr ip_hw_attr[] = { 770 __ATTR_RO(hw_id), 771 __ATTR_RO(num_instance), 772 __ATTR_RO(major), 773 __ATTR_RO(minor), 774 __ATTR_RO(revision), 775 __ATTR_RO(harvest), 776 __ATTR_RO(num_base_addresses), 777 __ATTR_RO(base_addr), 778 }; 779 780 static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1]; 781 ATTRIBUTE_GROUPS(ip_hw_instance); 782 783 #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj) 784 #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr) 785 786 static ssize_t ip_hw_instance_attr_show(struct kobject *kobj, 787 struct attribute *attr, 788 char *buf) 789 { 790 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 791 struct ip_hw_instance_attr *ip_hw_attr = to_ip_hw_instance_attr(attr); 792 793 if (!ip_hw_attr->show) 794 return -EIO; 795 796 return ip_hw_attr->show(ip_hw_instance, buf); 797 } 798 799 static const struct sysfs_ops ip_hw_instance_sysfs_ops = { 800 .show = ip_hw_instance_attr_show, 801 }; 802 803 static void ip_hw_instance_release(struct kobject *kobj) 804 { 805 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 806 807 kfree(ip_hw_instance); 808 } 809 810 static const struct kobj_type ip_hw_instance_ktype = { 811 .release = ip_hw_instance_release, 812 .sysfs_ops = &ip_hw_instance_sysfs_ops, 813 .default_groups = ip_hw_instance_groups, 814 }; 815 816 /* -------------------------------------------------- */ 817 818 #define to_ip_hw_id(x) container_of(to_kset(x), struct ip_hw_id, hw_id_kset) 819 820 static void ip_hw_id_release(struct kobject *kobj) 821 { 822 struct ip_hw_id *ip_hw_id = to_ip_hw_id(kobj); 823 824 if (!list_empty(&ip_hw_id->hw_id_kset.list)) 825 DRM_ERROR("ip_hw_id->hw_id_kset is not empty"); 826 kfree(ip_hw_id); 827 } 828 829 static const struct kobj_type ip_hw_id_ktype = { 830 .release = ip_hw_id_release, 831 .sysfs_ops = &kobj_sysfs_ops, 832 }; 833 834 /* -------------------------------------------------- */ 835 836 static void die_kobj_release(struct kobject *kobj); 837 static void ip_disc_release(struct kobject *kobj); 838 839 struct ip_die_entry_attribute { 840 struct attribute attr; 841 ssize_t (*show)(struct ip_die_entry *ip_die_entry, char *buf); 842 }; 843 844 #define to_ip_die_entry_attr(x) container_of(x, struct ip_die_entry_attribute, attr) 845 846 static ssize_t num_ips_show(struct ip_die_entry *ip_die_entry, char *buf) 847 { 848 return sysfs_emit(buf, "%d\n", ip_die_entry->num_ips); 849 } 850 851 /* If there are more ip_die_entry attrs, other than the number of IPs, 852 * we can make this intro an array of attrs, and then initialize 853 * ip_die_entry_attrs in a loop. 854 */ 855 static struct ip_die_entry_attribute num_ips_attr = 856 __ATTR_RO(num_ips); 857 858 static struct attribute *ip_die_entry_attrs[] = { 859 &num_ips_attr.attr, 860 NULL, 861 }; 862 ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */ 863 864 #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset) 865 866 static ssize_t ip_die_entry_attr_show(struct kobject *kobj, 867 struct attribute *attr, 868 char *buf) 869 { 870 struct ip_die_entry_attribute *ip_die_entry_attr = to_ip_die_entry_attr(attr); 871 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 872 873 if (!ip_die_entry_attr->show) 874 return -EIO; 875 876 return ip_die_entry_attr->show(ip_die_entry, buf); 877 } 878 879 static void ip_die_entry_release(struct kobject *kobj) 880 { 881 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 882 883 if (!list_empty(&ip_die_entry->ip_kset.list)) 884 DRM_ERROR("ip_die_entry->ip_kset is not empty"); 885 kfree(ip_die_entry); 886 } 887 888 static const struct sysfs_ops ip_die_entry_sysfs_ops = { 889 .show = ip_die_entry_attr_show, 890 }; 891 892 static const struct kobj_type ip_die_entry_ktype = { 893 .release = ip_die_entry_release, 894 .sysfs_ops = &ip_die_entry_sysfs_ops, 895 .default_groups = ip_die_entry_groups, 896 }; 897 898 static const struct kobj_type die_kobj_ktype = { 899 .release = die_kobj_release, 900 .sysfs_ops = &kobj_sysfs_ops, 901 }; 902 903 static const struct kobj_type ip_discovery_ktype = { 904 .release = ip_disc_release, 905 .sysfs_ops = &kobj_sysfs_ops, 906 }; 907 908 struct ip_discovery_top { 909 struct kobject kobj; /* ip_discovery/ */ 910 struct kset die_kset; /* ip_discovery/die/, contains ip_die_entry */ 911 struct amdgpu_device *adev; 912 }; 913 914 static void die_kobj_release(struct kobject *kobj) 915 { 916 struct ip_discovery_top *ip_top = container_of(to_kset(kobj), 917 struct ip_discovery_top, 918 die_kset); 919 if (!list_empty(&ip_top->die_kset.list)) 920 DRM_ERROR("ip_top->die_kset is not empty"); 921 } 922 923 static void ip_disc_release(struct kobject *kobj) 924 { 925 struct ip_discovery_top *ip_top = container_of(kobj, struct ip_discovery_top, 926 kobj); 927 struct amdgpu_device *adev = ip_top->adev; 928 929 adev->ip_top = NULL; 930 kfree(ip_top); 931 } 932 933 static uint8_t amdgpu_discovery_get_harvest_info(struct amdgpu_device *adev, 934 uint16_t hw_id, uint8_t inst) 935 { 936 uint8_t harvest = 0; 937 938 /* Until a uniform way is figured, get mask based on hwid */ 939 switch (hw_id) { 940 case VCN_HWID: 941 harvest = ((1 << inst) & adev->vcn.inst_mask) == 0; 942 break; 943 case DMU_HWID: 944 if (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK) 945 harvest = 0x1; 946 break; 947 case UMC_HWID: 948 /* TODO: It needs another parsing; for now, ignore.*/ 949 break; 950 case GC_HWID: 951 harvest = ((1 << inst) & adev->gfx.xcc_mask) == 0; 952 break; 953 case SDMA0_HWID: 954 harvest = ((1 << inst) & adev->sdma.sdma_mask) == 0; 955 break; 956 default: 957 break; 958 } 959 960 return harvest; 961 } 962 963 static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev, 964 struct ip_die_entry *ip_die_entry, 965 const size_t _ip_offset, const int num_ips, 966 bool reg_base_64) 967 { 968 int ii, jj, kk, res; 969 970 DRM_DEBUG("num_ips:%d", num_ips); 971 972 /* Find all IPs of a given HW ID, and add their instance to 973 * #die/#hw_id/#instance/<attributes> 974 */ 975 for (ii = 0; ii < HW_ID_MAX; ii++) { 976 struct ip_hw_id *ip_hw_id = NULL; 977 size_t ip_offset = _ip_offset; 978 979 for (jj = 0; jj < num_ips; jj++) { 980 struct ip_v4 *ip; 981 struct ip_hw_instance *ip_hw_instance; 982 983 ip = (struct ip_v4 *)(adev->mman.discovery_bin + ip_offset); 984 if (amdgpu_discovery_validate_ip(ip) || 985 le16_to_cpu(ip->hw_id) != ii) 986 goto next_ip; 987 988 DRM_DEBUG("match:%d @ ip_offset:%zu", ii, ip_offset); 989 990 /* We have a hw_id match; register the hw 991 * block if not yet registered. 992 */ 993 if (!ip_hw_id) { 994 ip_hw_id = kzalloc(sizeof(*ip_hw_id), GFP_KERNEL); 995 if (!ip_hw_id) 996 return -ENOMEM; 997 ip_hw_id->hw_id = ii; 998 999 kobject_set_name(&ip_hw_id->hw_id_kset.kobj, "%d", ii); 1000 ip_hw_id->hw_id_kset.kobj.kset = &ip_die_entry->ip_kset; 1001 ip_hw_id->hw_id_kset.kobj.ktype = &ip_hw_id_ktype; 1002 res = kset_register(&ip_hw_id->hw_id_kset); 1003 if (res) { 1004 DRM_ERROR("Couldn't register ip_hw_id kset"); 1005 kfree(ip_hw_id); 1006 return res; 1007 } 1008 if (hw_id_names[ii]) { 1009 res = sysfs_create_link(&ip_die_entry->ip_kset.kobj, 1010 &ip_hw_id->hw_id_kset.kobj, 1011 hw_id_names[ii]); 1012 if (res) { 1013 DRM_ERROR("Couldn't create IP link %s in IP Die:%s\n", 1014 hw_id_names[ii], 1015 kobject_name(&ip_die_entry->ip_kset.kobj)); 1016 } 1017 } 1018 } 1019 1020 /* Now register its instance. 1021 */ 1022 ip_hw_instance = kzalloc(struct_size(ip_hw_instance, 1023 base_addr, 1024 ip->num_base_address), 1025 GFP_KERNEL); 1026 if (!ip_hw_instance) { 1027 DRM_ERROR("no memory for ip_hw_instance"); 1028 return -ENOMEM; 1029 } 1030 ip_hw_instance->hw_id = le16_to_cpu(ip->hw_id); /* == ii */ 1031 ip_hw_instance->num_instance = ip->instance_number; 1032 ip_hw_instance->major = ip->major; 1033 ip_hw_instance->minor = ip->minor; 1034 ip_hw_instance->revision = ip->revision; 1035 ip_hw_instance->harvest = 1036 amdgpu_discovery_get_harvest_info( 1037 adev, ip_hw_instance->hw_id, 1038 ip_hw_instance->num_instance); 1039 ip_hw_instance->num_base_addresses = ip->num_base_address; 1040 1041 for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++) { 1042 if (reg_base_64) 1043 ip_hw_instance->base_addr[kk] = 1044 lower_32_bits(le64_to_cpu(ip->base_address_64[kk])) & 0x3FFFFFFF; 1045 else 1046 ip_hw_instance->base_addr[kk] = ip->base_address[kk]; 1047 } 1048 1049 kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype); 1050 ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset; 1051 res = kobject_add(&ip_hw_instance->kobj, NULL, 1052 "%d", ip_hw_instance->num_instance); 1053 next_ip: 1054 if (reg_base_64) 1055 ip_offset += struct_size(ip, base_address_64, 1056 ip->num_base_address); 1057 else 1058 ip_offset += struct_size(ip, base_address, 1059 ip->num_base_address); 1060 } 1061 } 1062 1063 return 0; 1064 } 1065 1066 static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev) 1067 { 1068 struct binary_header *bhdr; 1069 struct ip_discovery_header *ihdr; 1070 struct die_header *dhdr; 1071 struct kset *die_kset = &adev->ip_top->die_kset; 1072 u16 num_dies, die_offset, num_ips; 1073 size_t ip_offset; 1074 int ii, res; 1075 1076 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1077 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 1078 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 1079 num_dies = le16_to_cpu(ihdr->num_dies); 1080 1081 DRM_DEBUG("number of dies: %d\n", num_dies); 1082 1083 for (ii = 0; ii < num_dies; ii++) { 1084 struct ip_die_entry *ip_die_entry; 1085 1086 die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset); 1087 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 1088 num_ips = le16_to_cpu(dhdr->num_ips); 1089 ip_offset = die_offset + sizeof(*dhdr); 1090 1091 /* Add the die to the kset. 1092 * 1093 * dhdr->die_id == ii, which was checked in 1094 * amdgpu_discovery_reg_base_init(). 1095 */ 1096 1097 ip_die_entry = kzalloc(sizeof(*ip_die_entry), GFP_KERNEL); 1098 if (!ip_die_entry) 1099 return -ENOMEM; 1100 1101 ip_die_entry->num_ips = num_ips; 1102 1103 kobject_set_name(&ip_die_entry->ip_kset.kobj, "%d", le16_to_cpu(dhdr->die_id)); 1104 ip_die_entry->ip_kset.kobj.kset = die_kset; 1105 ip_die_entry->ip_kset.kobj.ktype = &ip_die_entry_ktype; 1106 res = kset_register(&ip_die_entry->ip_kset); 1107 if (res) { 1108 DRM_ERROR("Couldn't register ip_die_entry kset"); 1109 kfree(ip_die_entry); 1110 return res; 1111 } 1112 1113 amdgpu_discovery_sysfs_ips(adev, ip_die_entry, ip_offset, num_ips, !!ihdr->base_addr_64_bit); 1114 } 1115 1116 return 0; 1117 } 1118 1119 static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev) 1120 { 1121 struct kset *die_kset; 1122 int res, ii; 1123 1124 if (!adev->mman.discovery_bin) 1125 return -EINVAL; 1126 1127 adev->ip_top = kzalloc(sizeof(*adev->ip_top), GFP_KERNEL); 1128 if (!adev->ip_top) 1129 return -ENOMEM; 1130 1131 adev->ip_top->adev = adev; 1132 1133 res = kobject_init_and_add(&adev->ip_top->kobj, &ip_discovery_ktype, 1134 &adev->dev->kobj, "ip_discovery"); 1135 if (res) { 1136 DRM_ERROR("Couldn't init and add ip_discovery/"); 1137 goto Err; 1138 } 1139 1140 die_kset = &adev->ip_top->die_kset; 1141 kobject_set_name(&die_kset->kobj, "%s", "die"); 1142 die_kset->kobj.parent = &adev->ip_top->kobj; 1143 die_kset->kobj.ktype = &die_kobj_ktype; 1144 res = kset_register(&adev->ip_top->die_kset); 1145 if (res) { 1146 DRM_ERROR("Couldn't register die_kset"); 1147 goto Err; 1148 } 1149 1150 for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++) 1151 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr; 1152 ip_hw_instance_attrs[ii] = NULL; 1153 1154 res = amdgpu_discovery_sysfs_recurse(adev); 1155 1156 return res; 1157 Err: 1158 kobject_put(&adev->ip_top->kobj); 1159 return res; 1160 } 1161 1162 /* -------------------------------------------------- */ 1163 1164 #define list_to_kobj(el) container_of(el, struct kobject, entry) 1165 1166 static void amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id *ip_hw_id) 1167 { 1168 struct list_head *el, *tmp; 1169 struct kset *hw_id_kset; 1170 1171 hw_id_kset = &ip_hw_id->hw_id_kset; 1172 spin_lock(&hw_id_kset->list_lock); 1173 list_for_each_prev_safe(el, tmp, &hw_id_kset->list) { 1174 list_del_init(el); 1175 spin_unlock(&hw_id_kset->list_lock); 1176 /* kobject is embedded in ip_hw_instance */ 1177 kobject_put(list_to_kobj(el)); 1178 spin_lock(&hw_id_kset->list_lock); 1179 } 1180 spin_unlock(&hw_id_kset->list_lock); 1181 kobject_put(&ip_hw_id->hw_id_kset.kobj); 1182 } 1183 1184 static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry) 1185 { 1186 struct list_head *el, *tmp; 1187 struct kset *ip_kset; 1188 1189 ip_kset = &ip_die_entry->ip_kset; 1190 spin_lock(&ip_kset->list_lock); 1191 list_for_each_prev_safe(el, tmp, &ip_kset->list) { 1192 list_del_init(el); 1193 spin_unlock(&ip_kset->list_lock); 1194 amdgpu_discovery_sysfs_ip_hw_free(to_ip_hw_id(list_to_kobj(el))); 1195 spin_lock(&ip_kset->list_lock); 1196 } 1197 spin_unlock(&ip_kset->list_lock); 1198 kobject_put(&ip_die_entry->ip_kset.kobj); 1199 } 1200 1201 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev) 1202 { 1203 struct list_head *el, *tmp; 1204 struct kset *die_kset; 1205 1206 die_kset = &adev->ip_top->die_kset; 1207 spin_lock(&die_kset->list_lock); 1208 list_for_each_prev_safe(el, tmp, &die_kset->list) { 1209 list_del_init(el); 1210 spin_unlock(&die_kset->list_lock); 1211 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el))); 1212 spin_lock(&die_kset->list_lock); 1213 } 1214 spin_unlock(&die_kset->list_lock); 1215 kobject_put(&adev->ip_top->die_kset.kobj); 1216 kobject_put(&adev->ip_top->kobj); 1217 } 1218 1219 /* ================================================== */ 1220 1221 static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) 1222 { 1223 uint8_t num_base_address, subrev, variant; 1224 struct binary_header *bhdr; 1225 struct ip_discovery_header *ihdr; 1226 struct die_header *dhdr; 1227 struct ip_v4 *ip; 1228 uint16_t die_offset; 1229 uint16_t ip_offset; 1230 uint16_t num_dies; 1231 uint16_t num_ips; 1232 int hw_ip; 1233 int i, j, k; 1234 int r; 1235 1236 r = amdgpu_discovery_init(adev); 1237 if (r) { 1238 DRM_ERROR("amdgpu_discovery_init failed\n"); 1239 return r; 1240 } 1241 1242 adev->gfx.xcc_mask = 0; 1243 adev->sdma.sdma_mask = 0; 1244 adev->vcn.inst_mask = 0; 1245 adev->jpeg.inst_mask = 0; 1246 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1247 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 1248 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 1249 num_dies = le16_to_cpu(ihdr->num_dies); 1250 1251 DRM_DEBUG("number of dies: %d\n", num_dies); 1252 1253 for (i = 0; i < num_dies; i++) { 1254 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 1255 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 1256 num_ips = le16_to_cpu(dhdr->num_ips); 1257 ip_offset = die_offset + sizeof(*dhdr); 1258 1259 if (le16_to_cpu(dhdr->die_id) != i) { 1260 DRM_ERROR("invalid die id %d, expected %d\n", 1261 le16_to_cpu(dhdr->die_id), i); 1262 return -EINVAL; 1263 } 1264 1265 DRM_DEBUG("number of hardware IPs on die%d: %d\n", 1266 le16_to_cpu(dhdr->die_id), num_ips); 1267 1268 for (j = 0; j < num_ips; j++) { 1269 ip = (struct ip_v4 *)(adev->mman.discovery_bin + ip_offset); 1270 1271 if (amdgpu_discovery_validate_ip(ip)) 1272 goto next_ip; 1273 1274 num_base_address = ip->num_base_address; 1275 1276 DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n", 1277 hw_id_names[le16_to_cpu(ip->hw_id)], 1278 le16_to_cpu(ip->hw_id), 1279 ip->instance_number, 1280 ip->major, ip->minor, 1281 ip->revision); 1282 1283 if (le16_to_cpu(ip->hw_id) == VCN_HWID) { 1284 /* Bit [5:0]: original revision value 1285 * Bit [7:6]: en/decode capability: 1286 * 0b00 : VCN function normally 1287 * 0b10 : encode is disabled 1288 * 0b01 : decode is disabled 1289 */ 1290 if (adev->vcn.num_vcn_inst < 1291 AMDGPU_MAX_VCN_INSTANCES) { 1292 adev->vcn.vcn_config[adev->vcn.num_vcn_inst] = 1293 ip->revision & 0xc0; 1294 adev->vcn.num_vcn_inst++; 1295 adev->vcn.inst_mask |= 1296 (1U << ip->instance_number); 1297 adev->jpeg.inst_mask |= 1298 (1U << ip->instance_number); 1299 } else { 1300 dev_err(adev->dev, "Too many VCN instances: %d vs %d\n", 1301 adev->vcn.num_vcn_inst + 1, 1302 AMDGPU_MAX_VCN_INSTANCES); 1303 } 1304 ip->revision &= ~0xc0; 1305 } 1306 if (le16_to_cpu(ip->hw_id) == SDMA0_HWID || 1307 le16_to_cpu(ip->hw_id) == SDMA1_HWID || 1308 le16_to_cpu(ip->hw_id) == SDMA2_HWID || 1309 le16_to_cpu(ip->hw_id) == SDMA3_HWID) { 1310 if (adev->sdma.num_instances < 1311 AMDGPU_MAX_SDMA_INSTANCES) { 1312 adev->sdma.num_instances++; 1313 adev->sdma.sdma_mask |= 1314 (1U << ip->instance_number); 1315 } else { 1316 dev_err(adev->dev, "Too many SDMA instances: %d vs %d\n", 1317 adev->sdma.num_instances + 1, 1318 AMDGPU_MAX_SDMA_INSTANCES); 1319 } 1320 } 1321 1322 if (le16_to_cpu(ip->hw_id) == UMC_HWID) { 1323 adev->gmc.num_umc++; 1324 adev->umc.node_inst_num++; 1325 } 1326 1327 if (le16_to_cpu(ip->hw_id) == GC_HWID) 1328 adev->gfx.xcc_mask |= 1329 (1U << ip->instance_number); 1330 1331 for (k = 0; k < num_base_address; k++) { 1332 /* 1333 * convert the endianness of base addresses in place, 1334 * so that we don't need to convert them when accessing adev->reg_offset. 1335 */ 1336 if (ihdr->base_addr_64_bit) 1337 /* Truncate the 64bit base address from ip discovery 1338 * and only store lower 32bit ip base in reg_offset[]. 1339 * Bits > 32 follows ASIC specific format, thus just 1340 * discard them and handle it within specific ASIC. 1341 * By this way reg_offset[] and related helpers can 1342 * stay unchanged. 1343 * The base address is in dwords, thus clear the 1344 * highest 2 bits to store. 1345 */ 1346 ip->base_address[k] = 1347 lower_32_bits(le64_to_cpu(ip->base_address_64[k])) & 0x3FFFFFFF; 1348 else 1349 ip->base_address[k] = le32_to_cpu(ip->base_address[k]); 1350 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]); 1351 } 1352 1353 for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) { 1354 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id) && 1355 hw_id_map[hw_ip] != 0) { 1356 DRM_DEBUG("set register base offset for %s\n", 1357 hw_id_names[le16_to_cpu(ip->hw_id)]); 1358 adev->reg_offset[hw_ip][ip->instance_number] = 1359 ip->base_address; 1360 /* Instance support is somewhat inconsistent. 1361 * SDMA is a good example. Sienna cichlid has 4 total 1362 * SDMA instances, each enumerated separately (HWIDs 1363 * 42, 43, 68, 69). Arcturus has 8 total SDMA instances, 1364 * but they are enumerated as multiple instances of the 1365 * same HWIDs (4x HWID 42, 4x HWID 43). UMC is another 1366 * example. On most chips there are multiple instances 1367 * with the same HWID. 1368 */ 1369 1370 if (ihdr->version < 3) { 1371 subrev = 0; 1372 variant = 0; 1373 } else { 1374 subrev = ip->sub_revision; 1375 variant = ip->variant; 1376 } 1377 1378 adev->ip_versions[hw_ip] 1379 [ip->instance_number] = 1380 IP_VERSION_FULL(ip->major, 1381 ip->minor, 1382 ip->revision, 1383 variant, 1384 subrev); 1385 } 1386 } 1387 1388 next_ip: 1389 if (ihdr->base_addr_64_bit) 1390 ip_offset += struct_size(ip, base_address_64, ip->num_base_address); 1391 else 1392 ip_offset += struct_size(ip, base_address, ip->num_base_address); 1393 } 1394 } 1395 1396 return 0; 1397 } 1398 1399 static void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev) 1400 { 1401 int vcn_harvest_count = 0; 1402 int umc_harvest_count = 0; 1403 1404 /* 1405 * Harvest table does not fit Navi1x and legacy GPUs, 1406 * so read harvest bit per IP data structure to set 1407 * harvest configuration. 1408 */ 1409 if (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 2, 0) && 1410 amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 3)) { 1411 if ((adev->pdev->device == 0x731E && 1412 (adev->pdev->revision == 0xC6 || 1413 adev->pdev->revision == 0xC7)) || 1414 (adev->pdev->device == 0x7340 && 1415 adev->pdev->revision == 0xC9) || 1416 (adev->pdev->device == 0x7360 && 1417 adev->pdev->revision == 0xC7)) 1418 amdgpu_discovery_read_harvest_bit_per_ip(adev, 1419 &vcn_harvest_count); 1420 } else { 1421 amdgpu_discovery_read_from_harvest_table(adev, 1422 &vcn_harvest_count, 1423 &umc_harvest_count); 1424 } 1425 1426 amdgpu_discovery_harvest_config_quirk(adev); 1427 1428 if (vcn_harvest_count == adev->vcn.num_vcn_inst) { 1429 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK; 1430 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK; 1431 } 1432 1433 if (umc_harvest_count < adev->gmc.num_umc) { 1434 adev->gmc.num_umc -= umc_harvest_count; 1435 } 1436 } 1437 1438 union gc_info { 1439 struct gc_info_v1_0 v1; 1440 struct gc_info_v1_1 v1_1; 1441 struct gc_info_v1_2 v1_2; 1442 struct gc_info_v2_0 v2; 1443 struct gc_info_v2_1 v2_1; 1444 }; 1445 1446 static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) 1447 { 1448 struct binary_header *bhdr; 1449 union gc_info *gc_info; 1450 u16 offset; 1451 1452 if (!adev->mman.discovery_bin) { 1453 DRM_ERROR("ip discovery uninitialized\n"); 1454 return -EINVAL; 1455 } 1456 1457 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1458 offset = le16_to_cpu(bhdr->table_list[GC].offset); 1459 1460 if (!offset) 1461 return 0; 1462 1463 gc_info = (union gc_info *)(adev->mman.discovery_bin + offset); 1464 1465 switch (le16_to_cpu(gc_info->v1.header.version_major)) { 1466 case 1: 1467 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se); 1468 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) + 1469 le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa)); 1470 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1471 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se); 1472 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c); 1473 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs); 1474 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds); 1475 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth); 1476 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth); 1477 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer); 1478 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size); 1479 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd); 1480 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu); 1481 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size); 1482 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) / 1483 le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1484 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc); 1485 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 1) { 1486 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v1_1.gc_num_tcp_per_sa); 1487 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v1_1.gc_num_sdp_interface); 1488 adev->gfx.config.gc_num_tcps = le32_to_cpu(gc_info->v1_1.gc_num_tcps); 1489 } 1490 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 2) { 1491 adev->gfx.config.gc_num_tcp_per_wpg = le32_to_cpu(gc_info->v1_2.gc_num_tcp_per_wpg); 1492 adev->gfx.config.gc_tcp_l1_size = le32_to_cpu(gc_info->v1_2.gc_tcp_l1_size); 1493 adev->gfx.config.gc_num_sqc_per_wgp = le32_to_cpu(gc_info->v1_2.gc_num_sqc_per_wgp); 1494 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_instruction_cache_size_per_sqc); 1495 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_data_cache_size_per_sqc); 1496 adev->gfx.config.gc_gl1c_per_sa = le32_to_cpu(gc_info->v1_2.gc_gl1c_per_sa); 1497 adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance); 1498 adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu); 1499 } 1500 break; 1501 case 2: 1502 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se); 1503 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh); 1504 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1505 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se); 1506 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs); 1507 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs); 1508 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds); 1509 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth); 1510 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth); 1511 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer); 1512 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size); 1513 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd); 1514 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu); 1515 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size); 1516 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) / 1517 le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1518 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc); 1519 if (le16_to_cpu(gc_info->v2.header.version_minor) == 1) { 1520 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v2_1.gc_num_tcp_per_sh); 1521 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v2_1.gc_tcp_size_per_cu); 1522 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v2_1.gc_num_sdp_interface); /* per XCD */ 1523 adev->gfx.config.gc_num_cu_per_sqc = le32_to_cpu(gc_info->v2_1.gc_num_cu_per_sqc); 1524 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_instruction_cache_size_per_sqc); 1525 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_scalar_data_cache_size_per_sqc); 1526 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v2_1.gc_tcc_size); /* per XCD */ 1527 } 1528 break; 1529 default: 1530 dev_err(adev->dev, 1531 "Unhandled GC info table %d.%d\n", 1532 le16_to_cpu(gc_info->v1.header.version_major), 1533 le16_to_cpu(gc_info->v1.header.version_minor)); 1534 return -EINVAL; 1535 } 1536 return 0; 1537 } 1538 1539 union mall_info { 1540 struct mall_info_v1_0 v1; 1541 struct mall_info_v2_0 v2; 1542 }; 1543 1544 static int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev) 1545 { 1546 struct binary_header *bhdr; 1547 union mall_info *mall_info; 1548 u32 u, mall_size_per_umc, m_s_present, half_use; 1549 u64 mall_size; 1550 u16 offset; 1551 1552 if (!adev->mman.discovery_bin) { 1553 DRM_ERROR("ip discovery uninitialized\n"); 1554 return -EINVAL; 1555 } 1556 1557 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1558 offset = le16_to_cpu(bhdr->table_list[MALL_INFO].offset); 1559 1560 if (!offset) 1561 return 0; 1562 1563 mall_info = (union mall_info *)(adev->mman.discovery_bin + offset); 1564 1565 switch (le16_to_cpu(mall_info->v1.header.version_major)) { 1566 case 1: 1567 mall_size = 0; 1568 mall_size_per_umc = le32_to_cpu(mall_info->v1.mall_size_per_m); 1569 m_s_present = le32_to_cpu(mall_info->v1.m_s_present); 1570 half_use = le32_to_cpu(mall_info->v1.m_half_use); 1571 for (u = 0; u < adev->gmc.num_umc; u++) { 1572 if (m_s_present & (1 << u)) 1573 mall_size += mall_size_per_umc * 2; 1574 else if (half_use & (1 << u)) 1575 mall_size += mall_size_per_umc / 2; 1576 else 1577 mall_size += mall_size_per_umc; 1578 } 1579 adev->gmc.mall_size = mall_size; 1580 adev->gmc.m_half_use = half_use; 1581 break; 1582 case 2: 1583 mall_size_per_umc = le32_to_cpu(mall_info->v2.mall_size_per_umc); 1584 adev->gmc.mall_size = mall_size_per_umc * adev->gmc.num_umc; 1585 break; 1586 default: 1587 dev_err(adev->dev, 1588 "Unhandled MALL info table %d.%d\n", 1589 le16_to_cpu(mall_info->v1.header.version_major), 1590 le16_to_cpu(mall_info->v1.header.version_minor)); 1591 return -EINVAL; 1592 } 1593 return 0; 1594 } 1595 1596 union vcn_info { 1597 struct vcn_info_v1_0 v1; 1598 }; 1599 1600 static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev) 1601 { 1602 struct binary_header *bhdr; 1603 union vcn_info *vcn_info; 1604 u16 offset; 1605 int v; 1606 1607 if (!adev->mman.discovery_bin) { 1608 DRM_ERROR("ip discovery uninitialized\n"); 1609 return -EINVAL; 1610 } 1611 1612 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES 1613 * which is smaller than VCN_INFO_TABLE_MAX_NUM_INSTANCES 1614 * but that may change in the future with new GPUs so keep this 1615 * check for defensive purposes. 1616 */ 1617 if (adev->vcn.num_vcn_inst > VCN_INFO_TABLE_MAX_NUM_INSTANCES) { 1618 dev_err(adev->dev, "invalid vcn instances\n"); 1619 return -EINVAL; 1620 } 1621 1622 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1623 offset = le16_to_cpu(bhdr->table_list[VCN_INFO].offset); 1624 1625 if (!offset) 1626 return 0; 1627 1628 vcn_info = (union vcn_info *)(adev->mman.discovery_bin + offset); 1629 1630 switch (le16_to_cpu(vcn_info->v1.header.version_major)) { 1631 case 1: 1632 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES 1633 * so this won't overflow. 1634 */ 1635 for (v = 0; v < adev->vcn.num_vcn_inst; v++) { 1636 adev->vcn.vcn_codec_disable_mask[v] = 1637 le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits); 1638 } 1639 break; 1640 default: 1641 dev_err(adev->dev, 1642 "Unhandled VCN info table %d.%d\n", 1643 le16_to_cpu(vcn_info->v1.header.version_major), 1644 le16_to_cpu(vcn_info->v1.header.version_minor)); 1645 return -EINVAL; 1646 } 1647 return 0; 1648 } 1649 1650 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev) 1651 { 1652 /* what IP to use for this? */ 1653 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1654 case IP_VERSION(9, 0, 1): 1655 case IP_VERSION(9, 1, 0): 1656 case IP_VERSION(9, 2, 1): 1657 case IP_VERSION(9, 2, 2): 1658 case IP_VERSION(9, 3, 0): 1659 case IP_VERSION(9, 4, 0): 1660 case IP_VERSION(9, 4, 1): 1661 case IP_VERSION(9, 4, 2): 1662 case IP_VERSION(9, 4, 3): 1663 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 1664 break; 1665 case IP_VERSION(10, 1, 10): 1666 case IP_VERSION(10, 1, 1): 1667 case IP_VERSION(10, 1, 2): 1668 case IP_VERSION(10, 1, 3): 1669 case IP_VERSION(10, 1, 4): 1670 case IP_VERSION(10, 3, 0): 1671 case IP_VERSION(10, 3, 1): 1672 case IP_VERSION(10, 3, 2): 1673 case IP_VERSION(10, 3, 3): 1674 case IP_VERSION(10, 3, 4): 1675 case IP_VERSION(10, 3, 5): 1676 case IP_VERSION(10, 3, 6): 1677 case IP_VERSION(10, 3, 7): 1678 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 1679 break; 1680 case IP_VERSION(11, 0, 0): 1681 case IP_VERSION(11, 0, 1): 1682 case IP_VERSION(11, 0, 2): 1683 case IP_VERSION(11, 0, 3): 1684 case IP_VERSION(11, 0, 4): 1685 case IP_VERSION(11, 5, 0): 1686 amdgpu_device_ip_block_add(adev, &soc21_common_ip_block); 1687 break; 1688 default: 1689 dev_err(adev->dev, 1690 "Failed to add common ip block(GC_HWIP:0x%x)\n", 1691 amdgpu_ip_version(adev, GC_HWIP, 0)); 1692 return -EINVAL; 1693 } 1694 return 0; 1695 } 1696 1697 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev) 1698 { 1699 /* use GC or MMHUB IP version */ 1700 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1701 case IP_VERSION(9, 0, 1): 1702 case IP_VERSION(9, 1, 0): 1703 case IP_VERSION(9, 2, 1): 1704 case IP_VERSION(9, 2, 2): 1705 case IP_VERSION(9, 3, 0): 1706 case IP_VERSION(9, 4, 0): 1707 case IP_VERSION(9, 4, 1): 1708 case IP_VERSION(9, 4, 2): 1709 case IP_VERSION(9, 4, 3): 1710 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 1711 break; 1712 case IP_VERSION(10, 1, 10): 1713 case IP_VERSION(10, 1, 1): 1714 case IP_VERSION(10, 1, 2): 1715 case IP_VERSION(10, 1, 3): 1716 case IP_VERSION(10, 1, 4): 1717 case IP_VERSION(10, 3, 0): 1718 case IP_VERSION(10, 3, 1): 1719 case IP_VERSION(10, 3, 2): 1720 case IP_VERSION(10, 3, 3): 1721 case IP_VERSION(10, 3, 4): 1722 case IP_VERSION(10, 3, 5): 1723 case IP_VERSION(10, 3, 6): 1724 case IP_VERSION(10, 3, 7): 1725 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 1726 break; 1727 case IP_VERSION(11, 0, 0): 1728 case IP_VERSION(11, 0, 1): 1729 case IP_VERSION(11, 0, 2): 1730 case IP_VERSION(11, 0, 3): 1731 case IP_VERSION(11, 0, 4): 1732 case IP_VERSION(11, 5, 0): 1733 amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block); 1734 break; 1735 default: 1736 dev_err(adev->dev, "Failed to add gmc ip block(GC_HWIP:0x%x)\n", 1737 amdgpu_ip_version(adev, GC_HWIP, 0)); 1738 return -EINVAL; 1739 } 1740 return 0; 1741 } 1742 1743 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev) 1744 { 1745 switch (amdgpu_ip_version(adev, OSSSYS_HWIP, 0)) { 1746 case IP_VERSION(4, 0, 0): 1747 case IP_VERSION(4, 0, 1): 1748 case IP_VERSION(4, 1, 0): 1749 case IP_VERSION(4, 1, 1): 1750 case IP_VERSION(4, 3, 0): 1751 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 1752 break; 1753 case IP_VERSION(4, 2, 0): 1754 case IP_VERSION(4, 2, 1): 1755 case IP_VERSION(4, 4, 0): 1756 case IP_VERSION(4, 4, 2): 1757 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 1758 break; 1759 case IP_VERSION(5, 0, 0): 1760 case IP_VERSION(5, 0, 1): 1761 case IP_VERSION(5, 0, 2): 1762 case IP_VERSION(5, 0, 3): 1763 case IP_VERSION(5, 2, 0): 1764 case IP_VERSION(5, 2, 1): 1765 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 1766 break; 1767 case IP_VERSION(6, 0, 0): 1768 case IP_VERSION(6, 0, 1): 1769 case IP_VERSION(6, 0, 2): 1770 amdgpu_device_ip_block_add(adev, &ih_v6_0_ip_block); 1771 break; 1772 case IP_VERSION(6, 1, 0): 1773 amdgpu_device_ip_block_add(adev, &ih_v6_1_ip_block); 1774 break; 1775 case IP_VERSION(7, 0, 0): 1776 amdgpu_device_ip_block_add(adev, &ih_v7_0_ip_block); 1777 break; 1778 default: 1779 dev_err(adev->dev, 1780 "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n", 1781 amdgpu_ip_version(adev, OSSSYS_HWIP, 0)); 1782 return -EINVAL; 1783 } 1784 return 0; 1785 } 1786 1787 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev) 1788 { 1789 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 1790 case IP_VERSION(9, 0, 0): 1791 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 1792 break; 1793 case IP_VERSION(10, 0, 0): 1794 case IP_VERSION(10, 0, 1): 1795 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); 1796 break; 1797 case IP_VERSION(11, 0, 0): 1798 case IP_VERSION(11, 0, 2): 1799 case IP_VERSION(11, 0, 4): 1800 case IP_VERSION(11, 0, 5): 1801 case IP_VERSION(11, 0, 9): 1802 case IP_VERSION(11, 0, 7): 1803 case IP_VERSION(11, 0, 11): 1804 case IP_VERSION(11, 0, 12): 1805 case IP_VERSION(11, 0, 13): 1806 case IP_VERSION(11, 5, 0): 1807 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 1808 break; 1809 case IP_VERSION(11, 0, 8): 1810 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block); 1811 break; 1812 case IP_VERSION(11, 0, 3): 1813 case IP_VERSION(12, 0, 1): 1814 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); 1815 break; 1816 case IP_VERSION(13, 0, 0): 1817 case IP_VERSION(13, 0, 1): 1818 case IP_VERSION(13, 0, 2): 1819 case IP_VERSION(13, 0, 3): 1820 case IP_VERSION(13, 0, 5): 1821 case IP_VERSION(13, 0, 6): 1822 case IP_VERSION(13, 0, 7): 1823 case IP_VERSION(13, 0, 8): 1824 case IP_VERSION(13, 0, 10): 1825 case IP_VERSION(13, 0, 11): 1826 case IP_VERSION(14, 0, 0): 1827 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); 1828 break; 1829 case IP_VERSION(13, 0, 4): 1830 amdgpu_device_ip_block_add(adev, &psp_v13_0_4_ip_block); 1831 break; 1832 default: 1833 dev_err(adev->dev, 1834 "Failed to add psp ip block(MP0_HWIP:0x%x)\n", 1835 amdgpu_ip_version(adev, MP0_HWIP, 0)); 1836 return -EINVAL; 1837 } 1838 return 0; 1839 } 1840 1841 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev) 1842 { 1843 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1844 case IP_VERSION(9, 0, 0): 1845 case IP_VERSION(10, 0, 0): 1846 case IP_VERSION(10, 0, 1): 1847 case IP_VERSION(11, 0, 2): 1848 if (adev->asic_type == CHIP_ARCTURUS) 1849 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 1850 else 1851 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 1852 break; 1853 case IP_VERSION(11, 0, 0): 1854 case IP_VERSION(11, 0, 5): 1855 case IP_VERSION(11, 0, 9): 1856 case IP_VERSION(11, 0, 7): 1857 case IP_VERSION(11, 0, 8): 1858 case IP_VERSION(11, 0, 11): 1859 case IP_VERSION(11, 0, 12): 1860 case IP_VERSION(11, 0, 13): 1861 case IP_VERSION(11, 5, 0): 1862 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 1863 break; 1864 case IP_VERSION(12, 0, 0): 1865 case IP_VERSION(12, 0, 1): 1866 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); 1867 break; 1868 case IP_VERSION(13, 0, 0): 1869 case IP_VERSION(13, 0, 1): 1870 case IP_VERSION(13, 0, 2): 1871 case IP_VERSION(13, 0, 3): 1872 case IP_VERSION(13, 0, 4): 1873 case IP_VERSION(13, 0, 5): 1874 case IP_VERSION(13, 0, 6): 1875 case IP_VERSION(13, 0, 7): 1876 case IP_VERSION(13, 0, 8): 1877 case IP_VERSION(13, 0, 10): 1878 case IP_VERSION(13, 0, 11): 1879 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); 1880 break; 1881 case IP_VERSION(14, 0, 0): 1882 amdgpu_device_ip_block_add(adev, &smu_v14_0_ip_block); 1883 break; 1884 default: 1885 dev_err(adev->dev, 1886 "Failed to add smu ip block(MP1_HWIP:0x%x)\n", 1887 amdgpu_ip_version(adev, MP1_HWIP, 0)); 1888 return -EINVAL; 1889 } 1890 return 0; 1891 } 1892 1893 #if defined(CONFIG_DRM_AMD_DC) 1894 static void amdgpu_discovery_set_sriov_display(struct amdgpu_device *adev) 1895 { 1896 amdgpu_device_set_sriov_virtual_display(adev); 1897 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 1898 } 1899 #endif 1900 1901 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev) 1902 { 1903 if (adev->enable_virtual_display) { 1904 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 1905 return 0; 1906 } 1907 1908 if (!amdgpu_device_has_dc_support(adev)) 1909 return 0; 1910 1911 #if defined(CONFIG_DRM_AMD_DC) 1912 if (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1913 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1914 case IP_VERSION(1, 0, 0): 1915 case IP_VERSION(1, 0, 1): 1916 case IP_VERSION(2, 0, 2): 1917 case IP_VERSION(2, 0, 0): 1918 case IP_VERSION(2, 0, 3): 1919 case IP_VERSION(2, 1, 0): 1920 case IP_VERSION(3, 0, 0): 1921 case IP_VERSION(3, 0, 2): 1922 case IP_VERSION(3, 0, 3): 1923 case IP_VERSION(3, 0, 1): 1924 case IP_VERSION(3, 1, 2): 1925 case IP_VERSION(3, 1, 3): 1926 case IP_VERSION(3, 1, 4): 1927 case IP_VERSION(3, 1, 5): 1928 case IP_VERSION(3, 1, 6): 1929 case IP_VERSION(3, 2, 0): 1930 case IP_VERSION(3, 2, 1): 1931 case IP_VERSION(3, 5, 0): 1932 if (amdgpu_sriov_vf(adev)) 1933 amdgpu_discovery_set_sriov_display(adev); 1934 else 1935 amdgpu_device_ip_block_add(adev, &dm_ip_block); 1936 break; 1937 default: 1938 dev_err(adev->dev, 1939 "Failed to add dm ip block(DCE_HWIP:0x%x)\n", 1940 amdgpu_ip_version(adev, DCE_HWIP, 0)); 1941 return -EINVAL; 1942 } 1943 } else if (amdgpu_ip_version(adev, DCI_HWIP, 0)) { 1944 switch (amdgpu_ip_version(adev, DCI_HWIP, 0)) { 1945 case IP_VERSION(12, 0, 0): 1946 case IP_VERSION(12, 0, 1): 1947 case IP_VERSION(12, 1, 0): 1948 if (amdgpu_sriov_vf(adev)) 1949 amdgpu_discovery_set_sriov_display(adev); 1950 else 1951 amdgpu_device_ip_block_add(adev, &dm_ip_block); 1952 break; 1953 default: 1954 dev_err(adev->dev, 1955 "Failed to add dm ip block(DCI_HWIP:0x%x)\n", 1956 amdgpu_ip_version(adev, DCI_HWIP, 0)); 1957 return -EINVAL; 1958 } 1959 } 1960 #endif 1961 return 0; 1962 } 1963 1964 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) 1965 { 1966 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1967 case IP_VERSION(9, 0, 1): 1968 case IP_VERSION(9, 1, 0): 1969 case IP_VERSION(9, 2, 1): 1970 case IP_VERSION(9, 2, 2): 1971 case IP_VERSION(9, 3, 0): 1972 case IP_VERSION(9, 4, 0): 1973 case IP_VERSION(9, 4, 1): 1974 case IP_VERSION(9, 4, 2): 1975 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 1976 break; 1977 case IP_VERSION(9, 4, 3): 1978 amdgpu_device_ip_block_add(adev, &gfx_v9_4_3_ip_block); 1979 break; 1980 case IP_VERSION(10, 1, 10): 1981 case IP_VERSION(10, 1, 2): 1982 case IP_VERSION(10, 1, 1): 1983 case IP_VERSION(10, 1, 3): 1984 case IP_VERSION(10, 1, 4): 1985 case IP_VERSION(10, 3, 0): 1986 case IP_VERSION(10, 3, 2): 1987 case IP_VERSION(10, 3, 1): 1988 case IP_VERSION(10, 3, 4): 1989 case IP_VERSION(10, 3, 5): 1990 case IP_VERSION(10, 3, 6): 1991 case IP_VERSION(10, 3, 3): 1992 case IP_VERSION(10, 3, 7): 1993 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 1994 break; 1995 case IP_VERSION(11, 0, 0): 1996 case IP_VERSION(11, 0, 1): 1997 case IP_VERSION(11, 0, 2): 1998 case IP_VERSION(11, 0, 3): 1999 case IP_VERSION(11, 0, 4): 2000 case IP_VERSION(11, 5, 0): 2001 amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block); 2002 break; 2003 default: 2004 dev_err(adev->dev, "Failed to add gfx ip block(GC_HWIP:0x%x)\n", 2005 amdgpu_ip_version(adev, GC_HWIP, 0)); 2006 return -EINVAL; 2007 } 2008 return 0; 2009 } 2010 2011 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev) 2012 { 2013 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 2014 case IP_VERSION(4, 0, 0): 2015 case IP_VERSION(4, 0, 1): 2016 case IP_VERSION(4, 1, 0): 2017 case IP_VERSION(4, 1, 1): 2018 case IP_VERSION(4, 1, 2): 2019 case IP_VERSION(4, 2, 0): 2020 case IP_VERSION(4, 2, 2): 2021 case IP_VERSION(4, 4, 0): 2022 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 2023 break; 2024 case IP_VERSION(4, 4, 2): 2025 amdgpu_device_ip_block_add(adev, &sdma_v4_4_2_ip_block); 2026 break; 2027 case IP_VERSION(5, 0, 0): 2028 case IP_VERSION(5, 0, 1): 2029 case IP_VERSION(5, 0, 2): 2030 case IP_VERSION(5, 0, 5): 2031 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 2032 break; 2033 case IP_VERSION(5, 2, 0): 2034 case IP_VERSION(5, 2, 2): 2035 case IP_VERSION(5, 2, 4): 2036 case IP_VERSION(5, 2, 5): 2037 case IP_VERSION(5, 2, 6): 2038 case IP_VERSION(5, 2, 3): 2039 case IP_VERSION(5, 2, 1): 2040 case IP_VERSION(5, 2, 7): 2041 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 2042 break; 2043 case IP_VERSION(6, 0, 0): 2044 case IP_VERSION(6, 0, 1): 2045 case IP_VERSION(6, 0, 2): 2046 case IP_VERSION(6, 0, 3): 2047 case IP_VERSION(6, 1, 0): 2048 amdgpu_device_ip_block_add(adev, &sdma_v6_0_ip_block); 2049 break; 2050 default: 2051 dev_err(adev->dev, 2052 "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n", 2053 amdgpu_ip_version(adev, SDMA0_HWIP, 0)); 2054 return -EINVAL; 2055 } 2056 return 0; 2057 } 2058 2059 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) 2060 { 2061 if (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 2062 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 2063 case IP_VERSION(7, 0, 0): 2064 case IP_VERSION(7, 2, 0): 2065 /* UVD is not supported on vega20 SR-IOV */ 2066 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 2067 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); 2068 break; 2069 default: 2070 dev_err(adev->dev, 2071 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n", 2072 amdgpu_ip_version(adev, UVD_HWIP, 0)); 2073 return -EINVAL; 2074 } 2075 switch (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 2076 case IP_VERSION(4, 0, 0): 2077 case IP_VERSION(4, 1, 0): 2078 /* VCE is not supported on vega20 SR-IOV */ 2079 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 2080 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); 2081 break; 2082 default: 2083 dev_err(adev->dev, 2084 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n", 2085 amdgpu_ip_version(adev, VCE_HWIP, 0)); 2086 return -EINVAL; 2087 } 2088 } else { 2089 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 2090 case IP_VERSION(1, 0, 0): 2091 case IP_VERSION(1, 0, 1): 2092 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); 2093 break; 2094 case IP_VERSION(2, 0, 0): 2095 case IP_VERSION(2, 0, 2): 2096 case IP_VERSION(2, 2, 0): 2097 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 2098 if (!amdgpu_sriov_vf(adev)) 2099 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 2100 break; 2101 case IP_VERSION(2, 0, 3): 2102 break; 2103 case IP_VERSION(2, 5, 0): 2104 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 2105 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block); 2106 break; 2107 case IP_VERSION(2, 6, 0): 2108 amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block); 2109 amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block); 2110 break; 2111 case IP_VERSION(3, 0, 0): 2112 case IP_VERSION(3, 0, 16): 2113 case IP_VERSION(3, 1, 1): 2114 case IP_VERSION(3, 1, 2): 2115 case IP_VERSION(3, 0, 2): 2116 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 2117 if (!amdgpu_sriov_vf(adev)) 2118 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 2119 break; 2120 case IP_VERSION(3, 0, 33): 2121 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 2122 break; 2123 case IP_VERSION(4, 0, 0): 2124 case IP_VERSION(4, 0, 2): 2125 case IP_VERSION(4, 0, 4): 2126 amdgpu_device_ip_block_add(adev, &vcn_v4_0_ip_block); 2127 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block); 2128 break; 2129 case IP_VERSION(4, 0, 3): 2130 amdgpu_device_ip_block_add(adev, &vcn_v4_0_3_ip_block); 2131 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_3_ip_block); 2132 break; 2133 case IP_VERSION(4, 0, 5): 2134 amdgpu_device_ip_block_add(adev, &vcn_v4_0_5_ip_block); 2135 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_5_ip_block); 2136 break; 2137 case IP_VERSION(5, 0, 0): 2138 amdgpu_device_ip_block_add(adev, &vcn_v5_0_0_ip_block); 2139 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_0_ip_block); 2140 break; 2141 default: 2142 dev_err(adev->dev, 2143 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n", 2144 amdgpu_ip_version(adev, UVD_HWIP, 0)); 2145 return -EINVAL; 2146 } 2147 } 2148 return 0; 2149 } 2150 2151 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev) 2152 { 2153 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2154 case IP_VERSION(10, 1, 10): 2155 case IP_VERSION(10, 1, 1): 2156 case IP_VERSION(10, 1, 2): 2157 case IP_VERSION(10, 1, 3): 2158 case IP_VERSION(10, 1, 4): 2159 case IP_VERSION(10, 3, 0): 2160 case IP_VERSION(10, 3, 1): 2161 case IP_VERSION(10, 3, 2): 2162 case IP_VERSION(10, 3, 3): 2163 case IP_VERSION(10, 3, 4): 2164 case IP_VERSION(10, 3, 5): 2165 case IP_VERSION(10, 3, 6): 2166 if (amdgpu_mes) { 2167 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 2168 adev->enable_mes = true; 2169 if (amdgpu_mes_kiq) 2170 adev->enable_mes_kiq = true; 2171 } 2172 break; 2173 case IP_VERSION(11, 0, 0): 2174 case IP_VERSION(11, 0, 1): 2175 case IP_VERSION(11, 0, 2): 2176 case IP_VERSION(11, 0, 3): 2177 case IP_VERSION(11, 0, 4): 2178 case IP_VERSION(11, 5, 0): 2179 amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block); 2180 adev->enable_mes = true; 2181 adev->enable_mes_kiq = true; 2182 break; 2183 default: 2184 break; 2185 } 2186 return 0; 2187 } 2188 2189 static void amdgpu_discovery_init_soc_config(struct amdgpu_device *adev) 2190 { 2191 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2192 case IP_VERSION(9, 4, 3): 2193 aqua_vanjaram_init_soc_config(adev); 2194 break; 2195 default: 2196 break; 2197 } 2198 } 2199 2200 static int amdgpu_discovery_set_vpe_ip_blocks(struct amdgpu_device *adev) 2201 { 2202 switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) { 2203 case IP_VERSION(6, 1, 0): 2204 amdgpu_device_ip_block_add(adev, &vpe_v6_1_ip_block); 2205 break; 2206 default: 2207 break; 2208 } 2209 2210 return 0; 2211 } 2212 2213 static int amdgpu_discovery_set_umsch_mm_ip_blocks(struct amdgpu_device *adev) 2214 { 2215 switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) { 2216 case IP_VERSION(4, 0, 5): 2217 if (amdgpu_umsch_mm & 0x1) { 2218 amdgpu_device_ip_block_add(adev, &umsch_mm_v4_0_ip_block); 2219 adev->enable_umsch_mm = true; 2220 } 2221 break; 2222 default: 2223 break; 2224 } 2225 2226 return 0; 2227 } 2228 2229 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 2230 { 2231 int r; 2232 2233 switch (adev->asic_type) { 2234 case CHIP_VEGA10: 2235 vega10_reg_base_init(adev); 2236 adev->sdma.num_instances = 2; 2237 adev->gmc.num_umc = 4; 2238 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0); 2239 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0); 2240 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0); 2241 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0); 2242 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0); 2243 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0); 2244 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 2245 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0); 2246 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0); 2247 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 2248 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 2249 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 2250 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0); 2251 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1); 2252 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 2253 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 2254 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0); 2255 break; 2256 case CHIP_VEGA12: 2257 vega10_reg_base_init(adev); 2258 adev->sdma.num_instances = 2; 2259 adev->gmc.num_umc = 4; 2260 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0); 2261 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0); 2262 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1); 2263 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1); 2264 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1); 2265 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1); 2266 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0); 2267 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0); 2268 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0); 2269 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 2270 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 2271 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 2272 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1); 2273 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1); 2274 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 2275 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 2276 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1); 2277 break; 2278 case CHIP_RAVEN: 2279 vega10_reg_base_init(adev); 2280 adev->sdma.num_instances = 1; 2281 adev->vcn.num_vcn_inst = 1; 2282 adev->gmc.num_umc = 2; 2283 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { 2284 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0); 2285 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0); 2286 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1); 2287 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1); 2288 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1); 2289 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1); 2290 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1); 2291 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0); 2292 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1); 2293 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1); 2294 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0); 2295 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1); 2296 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2); 2297 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1); 2298 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1); 2299 } else { 2300 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0); 2301 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0); 2302 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0); 2303 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0); 2304 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0); 2305 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 2306 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0); 2307 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0); 2308 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0); 2309 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0); 2310 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0); 2311 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0); 2312 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0); 2313 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0); 2314 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0); 2315 } 2316 break; 2317 case CHIP_VEGA20: 2318 vega20_reg_base_init(adev); 2319 adev->sdma.num_instances = 2; 2320 adev->gmc.num_umc = 8; 2321 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2322 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2323 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0); 2324 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0); 2325 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0); 2326 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0); 2327 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0); 2328 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0); 2329 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1); 2330 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2); 2331 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2332 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2); 2333 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2); 2334 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0); 2335 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0); 2336 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0); 2337 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0); 2338 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0); 2339 break; 2340 case CHIP_ARCTURUS: 2341 arct_reg_base_init(adev); 2342 adev->sdma.num_instances = 8; 2343 adev->vcn.num_vcn_inst = 2; 2344 adev->gmc.num_umc = 8; 2345 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2346 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2347 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1); 2348 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1); 2349 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2); 2350 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2); 2351 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2); 2352 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2); 2353 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2); 2354 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2); 2355 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2); 2356 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2); 2357 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1); 2358 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1); 2359 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2); 2360 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4); 2361 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2362 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3); 2363 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3); 2364 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1); 2365 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0); 2366 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0); 2367 break; 2368 case CHIP_ALDEBARAN: 2369 aldebaran_reg_base_init(adev); 2370 adev->sdma.num_instances = 5; 2371 adev->vcn.num_vcn_inst = 2; 2372 adev->gmc.num_umc = 4; 2373 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2374 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2375 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0); 2376 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0); 2377 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0); 2378 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0); 2379 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0); 2380 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0); 2381 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0); 2382 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2); 2383 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4); 2384 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0); 2385 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2); 2386 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2); 2387 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2); 2388 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2); 2389 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2); 2390 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0); 2391 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0); 2392 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0); 2393 break; 2394 default: 2395 r = amdgpu_discovery_reg_base_init(adev); 2396 if (r) 2397 return -EINVAL; 2398 2399 amdgpu_discovery_harvest_ip(adev); 2400 amdgpu_discovery_get_gfx_info(adev); 2401 amdgpu_discovery_get_mall_info(adev); 2402 amdgpu_discovery_get_vcn_info(adev); 2403 break; 2404 } 2405 2406 amdgpu_discovery_init_soc_config(adev); 2407 amdgpu_discovery_sysfs_init(adev); 2408 2409 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2410 case IP_VERSION(9, 0, 1): 2411 case IP_VERSION(9, 2, 1): 2412 case IP_VERSION(9, 4, 0): 2413 case IP_VERSION(9, 4, 1): 2414 case IP_VERSION(9, 4, 2): 2415 case IP_VERSION(9, 4, 3): 2416 adev->family = AMDGPU_FAMILY_AI; 2417 break; 2418 case IP_VERSION(9, 1, 0): 2419 case IP_VERSION(9, 2, 2): 2420 case IP_VERSION(9, 3, 0): 2421 adev->family = AMDGPU_FAMILY_RV; 2422 break; 2423 case IP_VERSION(10, 1, 10): 2424 case IP_VERSION(10, 1, 1): 2425 case IP_VERSION(10, 1, 2): 2426 case IP_VERSION(10, 1, 3): 2427 case IP_VERSION(10, 1, 4): 2428 case IP_VERSION(10, 3, 0): 2429 case IP_VERSION(10, 3, 2): 2430 case IP_VERSION(10, 3, 4): 2431 case IP_VERSION(10, 3, 5): 2432 adev->family = AMDGPU_FAMILY_NV; 2433 break; 2434 case IP_VERSION(10, 3, 1): 2435 adev->family = AMDGPU_FAMILY_VGH; 2436 adev->apu_flags |= AMD_APU_IS_VANGOGH; 2437 break; 2438 case IP_VERSION(10, 3, 3): 2439 adev->family = AMDGPU_FAMILY_YC; 2440 break; 2441 case IP_VERSION(10, 3, 6): 2442 adev->family = AMDGPU_FAMILY_GC_10_3_6; 2443 break; 2444 case IP_VERSION(10, 3, 7): 2445 adev->family = AMDGPU_FAMILY_GC_10_3_7; 2446 break; 2447 case IP_VERSION(11, 0, 0): 2448 case IP_VERSION(11, 0, 2): 2449 case IP_VERSION(11, 0, 3): 2450 adev->family = AMDGPU_FAMILY_GC_11_0_0; 2451 break; 2452 case IP_VERSION(11, 0, 1): 2453 case IP_VERSION(11, 0, 4): 2454 adev->family = AMDGPU_FAMILY_GC_11_0_1; 2455 break; 2456 case IP_VERSION(11, 5, 0): 2457 adev->family = AMDGPU_FAMILY_GC_11_5_0; 2458 break; 2459 default: 2460 return -EINVAL; 2461 } 2462 2463 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2464 case IP_VERSION(9, 1, 0): 2465 case IP_VERSION(9, 2, 2): 2466 case IP_VERSION(9, 3, 0): 2467 case IP_VERSION(10, 1, 3): 2468 case IP_VERSION(10, 1, 4): 2469 case IP_VERSION(10, 3, 1): 2470 case IP_VERSION(10, 3, 3): 2471 case IP_VERSION(10, 3, 6): 2472 case IP_VERSION(10, 3, 7): 2473 case IP_VERSION(11, 0, 1): 2474 case IP_VERSION(11, 0, 4): 2475 case IP_VERSION(11, 5, 0): 2476 adev->flags |= AMD_IS_APU; 2477 break; 2478 default: 2479 break; 2480 } 2481 2482 if (amdgpu_ip_version(adev, XGMI_HWIP, 0) == IP_VERSION(4, 8, 0)) 2483 adev->gmc.xgmi.supported = true; 2484 2485 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) 2486 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 4, 0); 2487 2488 /* set NBIO version */ 2489 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { 2490 case IP_VERSION(6, 1, 0): 2491 case IP_VERSION(6, 2, 0): 2492 adev->nbio.funcs = &nbio_v6_1_funcs; 2493 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; 2494 break; 2495 case IP_VERSION(7, 0, 0): 2496 case IP_VERSION(7, 0, 1): 2497 case IP_VERSION(2, 5, 0): 2498 adev->nbio.funcs = &nbio_v7_0_funcs; 2499 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; 2500 break; 2501 case IP_VERSION(7, 4, 0): 2502 case IP_VERSION(7, 4, 1): 2503 case IP_VERSION(7, 4, 4): 2504 adev->nbio.funcs = &nbio_v7_4_funcs; 2505 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; 2506 break; 2507 case IP_VERSION(7, 9, 0): 2508 adev->nbio.funcs = &nbio_v7_9_funcs; 2509 adev->nbio.hdp_flush_reg = &nbio_v7_9_hdp_flush_reg; 2510 break; 2511 case IP_VERSION(7, 11, 0): 2512 adev->nbio.funcs = &nbio_v7_11_funcs; 2513 adev->nbio.hdp_flush_reg = &nbio_v7_11_hdp_flush_reg; 2514 break; 2515 case IP_VERSION(7, 2, 0): 2516 case IP_VERSION(7, 2, 1): 2517 case IP_VERSION(7, 3, 0): 2518 case IP_VERSION(7, 5, 0): 2519 case IP_VERSION(7, 5, 1): 2520 adev->nbio.funcs = &nbio_v7_2_funcs; 2521 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; 2522 break; 2523 case IP_VERSION(2, 1, 1): 2524 case IP_VERSION(2, 3, 0): 2525 case IP_VERSION(2, 3, 1): 2526 case IP_VERSION(2, 3, 2): 2527 case IP_VERSION(3, 3, 0): 2528 case IP_VERSION(3, 3, 1): 2529 case IP_VERSION(3, 3, 2): 2530 case IP_VERSION(3, 3, 3): 2531 adev->nbio.funcs = &nbio_v2_3_funcs; 2532 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 2533 break; 2534 case IP_VERSION(4, 3, 0): 2535 case IP_VERSION(4, 3, 1): 2536 if (amdgpu_sriov_vf(adev)) 2537 adev->nbio.funcs = &nbio_v4_3_sriov_funcs; 2538 else 2539 adev->nbio.funcs = &nbio_v4_3_funcs; 2540 adev->nbio.hdp_flush_reg = &nbio_v4_3_hdp_flush_reg; 2541 break; 2542 case IP_VERSION(7, 7, 0): 2543 case IP_VERSION(7, 7, 1): 2544 adev->nbio.funcs = &nbio_v7_7_funcs; 2545 adev->nbio.hdp_flush_reg = &nbio_v7_7_hdp_flush_reg; 2546 break; 2547 default: 2548 break; 2549 } 2550 2551 switch (amdgpu_ip_version(adev, HDP_HWIP, 0)) { 2552 case IP_VERSION(4, 0, 0): 2553 case IP_VERSION(4, 0, 1): 2554 case IP_VERSION(4, 1, 0): 2555 case IP_VERSION(4, 1, 1): 2556 case IP_VERSION(4, 1, 2): 2557 case IP_VERSION(4, 2, 0): 2558 case IP_VERSION(4, 2, 1): 2559 case IP_VERSION(4, 4, 0): 2560 case IP_VERSION(4, 4, 2): 2561 adev->hdp.funcs = &hdp_v4_0_funcs; 2562 break; 2563 case IP_VERSION(5, 0, 0): 2564 case IP_VERSION(5, 0, 1): 2565 case IP_VERSION(5, 0, 2): 2566 case IP_VERSION(5, 0, 3): 2567 case IP_VERSION(5, 0, 4): 2568 case IP_VERSION(5, 2, 0): 2569 adev->hdp.funcs = &hdp_v5_0_funcs; 2570 break; 2571 case IP_VERSION(5, 2, 1): 2572 adev->hdp.funcs = &hdp_v5_2_funcs; 2573 break; 2574 case IP_VERSION(6, 0, 0): 2575 case IP_VERSION(6, 0, 1): 2576 case IP_VERSION(6, 1, 0): 2577 adev->hdp.funcs = &hdp_v6_0_funcs; 2578 break; 2579 case IP_VERSION(7, 0, 0): 2580 adev->hdp.funcs = &hdp_v7_0_funcs; 2581 break; 2582 default: 2583 break; 2584 } 2585 2586 switch (amdgpu_ip_version(adev, DF_HWIP, 0)) { 2587 case IP_VERSION(3, 6, 0): 2588 case IP_VERSION(3, 6, 1): 2589 case IP_VERSION(3, 6, 2): 2590 adev->df.funcs = &df_v3_6_funcs; 2591 break; 2592 case IP_VERSION(2, 1, 0): 2593 case IP_VERSION(2, 1, 1): 2594 case IP_VERSION(2, 5, 0): 2595 case IP_VERSION(3, 5, 1): 2596 case IP_VERSION(3, 5, 2): 2597 adev->df.funcs = &df_v1_7_funcs; 2598 break; 2599 case IP_VERSION(4, 3, 0): 2600 adev->df.funcs = &df_v4_3_funcs; 2601 break; 2602 case IP_VERSION(4, 6, 2): 2603 adev->df.funcs = &df_v4_6_2_funcs; 2604 break; 2605 default: 2606 break; 2607 } 2608 2609 switch (amdgpu_ip_version(adev, SMUIO_HWIP, 0)) { 2610 case IP_VERSION(9, 0, 0): 2611 case IP_VERSION(9, 0, 1): 2612 case IP_VERSION(10, 0, 0): 2613 case IP_VERSION(10, 0, 1): 2614 case IP_VERSION(10, 0, 2): 2615 adev->smuio.funcs = &smuio_v9_0_funcs; 2616 break; 2617 case IP_VERSION(11, 0, 0): 2618 case IP_VERSION(11, 0, 2): 2619 case IP_VERSION(11, 0, 3): 2620 case IP_VERSION(11, 0, 4): 2621 case IP_VERSION(11, 0, 7): 2622 case IP_VERSION(11, 0, 8): 2623 adev->smuio.funcs = &smuio_v11_0_funcs; 2624 break; 2625 case IP_VERSION(11, 0, 6): 2626 case IP_VERSION(11, 0, 10): 2627 case IP_VERSION(11, 0, 11): 2628 case IP_VERSION(11, 5, 0): 2629 case IP_VERSION(13, 0, 1): 2630 case IP_VERSION(13, 0, 9): 2631 case IP_VERSION(13, 0, 10): 2632 adev->smuio.funcs = &smuio_v11_0_6_funcs; 2633 break; 2634 case IP_VERSION(13, 0, 2): 2635 adev->smuio.funcs = &smuio_v13_0_funcs; 2636 break; 2637 case IP_VERSION(13, 0, 3): 2638 adev->smuio.funcs = &smuio_v13_0_3_funcs; 2639 if (adev->smuio.funcs->get_pkg_type(adev) == AMDGPU_PKG_TYPE_APU) { 2640 adev->flags |= AMD_IS_APU; 2641 } 2642 break; 2643 case IP_VERSION(13, 0, 6): 2644 case IP_VERSION(13, 0, 8): 2645 case IP_VERSION(14, 0, 0): 2646 adev->smuio.funcs = &smuio_v13_0_6_funcs; 2647 break; 2648 default: 2649 break; 2650 } 2651 2652 switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) { 2653 case IP_VERSION(6, 0, 0): 2654 case IP_VERSION(6, 0, 1): 2655 case IP_VERSION(6, 0, 2): 2656 case IP_VERSION(6, 0, 3): 2657 adev->lsdma.funcs = &lsdma_v6_0_funcs; 2658 break; 2659 case IP_VERSION(7, 0, 0): 2660 case IP_VERSION(7, 0, 1): 2661 adev->lsdma.funcs = &lsdma_v7_0_funcs; 2662 break; 2663 default: 2664 break; 2665 } 2666 2667 r = amdgpu_discovery_set_common_ip_blocks(adev); 2668 if (r) 2669 return r; 2670 2671 r = amdgpu_discovery_set_gmc_ip_blocks(adev); 2672 if (r) 2673 return r; 2674 2675 /* For SR-IOV, PSP needs to be initialized before IH */ 2676 if (amdgpu_sriov_vf(adev)) { 2677 r = amdgpu_discovery_set_psp_ip_blocks(adev); 2678 if (r) 2679 return r; 2680 r = amdgpu_discovery_set_ih_ip_blocks(adev); 2681 if (r) 2682 return r; 2683 } else { 2684 r = amdgpu_discovery_set_ih_ip_blocks(adev); 2685 if (r) 2686 return r; 2687 2688 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 2689 r = amdgpu_discovery_set_psp_ip_blocks(adev); 2690 if (r) 2691 return r; 2692 } 2693 } 2694 2695 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 2696 r = amdgpu_discovery_set_smu_ip_blocks(adev); 2697 if (r) 2698 return r; 2699 } 2700 2701 r = amdgpu_discovery_set_display_ip_blocks(adev); 2702 if (r) 2703 return r; 2704 2705 r = amdgpu_discovery_set_gc_ip_blocks(adev); 2706 if (r) 2707 return r; 2708 2709 r = amdgpu_discovery_set_sdma_ip_blocks(adev); 2710 if (r) 2711 return r; 2712 2713 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 2714 !amdgpu_sriov_vf(adev)) || 2715 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) { 2716 r = amdgpu_discovery_set_smu_ip_blocks(adev); 2717 if (r) 2718 return r; 2719 } 2720 2721 r = amdgpu_discovery_set_mm_ip_blocks(adev); 2722 if (r) 2723 return r; 2724 2725 r = amdgpu_discovery_set_mes_ip_blocks(adev); 2726 if (r) 2727 return r; 2728 2729 r = amdgpu_discovery_set_vpe_ip_blocks(adev); 2730 if (r) 2731 return r; 2732 2733 r = amdgpu_discovery_set_umsch_mm_ip_blocks(adev); 2734 if (r) 2735 return r; 2736 2737 return 0; 2738 } 2739 2740