1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_discovery.h" 28 #include "soc15_hw_ip.h" 29 #include "discovery.h" 30 31 #include "soc15.h" 32 #include "gfx_v9_0.h" 33 #include "gfx_v9_4_3.h" 34 #include "gmc_v9_0.h" 35 #include "df_v1_7.h" 36 #include "df_v3_6.h" 37 #include "df_v4_3.h" 38 #include "nbio_v6_1.h" 39 #include "nbio_v7_0.h" 40 #include "nbio_v7_4.h" 41 #include "nbio_v7_9.h" 42 #include "nbio_v7_11.h" 43 #include "hdp_v4_0.h" 44 #include "vega10_ih.h" 45 #include "vega20_ih.h" 46 #include "sdma_v4_0.h" 47 #include "sdma_v4_4_2.h" 48 #include "uvd_v7_0.h" 49 #include "vce_v4_0.h" 50 #include "vcn_v1_0.h" 51 #include "vcn_v2_5.h" 52 #include "jpeg_v2_5.h" 53 #include "smuio_v9_0.h" 54 #include "gmc_v10_0.h" 55 #include "gmc_v11_0.h" 56 #include "gfxhub_v2_0.h" 57 #include "mmhub_v2_0.h" 58 #include "nbio_v2_3.h" 59 #include "nbio_v4_3.h" 60 #include "nbio_v7_2.h" 61 #include "nbio_v7_7.h" 62 #include "hdp_v5_0.h" 63 #include "hdp_v5_2.h" 64 #include "hdp_v6_0.h" 65 #include "nv.h" 66 #include "soc21.h" 67 #include "navi10_ih.h" 68 #include "ih_v6_0.h" 69 #include "ih_v6_1.h" 70 #include "gfx_v10_0.h" 71 #include "gfx_v11_0.h" 72 #include "sdma_v5_0.h" 73 #include "sdma_v5_2.h" 74 #include "sdma_v6_0.h" 75 #include "lsdma_v6_0.h" 76 #include "vcn_v2_0.h" 77 #include "jpeg_v2_0.h" 78 #include "vcn_v3_0.h" 79 #include "jpeg_v3_0.h" 80 #include "vcn_v4_0.h" 81 #include "jpeg_v4_0.h" 82 #include "vcn_v4_0_3.h" 83 #include "jpeg_v4_0_3.h" 84 #include "amdgpu_vkms.h" 85 #include "mes_v10_1.h" 86 #include "mes_v11_0.h" 87 #include "smuio_v11_0.h" 88 #include "smuio_v11_0_6.h" 89 #include "smuio_v13_0.h" 90 #include "smuio_v13_0_3.h" 91 #include "smuio_v13_0_6.h" 92 93 #define FIRMWARE_IP_DISCOVERY "amdgpu/ip_discovery.bin" 94 MODULE_FIRMWARE(FIRMWARE_IP_DISCOVERY); 95 96 #define mmRCC_CONFIG_MEMSIZE 0xde3 97 #define mmMM_INDEX 0x0 98 #define mmMM_INDEX_HI 0x6 99 #define mmMM_DATA 0x1 100 101 static const char *hw_id_names[HW_ID_MAX] = { 102 [MP1_HWID] = "MP1", 103 [MP2_HWID] = "MP2", 104 [THM_HWID] = "THM", 105 [SMUIO_HWID] = "SMUIO", 106 [FUSE_HWID] = "FUSE", 107 [CLKA_HWID] = "CLKA", 108 [PWR_HWID] = "PWR", 109 [GC_HWID] = "GC", 110 [UVD_HWID] = "UVD", 111 [AUDIO_AZ_HWID] = "AUDIO_AZ", 112 [ACP_HWID] = "ACP", 113 [DCI_HWID] = "DCI", 114 [DMU_HWID] = "DMU", 115 [DCO_HWID] = "DCO", 116 [DIO_HWID] = "DIO", 117 [XDMA_HWID] = "XDMA", 118 [DCEAZ_HWID] = "DCEAZ", 119 [DAZ_HWID] = "DAZ", 120 [SDPMUX_HWID] = "SDPMUX", 121 [NTB_HWID] = "NTB", 122 [IOHC_HWID] = "IOHC", 123 [L2IMU_HWID] = "L2IMU", 124 [VCE_HWID] = "VCE", 125 [MMHUB_HWID] = "MMHUB", 126 [ATHUB_HWID] = "ATHUB", 127 [DBGU_NBIO_HWID] = "DBGU_NBIO", 128 [DFX_HWID] = "DFX", 129 [DBGU0_HWID] = "DBGU0", 130 [DBGU1_HWID] = "DBGU1", 131 [OSSSYS_HWID] = "OSSSYS", 132 [HDP_HWID] = "HDP", 133 [SDMA0_HWID] = "SDMA0", 134 [SDMA1_HWID] = "SDMA1", 135 [SDMA2_HWID] = "SDMA2", 136 [SDMA3_HWID] = "SDMA3", 137 [LSDMA_HWID] = "LSDMA", 138 [ISP_HWID] = "ISP", 139 [DBGU_IO_HWID] = "DBGU_IO", 140 [DF_HWID] = "DF", 141 [CLKB_HWID] = "CLKB", 142 [FCH_HWID] = "FCH", 143 [DFX_DAP_HWID] = "DFX_DAP", 144 [L1IMU_PCIE_HWID] = "L1IMU_PCIE", 145 [L1IMU_NBIF_HWID] = "L1IMU_NBIF", 146 [L1IMU_IOAGR_HWID] = "L1IMU_IOAGR", 147 [L1IMU3_HWID] = "L1IMU3", 148 [L1IMU4_HWID] = "L1IMU4", 149 [L1IMU5_HWID] = "L1IMU5", 150 [L1IMU6_HWID] = "L1IMU6", 151 [L1IMU7_HWID] = "L1IMU7", 152 [L1IMU8_HWID] = "L1IMU8", 153 [L1IMU9_HWID] = "L1IMU9", 154 [L1IMU10_HWID] = "L1IMU10", 155 [L1IMU11_HWID] = "L1IMU11", 156 [L1IMU12_HWID] = "L1IMU12", 157 [L1IMU13_HWID] = "L1IMU13", 158 [L1IMU14_HWID] = "L1IMU14", 159 [L1IMU15_HWID] = "L1IMU15", 160 [WAFLC_HWID] = "WAFLC", 161 [FCH_USB_PD_HWID] = "FCH_USB_PD", 162 [PCIE_HWID] = "PCIE", 163 [PCS_HWID] = "PCS", 164 [DDCL_HWID] = "DDCL", 165 [SST_HWID] = "SST", 166 [IOAGR_HWID] = "IOAGR", 167 [NBIF_HWID] = "NBIF", 168 [IOAPIC_HWID] = "IOAPIC", 169 [SYSTEMHUB_HWID] = "SYSTEMHUB", 170 [NTBCCP_HWID] = "NTBCCP", 171 [UMC_HWID] = "UMC", 172 [SATA_HWID] = "SATA", 173 [USB_HWID] = "USB", 174 [CCXSEC_HWID] = "CCXSEC", 175 [XGMI_HWID] = "XGMI", 176 [XGBE_HWID] = "XGBE", 177 [MP0_HWID] = "MP0", 178 }; 179 180 static int hw_id_map[MAX_HWIP] = { 181 [GC_HWIP] = GC_HWID, 182 [HDP_HWIP] = HDP_HWID, 183 [SDMA0_HWIP] = SDMA0_HWID, 184 [SDMA1_HWIP] = SDMA1_HWID, 185 [SDMA2_HWIP] = SDMA2_HWID, 186 [SDMA3_HWIP] = SDMA3_HWID, 187 [LSDMA_HWIP] = LSDMA_HWID, 188 [MMHUB_HWIP] = MMHUB_HWID, 189 [ATHUB_HWIP] = ATHUB_HWID, 190 [NBIO_HWIP] = NBIF_HWID, 191 [MP0_HWIP] = MP0_HWID, 192 [MP1_HWIP] = MP1_HWID, 193 [UVD_HWIP] = UVD_HWID, 194 [VCE_HWIP] = VCE_HWID, 195 [DF_HWIP] = DF_HWID, 196 [DCE_HWIP] = DMU_HWID, 197 [OSSSYS_HWIP] = OSSSYS_HWID, 198 [SMUIO_HWIP] = SMUIO_HWID, 199 [PWR_HWIP] = PWR_HWID, 200 [NBIF_HWIP] = NBIF_HWID, 201 [THM_HWIP] = THM_HWID, 202 [CLK_HWIP] = CLKA_HWID, 203 [UMC_HWIP] = UMC_HWID, 204 [XGMI_HWIP] = XGMI_HWID, 205 [DCI_HWIP] = DCI_HWID, 206 [PCIE_HWIP] = PCIE_HWID, 207 }; 208 209 static int amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device *adev, uint8_t *binary) 210 { 211 u64 tmr_offset, tmr_size, pos; 212 void *discv_regn; 213 int ret; 214 215 ret = amdgpu_acpi_get_tmr_info(adev, &tmr_offset, &tmr_size); 216 if (ret) 217 return ret; 218 219 pos = tmr_offset + tmr_size - DISCOVERY_TMR_OFFSET; 220 221 /* This region is read-only and reserved from system use */ 222 discv_regn = memremap(pos, adev->mman.discovery_tmr_size, MEMREMAP_WC); 223 if (discv_regn) { 224 memcpy(binary, discv_regn, adev->mman.discovery_tmr_size); 225 memunmap(discv_regn); 226 return 0; 227 } 228 229 return -ENOENT; 230 } 231 232 static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev, 233 uint8_t *binary) 234 { 235 uint64_t vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20; 236 int ret = 0; 237 238 if (vram_size) { 239 uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET; 240 amdgpu_device_vram_access(adev, pos, (uint32_t *)binary, 241 adev->mman.discovery_tmr_size, false); 242 } else { 243 ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary); 244 } 245 246 return ret; 247 } 248 249 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, uint8_t *binary) 250 { 251 const struct firmware *fw; 252 const char *fw_name; 253 int r; 254 255 switch (amdgpu_discovery) { 256 case 2: 257 fw_name = FIRMWARE_IP_DISCOVERY; 258 break; 259 default: 260 dev_warn(adev->dev, "amdgpu_discovery is not set properly\n"); 261 return -EINVAL; 262 } 263 264 r = request_firmware(&fw, fw_name, adev->dev); 265 if (r) { 266 dev_err(adev->dev, "can't load firmware \"%s\"\n", 267 fw_name); 268 return r; 269 } 270 271 memcpy((u8 *)binary, (u8 *)fw->data, fw->size); 272 release_firmware(fw); 273 274 return 0; 275 } 276 277 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size) 278 { 279 uint16_t checksum = 0; 280 int i; 281 282 for (i = 0; i < size; i++) 283 checksum += data[i]; 284 285 return checksum; 286 } 287 288 static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size, 289 uint16_t expected) 290 { 291 return !!(amdgpu_discovery_calculate_checksum(data, size) == expected); 292 } 293 294 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary) 295 { 296 struct binary_header *bhdr; 297 bhdr = (struct binary_header *)binary; 298 299 return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE); 300 } 301 302 static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev) 303 { 304 /* 305 * So far, apply this quirk only on those Navy Flounder boards which 306 * have a bad harvest table of VCN config. 307 */ 308 if ((adev->ip_versions[UVD_HWIP][1] == IP_VERSION(3, 0, 1)) && 309 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 2))) { 310 switch (adev->pdev->revision) { 311 case 0xC1: 312 case 0xC2: 313 case 0xC3: 314 case 0xC5: 315 case 0xC7: 316 case 0xCF: 317 case 0xDF: 318 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 319 adev->vcn.inst_mask &= ~AMDGPU_VCN_HARVEST_VCN1; 320 break; 321 default: 322 break; 323 } 324 } 325 } 326 327 static int amdgpu_discovery_init(struct amdgpu_device *adev) 328 { 329 struct table_info *info; 330 struct binary_header *bhdr; 331 uint16_t offset; 332 uint16_t size; 333 uint16_t checksum; 334 int r; 335 336 adev->mman.discovery_tmr_size = DISCOVERY_TMR_SIZE; 337 adev->mman.discovery_bin = kzalloc(adev->mman.discovery_tmr_size, GFP_KERNEL); 338 if (!adev->mman.discovery_bin) 339 return -ENOMEM; 340 341 /* Read from file if it is the preferred option */ 342 if (amdgpu_discovery == 2) { 343 dev_info(adev->dev, "use ip discovery information from file"); 344 r = amdgpu_discovery_read_binary_from_file(adev, adev->mman.discovery_bin); 345 346 if (r) { 347 dev_err(adev->dev, "failed to read ip discovery binary from file\n"); 348 r = -EINVAL; 349 goto out; 350 } 351 352 } else { 353 r = amdgpu_discovery_read_binary_from_mem( 354 adev, adev->mman.discovery_bin); 355 if (r) 356 goto out; 357 } 358 359 /* check the ip discovery binary signature */ 360 if (!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) { 361 dev_err(adev->dev, 362 "get invalid ip discovery binary signature\n"); 363 r = -EINVAL; 364 goto out; 365 } 366 367 bhdr = (struct binary_header *)adev->mman.discovery_bin; 368 369 offset = offsetof(struct binary_header, binary_checksum) + 370 sizeof(bhdr->binary_checksum); 371 size = le16_to_cpu(bhdr->binary_size) - offset; 372 checksum = le16_to_cpu(bhdr->binary_checksum); 373 374 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 375 size, checksum)) { 376 dev_err(adev->dev, "invalid ip discovery binary checksum\n"); 377 r = -EINVAL; 378 goto out; 379 } 380 381 info = &bhdr->table_list[IP_DISCOVERY]; 382 offset = le16_to_cpu(info->offset); 383 checksum = le16_to_cpu(info->checksum); 384 385 if (offset) { 386 struct ip_discovery_header *ihdr = 387 (struct ip_discovery_header *)(adev->mman.discovery_bin + offset); 388 if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) { 389 dev_err(adev->dev, "invalid ip discovery data table signature\n"); 390 r = -EINVAL; 391 goto out; 392 } 393 394 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 395 le16_to_cpu(ihdr->size), checksum)) { 396 dev_err(adev->dev, "invalid ip discovery data table checksum\n"); 397 r = -EINVAL; 398 goto out; 399 } 400 } 401 402 info = &bhdr->table_list[GC]; 403 offset = le16_to_cpu(info->offset); 404 checksum = le16_to_cpu(info->checksum); 405 406 if (offset) { 407 struct gpu_info_header *ghdr = 408 (struct gpu_info_header *)(adev->mman.discovery_bin + offset); 409 410 if (le32_to_cpu(ghdr->table_id) != GC_TABLE_ID) { 411 dev_err(adev->dev, "invalid ip discovery gc table id\n"); 412 r = -EINVAL; 413 goto out; 414 } 415 416 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 417 le32_to_cpu(ghdr->size), checksum)) { 418 dev_err(adev->dev, "invalid gc data table checksum\n"); 419 r = -EINVAL; 420 goto out; 421 } 422 } 423 424 info = &bhdr->table_list[HARVEST_INFO]; 425 offset = le16_to_cpu(info->offset); 426 checksum = le16_to_cpu(info->checksum); 427 428 if (offset) { 429 struct harvest_info_header *hhdr = 430 (struct harvest_info_header *)(adev->mman.discovery_bin + offset); 431 432 if (le32_to_cpu(hhdr->signature) != HARVEST_TABLE_SIGNATURE) { 433 dev_err(adev->dev, "invalid ip discovery harvest table signature\n"); 434 r = -EINVAL; 435 goto out; 436 } 437 438 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 439 sizeof(struct harvest_table), checksum)) { 440 dev_err(adev->dev, "invalid harvest data table checksum\n"); 441 r = -EINVAL; 442 goto out; 443 } 444 } 445 446 info = &bhdr->table_list[VCN_INFO]; 447 offset = le16_to_cpu(info->offset); 448 checksum = le16_to_cpu(info->checksum); 449 450 if (offset) { 451 struct vcn_info_header *vhdr = 452 (struct vcn_info_header *)(adev->mman.discovery_bin + offset); 453 454 if (le32_to_cpu(vhdr->table_id) != VCN_INFO_TABLE_ID) { 455 dev_err(adev->dev, "invalid ip discovery vcn table id\n"); 456 r = -EINVAL; 457 goto out; 458 } 459 460 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 461 le32_to_cpu(vhdr->size_bytes), checksum)) { 462 dev_err(adev->dev, "invalid vcn data table checksum\n"); 463 r = -EINVAL; 464 goto out; 465 } 466 } 467 468 info = &bhdr->table_list[MALL_INFO]; 469 offset = le16_to_cpu(info->offset); 470 checksum = le16_to_cpu(info->checksum); 471 472 if (0 && offset) { 473 struct mall_info_header *mhdr = 474 (struct mall_info_header *)(adev->mman.discovery_bin + offset); 475 476 if (le32_to_cpu(mhdr->table_id) != MALL_INFO_TABLE_ID) { 477 dev_err(adev->dev, "invalid ip discovery mall table id\n"); 478 r = -EINVAL; 479 goto out; 480 } 481 482 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 483 le32_to_cpu(mhdr->size_bytes), checksum)) { 484 dev_err(adev->dev, "invalid mall data table checksum\n"); 485 r = -EINVAL; 486 goto out; 487 } 488 } 489 490 return 0; 491 492 out: 493 kfree(adev->mman.discovery_bin); 494 adev->mman.discovery_bin = NULL; 495 496 return r; 497 } 498 499 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev); 500 501 void amdgpu_discovery_fini(struct amdgpu_device *adev) 502 { 503 amdgpu_discovery_sysfs_fini(adev); 504 kfree(adev->mman.discovery_bin); 505 adev->mman.discovery_bin = NULL; 506 } 507 508 static int amdgpu_discovery_validate_ip(const struct ip_v4 *ip) 509 { 510 if (ip->instance_number >= HWIP_MAX_INSTANCE) { 511 DRM_ERROR("Unexpected instance_number (%d) from ip discovery blob\n", 512 ip->instance_number); 513 return -EINVAL; 514 } 515 if (le16_to_cpu(ip->hw_id) >= HW_ID_MAX) { 516 DRM_ERROR("Unexpected hw_id (%d) from ip discovery blob\n", 517 le16_to_cpu(ip->hw_id)); 518 return -EINVAL; 519 } 520 521 return 0; 522 } 523 524 static void amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device *adev, 525 uint32_t *vcn_harvest_count) 526 { 527 struct binary_header *bhdr; 528 struct ip_discovery_header *ihdr; 529 struct die_header *dhdr; 530 struct ip_v4 *ip; 531 uint16_t die_offset, ip_offset, num_dies, num_ips; 532 int i, j; 533 534 bhdr = (struct binary_header *)adev->mman.discovery_bin; 535 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 536 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 537 num_dies = le16_to_cpu(ihdr->num_dies); 538 539 /* scan harvest bit of all IP data structures */ 540 for (i = 0; i < num_dies; i++) { 541 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 542 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 543 num_ips = le16_to_cpu(dhdr->num_ips); 544 ip_offset = die_offset + sizeof(*dhdr); 545 546 for (j = 0; j < num_ips; j++) { 547 ip = (struct ip_v4 *)(adev->mman.discovery_bin + ip_offset); 548 549 if (amdgpu_discovery_validate_ip(ip)) 550 goto next_ip; 551 552 if (le16_to_cpu(ip->variant) == 1) { 553 switch (le16_to_cpu(ip->hw_id)) { 554 case VCN_HWID: 555 (*vcn_harvest_count)++; 556 if (ip->instance_number == 0) { 557 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0; 558 adev->vcn.inst_mask &= 559 ~AMDGPU_VCN_HARVEST_VCN0; 560 adev->jpeg.inst_mask &= 561 ~AMDGPU_VCN_HARVEST_VCN0; 562 } else { 563 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 564 adev->vcn.inst_mask &= 565 ~AMDGPU_VCN_HARVEST_VCN1; 566 adev->jpeg.inst_mask &= 567 ~AMDGPU_VCN_HARVEST_VCN1; 568 } 569 break; 570 case DMU_HWID: 571 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 572 break; 573 default: 574 break; 575 } 576 } 577 next_ip: 578 if (ihdr->base_addr_64_bit) 579 ip_offset += struct_size(ip, base_address_64, ip->num_base_address); 580 else 581 ip_offset += struct_size(ip, base_address, ip->num_base_address); 582 } 583 } 584 } 585 586 static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev, 587 uint32_t *vcn_harvest_count, 588 uint32_t *umc_harvest_count) 589 { 590 struct binary_header *bhdr; 591 struct harvest_table *harvest_info; 592 u16 offset; 593 int i; 594 uint32_t umc_harvest_config = 0; 595 596 bhdr = (struct binary_header *)adev->mman.discovery_bin; 597 offset = le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset); 598 599 if (!offset) { 600 dev_err(adev->dev, "invalid harvest table offset\n"); 601 return; 602 } 603 604 harvest_info = (struct harvest_table *)(adev->mman.discovery_bin + offset); 605 606 for (i = 0; i < 32; i++) { 607 if (le16_to_cpu(harvest_info->list[i].hw_id) == 0) 608 break; 609 610 switch (le16_to_cpu(harvest_info->list[i].hw_id)) { 611 case VCN_HWID: 612 (*vcn_harvest_count)++; 613 adev->vcn.harvest_config |= 614 (1 << harvest_info->list[i].number_instance); 615 adev->jpeg.harvest_config |= 616 (1 << harvest_info->list[i].number_instance); 617 618 adev->vcn.inst_mask &= 619 ~(1U << harvest_info->list[i].number_instance); 620 adev->jpeg.inst_mask &= 621 ~(1U << harvest_info->list[i].number_instance); 622 break; 623 case DMU_HWID: 624 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 625 break; 626 case UMC_HWID: 627 umc_harvest_config |= 628 1 << (le16_to_cpu(harvest_info->list[i].number_instance)); 629 (*umc_harvest_count)++; 630 break; 631 case GC_HWID: 632 adev->gfx.xcc_mask &= 633 ~(1U << harvest_info->list[i].number_instance); 634 break; 635 case SDMA0_HWID: 636 adev->sdma.sdma_mask &= 637 ~(1U << harvest_info->list[i].number_instance); 638 break; 639 default: 640 break; 641 } 642 } 643 644 adev->umc.active_mask = ((1 << adev->umc.node_inst_num) - 1) & 645 ~umc_harvest_config; 646 } 647 648 /* ================================================== */ 649 650 struct ip_hw_instance { 651 struct kobject kobj; /* ip_discovery/die/#die/#hw_id/#instance/<attrs...> */ 652 653 int hw_id; 654 u8 num_instance; 655 u8 major, minor, revision; 656 u8 harvest; 657 658 int num_base_addresses; 659 u32 base_addr[]; 660 }; 661 662 struct ip_hw_id { 663 struct kset hw_id_kset; /* ip_discovery/die/#die/#hw_id/, contains ip_hw_instance */ 664 int hw_id; 665 }; 666 667 struct ip_die_entry { 668 struct kset ip_kset; /* ip_discovery/die/#die/, contains ip_hw_id */ 669 u16 num_ips; 670 }; 671 672 /* -------------------------------------------------- */ 673 674 struct ip_hw_instance_attr { 675 struct attribute attr; 676 ssize_t (*show)(struct ip_hw_instance *ip_hw_instance, char *buf); 677 }; 678 679 static ssize_t hw_id_show(struct ip_hw_instance *ip_hw_instance, char *buf) 680 { 681 return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id); 682 } 683 684 static ssize_t num_instance_show(struct ip_hw_instance *ip_hw_instance, char *buf) 685 { 686 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance); 687 } 688 689 static ssize_t major_show(struct ip_hw_instance *ip_hw_instance, char *buf) 690 { 691 return sysfs_emit(buf, "%d\n", ip_hw_instance->major); 692 } 693 694 static ssize_t minor_show(struct ip_hw_instance *ip_hw_instance, char *buf) 695 { 696 return sysfs_emit(buf, "%d\n", ip_hw_instance->minor); 697 } 698 699 static ssize_t revision_show(struct ip_hw_instance *ip_hw_instance, char *buf) 700 { 701 return sysfs_emit(buf, "%d\n", ip_hw_instance->revision); 702 } 703 704 static ssize_t harvest_show(struct ip_hw_instance *ip_hw_instance, char *buf) 705 { 706 return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest); 707 } 708 709 static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, char *buf) 710 { 711 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses); 712 } 713 714 static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf) 715 { 716 ssize_t res, at; 717 int ii; 718 719 for (res = at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) { 720 /* Here we satisfy the condition that, at + size <= PAGE_SIZE. 721 */ 722 if (at + 12 > PAGE_SIZE) 723 break; 724 res = sysfs_emit_at(buf, at, "0x%08X\n", 725 ip_hw_instance->base_addr[ii]); 726 if (res <= 0) 727 break; 728 at += res; 729 } 730 731 return res < 0 ? res : at; 732 } 733 734 static struct ip_hw_instance_attr ip_hw_attr[] = { 735 __ATTR_RO(hw_id), 736 __ATTR_RO(num_instance), 737 __ATTR_RO(major), 738 __ATTR_RO(minor), 739 __ATTR_RO(revision), 740 __ATTR_RO(harvest), 741 __ATTR_RO(num_base_addresses), 742 __ATTR_RO(base_addr), 743 }; 744 745 static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1]; 746 ATTRIBUTE_GROUPS(ip_hw_instance); 747 748 #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj) 749 #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr) 750 751 static ssize_t ip_hw_instance_attr_show(struct kobject *kobj, 752 struct attribute *attr, 753 char *buf) 754 { 755 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 756 struct ip_hw_instance_attr *ip_hw_attr = to_ip_hw_instance_attr(attr); 757 758 if (!ip_hw_attr->show) 759 return -EIO; 760 761 return ip_hw_attr->show(ip_hw_instance, buf); 762 } 763 764 static const struct sysfs_ops ip_hw_instance_sysfs_ops = { 765 .show = ip_hw_instance_attr_show, 766 }; 767 768 static void ip_hw_instance_release(struct kobject *kobj) 769 { 770 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 771 772 kfree(ip_hw_instance); 773 } 774 775 static const struct kobj_type ip_hw_instance_ktype = { 776 .release = ip_hw_instance_release, 777 .sysfs_ops = &ip_hw_instance_sysfs_ops, 778 .default_groups = ip_hw_instance_groups, 779 }; 780 781 /* -------------------------------------------------- */ 782 783 #define to_ip_hw_id(x) container_of(to_kset(x), struct ip_hw_id, hw_id_kset) 784 785 static void ip_hw_id_release(struct kobject *kobj) 786 { 787 struct ip_hw_id *ip_hw_id = to_ip_hw_id(kobj); 788 789 if (!list_empty(&ip_hw_id->hw_id_kset.list)) 790 DRM_ERROR("ip_hw_id->hw_id_kset is not empty"); 791 kfree(ip_hw_id); 792 } 793 794 static const struct kobj_type ip_hw_id_ktype = { 795 .release = ip_hw_id_release, 796 .sysfs_ops = &kobj_sysfs_ops, 797 }; 798 799 /* -------------------------------------------------- */ 800 801 static void die_kobj_release(struct kobject *kobj); 802 static void ip_disc_release(struct kobject *kobj); 803 804 struct ip_die_entry_attribute { 805 struct attribute attr; 806 ssize_t (*show)(struct ip_die_entry *ip_die_entry, char *buf); 807 }; 808 809 #define to_ip_die_entry_attr(x) container_of(x, struct ip_die_entry_attribute, attr) 810 811 static ssize_t num_ips_show(struct ip_die_entry *ip_die_entry, char *buf) 812 { 813 return sysfs_emit(buf, "%d\n", ip_die_entry->num_ips); 814 } 815 816 /* If there are more ip_die_entry attrs, other than the number of IPs, 817 * we can make this intro an array of attrs, and then initialize 818 * ip_die_entry_attrs in a loop. 819 */ 820 static struct ip_die_entry_attribute num_ips_attr = 821 __ATTR_RO(num_ips); 822 823 static struct attribute *ip_die_entry_attrs[] = { 824 &num_ips_attr.attr, 825 NULL, 826 }; 827 ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */ 828 829 #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset) 830 831 static ssize_t ip_die_entry_attr_show(struct kobject *kobj, 832 struct attribute *attr, 833 char *buf) 834 { 835 struct ip_die_entry_attribute *ip_die_entry_attr = to_ip_die_entry_attr(attr); 836 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 837 838 if (!ip_die_entry_attr->show) 839 return -EIO; 840 841 return ip_die_entry_attr->show(ip_die_entry, buf); 842 } 843 844 static void ip_die_entry_release(struct kobject *kobj) 845 { 846 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 847 848 if (!list_empty(&ip_die_entry->ip_kset.list)) 849 DRM_ERROR("ip_die_entry->ip_kset is not empty"); 850 kfree(ip_die_entry); 851 } 852 853 static const struct sysfs_ops ip_die_entry_sysfs_ops = { 854 .show = ip_die_entry_attr_show, 855 }; 856 857 static const struct kobj_type ip_die_entry_ktype = { 858 .release = ip_die_entry_release, 859 .sysfs_ops = &ip_die_entry_sysfs_ops, 860 .default_groups = ip_die_entry_groups, 861 }; 862 863 static const struct kobj_type die_kobj_ktype = { 864 .release = die_kobj_release, 865 .sysfs_ops = &kobj_sysfs_ops, 866 }; 867 868 static const struct kobj_type ip_discovery_ktype = { 869 .release = ip_disc_release, 870 .sysfs_ops = &kobj_sysfs_ops, 871 }; 872 873 struct ip_discovery_top { 874 struct kobject kobj; /* ip_discovery/ */ 875 struct kset die_kset; /* ip_discovery/die/, contains ip_die_entry */ 876 struct amdgpu_device *adev; 877 }; 878 879 static void die_kobj_release(struct kobject *kobj) 880 { 881 struct ip_discovery_top *ip_top = container_of(to_kset(kobj), 882 struct ip_discovery_top, 883 die_kset); 884 if (!list_empty(&ip_top->die_kset.list)) 885 DRM_ERROR("ip_top->die_kset is not empty"); 886 } 887 888 static void ip_disc_release(struct kobject *kobj) 889 { 890 struct ip_discovery_top *ip_top = container_of(kobj, struct ip_discovery_top, 891 kobj); 892 struct amdgpu_device *adev = ip_top->adev; 893 894 adev->ip_top = NULL; 895 kfree(ip_top); 896 } 897 898 static uint8_t amdgpu_discovery_get_harvest_info(struct amdgpu_device *adev, 899 uint16_t hw_id, uint8_t inst) 900 { 901 uint8_t harvest = 0; 902 903 /* Until a uniform way is figured, get mask based on hwid */ 904 switch (hw_id) { 905 case VCN_HWID: 906 harvest = ((1 << inst) & adev->vcn.inst_mask) == 0; 907 break; 908 case DMU_HWID: 909 if (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK) 910 harvest = 0x1; 911 break; 912 case UMC_HWID: 913 /* TODO: It needs another parsing; for now, ignore.*/ 914 break; 915 case GC_HWID: 916 harvest = ((1 << inst) & adev->gfx.xcc_mask) == 0; 917 break; 918 case SDMA0_HWID: 919 harvest = ((1 << inst) & adev->sdma.sdma_mask) == 0; 920 break; 921 default: 922 break; 923 } 924 925 return harvest; 926 } 927 928 static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev, 929 struct ip_die_entry *ip_die_entry, 930 const size_t _ip_offset, const int num_ips, 931 bool reg_base_64) 932 { 933 int ii, jj, kk, res; 934 935 DRM_DEBUG("num_ips:%d", num_ips); 936 937 /* Find all IPs of a given HW ID, and add their instance to 938 * #die/#hw_id/#instance/<attributes> 939 */ 940 for (ii = 0; ii < HW_ID_MAX; ii++) { 941 struct ip_hw_id *ip_hw_id = NULL; 942 size_t ip_offset = _ip_offset; 943 944 for (jj = 0; jj < num_ips; jj++) { 945 struct ip_v4 *ip; 946 struct ip_hw_instance *ip_hw_instance; 947 948 ip = (struct ip_v4 *)(adev->mman.discovery_bin + ip_offset); 949 if (amdgpu_discovery_validate_ip(ip) || 950 le16_to_cpu(ip->hw_id) != ii) 951 goto next_ip; 952 953 DRM_DEBUG("match:%d @ ip_offset:%zu", ii, ip_offset); 954 955 /* We have a hw_id match; register the hw 956 * block if not yet registered. 957 */ 958 if (!ip_hw_id) { 959 ip_hw_id = kzalloc(sizeof(*ip_hw_id), GFP_KERNEL); 960 if (!ip_hw_id) 961 return -ENOMEM; 962 ip_hw_id->hw_id = ii; 963 964 kobject_set_name(&ip_hw_id->hw_id_kset.kobj, "%d", ii); 965 ip_hw_id->hw_id_kset.kobj.kset = &ip_die_entry->ip_kset; 966 ip_hw_id->hw_id_kset.kobj.ktype = &ip_hw_id_ktype; 967 res = kset_register(&ip_hw_id->hw_id_kset); 968 if (res) { 969 DRM_ERROR("Couldn't register ip_hw_id kset"); 970 kfree(ip_hw_id); 971 return res; 972 } 973 if (hw_id_names[ii]) { 974 res = sysfs_create_link(&ip_die_entry->ip_kset.kobj, 975 &ip_hw_id->hw_id_kset.kobj, 976 hw_id_names[ii]); 977 if (res) { 978 DRM_ERROR("Couldn't create IP link %s in IP Die:%s\n", 979 hw_id_names[ii], 980 kobject_name(&ip_die_entry->ip_kset.kobj)); 981 } 982 } 983 } 984 985 /* Now register its instance. 986 */ 987 ip_hw_instance = kzalloc(struct_size(ip_hw_instance, 988 base_addr, 989 ip->num_base_address), 990 GFP_KERNEL); 991 if (!ip_hw_instance) { 992 DRM_ERROR("no memory for ip_hw_instance"); 993 return -ENOMEM; 994 } 995 ip_hw_instance->hw_id = le16_to_cpu(ip->hw_id); /* == ii */ 996 ip_hw_instance->num_instance = ip->instance_number; 997 ip_hw_instance->major = ip->major; 998 ip_hw_instance->minor = ip->minor; 999 ip_hw_instance->revision = ip->revision; 1000 ip_hw_instance->harvest = 1001 amdgpu_discovery_get_harvest_info( 1002 adev, ip_hw_instance->hw_id, 1003 ip_hw_instance->num_instance); 1004 ip_hw_instance->num_base_addresses = ip->num_base_address; 1005 1006 for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++) { 1007 if (reg_base_64) 1008 ip_hw_instance->base_addr[kk] = 1009 lower_32_bits(le64_to_cpu(ip->base_address_64[kk])) & 0x3FFFFFFF; 1010 else 1011 ip_hw_instance->base_addr[kk] = ip->base_address[kk]; 1012 } 1013 1014 kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype); 1015 ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset; 1016 res = kobject_add(&ip_hw_instance->kobj, NULL, 1017 "%d", ip_hw_instance->num_instance); 1018 next_ip: 1019 if (reg_base_64) 1020 ip_offset += struct_size(ip, base_address_64, 1021 ip->num_base_address); 1022 else 1023 ip_offset += struct_size(ip, base_address, 1024 ip->num_base_address); 1025 } 1026 } 1027 1028 return 0; 1029 } 1030 1031 static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev) 1032 { 1033 struct binary_header *bhdr; 1034 struct ip_discovery_header *ihdr; 1035 struct die_header *dhdr; 1036 struct kset *die_kset = &adev->ip_top->die_kset; 1037 u16 num_dies, die_offset, num_ips; 1038 size_t ip_offset; 1039 int ii, res; 1040 1041 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1042 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 1043 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 1044 num_dies = le16_to_cpu(ihdr->num_dies); 1045 1046 DRM_DEBUG("number of dies: %d\n", num_dies); 1047 1048 for (ii = 0; ii < num_dies; ii++) { 1049 struct ip_die_entry *ip_die_entry; 1050 1051 die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset); 1052 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 1053 num_ips = le16_to_cpu(dhdr->num_ips); 1054 ip_offset = die_offset + sizeof(*dhdr); 1055 1056 /* Add the die to the kset. 1057 * 1058 * dhdr->die_id == ii, which was checked in 1059 * amdgpu_discovery_reg_base_init(). 1060 */ 1061 1062 ip_die_entry = kzalloc(sizeof(*ip_die_entry), GFP_KERNEL); 1063 if (!ip_die_entry) 1064 return -ENOMEM; 1065 1066 ip_die_entry->num_ips = num_ips; 1067 1068 kobject_set_name(&ip_die_entry->ip_kset.kobj, "%d", le16_to_cpu(dhdr->die_id)); 1069 ip_die_entry->ip_kset.kobj.kset = die_kset; 1070 ip_die_entry->ip_kset.kobj.ktype = &ip_die_entry_ktype; 1071 res = kset_register(&ip_die_entry->ip_kset); 1072 if (res) { 1073 DRM_ERROR("Couldn't register ip_die_entry kset"); 1074 kfree(ip_die_entry); 1075 return res; 1076 } 1077 1078 amdgpu_discovery_sysfs_ips(adev, ip_die_entry, ip_offset, num_ips, !!ihdr->base_addr_64_bit); 1079 } 1080 1081 return 0; 1082 } 1083 1084 static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev) 1085 { 1086 struct kset *die_kset; 1087 int res, ii; 1088 1089 if (!adev->mman.discovery_bin) 1090 return -EINVAL; 1091 1092 adev->ip_top = kzalloc(sizeof(*adev->ip_top), GFP_KERNEL); 1093 if (!adev->ip_top) 1094 return -ENOMEM; 1095 1096 adev->ip_top->adev = adev; 1097 1098 res = kobject_init_and_add(&adev->ip_top->kobj, &ip_discovery_ktype, 1099 &adev->dev->kobj, "ip_discovery"); 1100 if (res) { 1101 DRM_ERROR("Couldn't init and add ip_discovery/"); 1102 goto Err; 1103 } 1104 1105 die_kset = &adev->ip_top->die_kset; 1106 kobject_set_name(&die_kset->kobj, "%s", "die"); 1107 die_kset->kobj.parent = &adev->ip_top->kobj; 1108 die_kset->kobj.ktype = &die_kobj_ktype; 1109 res = kset_register(&adev->ip_top->die_kset); 1110 if (res) { 1111 DRM_ERROR("Couldn't register die_kset"); 1112 goto Err; 1113 } 1114 1115 for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++) 1116 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr; 1117 ip_hw_instance_attrs[ii] = NULL; 1118 1119 res = amdgpu_discovery_sysfs_recurse(adev); 1120 1121 return res; 1122 Err: 1123 kobject_put(&adev->ip_top->kobj); 1124 return res; 1125 } 1126 1127 /* -------------------------------------------------- */ 1128 1129 #define list_to_kobj(el) container_of(el, struct kobject, entry) 1130 1131 static void amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id *ip_hw_id) 1132 { 1133 struct list_head *el, *tmp; 1134 struct kset *hw_id_kset; 1135 1136 hw_id_kset = &ip_hw_id->hw_id_kset; 1137 spin_lock(&hw_id_kset->list_lock); 1138 list_for_each_prev_safe(el, tmp, &hw_id_kset->list) { 1139 list_del_init(el); 1140 spin_unlock(&hw_id_kset->list_lock); 1141 /* kobject is embedded in ip_hw_instance */ 1142 kobject_put(list_to_kobj(el)); 1143 spin_lock(&hw_id_kset->list_lock); 1144 } 1145 spin_unlock(&hw_id_kset->list_lock); 1146 kobject_put(&ip_hw_id->hw_id_kset.kobj); 1147 } 1148 1149 static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry) 1150 { 1151 struct list_head *el, *tmp; 1152 struct kset *ip_kset; 1153 1154 ip_kset = &ip_die_entry->ip_kset; 1155 spin_lock(&ip_kset->list_lock); 1156 list_for_each_prev_safe(el, tmp, &ip_kset->list) { 1157 list_del_init(el); 1158 spin_unlock(&ip_kset->list_lock); 1159 amdgpu_discovery_sysfs_ip_hw_free(to_ip_hw_id(list_to_kobj(el))); 1160 spin_lock(&ip_kset->list_lock); 1161 } 1162 spin_unlock(&ip_kset->list_lock); 1163 kobject_put(&ip_die_entry->ip_kset.kobj); 1164 } 1165 1166 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev) 1167 { 1168 struct list_head *el, *tmp; 1169 struct kset *die_kset; 1170 1171 die_kset = &adev->ip_top->die_kset; 1172 spin_lock(&die_kset->list_lock); 1173 list_for_each_prev_safe(el, tmp, &die_kset->list) { 1174 list_del_init(el); 1175 spin_unlock(&die_kset->list_lock); 1176 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el))); 1177 spin_lock(&die_kset->list_lock); 1178 } 1179 spin_unlock(&die_kset->list_lock); 1180 kobject_put(&adev->ip_top->die_kset.kobj); 1181 kobject_put(&adev->ip_top->kobj); 1182 } 1183 1184 /* ================================================== */ 1185 1186 static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) 1187 { 1188 struct binary_header *bhdr; 1189 struct ip_discovery_header *ihdr; 1190 struct die_header *dhdr; 1191 struct ip_v4 *ip; 1192 uint16_t die_offset; 1193 uint16_t ip_offset; 1194 uint16_t num_dies; 1195 uint16_t num_ips; 1196 uint8_t num_base_address; 1197 int hw_ip; 1198 int i, j, k; 1199 int r; 1200 1201 r = amdgpu_discovery_init(adev); 1202 if (r) { 1203 DRM_ERROR("amdgpu_discovery_init failed\n"); 1204 return r; 1205 } 1206 1207 adev->gfx.xcc_mask = 0; 1208 adev->sdma.sdma_mask = 0; 1209 adev->vcn.inst_mask = 0; 1210 adev->jpeg.inst_mask = 0; 1211 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1212 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 1213 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 1214 num_dies = le16_to_cpu(ihdr->num_dies); 1215 1216 DRM_DEBUG("number of dies: %d\n", num_dies); 1217 1218 for (i = 0; i < num_dies; i++) { 1219 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 1220 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 1221 num_ips = le16_to_cpu(dhdr->num_ips); 1222 ip_offset = die_offset + sizeof(*dhdr); 1223 1224 if (le16_to_cpu(dhdr->die_id) != i) { 1225 DRM_ERROR("invalid die id %d, expected %d\n", 1226 le16_to_cpu(dhdr->die_id), i); 1227 return -EINVAL; 1228 } 1229 1230 DRM_DEBUG("number of hardware IPs on die%d: %d\n", 1231 le16_to_cpu(dhdr->die_id), num_ips); 1232 1233 for (j = 0; j < num_ips; j++) { 1234 ip = (struct ip_v4 *)(adev->mman.discovery_bin + ip_offset); 1235 1236 if (amdgpu_discovery_validate_ip(ip)) 1237 goto next_ip; 1238 1239 num_base_address = ip->num_base_address; 1240 1241 DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n", 1242 hw_id_names[le16_to_cpu(ip->hw_id)], 1243 le16_to_cpu(ip->hw_id), 1244 ip->instance_number, 1245 ip->major, ip->minor, 1246 ip->revision); 1247 1248 if (le16_to_cpu(ip->hw_id) == VCN_HWID) { 1249 /* Bit [5:0]: original revision value 1250 * Bit [7:6]: en/decode capability: 1251 * 0b00 : VCN function normally 1252 * 0b10 : encode is disabled 1253 * 0b01 : decode is disabled 1254 */ 1255 adev->vcn.vcn_config[adev->vcn.num_vcn_inst] = 1256 ip->revision & 0xc0; 1257 ip->revision &= ~0xc0; 1258 if (adev->vcn.num_vcn_inst < 1259 AMDGPU_MAX_VCN_INSTANCES) { 1260 adev->vcn.num_vcn_inst++; 1261 adev->vcn.inst_mask |= 1262 (1U << ip->instance_number); 1263 adev->jpeg.inst_mask |= 1264 (1U << ip->instance_number); 1265 } else { 1266 dev_err(adev->dev, "Too many VCN instances: %d vs %d\n", 1267 adev->vcn.num_vcn_inst + 1, 1268 AMDGPU_MAX_VCN_INSTANCES); 1269 } 1270 } 1271 if (le16_to_cpu(ip->hw_id) == SDMA0_HWID || 1272 le16_to_cpu(ip->hw_id) == SDMA1_HWID || 1273 le16_to_cpu(ip->hw_id) == SDMA2_HWID || 1274 le16_to_cpu(ip->hw_id) == SDMA3_HWID) { 1275 if (adev->sdma.num_instances < 1276 AMDGPU_MAX_SDMA_INSTANCES) { 1277 adev->sdma.num_instances++; 1278 adev->sdma.sdma_mask |= 1279 (1U << ip->instance_number); 1280 } else { 1281 dev_err(adev->dev, "Too many SDMA instances: %d vs %d\n", 1282 adev->sdma.num_instances + 1, 1283 AMDGPU_MAX_SDMA_INSTANCES); 1284 } 1285 } 1286 1287 if (le16_to_cpu(ip->hw_id) == UMC_HWID) { 1288 adev->gmc.num_umc++; 1289 adev->umc.node_inst_num++; 1290 } 1291 1292 if (le16_to_cpu(ip->hw_id) == GC_HWID) 1293 adev->gfx.xcc_mask |= 1294 (1U << ip->instance_number); 1295 1296 for (k = 0; k < num_base_address; k++) { 1297 /* 1298 * convert the endianness of base addresses in place, 1299 * so that we don't need to convert them when accessing adev->reg_offset. 1300 */ 1301 if (ihdr->base_addr_64_bit) 1302 /* Truncate the 64bit base address from ip discovery 1303 * and only store lower 32bit ip base in reg_offset[]. 1304 * Bits > 32 follows ASIC specific format, thus just 1305 * discard them and handle it within specific ASIC. 1306 * By this way reg_offset[] and related helpers can 1307 * stay unchanged. 1308 * The base address is in dwords, thus clear the 1309 * highest 2 bits to store. 1310 */ 1311 ip->base_address[k] = 1312 lower_32_bits(le64_to_cpu(ip->base_address_64[k])) & 0x3FFFFFFF; 1313 else 1314 ip->base_address[k] = le32_to_cpu(ip->base_address[k]); 1315 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]); 1316 } 1317 1318 for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) { 1319 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id) && 1320 hw_id_map[hw_ip] != 0) { 1321 DRM_DEBUG("set register base offset for %s\n", 1322 hw_id_names[le16_to_cpu(ip->hw_id)]); 1323 adev->reg_offset[hw_ip][ip->instance_number] = 1324 ip->base_address; 1325 /* Instance support is somewhat inconsistent. 1326 * SDMA is a good example. Sienna cichlid has 4 total 1327 * SDMA instances, each enumerated separately (HWIDs 1328 * 42, 43, 68, 69). Arcturus has 8 total SDMA instances, 1329 * but they are enumerated as multiple instances of the 1330 * same HWIDs (4x HWID 42, 4x HWID 43). UMC is another 1331 * example. On most chips there are multiple instances 1332 * with the same HWID. 1333 */ 1334 adev->ip_versions[hw_ip][ip->instance_number] = 1335 IP_VERSION(ip->major, ip->minor, ip->revision); 1336 } 1337 } 1338 1339 next_ip: 1340 if (ihdr->base_addr_64_bit) 1341 ip_offset += struct_size(ip, base_address_64, ip->num_base_address); 1342 else 1343 ip_offset += struct_size(ip, base_address, ip->num_base_address); 1344 } 1345 } 1346 1347 return 0; 1348 } 1349 1350 static void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev) 1351 { 1352 int vcn_harvest_count = 0; 1353 int umc_harvest_count = 0; 1354 1355 /* 1356 * Harvest table does not fit Navi1x and legacy GPUs, 1357 * so read harvest bit per IP data structure to set 1358 * harvest configuration. 1359 */ 1360 if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 2, 0) && 1361 adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 3)) { 1362 if ((adev->pdev->device == 0x731E && 1363 (adev->pdev->revision == 0xC6 || 1364 adev->pdev->revision == 0xC7)) || 1365 (adev->pdev->device == 0x7340 && 1366 adev->pdev->revision == 0xC9) || 1367 (adev->pdev->device == 0x7360 && 1368 adev->pdev->revision == 0xC7)) 1369 amdgpu_discovery_read_harvest_bit_per_ip(adev, 1370 &vcn_harvest_count); 1371 } else { 1372 amdgpu_discovery_read_from_harvest_table(adev, 1373 &vcn_harvest_count, 1374 &umc_harvest_count); 1375 } 1376 1377 amdgpu_discovery_harvest_config_quirk(adev); 1378 1379 if (vcn_harvest_count == adev->vcn.num_vcn_inst) { 1380 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK; 1381 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK; 1382 } 1383 1384 if (umc_harvest_count < adev->gmc.num_umc) { 1385 adev->gmc.num_umc -= umc_harvest_count; 1386 } 1387 } 1388 1389 union gc_info { 1390 struct gc_info_v1_0 v1; 1391 struct gc_info_v1_1 v1_1; 1392 struct gc_info_v1_2 v1_2; 1393 struct gc_info_v2_0 v2; 1394 struct gc_info_v2_1 v2_1; 1395 }; 1396 1397 static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) 1398 { 1399 struct binary_header *bhdr; 1400 union gc_info *gc_info; 1401 u16 offset; 1402 1403 if (!adev->mman.discovery_bin) { 1404 DRM_ERROR("ip discovery uninitialized\n"); 1405 return -EINVAL; 1406 } 1407 1408 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1409 offset = le16_to_cpu(bhdr->table_list[GC].offset); 1410 1411 if (!offset) 1412 return 0; 1413 1414 gc_info = (union gc_info *)(adev->mman.discovery_bin + offset); 1415 1416 switch (le16_to_cpu(gc_info->v1.header.version_major)) { 1417 case 1: 1418 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se); 1419 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) + 1420 le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa)); 1421 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1422 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se); 1423 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c); 1424 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs); 1425 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds); 1426 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth); 1427 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth); 1428 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer); 1429 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size); 1430 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd); 1431 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu); 1432 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size); 1433 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) / 1434 le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1435 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc); 1436 if (gc_info->v1.header.version_minor >= 1) { 1437 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v1_1.gc_num_tcp_per_sa); 1438 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v1_1.gc_num_sdp_interface); 1439 adev->gfx.config.gc_num_tcps = le32_to_cpu(gc_info->v1_1.gc_num_tcps); 1440 } 1441 if (gc_info->v1.header.version_minor >= 2) { 1442 adev->gfx.config.gc_num_tcp_per_wpg = le32_to_cpu(gc_info->v1_2.gc_num_tcp_per_wpg); 1443 adev->gfx.config.gc_tcp_l1_size = le32_to_cpu(gc_info->v1_2.gc_tcp_l1_size); 1444 adev->gfx.config.gc_num_sqc_per_wgp = le32_to_cpu(gc_info->v1_2.gc_num_sqc_per_wgp); 1445 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_instruction_cache_size_per_sqc); 1446 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_data_cache_size_per_sqc); 1447 adev->gfx.config.gc_gl1c_per_sa = le32_to_cpu(gc_info->v1_2.gc_gl1c_per_sa); 1448 adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance); 1449 adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu); 1450 } 1451 break; 1452 case 2: 1453 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se); 1454 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh); 1455 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1456 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se); 1457 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs); 1458 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs); 1459 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds); 1460 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth); 1461 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth); 1462 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer); 1463 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size); 1464 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd); 1465 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu); 1466 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size); 1467 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) / 1468 le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1469 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc); 1470 if (gc_info->v2.header.version_minor == 1) { 1471 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v2_1.gc_num_tcp_per_sh); 1472 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v2_1.gc_tcp_size_per_cu); 1473 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v2_1.gc_num_sdp_interface); /* per XCD */ 1474 adev->gfx.config.gc_num_cu_per_sqc = le32_to_cpu(gc_info->v2_1.gc_num_cu_per_sqc); 1475 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_instruction_cache_size_per_sqc); 1476 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_scalar_data_cache_size_per_sqc); 1477 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v2_1.gc_tcc_size); /* per XCD */ 1478 } 1479 break; 1480 default: 1481 dev_err(adev->dev, 1482 "Unhandled GC info table %d.%d\n", 1483 le16_to_cpu(gc_info->v1.header.version_major), 1484 le16_to_cpu(gc_info->v1.header.version_minor)); 1485 return -EINVAL; 1486 } 1487 return 0; 1488 } 1489 1490 union mall_info { 1491 struct mall_info_v1_0 v1; 1492 struct mall_info_v2_0 v2; 1493 }; 1494 1495 static int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev) 1496 { 1497 struct binary_header *bhdr; 1498 union mall_info *mall_info; 1499 u32 u, mall_size_per_umc, m_s_present, half_use; 1500 u64 mall_size; 1501 u16 offset; 1502 1503 if (!adev->mman.discovery_bin) { 1504 DRM_ERROR("ip discovery uninitialized\n"); 1505 return -EINVAL; 1506 } 1507 1508 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1509 offset = le16_to_cpu(bhdr->table_list[MALL_INFO].offset); 1510 1511 if (!offset) 1512 return 0; 1513 1514 mall_info = (union mall_info *)(adev->mman.discovery_bin + offset); 1515 1516 switch (le16_to_cpu(mall_info->v1.header.version_major)) { 1517 case 1: 1518 mall_size = 0; 1519 mall_size_per_umc = le32_to_cpu(mall_info->v1.mall_size_per_m); 1520 m_s_present = le32_to_cpu(mall_info->v1.m_s_present); 1521 half_use = le32_to_cpu(mall_info->v1.m_half_use); 1522 for (u = 0; u < adev->gmc.num_umc; u++) { 1523 if (m_s_present & (1 << u)) 1524 mall_size += mall_size_per_umc * 2; 1525 else if (half_use & (1 << u)) 1526 mall_size += mall_size_per_umc / 2; 1527 else 1528 mall_size += mall_size_per_umc; 1529 } 1530 adev->gmc.mall_size = mall_size; 1531 adev->gmc.m_half_use = half_use; 1532 break; 1533 case 2: 1534 mall_size_per_umc = le32_to_cpu(mall_info->v2.mall_size_per_umc); 1535 adev->gmc.mall_size = mall_size_per_umc * adev->gmc.num_umc; 1536 break; 1537 default: 1538 dev_err(adev->dev, 1539 "Unhandled MALL info table %d.%d\n", 1540 le16_to_cpu(mall_info->v1.header.version_major), 1541 le16_to_cpu(mall_info->v1.header.version_minor)); 1542 return -EINVAL; 1543 } 1544 return 0; 1545 } 1546 1547 union vcn_info { 1548 struct vcn_info_v1_0 v1; 1549 }; 1550 1551 static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev) 1552 { 1553 struct binary_header *bhdr; 1554 union vcn_info *vcn_info; 1555 u16 offset; 1556 int v; 1557 1558 if (!adev->mman.discovery_bin) { 1559 DRM_ERROR("ip discovery uninitialized\n"); 1560 return -EINVAL; 1561 } 1562 1563 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES 1564 * which is smaller than VCN_INFO_TABLE_MAX_NUM_INSTANCES 1565 * but that may change in the future with new GPUs so keep this 1566 * check for defensive purposes. 1567 */ 1568 if (adev->vcn.num_vcn_inst > VCN_INFO_TABLE_MAX_NUM_INSTANCES) { 1569 dev_err(adev->dev, "invalid vcn instances\n"); 1570 return -EINVAL; 1571 } 1572 1573 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1574 offset = le16_to_cpu(bhdr->table_list[VCN_INFO].offset); 1575 1576 if (!offset) 1577 return 0; 1578 1579 vcn_info = (union vcn_info *)(adev->mman.discovery_bin + offset); 1580 1581 switch (le16_to_cpu(vcn_info->v1.header.version_major)) { 1582 case 1: 1583 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES 1584 * so this won't overflow. 1585 */ 1586 for (v = 0; v < adev->vcn.num_vcn_inst; v++) { 1587 adev->vcn.vcn_codec_disable_mask[v] = 1588 le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits); 1589 } 1590 break; 1591 default: 1592 dev_err(adev->dev, 1593 "Unhandled VCN info table %d.%d\n", 1594 le16_to_cpu(vcn_info->v1.header.version_major), 1595 le16_to_cpu(vcn_info->v1.header.version_minor)); 1596 return -EINVAL; 1597 } 1598 return 0; 1599 } 1600 1601 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev) 1602 { 1603 /* what IP to use for this? */ 1604 switch (adev->ip_versions[GC_HWIP][0]) { 1605 case IP_VERSION(9, 0, 1): 1606 case IP_VERSION(9, 1, 0): 1607 case IP_VERSION(9, 2, 1): 1608 case IP_VERSION(9, 2, 2): 1609 case IP_VERSION(9, 3, 0): 1610 case IP_VERSION(9, 4, 0): 1611 case IP_VERSION(9, 4, 1): 1612 case IP_VERSION(9, 4, 2): 1613 case IP_VERSION(9, 4, 3): 1614 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 1615 break; 1616 case IP_VERSION(10, 1, 10): 1617 case IP_VERSION(10, 1, 1): 1618 case IP_VERSION(10, 1, 2): 1619 case IP_VERSION(10, 1, 3): 1620 case IP_VERSION(10, 1, 4): 1621 case IP_VERSION(10, 3, 0): 1622 case IP_VERSION(10, 3, 1): 1623 case IP_VERSION(10, 3, 2): 1624 case IP_VERSION(10, 3, 3): 1625 case IP_VERSION(10, 3, 4): 1626 case IP_VERSION(10, 3, 5): 1627 case IP_VERSION(10, 3, 6): 1628 case IP_VERSION(10, 3, 7): 1629 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 1630 break; 1631 case IP_VERSION(11, 0, 0): 1632 case IP_VERSION(11, 0, 1): 1633 case IP_VERSION(11, 0, 2): 1634 case IP_VERSION(11, 0, 3): 1635 case IP_VERSION(11, 0, 4): 1636 case IP_VERSION(11, 5, 0): 1637 amdgpu_device_ip_block_add(adev, &soc21_common_ip_block); 1638 break; 1639 default: 1640 dev_err(adev->dev, 1641 "Failed to add common ip block(GC_HWIP:0x%x)\n", 1642 adev->ip_versions[GC_HWIP][0]); 1643 return -EINVAL; 1644 } 1645 return 0; 1646 } 1647 1648 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev) 1649 { 1650 /* use GC or MMHUB IP version */ 1651 switch (adev->ip_versions[GC_HWIP][0]) { 1652 case IP_VERSION(9, 0, 1): 1653 case IP_VERSION(9, 1, 0): 1654 case IP_VERSION(9, 2, 1): 1655 case IP_VERSION(9, 2, 2): 1656 case IP_VERSION(9, 3, 0): 1657 case IP_VERSION(9, 4, 0): 1658 case IP_VERSION(9, 4, 1): 1659 case IP_VERSION(9, 4, 2): 1660 case IP_VERSION(9, 4, 3): 1661 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 1662 break; 1663 case IP_VERSION(10, 1, 10): 1664 case IP_VERSION(10, 1, 1): 1665 case IP_VERSION(10, 1, 2): 1666 case IP_VERSION(10, 1, 3): 1667 case IP_VERSION(10, 1, 4): 1668 case IP_VERSION(10, 3, 0): 1669 case IP_VERSION(10, 3, 1): 1670 case IP_VERSION(10, 3, 2): 1671 case IP_VERSION(10, 3, 3): 1672 case IP_VERSION(10, 3, 4): 1673 case IP_VERSION(10, 3, 5): 1674 case IP_VERSION(10, 3, 6): 1675 case IP_VERSION(10, 3, 7): 1676 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 1677 break; 1678 case IP_VERSION(11, 0, 0): 1679 case IP_VERSION(11, 0, 1): 1680 case IP_VERSION(11, 0, 2): 1681 case IP_VERSION(11, 0, 3): 1682 case IP_VERSION(11, 0, 4): 1683 case IP_VERSION(11, 5, 0): 1684 amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block); 1685 break; 1686 default: 1687 dev_err(adev->dev, 1688 "Failed to add gmc ip block(GC_HWIP:0x%x)\n", 1689 adev->ip_versions[GC_HWIP][0]); 1690 return -EINVAL; 1691 } 1692 return 0; 1693 } 1694 1695 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev) 1696 { 1697 switch (adev->ip_versions[OSSSYS_HWIP][0]) { 1698 case IP_VERSION(4, 0, 0): 1699 case IP_VERSION(4, 0, 1): 1700 case IP_VERSION(4, 1, 0): 1701 case IP_VERSION(4, 1, 1): 1702 case IP_VERSION(4, 3, 0): 1703 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 1704 break; 1705 case IP_VERSION(4, 2, 0): 1706 case IP_VERSION(4, 2, 1): 1707 case IP_VERSION(4, 4, 0): 1708 case IP_VERSION(4, 4, 2): 1709 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 1710 break; 1711 case IP_VERSION(5, 0, 0): 1712 case IP_VERSION(5, 0, 1): 1713 case IP_VERSION(5, 0, 2): 1714 case IP_VERSION(5, 0, 3): 1715 case IP_VERSION(5, 2, 0): 1716 case IP_VERSION(5, 2, 1): 1717 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 1718 break; 1719 case IP_VERSION(6, 0, 0): 1720 case IP_VERSION(6, 0, 1): 1721 case IP_VERSION(6, 0, 2): 1722 amdgpu_device_ip_block_add(adev, &ih_v6_0_ip_block); 1723 break; 1724 case IP_VERSION(6, 1, 0): 1725 amdgpu_device_ip_block_add(adev, &ih_v6_1_ip_block); 1726 break; 1727 default: 1728 dev_err(adev->dev, 1729 "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n", 1730 adev->ip_versions[OSSSYS_HWIP][0]); 1731 return -EINVAL; 1732 } 1733 return 0; 1734 } 1735 1736 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev) 1737 { 1738 switch (adev->ip_versions[MP0_HWIP][0]) { 1739 case IP_VERSION(9, 0, 0): 1740 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 1741 break; 1742 case IP_VERSION(10, 0, 0): 1743 case IP_VERSION(10, 0, 1): 1744 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); 1745 break; 1746 case IP_VERSION(11, 0, 0): 1747 case IP_VERSION(11, 0, 2): 1748 case IP_VERSION(11, 0, 4): 1749 case IP_VERSION(11, 0, 5): 1750 case IP_VERSION(11, 0, 9): 1751 case IP_VERSION(11, 0, 7): 1752 case IP_VERSION(11, 0, 11): 1753 case IP_VERSION(11, 0, 12): 1754 case IP_VERSION(11, 0, 13): 1755 case IP_VERSION(11, 5, 0): 1756 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 1757 break; 1758 case IP_VERSION(11, 0, 8): 1759 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block); 1760 break; 1761 case IP_VERSION(11, 0, 3): 1762 case IP_VERSION(12, 0, 1): 1763 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); 1764 break; 1765 case IP_VERSION(13, 0, 0): 1766 case IP_VERSION(13, 0, 1): 1767 case IP_VERSION(13, 0, 2): 1768 case IP_VERSION(13, 0, 3): 1769 case IP_VERSION(13, 0, 5): 1770 case IP_VERSION(13, 0, 6): 1771 case IP_VERSION(13, 0, 7): 1772 case IP_VERSION(13, 0, 8): 1773 case IP_VERSION(13, 0, 10): 1774 case IP_VERSION(13, 0, 11): 1775 case IP_VERSION(14, 0, 0): 1776 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); 1777 break; 1778 case IP_VERSION(13, 0, 4): 1779 amdgpu_device_ip_block_add(adev, &psp_v13_0_4_ip_block); 1780 break; 1781 default: 1782 dev_err(adev->dev, 1783 "Failed to add psp ip block(MP0_HWIP:0x%x)\n", 1784 adev->ip_versions[MP0_HWIP][0]); 1785 return -EINVAL; 1786 } 1787 return 0; 1788 } 1789 1790 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev) 1791 { 1792 switch (adev->ip_versions[MP1_HWIP][0]) { 1793 case IP_VERSION(9, 0, 0): 1794 case IP_VERSION(10, 0, 0): 1795 case IP_VERSION(10, 0, 1): 1796 case IP_VERSION(11, 0, 2): 1797 if (adev->asic_type == CHIP_ARCTURUS) 1798 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 1799 else 1800 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 1801 break; 1802 case IP_VERSION(11, 0, 0): 1803 case IP_VERSION(11, 0, 5): 1804 case IP_VERSION(11, 0, 9): 1805 case IP_VERSION(11, 0, 7): 1806 case IP_VERSION(11, 0, 8): 1807 case IP_VERSION(11, 0, 11): 1808 case IP_VERSION(11, 0, 12): 1809 case IP_VERSION(11, 0, 13): 1810 case IP_VERSION(11, 5, 0): 1811 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 1812 break; 1813 case IP_VERSION(12, 0, 0): 1814 case IP_VERSION(12, 0, 1): 1815 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); 1816 break; 1817 case IP_VERSION(13, 0, 0): 1818 case IP_VERSION(13, 0, 1): 1819 case IP_VERSION(13, 0, 2): 1820 case IP_VERSION(13, 0, 3): 1821 case IP_VERSION(13, 0, 4): 1822 case IP_VERSION(13, 0, 5): 1823 case IP_VERSION(13, 0, 6): 1824 case IP_VERSION(13, 0, 7): 1825 case IP_VERSION(13, 0, 8): 1826 case IP_VERSION(13, 0, 10): 1827 case IP_VERSION(13, 0, 11): 1828 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); 1829 break; 1830 default: 1831 dev_err(adev->dev, 1832 "Failed to add smu ip block(MP1_HWIP:0x%x)\n", 1833 adev->ip_versions[MP1_HWIP][0]); 1834 return -EINVAL; 1835 } 1836 return 0; 1837 } 1838 1839 #if defined(CONFIG_DRM_AMD_DC) 1840 static void amdgpu_discovery_set_sriov_display(struct amdgpu_device *adev) 1841 { 1842 amdgpu_device_set_sriov_virtual_display(adev); 1843 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 1844 } 1845 #endif 1846 1847 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev) 1848 { 1849 if (adev->enable_virtual_display) { 1850 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 1851 return 0; 1852 } 1853 1854 if (!amdgpu_device_has_dc_support(adev)) 1855 return 0; 1856 1857 #if defined(CONFIG_DRM_AMD_DC) 1858 if (adev->ip_versions[DCE_HWIP][0]) { 1859 switch (adev->ip_versions[DCE_HWIP][0]) { 1860 case IP_VERSION(1, 0, 0): 1861 case IP_VERSION(1, 0, 1): 1862 case IP_VERSION(2, 0, 2): 1863 case IP_VERSION(2, 0, 0): 1864 case IP_VERSION(2, 0, 3): 1865 case IP_VERSION(2, 1, 0): 1866 case IP_VERSION(3, 0, 0): 1867 case IP_VERSION(3, 0, 2): 1868 case IP_VERSION(3, 0, 3): 1869 case IP_VERSION(3, 0, 1): 1870 case IP_VERSION(3, 1, 2): 1871 case IP_VERSION(3, 1, 3): 1872 case IP_VERSION(3, 1, 4): 1873 case IP_VERSION(3, 1, 5): 1874 case IP_VERSION(3, 1, 6): 1875 case IP_VERSION(3, 2, 0): 1876 case IP_VERSION(3, 2, 1): 1877 if (amdgpu_sriov_vf(adev)) 1878 amdgpu_discovery_set_sriov_display(adev); 1879 else 1880 amdgpu_device_ip_block_add(adev, &dm_ip_block); 1881 break; 1882 default: 1883 dev_err(adev->dev, 1884 "Failed to add dm ip block(DCE_HWIP:0x%x)\n", 1885 adev->ip_versions[DCE_HWIP][0]); 1886 return -EINVAL; 1887 } 1888 } else if (adev->ip_versions[DCI_HWIP][0]) { 1889 switch (adev->ip_versions[DCI_HWIP][0]) { 1890 case IP_VERSION(12, 0, 0): 1891 case IP_VERSION(12, 0, 1): 1892 case IP_VERSION(12, 1, 0): 1893 if (amdgpu_sriov_vf(adev)) 1894 amdgpu_discovery_set_sriov_display(adev); 1895 else 1896 amdgpu_device_ip_block_add(adev, &dm_ip_block); 1897 break; 1898 default: 1899 dev_err(adev->dev, 1900 "Failed to add dm ip block(DCI_HWIP:0x%x)\n", 1901 adev->ip_versions[DCI_HWIP][0]); 1902 return -EINVAL; 1903 } 1904 } 1905 #endif 1906 return 0; 1907 } 1908 1909 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) 1910 { 1911 switch (adev->ip_versions[GC_HWIP][0]) { 1912 case IP_VERSION(9, 0, 1): 1913 case IP_VERSION(9, 1, 0): 1914 case IP_VERSION(9, 2, 1): 1915 case IP_VERSION(9, 2, 2): 1916 case IP_VERSION(9, 3, 0): 1917 case IP_VERSION(9, 4, 0): 1918 case IP_VERSION(9, 4, 1): 1919 case IP_VERSION(9, 4, 2): 1920 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 1921 break; 1922 case IP_VERSION(9, 4, 3): 1923 if (!amdgpu_exp_hw_support) 1924 return -EINVAL; 1925 amdgpu_device_ip_block_add(adev, &gfx_v9_4_3_ip_block); 1926 break; 1927 case IP_VERSION(10, 1, 10): 1928 case IP_VERSION(10, 1, 2): 1929 case IP_VERSION(10, 1, 1): 1930 case IP_VERSION(10, 1, 3): 1931 case IP_VERSION(10, 1, 4): 1932 case IP_VERSION(10, 3, 0): 1933 case IP_VERSION(10, 3, 2): 1934 case IP_VERSION(10, 3, 1): 1935 case IP_VERSION(10, 3, 4): 1936 case IP_VERSION(10, 3, 5): 1937 case IP_VERSION(10, 3, 6): 1938 case IP_VERSION(10, 3, 3): 1939 case IP_VERSION(10, 3, 7): 1940 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 1941 break; 1942 case IP_VERSION(11, 0, 0): 1943 case IP_VERSION(11, 0, 1): 1944 case IP_VERSION(11, 0, 2): 1945 case IP_VERSION(11, 0, 3): 1946 case IP_VERSION(11, 0, 4): 1947 case IP_VERSION(11, 5, 0): 1948 amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block); 1949 break; 1950 default: 1951 dev_err(adev->dev, 1952 "Failed to add gfx ip block(GC_HWIP:0x%x)\n", 1953 adev->ip_versions[GC_HWIP][0]); 1954 return -EINVAL; 1955 } 1956 return 0; 1957 } 1958 1959 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev) 1960 { 1961 switch (adev->ip_versions[SDMA0_HWIP][0]) { 1962 case IP_VERSION(4, 0, 0): 1963 case IP_VERSION(4, 0, 1): 1964 case IP_VERSION(4, 1, 0): 1965 case IP_VERSION(4, 1, 1): 1966 case IP_VERSION(4, 1, 2): 1967 case IP_VERSION(4, 2, 0): 1968 case IP_VERSION(4, 2, 2): 1969 case IP_VERSION(4, 4, 0): 1970 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 1971 break; 1972 case IP_VERSION(4, 4, 2): 1973 amdgpu_device_ip_block_add(adev, &sdma_v4_4_2_ip_block); 1974 break; 1975 case IP_VERSION(5, 0, 0): 1976 case IP_VERSION(5, 0, 1): 1977 case IP_VERSION(5, 0, 2): 1978 case IP_VERSION(5, 0, 5): 1979 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 1980 break; 1981 case IP_VERSION(5, 2, 0): 1982 case IP_VERSION(5, 2, 2): 1983 case IP_VERSION(5, 2, 4): 1984 case IP_VERSION(5, 2, 5): 1985 case IP_VERSION(5, 2, 6): 1986 case IP_VERSION(5, 2, 3): 1987 case IP_VERSION(5, 2, 1): 1988 case IP_VERSION(5, 2, 7): 1989 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 1990 break; 1991 case IP_VERSION(6, 0, 0): 1992 case IP_VERSION(6, 0, 1): 1993 case IP_VERSION(6, 0, 2): 1994 case IP_VERSION(6, 0, 3): 1995 case IP_VERSION(6, 1, 0): 1996 amdgpu_device_ip_block_add(adev, &sdma_v6_0_ip_block); 1997 break; 1998 default: 1999 dev_err(adev->dev, 2000 "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n", 2001 adev->ip_versions[SDMA0_HWIP][0]); 2002 return -EINVAL; 2003 } 2004 return 0; 2005 } 2006 2007 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) 2008 { 2009 if (adev->ip_versions[VCE_HWIP][0]) { 2010 switch (adev->ip_versions[UVD_HWIP][0]) { 2011 case IP_VERSION(7, 0, 0): 2012 case IP_VERSION(7, 2, 0): 2013 /* UVD is not supported on vega20 SR-IOV */ 2014 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 2015 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); 2016 break; 2017 default: 2018 dev_err(adev->dev, 2019 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n", 2020 adev->ip_versions[UVD_HWIP][0]); 2021 return -EINVAL; 2022 } 2023 switch (adev->ip_versions[VCE_HWIP][0]) { 2024 case IP_VERSION(4, 0, 0): 2025 case IP_VERSION(4, 1, 0): 2026 /* VCE is not supported on vega20 SR-IOV */ 2027 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 2028 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); 2029 break; 2030 default: 2031 dev_err(adev->dev, 2032 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n", 2033 adev->ip_versions[VCE_HWIP][0]); 2034 return -EINVAL; 2035 } 2036 } else { 2037 switch (adev->ip_versions[UVD_HWIP][0]) { 2038 case IP_VERSION(1, 0, 0): 2039 case IP_VERSION(1, 0, 1): 2040 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); 2041 break; 2042 case IP_VERSION(2, 0, 0): 2043 case IP_VERSION(2, 0, 2): 2044 case IP_VERSION(2, 2, 0): 2045 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 2046 if (!amdgpu_sriov_vf(adev)) 2047 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 2048 break; 2049 case IP_VERSION(2, 0, 3): 2050 break; 2051 case IP_VERSION(2, 5, 0): 2052 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 2053 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block); 2054 break; 2055 case IP_VERSION(2, 6, 0): 2056 amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block); 2057 amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block); 2058 break; 2059 case IP_VERSION(3, 0, 0): 2060 case IP_VERSION(3, 0, 16): 2061 case IP_VERSION(3, 1, 1): 2062 case IP_VERSION(3, 1, 2): 2063 case IP_VERSION(3, 0, 2): 2064 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 2065 if (!amdgpu_sriov_vf(adev)) 2066 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 2067 break; 2068 case IP_VERSION(3, 0, 33): 2069 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 2070 break; 2071 case IP_VERSION(4, 0, 0): 2072 case IP_VERSION(4, 0, 2): 2073 case IP_VERSION(4, 0, 4): 2074 amdgpu_device_ip_block_add(adev, &vcn_v4_0_ip_block); 2075 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block); 2076 break; 2077 case IP_VERSION(4, 0, 3): 2078 amdgpu_device_ip_block_add(adev, &vcn_v4_0_3_ip_block); 2079 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_3_ip_block); 2080 break; 2081 default: 2082 dev_err(adev->dev, 2083 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n", 2084 adev->ip_versions[UVD_HWIP][0]); 2085 return -EINVAL; 2086 } 2087 } 2088 return 0; 2089 } 2090 2091 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev) 2092 { 2093 switch (adev->ip_versions[GC_HWIP][0]) { 2094 case IP_VERSION(10, 1, 10): 2095 case IP_VERSION(10, 1, 1): 2096 case IP_VERSION(10, 1, 2): 2097 case IP_VERSION(10, 1, 3): 2098 case IP_VERSION(10, 1, 4): 2099 case IP_VERSION(10, 3, 0): 2100 case IP_VERSION(10, 3, 1): 2101 case IP_VERSION(10, 3, 2): 2102 case IP_VERSION(10, 3, 3): 2103 case IP_VERSION(10, 3, 4): 2104 case IP_VERSION(10, 3, 5): 2105 case IP_VERSION(10, 3, 6): 2106 if (amdgpu_mes) { 2107 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 2108 adev->enable_mes = true; 2109 if (amdgpu_mes_kiq) 2110 adev->enable_mes_kiq = true; 2111 } 2112 break; 2113 case IP_VERSION(11, 0, 0): 2114 case IP_VERSION(11, 0, 1): 2115 case IP_VERSION(11, 0, 2): 2116 case IP_VERSION(11, 0, 3): 2117 case IP_VERSION(11, 0, 4): 2118 case IP_VERSION(11, 5, 0): 2119 amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block); 2120 adev->enable_mes = true; 2121 adev->enable_mes_kiq = true; 2122 break; 2123 default: 2124 break; 2125 } 2126 return 0; 2127 } 2128 2129 static void amdgpu_discovery_init_soc_config(struct amdgpu_device *adev) 2130 { 2131 switch (adev->ip_versions[GC_HWIP][0]) { 2132 case IP_VERSION(9, 4, 3): 2133 aqua_vanjaram_init_soc_config(adev); 2134 break; 2135 default: 2136 break; 2137 } 2138 } 2139 2140 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 2141 { 2142 int r; 2143 2144 switch (adev->asic_type) { 2145 case CHIP_VEGA10: 2146 vega10_reg_base_init(adev); 2147 adev->sdma.num_instances = 2; 2148 adev->gmc.num_umc = 4; 2149 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0); 2150 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0); 2151 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0); 2152 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0); 2153 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0); 2154 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0); 2155 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 2156 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0); 2157 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0); 2158 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 2159 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 2160 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 2161 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0); 2162 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1); 2163 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 2164 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 2165 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0); 2166 break; 2167 case CHIP_VEGA12: 2168 vega10_reg_base_init(adev); 2169 adev->sdma.num_instances = 2; 2170 adev->gmc.num_umc = 4; 2171 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0); 2172 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0); 2173 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1); 2174 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1); 2175 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1); 2176 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1); 2177 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0); 2178 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0); 2179 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0); 2180 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 2181 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 2182 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 2183 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1); 2184 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1); 2185 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 2186 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 2187 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1); 2188 break; 2189 case CHIP_RAVEN: 2190 vega10_reg_base_init(adev); 2191 adev->sdma.num_instances = 1; 2192 adev->vcn.num_vcn_inst = 1; 2193 adev->gmc.num_umc = 2; 2194 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { 2195 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0); 2196 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0); 2197 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1); 2198 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1); 2199 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1); 2200 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1); 2201 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1); 2202 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0); 2203 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1); 2204 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1); 2205 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0); 2206 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1); 2207 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2); 2208 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1); 2209 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1); 2210 } else { 2211 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0); 2212 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0); 2213 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0); 2214 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0); 2215 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0); 2216 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 2217 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0); 2218 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0); 2219 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0); 2220 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0); 2221 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0); 2222 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0); 2223 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0); 2224 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0); 2225 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0); 2226 } 2227 break; 2228 case CHIP_VEGA20: 2229 vega20_reg_base_init(adev); 2230 adev->sdma.num_instances = 2; 2231 adev->gmc.num_umc = 8; 2232 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2233 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2234 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0); 2235 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0); 2236 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0); 2237 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0); 2238 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0); 2239 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0); 2240 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1); 2241 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2); 2242 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2243 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2); 2244 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2); 2245 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0); 2246 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0); 2247 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0); 2248 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0); 2249 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0); 2250 break; 2251 case CHIP_ARCTURUS: 2252 arct_reg_base_init(adev); 2253 adev->sdma.num_instances = 8; 2254 adev->vcn.num_vcn_inst = 2; 2255 adev->gmc.num_umc = 8; 2256 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2257 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2258 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1); 2259 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1); 2260 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2); 2261 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2); 2262 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2); 2263 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2); 2264 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2); 2265 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2); 2266 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2); 2267 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2); 2268 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1); 2269 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1); 2270 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2); 2271 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4); 2272 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2273 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3); 2274 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3); 2275 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1); 2276 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0); 2277 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0); 2278 break; 2279 case CHIP_ALDEBARAN: 2280 aldebaran_reg_base_init(adev); 2281 adev->sdma.num_instances = 5; 2282 adev->vcn.num_vcn_inst = 2; 2283 adev->gmc.num_umc = 4; 2284 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2285 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2286 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0); 2287 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0); 2288 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0); 2289 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0); 2290 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0); 2291 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0); 2292 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0); 2293 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2); 2294 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4); 2295 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0); 2296 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2); 2297 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2); 2298 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2); 2299 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2); 2300 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2); 2301 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0); 2302 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0); 2303 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0); 2304 break; 2305 default: 2306 r = amdgpu_discovery_reg_base_init(adev); 2307 if (r) 2308 return -EINVAL; 2309 2310 amdgpu_discovery_harvest_ip(adev); 2311 amdgpu_discovery_get_gfx_info(adev); 2312 amdgpu_discovery_get_mall_info(adev); 2313 amdgpu_discovery_get_vcn_info(adev); 2314 break; 2315 } 2316 2317 amdgpu_discovery_init_soc_config(adev); 2318 amdgpu_discovery_sysfs_init(adev); 2319 2320 switch (adev->ip_versions[GC_HWIP][0]) { 2321 case IP_VERSION(9, 0, 1): 2322 case IP_VERSION(9, 2, 1): 2323 case IP_VERSION(9, 4, 0): 2324 case IP_VERSION(9, 4, 1): 2325 case IP_VERSION(9, 4, 2): 2326 case IP_VERSION(9, 4, 3): 2327 adev->family = AMDGPU_FAMILY_AI; 2328 break; 2329 case IP_VERSION(9, 1, 0): 2330 case IP_VERSION(9, 2, 2): 2331 case IP_VERSION(9, 3, 0): 2332 adev->family = AMDGPU_FAMILY_RV; 2333 break; 2334 case IP_VERSION(10, 1, 10): 2335 case IP_VERSION(10, 1, 1): 2336 case IP_VERSION(10, 1, 2): 2337 case IP_VERSION(10, 1, 3): 2338 case IP_VERSION(10, 1, 4): 2339 case IP_VERSION(10, 3, 0): 2340 case IP_VERSION(10, 3, 2): 2341 case IP_VERSION(10, 3, 4): 2342 case IP_VERSION(10, 3, 5): 2343 adev->family = AMDGPU_FAMILY_NV; 2344 break; 2345 case IP_VERSION(10, 3, 1): 2346 adev->family = AMDGPU_FAMILY_VGH; 2347 adev->apu_flags |= AMD_APU_IS_VANGOGH; 2348 break; 2349 case IP_VERSION(10, 3, 3): 2350 adev->family = AMDGPU_FAMILY_YC; 2351 break; 2352 case IP_VERSION(10, 3, 6): 2353 adev->family = AMDGPU_FAMILY_GC_10_3_6; 2354 break; 2355 case IP_VERSION(10, 3, 7): 2356 adev->family = AMDGPU_FAMILY_GC_10_3_7; 2357 break; 2358 case IP_VERSION(11, 0, 0): 2359 case IP_VERSION(11, 0, 2): 2360 case IP_VERSION(11, 0, 3): 2361 adev->family = AMDGPU_FAMILY_GC_11_0_0; 2362 break; 2363 case IP_VERSION(11, 0, 1): 2364 case IP_VERSION(11, 0, 4): 2365 adev->family = AMDGPU_FAMILY_GC_11_0_1; 2366 break; 2367 case IP_VERSION(11, 5, 0): 2368 adev->family = AMDGPU_FAMILY_GC_11_5_0; 2369 break; 2370 default: 2371 return -EINVAL; 2372 } 2373 2374 switch (adev->ip_versions[GC_HWIP][0]) { 2375 case IP_VERSION(9, 1, 0): 2376 case IP_VERSION(9, 2, 2): 2377 case IP_VERSION(9, 3, 0): 2378 case IP_VERSION(10, 1, 3): 2379 case IP_VERSION(10, 1, 4): 2380 case IP_VERSION(10, 3, 1): 2381 case IP_VERSION(10, 3, 3): 2382 case IP_VERSION(10, 3, 6): 2383 case IP_VERSION(10, 3, 7): 2384 case IP_VERSION(11, 0, 1): 2385 case IP_VERSION(11, 0, 4): 2386 case IP_VERSION(11, 5, 0): 2387 adev->flags |= AMD_IS_APU; 2388 break; 2389 default: 2390 break; 2391 } 2392 2393 if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(4, 8, 0)) 2394 adev->gmc.xgmi.supported = true; 2395 2396 /* set NBIO version */ 2397 switch (adev->ip_versions[NBIO_HWIP][0]) { 2398 case IP_VERSION(6, 1, 0): 2399 case IP_VERSION(6, 2, 0): 2400 adev->nbio.funcs = &nbio_v6_1_funcs; 2401 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; 2402 break; 2403 case IP_VERSION(7, 0, 0): 2404 case IP_VERSION(7, 0, 1): 2405 case IP_VERSION(2, 5, 0): 2406 adev->nbio.funcs = &nbio_v7_0_funcs; 2407 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; 2408 break; 2409 case IP_VERSION(7, 4, 0): 2410 case IP_VERSION(7, 4, 1): 2411 case IP_VERSION(7, 4, 4): 2412 adev->nbio.funcs = &nbio_v7_4_funcs; 2413 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; 2414 break; 2415 case IP_VERSION(7, 9, 0): 2416 adev->nbio.funcs = &nbio_v7_9_funcs; 2417 adev->nbio.hdp_flush_reg = &nbio_v7_9_hdp_flush_reg; 2418 break; 2419 case IP_VERSION(7, 11, 0): 2420 adev->nbio.funcs = &nbio_v7_11_funcs; 2421 adev->nbio.hdp_flush_reg = &nbio_v7_11_hdp_flush_reg; 2422 break; 2423 case IP_VERSION(7, 2, 0): 2424 case IP_VERSION(7, 2, 1): 2425 case IP_VERSION(7, 3, 0): 2426 case IP_VERSION(7, 5, 0): 2427 case IP_VERSION(7, 5, 1): 2428 adev->nbio.funcs = &nbio_v7_2_funcs; 2429 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; 2430 break; 2431 case IP_VERSION(2, 1, 1): 2432 case IP_VERSION(2, 3, 0): 2433 case IP_VERSION(2, 3, 1): 2434 case IP_VERSION(2, 3, 2): 2435 case IP_VERSION(3, 3, 0): 2436 case IP_VERSION(3, 3, 1): 2437 case IP_VERSION(3, 3, 2): 2438 case IP_VERSION(3, 3, 3): 2439 adev->nbio.funcs = &nbio_v2_3_funcs; 2440 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 2441 break; 2442 case IP_VERSION(4, 3, 0): 2443 case IP_VERSION(4, 3, 1): 2444 if (amdgpu_sriov_vf(adev)) 2445 adev->nbio.funcs = &nbio_v4_3_sriov_funcs; 2446 else 2447 adev->nbio.funcs = &nbio_v4_3_funcs; 2448 adev->nbio.hdp_flush_reg = &nbio_v4_3_hdp_flush_reg; 2449 break; 2450 case IP_VERSION(7, 7, 0): 2451 case IP_VERSION(7, 7, 1): 2452 adev->nbio.funcs = &nbio_v7_7_funcs; 2453 adev->nbio.hdp_flush_reg = &nbio_v7_7_hdp_flush_reg; 2454 break; 2455 default: 2456 break; 2457 } 2458 2459 switch (adev->ip_versions[HDP_HWIP][0]) { 2460 case IP_VERSION(4, 0, 0): 2461 case IP_VERSION(4, 0, 1): 2462 case IP_VERSION(4, 1, 0): 2463 case IP_VERSION(4, 1, 1): 2464 case IP_VERSION(4, 1, 2): 2465 case IP_VERSION(4, 2, 0): 2466 case IP_VERSION(4, 2, 1): 2467 case IP_VERSION(4, 4, 0): 2468 case IP_VERSION(4, 4, 2): 2469 adev->hdp.funcs = &hdp_v4_0_funcs; 2470 break; 2471 case IP_VERSION(5, 0, 0): 2472 case IP_VERSION(5, 0, 1): 2473 case IP_VERSION(5, 0, 2): 2474 case IP_VERSION(5, 0, 3): 2475 case IP_VERSION(5, 0, 4): 2476 case IP_VERSION(5, 2, 0): 2477 adev->hdp.funcs = &hdp_v5_0_funcs; 2478 break; 2479 case IP_VERSION(5, 2, 1): 2480 adev->hdp.funcs = &hdp_v5_2_funcs; 2481 break; 2482 case IP_VERSION(6, 0, 0): 2483 case IP_VERSION(6, 0, 1): 2484 case IP_VERSION(6, 1, 0): 2485 adev->hdp.funcs = &hdp_v6_0_funcs; 2486 break; 2487 default: 2488 break; 2489 } 2490 2491 switch (adev->ip_versions[DF_HWIP][0]) { 2492 case IP_VERSION(3, 6, 0): 2493 case IP_VERSION(3, 6, 1): 2494 case IP_VERSION(3, 6, 2): 2495 adev->df.funcs = &df_v3_6_funcs; 2496 break; 2497 case IP_VERSION(2, 1, 0): 2498 case IP_VERSION(2, 1, 1): 2499 case IP_VERSION(2, 5, 0): 2500 case IP_VERSION(3, 5, 1): 2501 case IP_VERSION(3, 5, 2): 2502 adev->df.funcs = &df_v1_7_funcs; 2503 break; 2504 case IP_VERSION(4, 3, 0): 2505 adev->df.funcs = &df_v4_3_funcs; 2506 break; 2507 default: 2508 break; 2509 } 2510 2511 switch (adev->ip_versions[SMUIO_HWIP][0]) { 2512 case IP_VERSION(9, 0, 0): 2513 case IP_VERSION(9, 0, 1): 2514 case IP_VERSION(10, 0, 0): 2515 case IP_VERSION(10, 0, 1): 2516 case IP_VERSION(10, 0, 2): 2517 adev->smuio.funcs = &smuio_v9_0_funcs; 2518 break; 2519 case IP_VERSION(11, 0, 0): 2520 case IP_VERSION(11, 0, 2): 2521 case IP_VERSION(11, 0, 3): 2522 case IP_VERSION(11, 0, 4): 2523 case IP_VERSION(11, 0, 7): 2524 case IP_VERSION(11, 0, 8): 2525 adev->smuio.funcs = &smuio_v11_0_funcs; 2526 break; 2527 case IP_VERSION(11, 0, 6): 2528 case IP_VERSION(11, 0, 10): 2529 case IP_VERSION(11, 0, 11): 2530 case IP_VERSION(11, 5, 0): 2531 case IP_VERSION(13, 0, 1): 2532 case IP_VERSION(13, 0, 9): 2533 case IP_VERSION(13, 0, 10): 2534 adev->smuio.funcs = &smuio_v11_0_6_funcs; 2535 break; 2536 case IP_VERSION(13, 0, 2): 2537 adev->smuio.funcs = &smuio_v13_0_funcs; 2538 break; 2539 case IP_VERSION(13, 0, 3): 2540 adev->smuio.funcs = &smuio_v13_0_3_funcs; 2541 if (adev->smuio.funcs->get_pkg_type(adev) == AMDGPU_PKG_TYPE_APU) { 2542 adev->flags |= AMD_IS_APU; 2543 } 2544 break; 2545 case IP_VERSION(13, 0, 6): 2546 case IP_VERSION(13, 0, 8): 2547 case IP_VERSION(14, 0, 0): 2548 adev->smuio.funcs = &smuio_v13_0_6_funcs; 2549 break; 2550 default: 2551 break; 2552 } 2553 2554 switch (adev->ip_versions[LSDMA_HWIP][0]) { 2555 case IP_VERSION(6, 0, 0): 2556 case IP_VERSION(6, 0, 1): 2557 case IP_VERSION(6, 0, 2): 2558 case IP_VERSION(6, 0, 3): 2559 adev->lsdma.funcs = &lsdma_v6_0_funcs; 2560 break; 2561 default: 2562 break; 2563 } 2564 2565 r = amdgpu_discovery_set_common_ip_blocks(adev); 2566 if (r) 2567 return r; 2568 2569 r = amdgpu_discovery_set_gmc_ip_blocks(adev); 2570 if (r) 2571 return r; 2572 2573 /* For SR-IOV, PSP needs to be initialized before IH */ 2574 if (amdgpu_sriov_vf(adev)) { 2575 r = amdgpu_discovery_set_psp_ip_blocks(adev); 2576 if (r) 2577 return r; 2578 r = amdgpu_discovery_set_ih_ip_blocks(adev); 2579 if (r) 2580 return r; 2581 } else { 2582 r = amdgpu_discovery_set_ih_ip_blocks(adev); 2583 if (r) 2584 return r; 2585 2586 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 2587 r = amdgpu_discovery_set_psp_ip_blocks(adev); 2588 if (r) 2589 return r; 2590 } 2591 } 2592 2593 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 2594 r = amdgpu_discovery_set_smu_ip_blocks(adev); 2595 if (r) 2596 return r; 2597 } 2598 2599 r = amdgpu_discovery_set_display_ip_blocks(adev); 2600 if (r) 2601 return r; 2602 2603 r = amdgpu_discovery_set_gc_ip_blocks(adev); 2604 if (r) 2605 return r; 2606 2607 r = amdgpu_discovery_set_sdma_ip_blocks(adev); 2608 if (r) 2609 return r; 2610 2611 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 2612 !amdgpu_sriov_vf(adev)) || 2613 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) { 2614 r = amdgpu_discovery_set_smu_ip_blocks(adev); 2615 if (r) 2616 return r; 2617 } 2618 2619 r = amdgpu_discovery_set_mm_ip_blocks(adev); 2620 if (r) 2621 return r; 2622 2623 r = amdgpu_discovery_set_mes_ip_blocks(adev); 2624 if (r) 2625 return r; 2626 2627 return 0; 2628 } 2629 2630