1 /* 2 * Copyright 2018-2024 Advanced Micro Devices, Inc. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_discovery.h" 28 #include "soc15_hw_ip.h" 29 #include "discovery.h" 30 #include "amdgpu_ras.h" 31 32 #include "soc15.h" 33 #include "gfx_v9_0.h" 34 #include "gfx_v9_4_3.h" 35 #include "gmc_v9_0.h" 36 #include "df_v1_7.h" 37 #include "df_v3_6.h" 38 #include "df_v4_3.h" 39 #include "df_v4_6_2.h" 40 #include "df_v4_15.h" 41 #include "nbio_v6_1.h" 42 #include "nbio_v7_0.h" 43 #include "nbio_v7_4.h" 44 #include "nbio_v7_9.h" 45 #include "nbio_v7_11.h" 46 #include "hdp_v4_0.h" 47 #include "vega10_ih.h" 48 #include "vega20_ih.h" 49 #include "sdma_v4_0.h" 50 #include "sdma_v4_4_2.h" 51 #include "uvd_v7_0.h" 52 #include "vce_v4_0.h" 53 #include "vcn_v1_0.h" 54 #include "vcn_v2_5.h" 55 #include "jpeg_v2_5.h" 56 #include "smuio_v9_0.h" 57 #include "gmc_v10_0.h" 58 #include "gmc_v11_0.h" 59 #include "gmc_v12_0.h" 60 #include "gfxhub_v2_0.h" 61 #include "mmhub_v2_0.h" 62 #include "nbio_v2_3.h" 63 #include "nbio_v4_3.h" 64 #include "nbio_v7_2.h" 65 #include "nbio_v7_7.h" 66 #include "nbif_v6_3_1.h" 67 #include "hdp_v5_0.h" 68 #include "hdp_v5_2.h" 69 #include "hdp_v6_0.h" 70 #include "hdp_v7_0.h" 71 #include "nv.h" 72 #include "soc21.h" 73 #include "soc24.h" 74 #include "soc_v1_0.h" 75 #include "navi10_ih.h" 76 #include "ih_v6_0.h" 77 #include "ih_v6_1.h" 78 #include "ih_v7_0.h" 79 #include "gfx_v10_0.h" 80 #include "gfx_v11_0.h" 81 #include "gfx_v12_0.h" 82 #include "gfx_v12_1.h" 83 #include "sdma_v5_0.h" 84 #include "sdma_v5_2.h" 85 #include "sdma_v6_0.h" 86 #include "sdma_v7_0.h" 87 #include "sdma_v7_1.h" 88 #include "lsdma_v6_0.h" 89 #include "lsdma_v7_0.h" 90 #include "vcn_v2_0.h" 91 #include "jpeg_v2_0.h" 92 #include "vcn_v3_0.h" 93 #include "jpeg_v3_0.h" 94 #include "vcn_v4_0.h" 95 #include "jpeg_v4_0.h" 96 #include "vcn_v4_0_3.h" 97 #include "jpeg_v4_0_3.h" 98 #include "vcn_v4_0_5.h" 99 #include "jpeg_v4_0_5.h" 100 #include "amdgpu_vkms.h" 101 #include "mes_v11_0.h" 102 #include "mes_v12_0.h" 103 #include "mes_v12_1.h" 104 #include "smuio_v11_0.h" 105 #include "smuio_v11_0_6.h" 106 #include "smuio_v13_0.h" 107 #include "smuio_v13_0_3.h" 108 #include "smuio_v13_0_6.h" 109 #include "smuio_v14_0_2.h" 110 #include "smuio_v15_0_0.h" 111 #include "smuio_v15_0_8.h" 112 #include "vcn_v5_0_0.h" 113 #include "vcn_v5_0_1.h" 114 #include "jpeg_v5_0_0.h" 115 #include "jpeg_v5_0_1.h" 116 #include "jpeg_v5_3_0.h" 117 118 #include "amdgpu_ras_mgr.h" 119 120 #include "amdgpu_vpe.h" 121 #if defined(CONFIG_DRM_AMD_ISP) 122 #include "amdgpu_isp.h" 123 #endif 124 125 MODULE_FIRMWARE("amdgpu/ip_discovery.bin"); 126 MODULE_FIRMWARE("amdgpu/vega10_ip_discovery.bin"); 127 MODULE_FIRMWARE("amdgpu/vega12_ip_discovery.bin"); 128 MODULE_FIRMWARE("amdgpu/vega20_ip_discovery.bin"); 129 MODULE_FIRMWARE("amdgpu/raven_ip_discovery.bin"); 130 MODULE_FIRMWARE("amdgpu/raven2_ip_discovery.bin"); 131 MODULE_FIRMWARE("amdgpu/picasso_ip_discovery.bin"); 132 MODULE_FIRMWARE("amdgpu/arcturus_ip_discovery.bin"); 133 MODULE_FIRMWARE("amdgpu/aldebaran_ip_discovery.bin"); 134 135 #define mmIP_DISCOVERY_VERSION 0x16A00 136 #define mmRCC_CONFIG_MEMSIZE 0xde3 137 #define mmMP0_SMN_C2PMSG_33 0x16061 138 #define mmMM_INDEX 0x0 139 #define mmMM_INDEX_HI 0x6 140 #define mmMM_DATA 0x1 141 142 static const char *hw_id_names[HW_ID_MAX] = { 143 [MP1_HWID] = "MP1", 144 [MP2_HWID] = "MP2", 145 [THM_HWID] = "THM", 146 [SMUIO_HWID] = "SMUIO", 147 [FUSE_HWID] = "FUSE", 148 [CLKA_HWID] = "CLKA", 149 [PWR_HWID] = "PWR", 150 [GC_HWID] = "GC", 151 [UVD_HWID] = "UVD", 152 [AUDIO_AZ_HWID] = "AUDIO_AZ", 153 [ACP_HWID] = "ACP", 154 [DCI_HWID] = "DCI", 155 [DMU_HWID] = "DMU", 156 [DCO_HWID] = "DCO", 157 [DIO_HWID] = "DIO", 158 [XDMA_HWID] = "XDMA", 159 [DCEAZ_HWID] = "DCEAZ", 160 [DAZ_HWID] = "DAZ", 161 [SDPMUX_HWID] = "SDPMUX", 162 [NTB_HWID] = "NTB", 163 [IOHC_HWID] = "IOHC", 164 [L2IMU_HWID] = "L2IMU", 165 [VCE_HWID] = "VCE", 166 [MMHUB_HWID] = "MMHUB", 167 [ATHUB_HWID] = "ATHUB", 168 [DBGU_NBIO_HWID] = "DBGU_NBIO", 169 [DFX_HWID] = "DFX", 170 [DBGU0_HWID] = "DBGU0", 171 [DBGU1_HWID] = "DBGU1", 172 [OSSSYS_HWID] = "OSSSYS", 173 [HDP_HWID] = "HDP", 174 [SDMA0_HWID] = "SDMA0", 175 [SDMA1_HWID] = "SDMA1", 176 [SDMA2_HWID] = "SDMA2", 177 [SDMA3_HWID] = "SDMA3", 178 [LSDMA_HWID] = "LSDMA", 179 [ISP_HWID] = "ISP", 180 [DBGU_IO_HWID] = "DBGU_IO", 181 [DF_HWID] = "DF", 182 [CLKB_HWID] = "CLKB", 183 [FCH_HWID] = "FCH", 184 [DFX_DAP_HWID] = "DFX_DAP", 185 [L1IMU_PCIE_HWID] = "L1IMU_PCIE", 186 [L1IMU_NBIF_HWID] = "L1IMU_NBIF", 187 [L1IMU_IOAGR_HWID] = "L1IMU_IOAGR", 188 [L1IMU3_HWID] = "L1IMU3", 189 [L1IMU4_HWID] = "L1IMU4", 190 [L1IMU5_HWID] = "L1IMU5", 191 [L1IMU6_HWID] = "L1IMU6", 192 [L1IMU7_HWID] = "L1IMU7", 193 [L1IMU8_HWID] = "L1IMU8", 194 [L1IMU9_HWID] = "L1IMU9", 195 [L1IMU10_HWID] = "L1IMU10", 196 [L1IMU11_HWID] = "L1IMU11", 197 [L1IMU12_HWID] = "L1IMU12", 198 [L1IMU13_HWID] = "L1IMU13", 199 [L1IMU14_HWID] = "L1IMU14", 200 [L1IMU15_HWID] = "L1IMU15", 201 [WAFLC_HWID] = "WAFLC", 202 [FCH_USB_PD_HWID] = "FCH_USB_PD", 203 [PCIE_HWID] = "PCIE", 204 [PCS_HWID] = "PCS", 205 [DDCL_HWID] = "DDCL", 206 [SST_HWID] = "SST", 207 [IOAGR_HWID] = "IOAGR", 208 [NBIF_HWID] = "NBIF", 209 [IOAPIC_HWID] = "IOAPIC", 210 [SYSTEMHUB_HWID] = "SYSTEMHUB", 211 [NTBCCP_HWID] = "NTBCCP", 212 [UMC_HWID] = "UMC", 213 [SATA_HWID] = "SATA", 214 [USB_HWID] = "USB", 215 [CCXSEC_HWID] = "CCXSEC", 216 [XGMI_HWID] = "XGMI", 217 [XGBE_HWID] = "XGBE", 218 [MP0_HWID] = "MP0", 219 [VPE_HWID] = "VPE", 220 [ATU_HWID] = "ATU", 221 [AIGC_HWID] = "AIGC", 222 }; 223 224 static int hw_id_map[MAX_HWIP] = { 225 [GC_HWIP] = GC_HWID, 226 [HDP_HWIP] = HDP_HWID, 227 [SDMA0_HWIP] = SDMA0_HWID, 228 [SDMA1_HWIP] = SDMA1_HWID, 229 [SDMA2_HWIP] = SDMA2_HWID, 230 [SDMA3_HWIP] = SDMA3_HWID, 231 [LSDMA_HWIP] = LSDMA_HWID, 232 [MMHUB_HWIP] = MMHUB_HWID, 233 [ATHUB_HWIP] = ATHUB_HWID, 234 [NBIO_HWIP] = NBIF_HWID, 235 [MP0_HWIP] = MP0_HWID, 236 [MP1_HWIP] = MP1_HWID, 237 [UVD_HWIP] = UVD_HWID, 238 [VCE_HWIP] = VCE_HWID, 239 [DF_HWIP] = DF_HWID, 240 [DCE_HWIP] = DMU_HWID, 241 [OSSSYS_HWIP] = OSSSYS_HWID, 242 [SMUIO_HWIP] = SMUIO_HWID, 243 [PWR_HWIP] = PWR_HWID, 244 [NBIF_HWIP] = NBIF_HWID, 245 [THM_HWIP] = THM_HWID, 246 [CLK_HWIP] = CLKA_HWID, 247 [UMC_HWIP] = UMC_HWID, 248 [XGMI_HWIP] = XGMI_HWID, 249 [DCI_HWIP] = DCI_HWID, 250 [PCIE_HWIP] = PCIE_HWID, 251 [VPE_HWIP] = VPE_HWID, 252 [ISP_HWIP] = ISP_HWID, 253 [ATU_HWIP] = ATU_HWID, 254 }; 255 256 static int amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device *adev, uint8_t *binary) 257 { 258 u64 tmr_offset, tmr_size, pos; 259 void *discv_regn; 260 int ret; 261 262 ret = amdgpu_acpi_get_tmr_info(adev, &tmr_offset, &tmr_size); 263 if (ret) 264 return ret; 265 266 pos = tmr_offset + tmr_size - DISCOVERY_TMR_OFFSET; 267 268 /* This region is read-only and reserved from system use */ 269 discv_regn = memremap(pos, adev->discovery.size, MEMREMAP_WC); 270 if (discv_regn) { 271 memcpy(binary, discv_regn, adev->discovery.size); 272 memunmap(discv_regn); 273 return 0; 274 } 275 276 return -ENOENT; 277 } 278 279 #define IP_DISCOVERY_V2 2 280 #define IP_DISCOVERY_V4 4 281 282 static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev, 283 uint8_t *binary) 284 { 285 bool sz_valid = true; 286 uint64_t vram_size; 287 int i, ret = 0; 288 u32 msg; 289 290 if (!amdgpu_sriov_vf(adev)) { 291 /* It can take up to two second for IFWI init to complete on some dGPUs, 292 * but generally it should be in the 60-100ms range. Normally this starts 293 * as soon as the device gets power so by the time the OS loads this has long 294 * completed. However, when a card is hotplugged via e.g., USB4, we need to 295 * wait for this to complete. Once the C2PMSG is updated, we can 296 * continue. 297 */ 298 299 for (i = 0; i < 2000; i++) { 300 msg = RREG32(mmMP0_SMN_C2PMSG_33); 301 if (msg & 0x80000000) 302 break; 303 msleep(1); 304 } 305 } 306 307 vram_size = RREG32(mmRCC_CONFIG_MEMSIZE); 308 if (!vram_size || vram_size == U32_MAX) 309 sz_valid = false; 310 else 311 vram_size <<= 20; 312 313 /* 314 * If in VRAM, discovery TMR is marked for reservation. If it is in system mem, 315 * then it is not required to be reserved. 316 */ 317 if (sz_valid) { 318 if (amdgpu_sriov_vf(adev) && adev->virt.is_dynamic_crit_regn_enabled) { 319 /* For SRIOV VFs with dynamic critical region enabled, 320 * we will get the IPD binary via below call. 321 * If dynamic critical is disabled, fall through to normal seq. 322 */ 323 if (amdgpu_virt_get_dynamic_data_info(adev, 324 AMD_SRIOV_MSG_IPD_TABLE_ID, binary, 325 &adev->discovery.size)) { 326 dev_err(adev->dev, 327 "failed to read discovery info from dynamic critical region."); 328 ret = -EINVAL; 329 goto exit; 330 } 331 } else { 332 uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET; 333 334 amdgpu_device_vram_access(adev, pos, (uint32_t *)binary, 335 adev->discovery.size, false); 336 adev->discovery.reserve_tmr = true; 337 } 338 } else { 339 ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary); 340 } 341 342 if (ret) 343 dev_err(adev->dev, 344 "failed to read discovery info from memory, vram size read: %llx", 345 vram_size); 346 exit: 347 return ret; 348 } 349 350 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, 351 uint8_t *binary, 352 const char *fw_name) 353 { 354 const struct firmware *fw; 355 int r; 356 357 r = firmware_request_nowarn(&fw, fw_name, adev->dev); 358 if (r) { 359 if (amdgpu_discovery == 2) 360 dev_err(adev->dev, "can't load firmware \"%s\"\n", fw_name); 361 else 362 drm_info(&adev->ddev, "Optional firmware \"%s\" was not found\n", fw_name); 363 return r; 364 } 365 366 memcpy((u8 *)binary, (u8 *)fw->data, fw->size); 367 release_firmware(fw); 368 369 return 0; 370 } 371 372 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size) 373 { 374 uint16_t checksum = 0; 375 int i; 376 377 for (i = 0; i < size; i++) 378 checksum += data[i]; 379 380 return checksum; 381 } 382 383 static inline bool amdgpu_discovery_verify_checksum(struct amdgpu_device *adev, 384 uint8_t *data, uint32_t size, 385 uint16_t expected) 386 { 387 uint16_t calculated; 388 389 calculated = amdgpu_discovery_calculate_checksum(data, size); 390 391 if (calculated != expected) { 392 dev_err(adev->dev, "Discovery checksum failed: calc 0x%04x != exp 0x%04x, size %u.\n", 393 calculated, expected, size); 394 return false; 395 } 396 397 return true; 398 } 399 400 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary) 401 { 402 struct binary_header *bhdr; 403 bhdr = (struct binary_header *)binary; 404 405 return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE); 406 } 407 408 static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev) 409 { 410 /* 411 * So far, apply this quirk only on those Navy Flounder boards which 412 * have a bad harvest table of VCN config. 413 */ 414 if ((amdgpu_ip_version(adev, UVD_HWIP, 1) == IP_VERSION(3, 0, 1)) && 415 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 2))) { 416 switch (adev->pdev->revision) { 417 case 0xC1: 418 case 0xC2: 419 case 0xC3: 420 case 0xC5: 421 case 0xC7: 422 case 0xCF: 423 case 0xDF: 424 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 425 adev->vcn.inst_mask &= ~AMDGPU_VCN_HARVEST_VCN1; 426 break; 427 default: 428 break; 429 } 430 } 431 } 432 433 static int amdgpu_discovery_verify_npsinfo(struct amdgpu_device *adev, 434 struct binary_header *bhdr) 435 { 436 uint8_t *discovery_bin = adev->discovery.bin; 437 struct table_info *info; 438 uint16_t checksum; 439 uint16_t offset; 440 441 info = &bhdr->table_list[NPS_INFO]; 442 offset = le16_to_cpu(info->offset); 443 checksum = le16_to_cpu(info->checksum); 444 445 struct nps_info_header *nhdr = 446 (struct nps_info_header *)(discovery_bin + offset); 447 448 if (le32_to_cpu(nhdr->table_id) != NPS_INFO_TABLE_ID) { 449 dev_dbg(adev->dev, "invalid ip discovery nps info table id\n"); 450 return -EINVAL; 451 } 452 453 if (!amdgpu_discovery_verify_checksum(adev, discovery_bin + offset, 454 le32_to_cpu(nhdr->size_bytes), 455 checksum)) { 456 dev_dbg(adev->dev, "invalid nps info data table checksum\n"); 457 return -EINVAL; 458 } 459 460 return 0; 461 } 462 463 static const char *amdgpu_discovery_get_fw_name(struct amdgpu_device *adev) 464 { 465 if (amdgpu_discovery == 2) { 466 /* Assume there is valid discovery TMR in VRAM even if binary is sideloaded */ 467 adev->discovery.reserve_tmr = true; 468 return "amdgpu/ip_discovery.bin"; 469 } 470 471 switch (adev->asic_type) { 472 case CHIP_VEGA10: 473 return "amdgpu/vega10_ip_discovery.bin"; 474 case CHIP_VEGA12: 475 return "amdgpu/vega12_ip_discovery.bin"; 476 case CHIP_RAVEN: 477 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 478 return "amdgpu/raven2_ip_discovery.bin"; 479 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 480 return "amdgpu/picasso_ip_discovery.bin"; 481 else 482 return "amdgpu/raven_ip_discovery.bin"; 483 case CHIP_VEGA20: 484 return "amdgpu/vega20_ip_discovery.bin"; 485 case CHIP_ARCTURUS: 486 return "amdgpu/arcturus_ip_discovery.bin"; 487 case CHIP_ALDEBARAN: 488 return "amdgpu/aldebaran_ip_discovery.bin"; 489 default: 490 return NULL; 491 } 492 } 493 494 static int amdgpu_discovery_init(struct amdgpu_device *adev) 495 { 496 struct table_info *info; 497 struct binary_header *bhdr; 498 uint8_t *discovery_bin; 499 const char *fw_name; 500 uint16_t offset; 501 uint16_t size; 502 uint16_t checksum; 503 int r; 504 505 adev->discovery.bin = kzalloc(DISCOVERY_TMR_SIZE, GFP_KERNEL); 506 if (!adev->discovery.bin) 507 return -ENOMEM; 508 adev->discovery.size = DISCOVERY_TMR_SIZE; 509 adev->discovery.debugfs_blob.data = adev->discovery.bin; 510 adev->discovery.debugfs_blob.size = adev->discovery.size; 511 512 discovery_bin = adev->discovery.bin; 513 /* Read from file if it is the preferred option */ 514 fw_name = amdgpu_discovery_get_fw_name(adev); 515 if (fw_name != NULL) { 516 drm_dbg(&adev->ddev, "use ip discovery information from file"); 517 r = amdgpu_discovery_read_binary_from_file(adev, discovery_bin, 518 fw_name); 519 if (r) 520 goto out; 521 } else { 522 drm_dbg(&adev->ddev, "use ip discovery information from memory"); 523 r = amdgpu_discovery_read_binary_from_mem(adev, discovery_bin); 524 if (r) 525 goto out; 526 } 527 528 /* check the ip discovery binary signature */ 529 if (!amdgpu_discovery_verify_binary_signature(discovery_bin)) { 530 dev_err(adev->dev, 531 "get invalid ip discovery binary signature\n"); 532 r = -EINVAL; 533 goto out; 534 } 535 536 bhdr = (struct binary_header *)discovery_bin; 537 538 offset = offsetof(struct binary_header, binary_checksum) + 539 sizeof(bhdr->binary_checksum); 540 size = le16_to_cpu(bhdr->binary_size) - offset; 541 checksum = le16_to_cpu(bhdr->binary_checksum); 542 543 if (!amdgpu_discovery_verify_checksum(adev, discovery_bin + offset, size, 544 checksum)) { 545 dev_err(adev->dev, "invalid ip discovery binary checksum\n"); 546 r = -EINVAL; 547 goto out; 548 } 549 550 info = &bhdr->table_list[IP_DISCOVERY]; 551 offset = le16_to_cpu(info->offset); 552 checksum = le16_to_cpu(info->checksum); 553 554 if (offset) { 555 struct ip_discovery_header *ihdr = 556 (struct ip_discovery_header *)(discovery_bin + offset); 557 if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) { 558 dev_err(adev->dev, "invalid ip discovery data table signature\n"); 559 r = -EINVAL; 560 goto out; 561 } 562 563 if (!amdgpu_discovery_verify_checksum(adev, discovery_bin + offset, 564 le16_to_cpu(ihdr->size), 565 checksum)) { 566 dev_err(adev->dev, "invalid ip discovery data table checksum\n"); 567 r = -EINVAL; 568 goto out; 569 } 570 } 571 572 info = &bhdr->table_list[GC]; 573 offset = le16_to_cpu(info->offset); 574 checksum = le16_to_cpu(info->checksum); 575 576 if (offset) { 577 struct gpu_info_header *ghdr = 578 (struct gpu_info_header *)(discovery_bin + offset); 579 580 if (le32_to_cpu(ghdr->table_id) != GC_TABLE_ID) { 581 dev_err(adev->dev, "invalid ip discovery gc table id\n"); 582 r = -EINVAL; 583 goto out; 584 } 585 586 if (!amdgpu_discovery_verify_checksum(adev, discovery_bin + offset, 587 le32_to_cpu(ghdr->size), 588 checksum)) { 589 dev_err(adev->dev, "invalid gc data table checksum\n"); 590 r = -EINVAL; 591 goto out; 592 } 593 } 594 595 info = &bhdr->table_list[HARVEST_INFO]; 596 offset = le16_to_cpu(info->offset); 597 checksum = le16_to_cpu(info->checksum); 598 599 if (offset) { 600 struct harvest_info_header *hhdr = 601 (struct harvest_info_header *)(discovery_bin + offset); 602 603 if (le32_to_cpu(hhdr->signature) != HARVEST_TABLE_SIGNATURE) { 604 dev_err(adev->dev, "invalid ip discovery harvest table signature\n"); 605 r = -EINVAL; 606 goto out; 607 } 608 609 if (!amdgpu_discovery_verify_checksum(adev, 610 discovery_bin + offset, 611 sizeof(struct harvest_table), checksum)) { 612 dev_err(adev->dev, "invalid harvest data table checksum\n"); 613 r = -EINVAL; 614 goto out; 615 } 616 } 617 618 info = &bhdr->table_list[VCN_INFO]; 619 offset = le16_to_cpu(info->offset); 620 checksum = le16_to_cpu(info->checksum); 621 622 if (offset) { 623 struct vcn_info_header *vhdr = 624 (struct vcn_info_header *)(discovery_bin + offset); 625 626 if (le32_to_cpu(vhdr->table_id) != VCN_INFO_TABLE_ID) { 627 dev_err(adev->dev, "invalid ip discovery vcn table id\n"); 628 r = -EINVAL; 629 goto out; 630 } 631 632 if (!amdgpu_discovery_verify_checksum(adev, 633 discovery_bin + offset, 634 le32_to_cpu(vhdr->size_bytes), checksum)) { 635 dev_err(adev->dev, "invalid vcn data table checksum\n"); 636 r = -EINVAL; 637 goto out; 638 } 639 } 640 641 info = &bhdr->table_list[MALL_INFO]; 642 offset = le16_to_cpu(info->offset); 643 checksum = le16_to_cpu(info->checksum); 644 645 if (0 && offset) { 646 struct mall_info_header *mhdr = 647 (struct mall_info_header *)(discovery_bin + offset); 648 649 if (le32_to_cpu(mhdr->table_id) != MALL_INFO_TABLE_ID) { 650 dev_err(adev->dev, "invalid ip discovery mall table id\n"); 651 r = -EINVAL; 652 goto out; 653 } 654 655 if (!amdgpu_discovery_verify_checksum(adev, 656 discovery_bin + offset, 657 le32_to_cpu(mhdr->size_bytes), checksum)) { 658 dev_err(adev->dev, "invalid mall data table checksum\n"); 659 r = -EINVAL; 660 goto out; 661 } 662 } 663 664 return 0; 665 666 out: 667 kfree(adev->discovery.bin); 668 adev->discovery.bin = NULL; 669 if ((amdgpu_discovery != 2) && 670 (RREG32(mmIP_DISCOVERY_VERSION) == 4)) 671 amdgpu_ras_query_boot_status(adev, 4); 672 return r; 673 } 674 675 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev); 676 677 void amdgpu_discovery_fini(struct amdgpu_device *adev) 678 { 679 amdgpu_discovery_sysfs_fini(adev); 680 kfree(adev->discovery.bin); 681 adev->discovery.bin = NULL; 682 } 683 684 static int amdgpu_discovery_validate_ip(struct amdgpu_device *adev, 685 uint8_t instance, uint16_t hw_id) 686 { 687 if (instance >= HWIP_MAX_INSTANCE) { 688 dev_err(adev->dev, 689 "Unexpected instance_number (%d) from ip discovery blob\n", 690 instance); 691 return -EINVAL; 692 } 693 if (hw_id >= HW_ID_MAX) { 694 dev_err(adev->dev, 695 "Unexpected hw_id (%d) from ip discovery blob\n", 696 hw_id); 697 return -EINVAL; 698 } 699 700 return 0; 701 } 702 703 static void amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device *adev, 704 uint32_t *vcn_harvest_count) 705 { 706 uint8_t *discovery_bin = adev->discovery.bin; 707 struct binary_header *bhdr; 708 struct ip_discovery_header *ihdr; 709 struct die_header *dhdr; 710 struct ip *ip; 711 uint16_t die_offset, ip_offset, num_dies, num_ips; 712 uint16_t hw_id; 713 uint8_t inst; 714 int i, j; 715 716 bhdr = (struct binary_header *)discovery_bin; 717 ihdr = (struct ip_discovery_header 718 *)(discovery_bin + 719 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 720 num_dies = le16_to_cpu(ihdr->num_dies); 721 722 /* scan harvest bit of all IP data structures */ 723 for (i = 0; i < num_dies; i++) { 724 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 725 dhdr = (struct die_header *)(discovery_bin + die_offset); 726 num_ips = le16_to_cpu(dhdr->num_ips); 727 ip_offset = die_offset + sizeof(*dhdr); 728 729 for (j = 0; j < num_ips; j++) { 730 ip = (struct ip *)(discovery_bin + ip_offset); 731 inst = ip->number_instance; 732 hw_id = le16_to_cpu(ip->hw_id); 733 if (amdgpu_discovery_validate_ip(adev, inst, hw_id)) 734 goto next_ip; 735 736 if (ip->harvest == 1) { 737 switch (hw_id) { 738 case VCN_HWID: 739 (*vcn_harvest_count)++; 740 if (inst == 0) { 741 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0; 742 adev->vcn.inst_mask &= 743 ~AMDGPU_VCN_HARVEST_VCN0; 744 adev->jpeg.inst_mask &= 745 ~AMDGPU_VCN_HARVEST_VCN0; 746 } else { 747 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 748 adev->vcn.inst_mask &= 749 ~AMDGPU_VCN_HARVEST_VCN1; 750 adev->jpeg.inst_mask &= 751 ~AMDGPU_VCN_HARVEST_VCN1; 752 } 753 break; 754 case DMU_HWID: 755 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 756 break; 757 default: 758 break; 759 } 760 } 761 next_ip: 762 ip_offset += struct_size(ip, base_address, 763 ip->num_base_address); 764 } 765 } 766 } 767 768 static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev, 769 uint32_t *vcn_harvest_count, 770 uint32_t *umc_harvest_count) 771 { 772 uint8_t *discovery_bin = adev->discovery.bin; 773 struct binary_header *bhdr; 774 struct harvest_table *harvest_info; 775 u16 offset; 776 int i; 777 uint32_t umc_harvest_config = 0; 778 779 bhdr = (struct binary_header *)discovery_bin; 780 offset = le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset); 781 782 if (!offset) { 783 dev_err(adev->dev, "invalid harvest table offset\n"); 784 return; 785 } 786 787 harvest_info = (struct harvest_table *)(discovery_bin + offset); 788 789 for (i = 0; i < 32; i++) { 790 if (le16_to_cpu(harvest_info->list[i].hw_id) == 0) 791 break; 792 793 switch (le16_to_cpu(harvest_info->list[i].hw_id)) { 794 case VCN_HWID: 795 (*vcn_harvest_count)++; 796 adev->vcn.harvest_config |= 797 (1 << harvest_info->list[i].number_instance); 798 adev->jpeg.harvest_config |= 799 (1 << harvest_info->list[i].number_instance); 800 801 adev->vcn.inst_mask &= 802 ~(1U << harvest_info->list[i].number_instance); 803 adev->jpeg.inst_mask &= 804 ~(1U << harvest_info->list[i].number_instance); 805 break; 806 case DMU_HWID: 807 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 808 break; 809 case UMC_HWID: 810 umc_harvest_config |= 811 1 << (le16_to_cpu(harvest_info->list[i].number_instance)); 812 (*umc_harvest_count)++; 813 break; 814 case GC_HWID: 815 adev->gfx.xcc_mask &= 816 ~(1U << harvest_info->list[i].number_instance); 817 break; 818 case SDMA0_HWID: 819 adev->sdma.sdma_mask &= 820 ~(1U << harvest_info->list[i].number_instance); 821 break; 822 #if defined(CONFIG_DRM_AMD_ISP) 823 case ISP_HWID: 824 adev->isp.harvest_config |= 825 ~(1U << harvest_info->list[i].number_instance); 826 break; 827 #endif 828 default: 829 break; 830 } 831 } 832 833 adev->umc.active_mask = ((1 << adev->umc.node_inst_num) - 1) & 834 ~umc_harvest_config; 835 } 836 837 /* ================================================== */ 838 839 struct ip_hw_instance { 840 struct kobject kobj; /* ip_discovery/die/#die/#hw_id/#instance/<attrs...> */ 841 842 int hw_id; 843 u8 num_instance; 844 u8 major, minor, revision; 845 u8 harvest; 846 847 int num_base_addresses; 848 u32 base_addr[] __counted_by(num_base_addresses); 849 }; 850 851 struct ip_hw_id { 852 struct kset hw_id_kset; /* ip_discovery/die/#die/#hw_id/, contains ip_hw_instance */ 853 int hw_id; 854 }; 855 856 struct ip_die_entry { 857 struct kset ip_kset; /* ip_discovery/die/#die/, contains ip_hw_id */ 858 u16 num_ips; 859 }; 860 861 /* -------------------------------------------------- */ 862 863 struct ip_hw_instance_attr { 864 struct attribute attr; 865 ssize_t (*show)(struct ip_hw_instance *ip_hw_instance, char *buf); 866 }; 867 868 static ssize_t hw_id_show(struct ip_hw_instance *ip_hw_instance, char *buf) 869 { 870 return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id); 871 } 872 873 static ssize_t num_instance_show(struct ip_hw_instance *ip_hw_instance, char *buf) 874 { 875 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance); 876 } 877 878 static ssize_t major_show(struct ip_hw_instance *ip_hw_instance, char *buf) 879 { 880 return sysfs_emit(buf, "%d\n", ip_hw_instance->major); 881 } 882 883 static ssize_t minor_show(struct ip_hw_instance *ip_hw_instance, char *buf) 884 { 885 return sysfs_emit(buf, "%d\n", ip_hw_instance->minor); 886 } 887 888 static ssize_t revision_show(struct ip_hw_instance *ip_hw_instance, char *buf) 889 { 890 return sysfs_emit(buf, "%d\n", ip_hw_instance->revision); 891 } 892 893 static ssize_t harvest_show(struct ip_hw_instance *ip_hw_instance, char *buf) 894 { 895 return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest); 896 } 897 898 static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, char *buf) 899 { 900 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses); 901 } 902 903 static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf) 904 { 905 ssize_t at; 906 int ii; 907 908 for (at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) { 909 /* Here we satisfy the condition that, at + size <= PAGE_SIZE. 910 */ 911 if (at + 12 > PAGE_SIZE) 912 break; 913 at += sysfs_emit_at(buf, at, "0x%08X\n", 914 ip_hw_instance->base_addr[ii]); 915 } 916 917 return at; 918 } 919 920 static struct ip_hw_instance_attr ip_hw_attr[] = { 921 __ATTR_RO(hw_id), 922 __ATTR_RO(num_instance), 923 __ATTR_RO(major), 924 __ATTR_RO(minor), 925 __ATTR_RO(revision), 926 __ATTR_RO(harvest), 927 __ATTR_RO(num_base_addresses), 928 __ATTR_RO(base_addr), 929 }; 930 931 static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1]; 932 ATTRIBUTE_GROUPS(ip_hw_instance); 933 934 #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj) 935 #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr) 936 937 static ssize_t ip_hw_instance_attr_show(struct kobject *kobj, 938 struct attribute *attr, 939 char *buf) 940 { 941 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 942 struct ip_hw_instance_attr *ip_hw_attr = to_ip_hw_instance_attr(attr); 943 944 if (!ip_hw_attr->show) 945 return -EIO; 946 947 return ip_hw_attr->show(ip_hw_instance, buf); 948 } 949 950 static const struct sysfs_ops ip_hw_instance_sysfs_ops = { 951 .show = ip_hw_instance_attr_show, 952 }; 953 954 static void ip_hw_instance_release(struct kobject *kobj) 955 { 956 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 957 958 kfree(ip_hw_instance); 959 } 960 961 static const struct kobj_type ip_hw_instance_ktype = { 962 .release = ip_hw_instance_release, 963 .sysfs_ops = &ip_hw_instance_sysfs_ops, 964 .default_groups = ip_hw_instance_groups, 965 }; 966 967 /* -------------------------------------------------- */ 968 969 #define to_ip_hw_id(x) container_of(to_kset(x), struct ip_hw_id, hw_id_kset) 970 971 static void ip_hw_id_release(struct kobject *kobj) 972 { 973 struct ip_hw_id *ip_hw_id = to_ip_hw_id(kobj); 974 975 if (!list_empty(&ip_hw_id->hw_id_kset.list)) 976 DRM_ERROR("ip_hw_id->hw_id_kset is not empty"); 977 kfree(ip_hw_id); 978 } 979 980 static const struct kobj_type ip_hw_id_ktype = { 981 .release = ip_hw_id_release, 982 .sysfs_ops = &kobj_sysfs_ops, 983 }; 984 985 /* -------------------------------------------------- */ 986 987 static void die_kobj_release(struct kobject *kobj); 988 static void ip_disc_release(struct kobject *kobj); 989 990 struct ip_die_entry_attribute { 991 struct attribute attr; 992 ssize_t (*show)(struct ip_die_entry *ip_die_entry, char *buf); 993 }; 994 995 #define to_ip_die_entry_attr(x) container_of(x, struct ip_die_entry_attribute, attr) 996 997 static ssize_t num_ips_show(struct ip_die_entry *ip_die_entry, char *buf) 998 { 999 return sysfs_emit(buf, "%d\n", ip_die_entry->num_ips); 1000 } 1001 1002 /* If there are more ip_die_entry attrs, other than the number of IPs, 1003 * we can make this intro an array of attrs, and then initialize 1004 * ip_die_entry_attrs in a loop. 1005 */ 1006 static struct ip_die_entry_attribute num_ips_attr = 1007 __ATTR_RO(num_ips); 1008 1009 static struct attribute *ip_die_entry_attrs[] = { 1010 &num_ips_attr.attr, 1011 NULL, 1012 }; 1013 ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */ 1014 1015 #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset) 1016 1017 static ssize_t ip_die_entry_attr_show(struct kobject *kobj, 1018 struct attribute *attr, 1019 char *buf) 1020 { 1021 struct ip_die_entry_attribute *ip_die_entry_attr = to_ip_die_entry_attr(attr); 1022 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 1023 1024 if (!ip_die_entry_attr->show) 1025 return -EIO; 1026 1027 return ip_die_entry_attr->show(ip_die_entry, buf); 1028 } 1029 1030 static void ip_die_entry_release(struct kobject *kobj) 1031 { 1032 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 1033 1034 if (!list_empty(&ip_die_entry->ip_kset.list)) 1035 DRM_ERROR("ip_die_entry->ip_kset is not empty"); 1036 kfree(ip_die_entry); 1037 } 1038 1039 static const struct sysfs_ops ip_die_entry_sysfs_ops = { 1040 .show = ip_die_entry_attr_show, 1041 }; 1042 1043 static const struct kobj_type ip_die_entry_ktype = { 1044 .release = ip_die_entry_release, 1045 .sysfs_ops = &ip_die_entry_sysfs_ops, 1046 .default_groups = ip_die_entry_groups, 1047 }; 1048 1049 static const struct kobj_type die_kobj_ktype = { 1050 .release = die_kobj_release, 1051 .sysfs_ops = &kobj_sysfs_ops, 1052 }; 1053 1054 static const struct kobj_type ip_discovery_ktype = { 1055 .release = ip_disc_release, 1056 .sysfs_ops = &kobj_sysfs_ops, 1057 }; 1058 1059 struct ip_discovery_top { 1060 struct kobject kobj; /* ip_discovery/ */ 1061 struct kset die_kset; /* ip_discovery/die/, contains ip_die_entry */ 1062 struct amdgpu_device *adev; 1063 }; 1064 1065 static void die_kobj_release(struct kobject *kobj) 1066 { 1067 struct ip_discovery_top *ip_top = container_of(to_kset(kobj), 1068 struct ip_discovery_top, 1069 die_kset); 1070 if (!list_empty(&ip_top->die_kset.list)) 1071 DRM_ERROR("ip_top->die_kset is not empty"); 1072 } 1073 1074 static void ip_disc_release(struct kobject *kobj) 1075 { 1076 struct ip_discovery_top *ip_top = container_of(kobj, struct ip_discovery_top, 1077 kobj); 1078 struct amdgpu_device *adev = ip_top->adev; 1079 1080 kfree(ip_top); 1081 adev->discovery.ip_top = NULL; 1082 } 1083 1084 static uint8_t amdgpu_discovery_get_harvest_info(struct amdgpu_device *adev, 1085 uint16_t hw_id, uint8_t inst) 1086 { 1087 uint8_t harvest = 0; 1088 1089 /* Until a uniform way is figured, get mask based on hwid */ 1090 switch (hw_id) { 1091 case VCN_HWID: 1092 /* VCN vs UVD+VCE */ 1093 if (!amdgpu_ip_version(adev, VCE_HWIP, 0)) 1094 harvest = ((1 << inst) & adev->vcn.inst_mask) == 0; 1095 break; 1096 case DMU_HWID: 1097 if (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK) 1098 harvest = 0x1; 1099 break; 1100 case UMC_HWID: 1101 /* TODO: It needs another parsing; for now, ignore.*/ 1102 break; 1103 case GC_HWID: 1104 harvest = ((1 << inst) & adev->gfx.xcc_mask) == 0; 1105 break; 1106 case SDMA0_HWID: 1107 harvest = ((1 << inst) & adev->sdma.sdma_mask) == 0; 1108 break; 1109 default: 1110 break; 1111 } 1112 1113 return harvest; 1114 } 1115 1116 static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev, 1117 struct ip_die_entry *ip_die_entry, 1118 const size_t _ip_offset, const int num_ips, 1119 bool reg_base_64) 1120 { 1121 uint8_t *discovery_bin = adev->discovery.bin; 1122 int ii, jj, kk, res; 1123 uint16_t hw_id; 1124 uint8_t inst; 1125 1126 DRM_DEBUG("num_ips:%d", num_ips); 1127 1128 /* Find all IPs of a given HW ID, and add their instance to 1129 * #die/#hw_id/#instance/<attributes> 1130 */ 1131 for (ii = 0; ii < HW_ID_MAX; ii++) { 1132 struct ip_hw_id *ip_hw_id = NULL; 1133 size_t ip_offset = _ip_offset; 1134 1135 for (jj = 0; jj < num_ips; jj++) { 1136 struct ip_v4 *ip; 1137 struct ip_hw_instance *ip_hw_instance; 1138 1139 ip = (struct ip_v4 *)(discovery_bin + ip_offset); 1140 inst = ip->instance_number; 1141 hw_id = le16_to_cpu(ip->hw_id); 1142 if (amdgpu_discovery_validate_ip(adev, inst, hw_id) || 1143 hw_id != ii) 1144 goto next_ip; 1145 1146 DRM_DEBUG("match:%d @ ip_offset:%zu", ii, ip_offset); 1147 1148 /* We have a hw_id match; register the hw 1149 * block if not yet registered. 1150 */ 1151 if (!ip_hw_id) { 1152 ip_hw_id = kzalloc_obj(*ip_hw_id); 1153 if (!ip_hw_id) 1154 return -ENOMEM; 1155 ip_hw_id->hw_id = ii; 1156 1157 kobject_set_name(&ip_hw_id->hw_id_kset.kobj, "%d", ii); 1158 ip_hw_id->hw_id_kset.kobj.kset = &ip_die_entry->ip_kset; 1159 ip_hw_id->hw_id_kset.kobj.ktype = &ip_hw_id_ktype; 1160 res = kset_register(&ip_hw_id->hw_id_kset); 1161 if (res) { 1162 DRM_ERROR("Couldn't register ip_hw_id kset"); 1163 kfree(ip_hw_id); 1164 return res; 1165 } 1166 if (hw_id_names[ii]) { 1167 res = sysfs_create_link(&ip_die_entry->ip_kset.kobj, 1168 &ip_hw_id->hw_id_kset.kobj, 1169 hw_id_names[ii]); 1170 if (res) { 1171 DRM_ERROR("Couldn't create IP link %s in IP Die:%s\n", 1172 hw_id_names[ii], 1173 kobject_name(&ip_die_entry->ip_kset.kobj)); 1174 } 1175 } 1176 } 1177 1178 /* Now register its instance. 1179 */ 1180 ip_hw_instance = kzalloc_flex(*ip_hw_instance, 1181 base_addr, 1182 ip->num_base_address); 1183 if (!ip_hw_instance) { 1184 DRM_ERROR("no memory for ip_hw_instance"); 1185 return -ENOMEM; 1186 } 1187 ip_hw_instance->hw_id = le16_to_cpu(ip->hw_id); /* == ii */ 1188 ip_hw_instance->num_instance = ip->instance_number; 1189 ip_hw_instance->major = ip->major; 1190 ip_hw_instance->minor = ip->minor; 1191 ip_hw_instance->revision = ip->revision; 1192 ip_hw_instance->harvest = 1193 amdgpu_discovery_get_harvest_info( 1194 adev, ip_hw_instance->hw_id, 1195 ip_hw_instance->num_instance); 1196 ip_hw_instance->num_base_addresses = ip->num_base_address; 1197 1198 for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++) { 1199 if (reg_base_64) 1200 ip_hw_instance->base_addr[kk] = 1201 lower_32_bits(le64_to_cpu(ip->base_address_64[kk])) & 0x3FFFFFFF; 1202 else 1203 ip_hw_instance->base_addr[kk] = ip->base_address[kk]; 1204 } 1205 1206 kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype); 1207 ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset; 1208 res = kobject_add(&ip_hw_instance->kobj, NULL, 1209 "%d", ip_hw_instance->num_instance); 1210 next_ip: 1211 if (reg_base_64) 1212 ip_offset += struct_size(ip, base_address_64, 1213 ip->num_base_address); 1214 else 1215 ip_offset += struct_size(ip, base_address, 1216 ip->num_base_address); 1217 } 1218 } 1219 1220 return 0; 1221 } 1222 1223 static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev) 1224 { 1225 struct ip_discovery_top *ip_top = adev->discovery.ip_top; 1226 uint8_t *discovery_bin = adev->discovery.bin; 1227 struct binary_header *bhdr; 1228 struct ip_discovery_header *ihdr; 1229 struct die_header *dhdr; 1230 struct kset *die_kset = &ip_top->die_kset; 1231 u16 num_dies, die_offset, num_ips; 1232 size_t ip_offset; 1233 int ii, res; 1234 1235 bhdr = (struct binary_header *)discovery_bin; 1236 ihdr = (struct ip_discovery_header 1237 *)(discovery_bin + 1238 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 1239 num_dies = le16_to_cpu(ihdr->num_dies); 1240 1241 DRM_DEBUG("number of dies: %d\n", num_dies); 1242 1243 for (ii = 0; ii < num_dies; ii++) { 1244 struct ip_die_entry *ip_die_entry; 1245 1246 die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset); 1247 dhdr = (struct die_header *)(discovery_bin + die_offset); 1248 num_ips = le16_to_cpu(dhdr->num_ips); 1249 ip_offset = die_offset + sizeof(*dhdr); 1250 1251 /* Add the die to the kset. 1252 * 1253 * dhdr->die_id == ii, which was checked in 1254 * amdgpu_discovery_reg_base_init(). 1255 */ 1256 1257 ip_die_entry = kzalloc_obj(*ip_die_entry); 1258 if (!ip_die_entry) 1259 return -ENOMEM; 1260 1261 ip_die_entry->num_ips = num_ips; 1262 1263 kobject_set_name(&ip_die_entry->ip_kset.kobj, "%d", le16_to_cpu(dhdr->die_id)); 1264 ip_die_entry->ip_kset.kobj.kset = die_kset; 1265 ip_die_entry->ip_kset.kobj.ktype = &ip_die_entry_ktype; 1266 res = kset_register(&ip_die_entry->ip_kset); 1267 if (res) { 1268 DRM_ERROR("Couldn't register ip_die_entry kset"); 1269 kfree(ip_die_entry); 1270 return res; 1271 } 1272 1273 amdgpu_discovery_sysfs_ips(adev, ip_die_entry, ip_offset, num_ips, !!ihdr->base_addr_64_bit); 1274 } 1275 1276 return 0; 1277 } 1278 1279 static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev) 1280 { 1281 uint8_t *discovery_bin = adev->discovery.bin; 1282 struct ip_discovery_top *ip_top; 1283 struct kset *die_kset; 1284 int res, ii; 1285 1286 if (!discovery_bin) 1287 return -EINVAL; 1288 1289 ip_top = kzalloc_obj(*ip_top); 1290 if (!ip_top) 1291 return -ENOMEM; 1292 1293 ip_top->adev = adev; 1294 adev->discovery.ip_top = ip_top; 1295 res = kobject_init_and_add(&ip_top->kobj, &ip_discovery_ktype, 1296 &adev->dev->kobj, "ip_discovery"); 1297 if (res) { 1298 DRM_ERROR("Couldn't init and add ip_discovery/"); 1299 goto Err; 1300 } 1301 1302 die_kset = &ip_top->die_kset; 1303 kobject_set_name(&die_kset->kobj, "%s", "die"); 1304 die_kset->kobj.parent = &ip_top->kobj; 1305 die_kset->kobj.ktype = &die_kobj_ktype; 1306 res = kset_register(&ip_top->die_kset); 1307 if (res) { 1308 DRM_ERROR("Couldn't register die_kset"); 1309 goto Err; 1310 } 1311 1312 for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++) 1313 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr; 1314 ip_hw_instance_attrs[ii] = NULL; 1315 1316 res = amdgpu_discovery_sysfs_recurse(adev); 1317 1318 return res; 1319 Err: 1320 kobject_put(&ip_top->kobj); 1321 return res; 1322 } 1323 1324 /* -------------------------------------------------- */ 1325 1326 #define list_to_kobj(el) container_of(el, struct kobject, entry) 1327 1328 static void amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id *ip_hw_id) 1329 { 1330 struct list_head *el, *tmp; 1331 struct kset *hw_id_kset; 1332 1333 hw_id_kset = &ip_hw_id->hw_id_kset; 1334 spin_lock(&hw_id_kset->list_lock); 1335 list_for_each_prev_safe(el, tmp, &hw_id_kset->list) { 1336 list_del_init(el); 1337 spin_unlock(&hw_id_kset->list_lock); 1338 /* kobject is embedded in ip_hw_instance */ 1339 kobject_put(list_to_kobj(el)); 1340 spin_lock(&hw_id_kset->list_lock); 1341 } 1342 spin_unlock(&hw_id_kset->list_lock); 1343 kobject_put(&ip_hw_id->hw_id_kset.kobj); 1344 } 1345 1346 static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry) 1347 { 1348 struct list_head *el, *tmp; 1349 struct kset *ip_kset; 1350 1351 ip_kset = &ip_die_entry->ip_kset; 1352 spin_lock(&ip_kset->list_lock); 1353 list_for_each_prev_safe(el, tmp, &ip_kset->list) { 1354 list_del_init(el); 1355 spin_unlock(&ip_kset->list_lock); 1356 amdgpu_discovery_sysfs_ip_hw_free(to_ip_hw_id(list_to_kobj(el))); 1357 spin_lock(&ip_kset->list_lock); 1358 } 1359 spin_unlock(&ip_kset->list_lock); 1360 kobject_put(&ip_die_entry->ip_kset.kobj); 1361 } 1362 1363 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev) 1364 { 1365 struct ip_discovery_top *ip_top = adev->discovery.ip_top; 1366 struct list_head *el, *tmp; 1367 struct kset *die_kset; 1368 1369 die_kset = &ip_top->die_kset; 1370 spin_lock(&die_kset->list_lock); 1371 list_for_each_prev_safe(el, tmp, &die_kset->list) { 1372 list_del_init(el); 1373 spin_unlock(&die_kset->list_lock); 1374 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el))); 1375 spin_lock(&die_kset->list_lock); 1376 } 1377 spin_unlock(&die_kset->list_lock); 1378 kobject_put(&ip_top->die_kset.kobj); 1379 kobject_put(&ip_top->kobj); 1380 } 1381 1382 /* devcoredump support */ 1383 void amdgpu_discovery_dump(struct amdgpu_device *adev, struct drm_printer *p) 1384 { 1385 struct ip_discovery_top *ip_top = adev->discovery.ip_top; 1386 struct ip_die_entry *ip_die_entry; 1387 struct list_head *el_die, *el_hw_id, *el_hw_inst; 1388 struct ip_hw_id *hw_id; 1389 struct kset *die_kset; 1390 struct ip_hw_instance *ip_inst; 1391 int i = 0, j; 1392 1393 die_kset = &ip_top->die_kset; 1394 1395 drm_printf(p, "\nHW IP Discovery\n"); 1396 spin_lock(&die_kset->list_lock); 1397 list_for_each(el_die, &die_kset->list) { 1398 drm_printf(p, "die %d\n", i++); 1399 ip_die_entry = to_ip_die_entry(list_to_kobj(el_die)); 1400 1401 list_for_each(el_hw_id, &ip_die_entry->ip_kset.list) { 1402 hw_id = to_ip_hw_id(list_to_kobj(el_hw_id)); 1403 drm_printf(p, "hw_id %d %s\n", hw_id->hw_id, hw_id_names[hw_id->hw_id]); 1404 1405 list_for_each(el_hw_inst, &hw_id->hw_id_kset.list) { 1406 ip_inst = to_ip_hw_instance(list_to_kobj(el_hw_inst)); 1407 drm_printf(p, "\tinstance %d\n", ip_inst->num_instance); 1408 drm_printf(p, "\tmajor %d\n", ip_inst->major); 1409 drm_printf(p, "\tminor %d\n", ip_inst->minor); 1410 drm_printf(p, "\trevision %d\n", ip_inst->revision); 1411 drm_printf(p, "\tharvest 0x%01X\n", ip_inst->harvest); 1412 drm_printf(p, "\tnum_base_addresses %d\n", 1413 ip_inst->num_base_addresses); 1414 for (j = 0; j < ip_inst->num_base_addresses; j++) 1415 drm_printf(p, "\tbase_addr[%d] 0x%08X\n", 1416 j, ip_inst->base_addr[j]); 1417 } 1418 } 1419 } 1420 spin_unlock(&die_kset->list_lock); 1421 } 1422 1423 1424 /* ================================================== */ 1425 1426 static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) 1427 { 1428 uint8_t num_base_address, subrev, variant; 1429 struct binary_header *bhdr; 1430 struct ip_discovery_header *ihdr; 1431 struct die_header *dhdr; 1432 uint8_t *discovery_bin; 1433 struct ip_v4 *ip; 1434 uint16_t die_offset; 1435 uint16_t ip_offset; 1436 uint16_t num_dies; 1437 uint32_t wafl_ver; 1438 uint16_t num_ips; 1439 uint16_t hw_id; 1440 uint8_t inst; 1441 int hw_ip; 1442 int i, j, k; 1443 int r; 1444 1445 r = amdgpu_discovery_init(adev); 1446 if (r) 1447 return r; 1448 discovery_bin = adev->discovery.bin; 1449 wafl_ver = 0; 1450 adev->gfx.xcc_mask = 0; 1451 adev->sdma.sdma_mask = 0; 1452 adev->vcn.inst_mask = 0; 1453 adev->jpeg.inst_mask = 0; 1454 bhdr = (struct binary_header *)discovery_bin; 1455 ihdr = (struct ip_discovery_header 1456 *)(discovery_bin + 1457 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 1458 num_dies = le16_to_cpu(ihdr->num_dies); 1459 1460 DRM_DEBUG("number of dies: %d\n", num_dies); 1461 1462 for (i = 0; i < num_dies; i++) { 1463 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 1464 dhdr = (struct die_header *)(discovery_bin + die_offset); 1465 num_ips = le16_to_cpu(dhdr->num_ips); 1466 ip_offset = die_offset + sizeof(*dhdr); 1467 1468 if (le16_to_cpu(dhdr->die_id) != i) { 1469 DRM_ERROR("invalid die id %d, expected %d\n", 1470 le16_to_cpu(dhdr->die_id), i); 1471 return -EINVAL; 1472 } 1473 1474 DRM_DEBUG("number of hardware IPs on die%d: %d\n", 1475 le16_to_cpu(dhdr->die_id), num_ips); 1476 1477 for (j = 0; j < num_ips; j++) { 1478 ip = (struct ip_v4 *)(discovery_bin + ip_offset); 1479 1480 inst = ip->instance_number; 1481 hw_id = le16_to_cpu(ip->hw_id); 1482 if (amdgpu_discovery_validate_ip(adev, inst, hw_id)) 1483 goto next_ip; 1484 1485 num_base_address = ip->num_base_address; 1486 1487 DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n", 1488 hw_id_names[le16_to_cpu(ip->hw_id)], 1489 le16_to_cpu(ip->hw_id), 1490 ip->instance_number, 1491 ip->major, ip->minor, 1492 ip->revision); 1493 1494 if (le16_to_cpu(ip->hw_id) == VCN_HWID) { 1495 /* Bit [5:0]: original revision value 1496 * Bit [7:6]: en/decode capability: 1497 * 0b00 : VCN function normally 1498 * 0b10 : encode is disabled 1499 * 0b01 : decode is disabled 1500 */ 1501 if (adev->vcn.num_vcn_inst < 1502 AMDGPU_MAX_VCN_INSTANCES) { 1503 adev->vcn.inst[adev->vcn.num_vcn_inst].vcn_config = 1504 ip->revision & 0xc0; 1505 adev->vcn.num_vcn_inst++; 1506 adev->vcn.inst_mask |= 1507 (1U << ip->instance_number); 1508 adev->jpeg.inst_mask |= 1509 (1U << ip->instance_number); 1510 } else { 1511 dev_err(adev->dev, "Too many VCN instances: %d vs %d\n", 1512 adev->vcn.num_vcn_inst + 1, 1513 AMDGPU_MAX_VCN_INSTANCES); 1514 } 1515 ip->revision &= ~0xc0; 1516 } 1517 if (le16_to_cpu(ip->hw_id) == SDMA0_HWID || 1518 le16_to_cpu(ip->hw_id) == SDMA1_HWID || 1519 le16_to_cpu(ip->hw_id) == SDMA2_HWID || 1520 le16_to_cpu(ip->hw_id) == SDMA3_HWID) { 1521 if (adev->sdma.num_instances < 1522 AMDGPU_MAX_SDMA_INSTANCES) { 1523 adev->sdma.num_instances++; 1524 adev->sdma.sdma_mask |= 1525 (1U << ip->instance_number); 1526 } else { 1527 dev_err(adev->dev, "Too many SDMA instances: %d vs %d\n", 1528 adev->sdma.num_instances + 1, 1529 AMDGPU_MAX_SDMA_INSTANCES); 1530 } 1531 } 1532 1533 if (le16_to_cpu(ip->hw_id) == VPE_HWID) { 1534 if (adev->vpe.num_instances < AMDGPU_MAX_VPE_INSTANCES) 1535 adev->vpe.num_instances++; 1536 else 1537 dev_err(adev->dev, "Too many VPE instances: %d vs %d\n", 1538 adev->vpe.num_instances + 1, 1539 AMDGPU_MAX_VPE_INSTANCES); 1540 } 1541 1542 if (le16_to_cpu(ip->hw_id) == UMC_HWID) { 1543 adev->gmc.num_umc++; 1544 adev->umc.node_inst_num++; 1545 } 1546 1547 if (le16_to_cpu(ip->hw_id) == GC_HWID) 1548 adev->gfx.xcc_mask |= 1549 (1U << ip->instance_number); 1550 1551 if (!wafl_ver && le16_to_cpu(ip->hw_id) == WAFLC_HWID) 1552 wafl_ver = IP_VERSION_FULL(ip->major, ip->minor, 1553 ip->revision, 0, 0); 1554 1555 for (k = 0; k < num_base_address; k++) { 1556 /* 1557 * convert the endianness of base addresses in place, 1558 * so that we don't need to convert them when accessing adev->reg_offset. 1559 */ 1560 if (ihdr->base_addr_64_bit) 1561 /* Truncate the 64bit base address from ip discovery 1562 * and only store lower 32bit ip base in reg_offset[]. 1563 * Bits > 32 follows ASIC specific format, thus just 1564 * discard them and handle it within specific ASIC. 1565 * By this way reg_offset[] and related helpers can 1566 * stay unchanged. 1567 * The base address is in dwords, thus clear the 1568 * highest 2 bits to store. 1569 */ 1570 ip->base_address[k] = 1571 lower_32_bits(le64_to_cpu(ip->base_address_64[k])) & 0x3FFFFFFF; 1572 else 1573 ip->base_address[k] = le32_to_cpu(ip->base_address[k]); 1574 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]); 1575 } 1576 1577 for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) { 1578 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id) && 1579 hw_id_map[hw_ip] != 0) { 1580 DRM_DEBUG("set register base offset for %s\n", 1581 hw_id_names[le16_to_cpu(ip->hw_id)]); 1582 adev->reg_offset[hw_ip][ip->instance_number] = 1583 ip->base_address; 1584 /* Instance support is somewhat inconsistent. 1585 * SDMA is a good example. Sienna cichlid has 4 total 1586 * SDMA instances, each enumerated separately (HWIDs 1587 * 42, 43, 68, 69). Arcturus has 8 total SDMA instances, 1588 * but they are enumerated as multiple instances of the 1589 * same HWIDs (4x HWID 42, 4x HWID 43). UMC is another 1590 * example. On most chips there are multiple instances 1591 * with the same HWID. 1592 */ 1593 1594 if (ihdr->version < 3) { 1595 subrev = 0; 1596 variant = 0; 1597 } else { 1598 subrev = ip->sub_revision; 1599 variant = ip->variant; 1600 } 1601 1602 adev->ip_versions[hw_ip] 1603 [ip->instance_number] = 1604 IP_VERSION_FULL(ip->major, 1605 ip->minor, 1606 ip->revision, 1607 variant, 1608 subrev); 1609 } 1610 } 1611 1612 next_ip: 1613 if (ihdr->base_addr_64_bit) 1614 ip_offset += struct_size(ip, base_address_64, ip->num_base_address); 1615 else 1616 ip_offset += struct_size(ip, base_address, ip->num_base_address); 1617 } 1618 } 1619 1620 if (wafl_ver && !adev->ip_versions[XGMI_HWIP][0]) 1621 adev->ip_versions[XGMI_HWIP][0] = wafl_ver; 1622 1623 return 0; 1624 } 1625 1626 static void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev) 1627 { 1628 uint8_t *discovery_bin = adev->discovery.bin; 1629 struct ip_discovery_header *ihdr; 1630 struct binary_header *bhdr; 1631 int vcn_harvest_count = 0; 1632 int umc_harvest_count = 0; 1633 uint16_t offset, ihdr_ver; 1634 1635 bhdr = (struct binary_header *)discovery_bin; 1636 offset = le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset); 1637 ihdr = (struct ip_discovery_header *)(discovery_bin + offset); 1638 ihdr_ver = le16_to_cpu(ihdr->version); 1639 /* 1640 * Harvest table does not fit Navi1x and legacy GPUs, 1641 * so read harvest bit per IP data structure to set 1642 * harvest configuration. 1643 */ 1644 if (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 2, 0) && 1645 ihdr_ver <= 2) { 1646 if ((adev->pdev->device == 0x731E && 1647 (adev->pdev->revision == 0xC6 || 1648 adev->pdev->revision == 0xC7)) || 1649 (adev->pdev->device == 0x7340 && 1650 adev->pdev->revision == 0xC9) || 1651 (adev->pdev->device == 0x7360 && 1652 adev->pdev->revision == 0xC7)) 1653 amdgpu_discovery_read_harvest_bit_per_ip(adev, 1654 &vcn_harvest_count); 1655 } else { 1656 amdgpu_discovery_read_from_harvest_table(adev, 1657 &vcn_harvest_count, 1658 &umc_harvest_count); 1659 } 1660 1661 amdgpu_discovery_harvest_config_quirk(adev); 1662 1663 if (vcn_harvest_count == adev->vcn.num_vcn_inst) { 1664 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK; 1665 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK; 1666 } 1667 1668 if (umc_harvest_count < adev->gmc.num_umc) { 1669 adev->gmc.num_umc -= umc_harvest_count; 1670 } 1671 } 1672 1673 union gc_info { 1674 struct gc_info_v1_0 v1; 1675 struct gc_info_v1_1 v1_1; 1676 struct gc_info_v1_2 v1_2; 1677 struct gc_info_v1_3 v1_3; 1678 struct gc_info_v2_0 v2; 1679 struct gc_info_v2_1 v2_1; 1680 }; 1681 1682 static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) 1683 { 1684 uint8_t *discovery_bin = adev->discovery.bin; 1685 struct binary_header *bhdr; 1686 union gc_info *gc_info; 1687 u16 offset; 1688 1689 if (!discovery_bin) { 1690 DRM_ERROR("ip discovery uninitialized\n"); 1691 return -EINVAL; 1692 } 1693 1694 bhdr = (struct binary_header *)discovery_bin; 1695 offset = le16_to_cpu(bhdr->table_list[GC].offset); 1696 1697 if (!offset) 1698 return 0; 1699 1700 gc_info = (union gc_info *)(discovery_bin + offset); 1701 1702 switch (le16_to_cpu(gc_info->v1.header.version_major)) { 1703 case 1: 1704 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se); 1705 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) + 1706 le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa)); 1707 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1708 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se); 1709 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c); 1710 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs); 1711 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds); 1712 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth); 1713 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth); 1714 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer); 1715 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size); 1716 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd); 1717 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu); 1718 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size); 1719 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) / 1720 le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1721 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc); 1722 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 1) { 1723 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v1_1.gc_num_tcp_per_sa); 1724 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v1_1.gc_num_sdp_interface); 1725 adev->gfx.config.gc_num_tcps = le32_to_cpu(gc_info->v1_1.gc_num_tcps); 1726 } 1727 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 2) { 1728 adev->gfx.config.gc_num_tcp_per_wpg = le32_to_cpu(gc_info->v1_2.gc_num_tcp_per_wpg); 1729 adev->gfx.config.gc_tcp_l1_size = le32_to_cpu(gc_info->v1_2.gc_tcp_l1_size); 1730 adev->gfx.config.gc_num_sqc_per_wgp = le32_to_cpu(gc_info->v1_2.gc_num_sqc_per_wgp); 1731 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_instruction_cache_size_per_sqc); 1732 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_data_cache_size_per_sqc); 1733 adev->gfx.config.gc_gl1c_per_sa = le32_to_cpu(gc_info->v1_2.gc_gl1c_per_sa); 1734 adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance); 1735 adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu); 1736 } 1737 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 3) { 1738 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v1_3.gc_tcp_size_per_cu); 1739 adev->gfx.config.gc_tcp_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcp_cache_line_size); 1740 adev->gfx.config.gc_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_size_per_sqc); 1741 adev->gfx.config.gc_instruction_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_line_size); 1742 adev->gfx.config.gc_scalar_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_size_per_sqc); 1743 adev->gfx.config.gc_scalar_data_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_line_size); 1744 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v1_3.gc_tcc_size); 1745 adev->gfx.config.gc_tcc_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcc_cache_line_size); 1746 } 1747 break; 1748 case 2: 1749 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se); 1750 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh); 1751 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1752 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se); 1753 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs); 1754 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs); 1755 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds); 1756 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth); 1757 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth); 1758 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer); 1759 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size); 1760 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd); 1761 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu); 1762 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size); 1763 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) / 1764 le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1765 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc); 1766 if (le16_to_cpu(gc_info->v2.header.version_minor) == 1) { 1767 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v2_1.gc_num_tcp_per_sh); 1768 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v2_1.gc_tcp_size_per_cu); 1769 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v2_1.gc_num_sdp_interface); /* per XCD */ 1770 adev->gfx.config.gc_num_cu_per_sqc = le32_to_cpu(gc_info->v2_1.gc_num_cu_per_sqc); 1771 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_instruction_cache_size_per_sqc); 1772 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_scalar_data_cache_size_per_sqc); 1773 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v2_1.gc_tcc_size); /* per XCD */ 1774 } 1775 break; 1776 default: 1777 dev_err(adev->dev, 1778 "Unhandled GC info table %d.%d\n", 1779 le16_to_cpu(gc_info->v1.header.version_major), 1780 le16_to_cpu(gc_info->v1.header.version_minor)); 1781 return -EINVAL; 1782 } 1783 return 0; 1784 } 1785 1786 union mall_info { 1787 struct mall_info_v1_0 v1; 1788 struct mall_info_v2_0 v2; 1789 }; 1790 1791 static int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev) 1792 { 1793 uint8_t *discovery_bin = adev->discovery.bin; 1794 struct binary_header *bhdr; 1795 union mall_info *mall_info; 1796 u32 u, mall_size_per_umc, m_s_present, half_use; 1797 u64 mall_size; 1798 u16 offset; 1799 1800 if (!discovery_bin) { 1801 DRM_ERROR("ip discovery uninitialized\n"); 1802 return -EINVAL; 1803 } 1804 1805 bhdr = (struct binary_header *)discovery_bin; 1806 offset = le16_to_cpu(bhdr->table_list[MALL_INFO].offset); 1807 1808 if (!offset) 1809 return 0; 1810 1811 mall_info = (union mall_info *)(discovery_bin + offset); 1812 1813 switch (le16_to_cpu(mall_info->v1.header.version_major)) { 1814 case 1: 1815 mall_size = 0; 1816 mall_size_per_umc = le32_to_cpu(mall_info->v1.mall_size_per_m); 1817 m_s_present = le32_to_cpu(mall_info->v1.m_s_present); 1818 half_use = le32_to_cpu(mall_info->v1.m_half_use); 1819 for (u = 0; u < adev->gmc.num_umc; u++) { 1820 if (m_s_present & (1 << u)) 1821 mall_size += mall_size_per_umc * 2; 1822 else if (half_use & (1 << u)) 1823 mall_size += mall_size_per_umc / 2; 1824 else 1825 mall_size += mall_size_per_umc; 1826 } 1827 adev->gmc.mall_size = mall_size; 1828 adev->gmc.m_half_use = half_use; 1829 break; 1830 case 2: 1831 mall_size_per_umc = le32_to_cpu(mall_info->v2.mall_size_per_umc); 1832 adev->gmc.mall_size = (uint64_t)mall_size_per_umc * adev->gmc.num_umc; 1833 break; 1834 default: 1835 dev_err(adev->dev, 1836 "Unhandled MALL info table %d.%d\n", 1837 le16_to_cpu(mall_info->v1.header.version_major), 1838 le16_to_cpu(mall_info->v1.header.version_minor)); 1839 return -EINVAL; 1840 } 1841 return 0; 1842 } 1843 1844 union vcn_info { 1845 struct vcn_info_v1_0 v1; 1846 }; 1847 1848 static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev) 1849 { 1850 uint8_t *discovery_bin = adev->discovery.bin; 1851 struct binary_header *bhdr; 1852 union vcn_info *vcn_info; 1853 u16 offset; 1854 int v; 1855 1856 if (!discovery_bin) { 1857 DRM_ERROR("ip discovery uninitialized\n"); 1858 return -EINVAL; 1859 } 1860 1861 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES 1862 * which is smaller than VCN_INFO_TABLE_MAX_NUM_INSTANCES 1863 * but that may change in the future with new GPUs so keep this 1864 * check for defensive purposes. 1865 */ 1866 if (adev->vcn.num_vcn_inst > VCN_INFO_TABLE_MAX_NUM_INSTANCES) { 1867 dev_err(adev->dev, "invalid vcn instances\n"); 1868 return -EINVAL; 1869 } 1870 1871 bhdr = (struct binary_header *)discovery_bin; 1872 offset = le16_to_cpu(bhdr->table_list[VCN_INFO].offset); 1873 1874 if (!offset) 1875 return 0; 1876 1877 vcn_info = (union vcn_info *)(discovery_bin + offset); 1878 1879 switch (le16_to_cpu(vcn_info->v1.header.version_major)) { 1880 case 1: 1881 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES 1882 * so this won't overflow. 1883 */ 1884 for (v = 0; v < adev->vcn.num_vcn_inst; v++) { 1885 adev->vcn.inst[v].vcn_codec_disable_mask = 1886 le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits); 1887 } 1888 break; 1889 default: 1890 dev_err(adev->dev, 1891 "Unhandled VCN info table %d.%d\n", 1892 le16_to_cpu(vcn_info->v1.header.version_major), 1893 le16_to_cpu(vcn_info->v1.header.version_minor)); 1894 return -EINVAL; 1895 } 1896 return 0; 1897 } 1898 1899 union nps_info { 1900 struct nps_info_v1_0 v1; 1901 }; 1902 1903 static int amdgpu_discovery_refresh_nps_info(struct amdgpu_device *adev, 1904 union nps_info *nps_data) 1905 { 1906 uint64_t vram_size, pos, offset; 1907 struct nps_info_header *nhdr; 1908 struct binary_header bhdr; 1909 uint16_t checksum; 1910 1911 vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20; 1912 pos = vram_size - DISCOVERY_TMR_OFFSET; 1913 amdgpu_device_vram_access(adev, pos, &bhdr, sizeof(bhdr), false); 1914 1915 offset = le16_to_cpu(bhdr.table_list[NPS_INFO].offset); 1916 checksum = le16_to_cpu(bhdr.table_list[NPS_INFO].checksum); 1917 1918 amdgpu_device_vram_access(adev, (pos + offset), nps_data, 1919 sizeof(*nps_data), false); 1920 1921 nhdr = (struct nps_info_header *)(nps_data); 1922 if (!amdgpu_discovery_verify_checksum(adev, (uint8_t *)nps_data, 1923 le32_to_cpu(nhdr->size_bytes), 1924 checksum)) { 1925 dev_err(adev->dev, "nps data refresh, checksum mismatch\n"); 1926 return -EINVAL; 1927 } 1928 1929 return 0; 1930 } 1931 1932 int amdgpu_discovery_get_nps_info(struct amdgpu_device *adev, 1933 uint32_t *nps_type, 1934 struct amdgpu_gmc_memrange **ranges, 1935 int *range_cnt, bool refresh) 1936 { 1937 uint8_t *discovery_bin = adev->discovery.bin; 1938 struct amdgpu_gmc_memrange *mem_ranges; 1939 struct binary_header *bhdr; 1940 union nps_info *nps_info; 1941 union nps_info nps_data; 1942 u16 offset; 1943 int i, r; 1944 1945 if (!nps_type || !range_cnt || !ranges) 1946 return -EINVAL; 1947 1948 if (refresh) { 1949 r = amdgpu_discovery_refresh_nps_info(adev, &nps_data); 1950 if (r) 1951 return r; 1952 nps_info = &nps_data; 1953 } else { 1954 if (!discovery_bin) { 1955 dev_err(adev->dev, 1956 "fetch mem range failed, ip discovery uninitialized\n"); 1957 return -EINVAL; 1958 } 1959 1960 bhdr = (struct binary_header *)discovery_bin; 1961 offset = le16_to_cpu(bhdr->table_list[NPS_INFO].offset); 1962 1963 if (!offset) 1964 return -ENOENT; 1965 1966 /* If verification fails, return as if NPS table doesn't exist */ 1967 if (amdgpu_discovery_verify_npsinfo(adev, bhdr)) 1968 return -ENOENT; 1969 1970 nps_info = (union nps_info *)(discovery_bin + offset); 1971 } 1972 1973 switch (le16_to_cpu(nps_info->v1.header.version_major)) { 1974 case 1: 1975 mem_ranges = kvzalloc_objs(*mem_ranges, nps_info->v1.count); 1976 if (!mem_ranges) 1977 return -ENOMEM; 1978 *nps_type = nps_info->v1.nps_type; 1979 *range_cnt = nps_info->v1.count; 1980 for (i = 0; i < *range_cnt; i++) { 1981 mem_ranges[i].base_address = 1982 nps_info->v1.instance_info[i].base_address; 1983 mem_ranges[i].limit_address = 1984 nps_info->v1.instance_info[i].limit_address; 1985 mem_ranges[i].nid_mask = -1; 1986 mem_ranges[i].flags = 0; 1987 } 1988 *ranges = mem_ranges; 1989 break; 1990 default: 1991 dev_err(adev->dev, "Unhandled NPS info table %d.%d\n", 1992 le16_to_cpu(nps_info->v1.header.version_major), 1993 le16_to_cpu(nps_info->v1.header.version_minor)); 1994 return -EINVAL; 1995 } 1996 1997 return 0; 1998 } 1999 2000 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev) 2001 { 2002 /* what IP to use for this? */ 2003 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2004 case IP_VERSION(9, 0, 1): 2005 case IP_VERSION(9, 1, 0): 2006 case IP_VERSION(9, 2, 1): 2007 case IP_VERSION(9, 2, 2): 2008 case IP_VERSION(9, 3, 0): 2009 case IP_VERSION(9, 4, 0): 2010 case IP_VERSION(9, 4, 1): 2011 case IP_VERSION(9, 4, 2): 2012 case IP_VERSION(9, 4, 3): 2013 case IP_VERSION(9, 4, 4): 2014 case IP_VERSION(9, 5, 0): 2015 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 2016 break; 2017 case IP_VERSION(10, 1, 10): 2018 case IP_VERSION(10, 1, 1): 2019 case IP_VERSION(10, 1, 2): 2020 case IP_VERSION(10, 1, 3): 2021 case IP_VERSION(10, 1, 4): 2022 case IP_VERSION(10, 3, 0): 2023 case IP_VERSION(10, 3, 1): 2024 case IP_VERSION(10, 3, 2): 2025 case IP_VERSION(10, 3, 3): 2026 case IP_VERSION(10, 3, 4): 2027 case IP_VERSION(10, 3, 5): 2028 case IP_VERSION(10, 3, 6): 2029 case IP_VERSION(10, 3, 7): 2030 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 2031 break; 2032 case IP_VERSION(11, 0, 0): 2033 case IP_VERSION(11, 0, 1): 2034 case IP_VERSION(11, 0, 2): 2035 case IP_VERSION(11, 0, 3): 2036 case IP_VERSION(11, 0, 4): 2037 case IP_VERSION(11, 5, 0): 2038 case IP_VERSION(11, 5, 1): 2039 case IP_VERSION(11, 5, 2): 2040 case IP_VERSION(11, 5, 3): 2041 case IP_VERSION(11, 5, 4): 2042 amdgpu_device_ip_block_add(adev, &soc21_common_ip_block); 2043 break; 2044 case IP_VERSION(12, 0, 0): 2045 case IP_VERSION(12, 0, 1): 2046 amdgpu_device_ip_block_add(adev, &soc24_common_ip_block); 2047 break; 2048 case IP_VERSION(12, 1, 0): 2049 amdgpu_device_ip_block_add(adev, &soc_v1_0_common_ip_block); 2050 break; 2051 default: 2052 dev_err(adev->dev, 2053 "Failed to add common ip block(GC_HWIP:0x%x)\n", 2054 amdgpu_ip_version(adev, GC_HWIP, 0)); 2055 return -EINVAL; 2056 } 2057 return 0; 2058 } 2059 2060 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev) 2061 { 2062 /* use GC or MMHUB IP version */ 2063 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2064 case IP_VERSION(9, 0, 1): 2065 case IP_VERSION(9, 1, 0): 2066 case IP_VERSION(9, 2, 1): 2067 case IP_VERSION(9, 2, 2): 2068 case IP_VERSION(9, 3, 0): 2069 case IP_VERSION(9, 4, 0): 2070 case IP_VERSION(9, 4, 1): 2071 case IP_VERSION(9, 4, 2): 2072 case IP_VERSION(9, 4, 3): 2073 case IP_VERSION(9, 4, 4): 2074 case IP_VERSION(9, 5, 0): 2075 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 2076 break; 2077 case IP_VERSION(10, 1, 10): 2078 case IP_VERSION(10, 1, 1): 2079 case IP_VERSION(10, 1, 2): 2080 case IP_VERSION(10, 1, 3): 2081 case IP_VERSION(10, 1, 4): 2082 case IP_VERSION(10, 3, 0): 2083 case IP_VERSION(10, 3, 1): 2084 case IP_VERSION(10, 3, 2): 2085 case IP_VERSION(10, 3, 3): 2086 case IP_VERSION(10, 3, 4): 2087 case IP_VERSION(10, 3, 5): 2088 case IP_VERSION(10, 3, 6): 2089 case IP_VERSION(10, 3, 7): 2090 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 2091 break; 2092 case IP_VERSION(11, 0, 0): 2093 case IP_VERSION(11, 0, 1): 2094 case IP_VERSION(11, 0, 2): 2095 case IP_VERSION(11, 0, 3): 2096 case IP_VERSION(11, 0, 4): 2097 case IP_VERSION(11, 5, 0): 2098 case IP_VERSION(11, 5, 1): 2099 case IP_VERSION(11, 5, 2): 2100 case IP_VERSION(11, 5, 3): 2101 case IP_VERSION(11, 5, 4): 2102 amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block); 2103 break; 2104 case IP_VERSION(12, 0, 0): 2105 case IP_VERSION(12, 0, 1): 2106 case IP_VERSION(12, 1, 0): 2107 amdgpu_device_ip_block_add(adev, &gmc_v12_0_ip_block); 2108 break; 2109 default: 2110 dev_err(adev->dev, "Failed to add gmc ip block(GC_HWIP:0x%x)\n", 2111 amdgpu_ip_version(adev, GC_HWIP, 0)); 2112 return -EINVAL; 2113 } 2114 return 0; 2115 } 2116 2117 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev) 2118 { 2119 switch (amdgpu_ip_version(adev, OSSSYS_HWIP, 0)) { 2120 case IP_VERSION(4, 0, 0): 2121 case IP_VERSION(4, 0, 1): 2122 case IP_VERSION(4, 1, 0): 2123 case IP_VERSION(4, 1, 1): 2124 case IP_VERSION(4, 3, 0): 2125 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 2126 break; 2127 case IP_VERSION(4, 2, 0): 2128 case IP_VERSION(4, 2, 1): 2129 case IP_VERSION(4, 4, 0): 2130 case IP_VERSION(4, 4, 2): 2131 case IP_VERSION(4, 4, 5): 2132 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 2133 break; 2134 case IP_VERSION(5, 0, 0): 2135 case IP_VERSION(5, 0, 1): 2136 case IP_VERSION(5, 0, 2): 2137 case IP_VERSION(5, 0, 3): 2138 case IP_VERSION(5, 2, 0): 2139 case IP_VERSION(5, 2, 1): 2140 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 2141 break; 2142 case IP_VERSION(6, 0, 0): 2143 case IP_VERSION(6, 0, 1): 2144 case IP_VERSION(6, 0, 2): 2145 amdgpu_device_ip_block_add(adev, &ih_v6_0_ip_block); 2146 break; 2147 case IP_VERSION(6, 1, 0): 2148 case IP_VERSION(6, 1, 1): 2149 amdgpu_device_ip_block_add(adev, &ih_v6_1_ip_block); 2150 break; 2151 case IP_VERSION(7, 0, 0): 2152 case IP_VERSION(7, 1, 0): 2153 amdgpu_device_ip_block_add(adev, &ih_v7_0_ip_block); 2154 break; 2155 default: 2156 dev_err(adev->dev, 2157 "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n", 2158 amdgpu_ip_version(adev, OSSSYS_HWIP, 0)); 2159 return -EINVAL; 2160 } 2161 return 0; 2162 } 2163 2164 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev) 2165 { 2166 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 2167 case IP_VERSION(9, 0, 0): 2168 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 2169 break; 2170 case IP_VERSION(10, 0, 0): 2171 case IP_VERSION(10, 0, 1): 2172 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); 2173 break; 2174 case IP_VERSION(11, 0, 0): 2175 case IP_VERSION(11, 0, 2): 2176 case IP_VERSION(11, 0, 4): 2177 case IP_VERSION(11, 0, 5): 2178 case IP_VERSION(11, 0, 9): 2179 case IP_VERSION(11, 0, 7): 2180 case IP_VERSION(11, 0, 11): 2181 case IP_VERSION(11, 0, 12): 2182 case IP_VERSION(11, 0, 13): 2183 case IP_VERSION(11, 5, 0): 2184 case IP_VERSION(11, 5, 2): 2185 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 2186 break; 2187 case IP_VERSION(11, 0, 8): 2188 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block); 2189 break; 2190 case IP_VERSION(11, 0, 3): 2191 case IP_VERSION(12, 0, 1): 2192 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); 2193 break; 2194 case IP_VERSION(13, 0, 0): 2195 case IP_VERSION(13, 0, 1): 2196 case IP_VERSION(13, 0, 2): 2197 case IP_VERSION(13, 0, 3): 2198 case IP_VERSION(13, 0, 5): 2199 case IP_VERSION(13, 0, 6): 2200 case IP_VERSION(13, 0, 7): 2201 case IP_VERSION(13, 0, 8): 2202 case IP_VERSION(13, 0, 10): 2203 case IP_VERSION(13, 0, 11): 2204 case IP_VERSION(13, 0, 12): 2205 case IP_VERSION(13, 0, 14): 2206 case IP_VERSION(13, 0, 15): 2207 case IP_VERSION(14, 0, 0): 2208 case IP_VERSION(14, 0, 1): 2209 case IP_VERSION(14, 0, 4): 2210 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); 2211 break; 2212 case IP_VERSION(13, 0, 4): 2213 amdgpu_device_ip_block_add(adev, &psp_v13_0_4_ip_block); 2214 break; 2215 case IP_VERSION(14, 0, 2): 2216 case IP_VERSION(14, 0, 3): 2217 case IP_VERSION(14, 0, 5): 2218 amdgpu_device_ip_block_add(adev, &psp_v14_0_ip_block); 2219 break; 2220 case IP_VERSION(15, 0, 0): 2221 amdgpu_device_ip_block_add(adev, &psp_v15_0_ip_block); 2222 break; 2223 case IP_VERSION(15, 0, 8): 2224 amdgpu_device_ip_block_add(adev, &psp_v15_0_8_ip_block); 2225 break; 2226 default: 2227 dev_err(adev->dev, 2228 "Failed to add psp ip block(MP0_HWIP:0x%x)\n", 2229 amdgpu_ip_version(adev, MP0_HWIP, 0)); 2230 return -EINVAL; 2231 } 2232 return 0; 2233 } 2234 2235 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev) 2236 { 2237 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2238 case IP_VERSION(9, 0, 0): 2239 case IP_VERSION(10, 0, 0): 2240 case IP_VERSION(10, 0, 1): 2241 case IP_VERSION(11, 0, 2): 2242 if (adev->asic_type == CHIP_ARCTURUS) 2243 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 2244 else 2245 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 2246 break; 2247 case IP_VERSION(11, 0, 0): 2248 case IP_VERSION(11, 0, 5): 2249 case IP_VERSION(11, 0, 9): 2250 case IP_VERSION(11, 0, 7): 2251 case IP_VERSION(11, 0, 11): 2252 case IP_VERSION(11, 0, 12): 2253 case IP_VERSION(11, 0, 13): 2254 case IP_VERSION(11, 5, 0): 2255 case IP_VERSION(11, 5, 2): 2256 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 2257 break; 2258 case IP_VERSION(11, 0, 8): 2259 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) 2260 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 2261 break; 2262 case IP_VERSION(12, 0, 0): 2263 case IP_VERSION(12, 0, 1): 2264 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); 2265 break; 2266 case IP_VERSION(13, 0, 0): 2267 case IP_VERSION(13, 0, 1): 2268 case IP_VERSION(13, 0, 2): 2269 case IP_VERSION(13, 0, 3): 2270 case IP_VERSION(13, 0, 4): 2271 case IP_VERSION(13, 0, 5): 2272 case IP_VERSION(13, 0, 6): 2273 case IP_VERSION(13, 0, 7): 2274 case IP_VERSION(13, 0, 8): 2275 case IP_VERSION(13, 0, 10): 2276 case IP_VERSION(13, 0, 11): 2277 case IP_VERSION(13, 0, 14): 2278 case IP_VERSION(13, 0, 12): 2279 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); 2280 break; 2281 case IP_VERSION(14, 0, 0): 2282 case IP_VERSION(14, 0, 1): 2283 case IP_VERSION(14, 0, 2): 2284 case IP_VERSION(14, 0, 3): 2285 case IP_VERSION(14, 0, 4): 2286 case IP_VERSION(14, 0, 5): 2287 amdgpu_device_ip_block_add(adev, &smu_v14_0_ip_block); 2288 break; 2289 case IP_VERSION(15, 0, 0): 2290 amdgpu_device_ip_block_add(adev, &smu_v15_0_ip_block); 2291 break; 2292 default: 2293 dev_err(adev->dev, 2294 "Failed to add smu ip block(MP1_HWIP:0x%x)\n", 2295 amdgpu_ip_version(adev, MP1_HWIP, 0)); 2296 return -EINVAL; 2297 } 2298 return 0; 2299 } 2300 2301 #if defined(CONFIG_DRM_AMD_DC) 2302 static void amdgpu_discovery_set_sriov_display(struct amdgpu_device *adev) 2303 { 2304 amdgpu_device_set_sriov_virtual_display(adev); 2305 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2306 } 2307 #endif 2308 2309 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev) 2310 { 2311 if (adev->enable_virtual_display) { 2312 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2313 return 0; 2314 } 2315 2316 if (!amdgpu_device_has_dc_support(adev)) 2317 return 0; 2318 2319 #if defined(CONFIG_DRM_AMD_DC) 2320 if (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2321 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2322 case IP_VERSION(1, 0, 0): 2323 case IP_VERSION(1, 0, 1): 2324 case IP_VERSION(2, 0, 2): 2325 case IP_VERSION(2, 0, 0): 2326 case IP_VERSION(2, 0, 3): 2327 case IP_VERSION(2, 1, 0): 2328 case IP_VERSION(3, 0, 0): 2329 case IP_VERSION(3, 0, 2): 2330 case IP_VERSION(3, 0, 3): 2331 case IP_VERSION(3, 0, 1): 2332 case IP_VERSION(3, 1, 2): 2333 case IP_VERSION(3, 1, 3): 2334 case IP_VERSION(3, 1, 4): 2335 case IP_VERSION(3, 1, 5): 2336 case IP_VERSION(3, 1, 6): 2337 case IP_VERSION(3, 2, 0): 2338 case IP_VERSION(3, 2, 1): 2339 case IP_VERSION(3, 5, 0): 2340 case IP_VERSION(3, 5, 1): 2341 case IP_VERSION(3, 6, 0): 2342 case IP_VERSION(4, 1, 0): 2343 case IP_VERSION(4, 2, 0): 2344 /* TODO: Fix IP version. DC code expects version 4.0.1 */ 2345 if (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(4, 1, 0)) 2346 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(4, 0, 1); 2347 2348 if (amdgpu_sriov_vf(adev)) 2349 amdgpu_discovery_set_sriov_display(adev); 2350 else 2351 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2352 break; 2353 default: 2354 dev_err(adev->dev, 2355 "Failed to add dm ip block(DCE_HWIP:0x%x)\n", 2356 amdgpu_ip_version(adev, DCE_HWIP, 0)); 2357 return -EINVAL; 2358 } 2359 } else if (amdgpu_ip_version(adev, DCI_HWIP, 0)) { 2360 switch (amdgpu_ip_version(adev, DCI_HWIP, 0)) { 2361 case IP_VERSION(12, 0, 0): 2362 case IP_VERSION(12, 0, 1): 2363 case IP_VERSION(12, 1, 0): 2364 if (amdgpu_sriov_vf(adev)) 2365 amdgpu_discovery_set_sriov_display(adev); 2366 else 2367 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2368 break; 2369 default: 2370 dev_err(adev->dev, 2371 "Failed to add dm ip block(DCI_HWIP:0x%x)\n", 2372 amdgpu_ip_version(adev, DCI_HWIP, 0)); 2373 return -EINVAL; 2374 } 2375 } 2376 #endif 2377 return 0; 2378 } 2379 2380 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) 2381 { 2382 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2383 case IP_VERSION(9, 0, 1): 2384 case IP_VERSION(9, 1, 0): 2385 case IP_VERSION(9, 2, 1): 2386 case IP_VERSION(9, 2, 2): 2387 case IP_VERSION(9, 3, 0): 2388 case IP_VERSION(9, 4, 0): 2389 case IP_VERSION(9, 4, 1): 2390 case IP_VERSION(9, 4, 2): 2391 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 2392 break; 2393 case IP_VERSION(9, 4, 3): 2394 case IP_VERSION(9, 4, 4): 2395 case IP_VERSION(9, 5, 0): 2396 amdgpu_device_ip_block_add(adev, &gfx_v9_4_3_ip_block); 2397 break; 2398 case IP_VERSION(10, 1, 10): 2399 case IP_VERSION(10, 1, 2): 2400 case IP_VERSION(10, 1, 1): 2401 case IP_VERSION(10, 1, 3): 2402 case IP_VERSION(10, 1, 4): 2403 case IP_VERSION(10, 3, 0): 2404 case IP_VERSION(10, 3, 2): 2405 case IP_VERSION(10, 3, 1): 2406 case IP_VERSION(10, 3, 4): 2407 case IP_VERSION(10, 3, 5): 2408 case IP_VERSION(10, 3, 6): 2409 case IP_VERSION(10, 3, 3): 2410 case IP_VERSION(10, 3, 7): 2411 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 2412 break; 2413 case IP_VERSION(11, 0, 0): 2414 case IP_VERSION(11, 0, 1): 2415 case IP_VERSION(11, 0, 2): 2416 case IP_VERSION(11, 0, 3): 2417 case IP_VERSION(11, 0, 4): 2418 case IP_VERSION(11, 5, 0): 2419 case IP_VERSION(11, 5, 1): 2420 case IP_VERSION(11, 5, 2): 2421 case IP_VERSION(11, 5, 3): 2422 case IP_VERSION(11, 5, 4): 2423 amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block); 2424 break; 2425 case IP_VERSION(12, 0, 0): 2426 case IP_VERSION(12, 0, 1): 2427 amdgpu_device_ip_block_add(adev, &gfx_v12_0_ip_block); 2428 break; 2429 case IP_VERSION(12, 1, 0): 2430 amdgpu_device_ip_block_add(adev, &gfx_v12_1_ip_block); 2431 break; 2432 default: 2433 dev_err(adev->dev, "Failed to add gfx ip block(GC_HWIP:0x%x)\n", 2434 amdgpu_ip_version(adev, GC_HWIP, 0)); 2435 return -EINVAL; 2436 } 2437 return 0; 2438 } 2439 2440 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev) 2441 { 2442 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 2443 case IP_VERSION(4, 0, 0): 2444 case IP_VERSION(4, 0, 1): 2445 case IP_VERSION(4, 1, 0): 2446 case IP_VERSION(4, 1, 1): 2447 case IP_VERSION(4, 1, 2): 2448 case IP_VERSION(4, 2, 0): 2449 case IP_VERSION(4, 2, 2): 2450 case IP_VERSION(4, 4, 0): 2451 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 2452 break; 2453 case IP_VERSION(4, 4, 2): 2454 case IP_VERSION(4, 4, 5): 2455 case IP_VERSION(4, 4, 4): 2456 amdgpu_device_ip_block_add(adev, &sdma_v4_4_2_ip_block); 2457 break; 2458 case IP_VERSION(5, 0, 0): 2459 case IP_VERSION(5, 0, 1): 2460 case IP_VERSION(5, 0, 2): 2461 case IP_VERSION(5, 0, 5): 2462 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 2463 break; 2464 case IP_VERSION(5, 2, 0): 2465 case IP_VERSION(5, 2, 2): 2466 case IP_VERSION(5, 2, 4): 2467 case IP_VERSION(5, 2, 5): 2468 case IP_VERSION(5, 2, 6): 2469 case IP_VERSION(5, 2, 3): 2470 case IP_VERSION(5, 2, 1): 2471 case IP_VERSION(5, 2, 7): 2472 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 2473 break; 2474 case IP_VERSION(6, 0, 0): 2475 case IP_VERSION(6, 0, 1): 2476 case IP_VERSION(6, 0, 2): 2477 case IP_VERSION(6, 0, 3): 2478 case IP_VERSION(6, 1, 0): 2479 case IP_VERSION(6, 1, 1): 2480 case IP_VERSION(6, 1, 2): 2481 case IP_VERSION(6, 1, 3): 2482 case IP_VERSION(6, 1, 4): 2483 amdgpu_device_ip_block_add(adev, &sdma_v6_0_ip_block); 2484 break; 2485 case IP_VERSION(7, 0, 0): 2486 case IP_VERSION(7, 0, 1): 2487 amdgpu_device_ip_block_add(adev, &sdma_v7_0_ip_block); 2488 break; 2489 case IP_VERSION(7, 1, 0): 2490 amdgpu_device_ip_block_add(adev, &sdma_v7_1_ip_block); 2491 break; 2492 default: 2493 dev_err(adev->dev, 2494 "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n", 2495 amdgpu_ip_version(adev, SDMA0_HWIP, 0)); 2496 return -EINVAL; 2497 } 2498 2499 return 0; 2500 } 2501 2502 static int amdgpu_discovery_set_ras_ip_blocks(struct amdgpu_device *adev) 2503 { 2504 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 2505 case IP_VERSION(13, 0, 6): 2506 case IP_VERSION(13, 0, 12): 2507 case IP_VERSION(13, 0, 14): 2508 amdgpu_device_ip_block_add(adev, &ras_v1_0_ip_block); 2509 break; 2510 default: 2511 break; 2512 } 2513 return 0; 2514 } 2515 2516 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) 2517 { 2518 if (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 2519 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 2520 case IP_VERSION(7, 0, 0): 2521 case IP_VERSION(7, 2, 0): 2522 /* UVD is not supported on vega20 SR-IOV */ 2523 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 2524 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); 2525 break; 2526 default: 2527 dev_err(adev->dev, 2528 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n", 2529 amdgpu_ip_version(adev, UVD_HWIP, 0)); 2530 return -EINVAL; 2531 } 2532 switch (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 2533 case IP_VERSION(4, 0, 0): 2534 case IP_VERSION(4, 1, 0): 2535 /* VCE is not supported on vega20 SR-IOV */ 2536 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 2537 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); 2538 break; 2539 default: 2540 dev_err(adev->dev, 2541 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n", 2542 amdgpu_ip_version(adev, VCE_HWIP, 0)); 2543 return -EINVAL; 2544 } 2545 } else { 2546 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 2547 case IP_VERSION(1, 0, 0): 2548 case IP_VERSION(1, 0, 1): 2549 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); 2550 break; 2551 case IP_VERSION(2, 0, 0): 2552 case IP_VERSION(2, 0, 2): 2553 case IP_VERSION(2, 2, 0): 2554 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 2555 if (!amdgpu_sriov_vf(adev)) 2556 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 2557 break; 2558 case IP_VERSION(2, 0, 3): 2559 break; 2560 case IP_VERSION(2, 5, 0): 2561 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 2562 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block); 2563 break; 2564 case IP_VERSION(2, 6, 0): 2565 amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block); 2566 amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block); 2567 break; 2568 case IP_VERSION(3, 0, 0): 2569 case IP_VERSION(3, 0, 16): 2570 case IP_VERSION(3, 1, 1): 2571 case IP_VERSION(3, 1, 2): 2572 case IP_VERSION(3, 0, 2): 2573 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 2574 if (!amdgpu_sriov_vf(adev)) 2575 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 2576 break; 2577 case IP_VERSION(3, 0, 33): 2578 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 2579 break; 2580 case IP_VERSION(4, 0, 0): 2581 case IP_VERSION(4, 0, 2): 2582 case IP_VERSION(4, 0, 4): 2583 amdgpu_device_ip_block_add(adev, &vcn_v4_0_ip_block); 2584 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block); 2585 break; 2586 case IP_VERSION(4, 0, 3): 2587 amdgpu_device_ip_block_add(adev, &vcn_v4_0_3_ip_block); 2588 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_3_ip_block); 2589 break; 2590 case IP_VERSION(4, 0, 5): 2591 case IP_VERSION(4, 0, 6): 2592 amdgpu_device_ip_block_add(adev, &vcn_v4_0_5_ip_block); 2593 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_5_ip_block); 2594 break; 2595 case IP_VERSION(5, 0, 0): 2596 amdgpu_device_ip_block_add(adev, &vcn_v5_0_0_ip_block); 2597 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_0_ip_block); 2598 break; 2599 case IP_VERSION(5, 3, 0): 2600 amdgpu_device_ip_block_add(adev, &vcn_v5_0_0_ip_block); 2601 amdgpu_device_ip_block_add(adev, &jpeg_v5_3_0_ip_block); 2602 break; 2603 case IP_VERSION(5, 0, 1): 2604 amdgpu_device_ip_block_add(adev, &vcn_v5_0_1_ip_block); 2605 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_1_ip_block); 2606 break; 2607 default: 2608 dev_err(adev->dev, 2609 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n", 2610 amdgpu_ip_version(adev, UVD_HWIP, 0)); 2611 return -EINVAL; 2612 } 2613 } 2614 return 0; 2615 } 2616 2617 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev) 2618 { 2619 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2620 case IP_VERSION(11, 0, 0): 2621 case IP_VERSION(11, 0, 1): 2622 case IP_VERSION(11, 0, 2): 2623 case IP_VERSION(11, 0, 3): 2624 case IP_VERSION(11, 0, 4): 2625 case IP_VERSION(11, 5, 0): 2626 case IP_VERSION(11, 5, 1): 2627 case IP_VERSION(11, 5, 2): 2628 case IP_VERSION(11, 5, 3): 2629 case IP_VERSION(11, 5, 4): 2630 amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block); 2631 adev->enable_mes = true; 2632 adev->enable_mes_kiq = true; 2633 break; 2634 case IP_VERSION(12, 0, 0): 2635 case IP_VERSION(12, 0, 1): 2636 amdgpu_device_ip_block_add(adev, &mes_v12_0_ip_block); 2637 adev->enable_mes = true; 2638 adev->enable_mes_kiq = true; 2639 if (amdgpu_uni_mes) 2640 adev->enable_uni_mes = true; 2641 break; 2642 case IP_VERSION(12, 1, 0): 2643 amdgpu_device_ip_block_add(adev, &mes_v12_1_ip_block); 2644 adev->enable_mes = true; 2645 adev->enable_mes_kiq = true; 2646 if (amdgpu_uni_mes) 2647 adev->enable_uni_mes = true; 2648 break; 2649 default: 2650 break; 2651 } 2652 return 0; 2653 } 2654 2655 static void amdgpu_discovery_init_soc_config(struct amdgpu_device *adev) 2656 { 2657 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2658 case IP_VERSION(9, 4, 3): 2659 case IP_VERSION(9, 4, 4): 2660 case IP_VERSION(9, 5, 0): 2661 aqua_vanjaram_init_soc_config(adev); 2662 break; 2663 case IP_VERSION(12, 1, 0): 2664 soc_v1_0_init_soc_config(adev); 2665 break; 2666 default: 2667 break; 2668 } 2669 } 2670 2671 static int amdgpu_discovery_set_vpe_ip_blocks(struct amdgpu_device *adev) 2672 { 2673 switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) { 2674 case IP_VERSION(6, 1, 0): 2675 case IP_VERSION(6, 1, 1): 2676 case IP_VERSION(6, 1, 3): 2677 amdgpu_device_ip_block_add(adev, &vpe_v6_1_ip_block); 2678 break; 2679 default: 2680 break; 2681 } 2682 2683 return 0; 2684 } 2685 2686 static int amdgpu_discovery_set_umsch_mm_ip_blocks(struct amdgpu_device *adev) 2687 { 2688 switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) { 2689 case IP_VERSION(4, 0, 5): 2690 case IP_VERSION(4, 0, 6): 2691 if (amdgpu_umsch_mm & 0x1) { 2692 amdgpu_device_ip_block_add(adev, &umsch_mm_v4_0_ip_block); 2693 adev->enable_umsch_mm = true; 2694 } 2695 break; 2696 default: 2697 break; 2698 } 2699 2700 return 0; 2701 } 2702 2703 static int amdgpu_discovery_set_isp_ip_blocks(struct amdgpu_device *adev) 2704 { 2705 #if defined(CONFIG_DRM_AMD_ISP) 2706 switch (amdgpu_ip_version(adev, ISP_HWIP, 0)) { 2707 case IP_VERSION(4, 1, 0): 2708 amdgpu_device_ip_block_add(adev, &isp_v4_1_0_ip_block); 2709 break; 2710 case IP_VERSION(4, 1, 1): 2711 amdgpu_device_ip_block_add(adev, &isp_v4_1_1_ip_block); 2712 break; 2713 default: 2714 break; 2715 } 2716 #endif 2717 2718 return 0; 2719 } 2720 2721 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 2722 { 2723 int r; 2724 2725 switch (adev->asic_type) { 2726 case CHIP_VEGA10: 2727 /* This is not fatal. We only need the discovery 2728 * binary for sysfs. We don't need it for a 2729 * functional system. 2730 */ 2731 amdgpu_discovery_init(adev); 2732 vega10_reg_base_init(adev); 2733 adev->sdma.num_instances = 2; 2734 adev->sdma.sdma_mask = 3; 2735 adev->gmc.num_umc = 4; 2736 adev->gfx.xcc_mask = 1; 2737 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0); 2738 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0); 2739 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0); 2740 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0); 2741 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0); 2742 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0); 2743 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 2744 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0); 2745 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0); 2746 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 2747 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 2748 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 2749 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0); 2750 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1); 2751 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 2752 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 2753 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0); 2754 break; 2755 case CHIP_VEGA12: 2756 /* This is not fatal. We only need the discovery 2757 * binary for sysfs. We don't need it for a 2758 * functional system. 2759 */ 2760 amdgpu_discovery_init(adev); 2761 vega10_reg_base_init(adev); 2762 adev->sdma.num_instances = 2; 2763 adev->sdma.sdma_mask = 3; 2764 adev->gmc.num_umc = 4; 2765 adev->gfx.xcc_mask = 1; 2766 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0); 2767 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0); 2768 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1); 2769 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1); 2770 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1); 2771 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1); 2772 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0); 2773 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0); 2774 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0); 2775 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 2776 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 2777 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 2778 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1); 2779 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1); 2780 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 2781 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 2782 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1); 2783 break; 2784 case CHIP_RAVEN: 2785 /* This is not fatal. We only need the discovery 2786 * binary for sysfs. We don't need it for a 2787 * functional system. 2788 */ 2789 amdgpu_discovery_init(adev); 2790 vega10_reg_base_init(adev); 2791 adev->sdma.num_instances = 1; 2792 adev->sdma.sdma_mask = 1; 2793 adev->vcn.num_vcn_inst = 1; 2794 adev->gmc.num_umc = 2; 2795 adev->gfx.xcc_mask = 1; 2796 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { 2797 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0); 2798 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0); 2799 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1); 2800 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1); 2801 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1); 2802 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1); 2803 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1); 2804 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0); 2805 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1); 2806 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1); 2807 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0); 2808 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1); 2809 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2); 2810 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1); 2811 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1); 2812 adev->ip_versions[ISP_HWIP][0] = IP_VERSION(2, 0, 0); 2813 } else { 2814 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0); 2815 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0); 2816 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0); 2817 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0); 2818 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0); 2819 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 2820 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0); 2821 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0); 2822 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0); 2823 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0); 2824 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0); 2825 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0); 2826 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0); 2827 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0); 2828 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0); 2829 adev->ip_versions[ISP_HWIP][0] = IP_VERSION(2, 0, 0); 2830 } 2831 break; 2832 case CHIP_VEGA20: 2833 /* This is not fatal. We only need the discovery 2834 * binary for sysfs. We don't need it for a 2835 * functional system. 2836 */ 2837 amdgpu_discovery_init(adev); 2838 vega20_reg_base_init(adev); 2839 adev->sdma.num_instances = 2; 2840 adev->sdma.sdma_mask = 3; 2841 adev->gmc.num_umc = 8; 2842 adev->gfx.xcc_mask = 1; 2843 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2844 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2845 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0); 2846 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0); 2847 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0); 2848 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0); 2849 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0); 2850 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0); 2851 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1); 2852 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2); 2853 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2854 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2); 2855 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2); 2856 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0); 2857 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0); 2858 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0); 2859 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0); 2860 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0); 2861 break; 2862 case CHIP_ARCTURUS: 2863 /* This is not fatal. We only need the discovery 2864 * binary for sysfs. We don't need it for a 2865 * functional system. 2866 */ 2867 amdgpu_discovery_init(adev); 2868 arct_reg_base_init(adev); 2869 adev->sdma.num_instances = 8; 2870 adev->sdma.sdma_mask = 0xff; 2871 adev->vcn.num_vcn_inst = 2; 2872 adev->gmc.num_umc = 8; 2873 adev->gfx.xcc_mask = 1; 2874 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2875 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2876 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1); 2877 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1); 2878 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2); 2879 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2); 2880 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2); 2881 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2); 2882 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2); 2883 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2); 2884 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2); 2885 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2); 2886 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1); 2887 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1); 2888 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2); 2889 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4); 2890 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2891 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3); 2892 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3); 2893 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1); 2894 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0); 2895 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0); 2896 break; 2897 case CHIP_ALDEBARAN: 2898 /* This is not fatal. We only need the discovery 2899 * binary for sysfs. We don't need it for a 2900 * functional system. 2901 */ 2902 amdgpu_discovery_init(adev); 2903 aldebaran_reg_base_init(adev); 2904 adev->sdma.num_instances = 5; 2905 adev->sdma.sdma_mask = 0x1f; 2906 adev->vcn.num_vcn_inst = 2; 2907 adev->gmc.num_umc = 4; 2908 adev->gfx.xcc_mask = 1; 2909 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2910 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2911 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0); 2912 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0); 2913 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0); 2914 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0); 2915 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0); 2916 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0); 2917 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0); 2918 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2); 2919 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4); 2920 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0); 2921 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2); 2922 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2); 2923 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2); 2924 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2); 2925 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2); 2926 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0); 2927 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0); 2928 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0); 2929 break; 2930 case CHIP_CYAN_SKILLFISH: 2931 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 2932 r = amdgpu_discovery_reg_base_init(adev); 2933 if (r) 2934 return -EINVAL; 2935 2936 amdgpu_discovery_harvest_ip(adev); 2937 amdgpu_discovery_get_gfx_info(adev); 2938 amdgpu_discovery_get_mall_info(adev); 2939 amdgpu_discovery_get_vcn_info(adev); 2940 } else { 2941 cyan_skillfish_reg_base_init(adev); 2942 adev->sdma.num_instances = 2; 2943 adev->sdma.sdma_mask = 3; 2944 adev->gfx.xcc_mask = 1; 2945 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(2, 0, 3); 2946 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(2, 0, 3); 2947 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(5, 0, 1); 2948 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(5, 0, 1); 2949 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(5, 0, 1); 2950 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(5, 0, 1); 2951 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 5, 0); 2952 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(2, 1, 1); 2953 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(8, 1, 1); 2954 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 8); 2955 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 8); 2956 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 1); 2957 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 8); 2958 adev->ip_versions[GC_HWIP][0] = IP_VERSION(10, 1, 3); 2959 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 0, 3); 2960 } 2961 break; 2962 default: 2963 r = amdgpu_discovery_reg_base_init(adev); 2964 if (r) { 2965 drm_err(&adev->ddev, "discovery failed: %d\n", r); 2966 return r; 2967 } 2968 2969 amdgpu_discovery_harvest_ip(adev); 2970 amdgpu_discovery_get_gfx_info(adev); 2971 amdgpu_discovery_get_mall_info(adev); 2972 amdgpu_discovery_get_vcn_info(adev); 2973 break; 2974 } 2975 2976 amdgpu_discovery_init_soc_config(adev); 2977 amdgpu_discovery_sysfs_init(adev); 2978 2979 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2980 case IP_VERSION(9, 0, 1): 2981 case IP_VERSION(9, 2, 1): 2982 case IP_VERSION(9, 4, 0): 2983 case IP_VERSION(9, 4, 1): 2984 case IP_VERSION(9, 4, 2): 2985 case IP_VERSION(9, 4, 3): 2986 case IP_VERSION(9, 4, 4): 2987 case IP_VERSION(9, 5, 0): 2988 adev->family = AMDGPU_FAMILY_AI; 2989 break; 2990 case IP_VERSION(9, 1, 0): 2991 case IP_VERSION(9, 2, 2): 2992 case IP_VERSION(9, 3, 0): 2993 adev->family = AMDGPU_FAMILY_RV; 2994 break; 2995 case IP_VERSION(10, 1, 10): 2996 case IP_VERSION(10, 1, 1): 2997 case IP_VERSION(10, 1, 2): 2998 case IP_VERSION(10, 1, 3): 2999 case IP_VERSION(10, 1, 4): 3000 case IP_VERSION(10, 3, 0): 3001 case IP_VERSION(10, 3, 2): 3002 case IP_VERSION(10, 3, 4): 3003 case IP_VERSION(10, 3, 5): 3004 adev->family = AMDGPU_FAMILY_NV; 3005 break; 3006 case IP_VERSION(10, 3, 1): 3007 adev->family = AMDGPU_FAMILY_VGH; 3008 adev->apu_flags |= AMD_APU_IS_VANGOGH; 3009 break; 3010 case IP_VERSION(10, 3, 3): 3011 adev->family = AMDGPU_FAMILY_YC; 3012 break; 3013 case IP_VERSION(10, 3, 6): 3014 adev->family = AMDGPU_FAMILY_GC_10_3_6; 3015 break; 3016 case IP_VERSION(10, 3, 7): 3017 adev->family = AMDGPU_FAMILY_GC_10_3_7; 3018 break; 3019 case IP_VERSION(11, 0, 0): 3020 case IP_VERSION(11, 0, 2): 3021 case IP_VERSION(11, 0, 3): 3022 adev->family = AMDGPU_FAMILY_GC_11_0_0; 3023 break; 3024 case IP_VERSION(11, 0, 1): 3025 case IP_VERSION(11, 0, 4): 3026 adev->family = AMDGPU_FAMILY_GC_11_0_1; 3027 break; 3028 case IP_VERSION(11, 5, 0): 3029 case IP_VERSION(11, 5, 1): 3030 case IP_VERSION(11, 5, 2): 3031 case IP_VERSION(11, 5, 3): 3032 adev->family = AMDGPU_FAMILY_GC_11_5_0; 3033 break; 3034 case IP_VERSION(11, 5, 4): 3035 adev->family = AMDGPU_FAMILY_GC_11_5_4; 3036 break; 3037 case IP_VERSION(12, 0, 0): 3038 case IP_VERSION(12, 0, 1): 3039 case IP_VERSION(12, 1, 0): 3040 adev->family = AMDGPU_FAMILY_GC_12_0_0; 3041 break; 3042 default: 3043 return -EINVAL; 3044 } 3045 3046 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3047 case IP_VERSION(9, 1, 0): 3048 case IP_VERSION(9, 2, 2): 3049 case IP_VERSION(9, 3, 0): 3050 case IP_VERSION(10, 1, 3): 3051 case IP_VERSION(10, 1, 4): 3052 case IP_VERSION(10, 3, 1): 3053 case IP_VERSION(10, 3, 3): 3054 case IP_VERSION(10, 3, 6): 3055 case IP_VERSION(10, 3, 7): 3056 case IP_VERSION(11, 0, 1): 3057 case IP_VERSION(11, 0, 4): 3058 case IP_VERSION(11, 5, 0): 3059 case IP_VERSION(11, 5, 1): 3060 case IP_VERSION(11, 5, 2): 3061 case IP_VERSION(11, 5, 3): 3062 case IP_VERSION(11, 5, 4): 3063 adev->flags |= AMD_IS_APU; 3064 break; 3065 default: 3066 break; 3067 } 3068 3069 /* set NBIO version */ 3070 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { 3071 case IP_VERSION(6, 1, 0): 3072 case IP_VERSION(6, 2, 0): 3073 adev->nbio.funcs = &nbio_v6_1_funcs; 3074 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; 3075 break; 3076 case IP_VERSION(7, 0, 0): 3077 case IP_VERSION(7, 0, 1): 3078 case IP_VERSION(2, 5, 0): 3079 adev->nbio.funcs = &nbio_v7_0_funcs; 3080 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; 3081 break; 3082 case IP_VERSION(7, 4, 0): 3083 case IP_VERSION(7, 4, 1): 3084 case IP_VERSION(7, 4, 4): 3085 adev->nbio.funcs = &nbio_v7_4_funcs; 3086 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; 3087 break; 3088 case IP_VERSION(7, 9, 0): 3089 case IP_VERSION(7, 9, 1): 3090 adev->nbio.funcs = &nbio_v7_9_funcs; 3091 adev->nbio.hdp_flush_reg = &nbio_v7_9_hdp_flush_reg; 3092 break; 3093 case IP_VERSION(7, 11, 0): 3094 case IP_VERSION(7, 11, 1): 3095 case IP_VERSION(7, 11, 2): 3096 case IP_VERSION(7, 11, 3): 3097 adev->nbio.funcs = &nbio_v7_11_funcs; 3098 adev->nbio.hdp_flush_reg = &nbio_v7_11_hdp_flush_reg; 3099 break; 3100 case IP_VERSION(7, 2, 0): 3101 case IP_VERSION(7, 2, 1): 3102 case IP_VERSION(7, 3, 0): 3103 case IP_VERSION(7, 5, 0): 3104 case IP_VERSION(7, 5, 1): 3105 adev->nbio.funcs = &nbio_v7_2_funcs; 3106 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; 3107 break; 3108 case IP_VERSION(2, 1, 1): 3109 case IP_VERSION(2, 3, 0): 3110 case IP_VERSION(2, 3, 1): 3111 case IP_VERSION(2, 3, 2): 3112 case IP_VERSION(3, 3, 0): 3113 case IP_VERSION(3, 3, 1): 3114 case IP_VERSION(3, 3, 2): 3115 case IP_VERSION(3, 3, 3): 3116 adev->nbio.funcs = &nbio_v2_3_funcs; 3117 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 3118 break; 3119 case IP_VERSION(4, 3, 0): 3120 case IP_VERSION(4, 3, 1): 3121 if (amdgpu_sriov_vf(adev)) 3122 adev->nbio.funcs = &nbio_v4_3_sriov_funcs; 3123 else 3124 adev->nbio.funcs = &nbio_v4_3_funcs; 3125 adev->nbio.hdp_flush_reg = &nbio_v4_3_hdp_flush_reg; 3126 break; 3127 case IP_VERSION(7, 7, 0): 3128 case IP_VERSION(7, 7, 1): 3129 adev->nbio.funcs = &nbio_v7_7_funcs; 3130 adev->nbio.hdp_flush_reg = &nbio_v7_7_hdp_flush_reg; 3131 break; 3132 case IP_VERSION(6, 3, 1): 3133 case IP_VERSION(7, 11, 4): 3134 adev->nbio.funcs = &nbif_v6_3_1_funcs; 3135 adev->nbio.hdp_flush_reg = &nbif_v6_3_1_hdp_flush_reg; 3136 break; 3137 default: 3138 break; 3139 } 3140 3141 switch (amdgpu_ip_version(adev, HDP_HWIP, 0)) { 3142 case IP_VERSION(4, 0, 0): 3143 case IP_VERSION(4, 0, 1): 3144 case IP_VERSION(4, 1, 0): 3145 case IP_VERSION(4, 1, 1): 3146 case IP_VERSION(4, 1, 2): 3147 case IP_VERSION(4, 2, 0): 3148 case IP_VERSION(4, 2, 1): 3149 case IP_VERSION(4, 4, 0): 3150 case IP_VERSION(4, 4, 2): 3151 case IP_VERSION(4, 4, 5): 3152 adev->hdp.funcs = &hdp_v4_0_funcs; 3153 break; 3154 case IP_VERSION(5, 0, 0): 3155 case IP_VERSION(5, 0, 1): 3156 case IP_VERSION(5, 0, 2): 3157 case IP_VERSION(5, 0, 3): 3158 case IP_VERSION(5, 0, 4): 3159 case IP_VERSION(5, 2, 0): 3160 adev->hdp.funcs = &hdp_v5_0_funcs; 3161 break; 3162 case IP_VERSION(5, 2, 1): 3163 adev->hdp.funcs = &hdp_v5_2_funcs; 3164 break; 3165 case IP_VERSION(6, 0, 0): 3166 case IP_VERSION(6, 0, 1): 3167 case IP_VERSION(6, 1, 0): 3168 case IP_VERSION(6, 1, 1): 3169 adev->hdp.funcs = &hdp_v6_0_funcs; 3170 break; 3171 case IP_VERSION(7, 0, 0): 3172 adev->hdp.funcs = &hdp_v7_0_funcs; 3173 break; 3174 default: 3175 break; 3176 } 3177 3178 switch (amdgpu_ip_version(adev, DF_HWIP, 0)) { 3179 case IP_VERSION(3, 6, 0): 3180 case IP_VERSION(3, 6, 1): 3181 case IP_VERSION(3, 6, 2): 3182 adev->df.funcs = &df_v3_6_funcs; 3183 break; 3184 case IP_VERSION(2, 1, 0): 3185 case IP_VERSION(2, 1, 1): 3186 case IP_VERSION(2, 5, 0): 3187 case IP_VERSION(3, 5, 1): 3188 case IP_VERSION(3, 5, 2): 3189 adev->df.funcs = &df_v1_7_funcs; 3190 break; 3191 case IP_VERSION(4, 3, 0): 3192 adev->df.funcs = &df_v4_3_funcs; 3193 break; 3194 case IP_VERSION(4, 6, 2): 3195 adev->df.funcs = &df_v4_6_2_funcs; 3196 break; 3197 case IP_VERSION(4, 15, 0): 3198 case IP_VERSION(4, 15, 1): 3199 adev->df.funcs = &df_v4_15_funcs; 3200 break; 3201 default: 3202 break; 3203 } 3204 3205 switch (amdgpu_ip_version(adev, SMUIO_HWIP, 0)) { 3206 case IP_VERSION(9, 0, 0): 3207 case IP_VERSION(9, 0, 1): 3208 case IP_VERSION(10, 0, 0): 3209 case IP_VERSION(10, 0, 1): 3210 case IP_VERSION(10, 0, 2): 3211 adev->smuio.funcs = &smuio_v9_0_funcs; 3212 break; 3213 case IP_VERSION(11, 0, 0): 3214 case IP_VERSION(11, 0, 2): 3215 case IP_VERSION(11, 0, 3): 3216 case IP_VERSION(11, 0, 4): 3217 case IP_VERSION(11, 0, 7): 3218 case IP_VERSION(11, 0, 8): 3219 adev->smuio.funcs = &smuio_v11_0_funcs; 3220 break; 3221 case IP_VERSION(11, 0, 6): 3222 case IP_VERSION(11, 0, 10): 3223 case IP_VERSION(11, 0, 11): 3224 case IP_VERSION(11, 5, 0): 3225 case IP_VERSION(11, 5, 2): 3226 case IP_VERSION(13, 0, 1): 3227 case IP_VERSION(13, 0, 9): 3228 case IP_VERSION(13, 0, 10): 3229 adev->smuio.funcs = &smuio_v11_0_6_funcs; 3230 break; 3231 case IP_VERSION(13, 0, 2): 3232 adev->smuio.funcs = &smuio_v13_0_funcs; 3233 break; 3234 case IP_VERSION(13, 0, 3): 3235 case IP_VERSION(13, 0, 11): 3236 adev->smuio.funcs = &smuio_v13_0_3_funcs; 3237 if (adev->smuio.funcs->get_pkg_type(adev) == AMDGPU_PKG_TYPE_APU) { 3238 adev->flags |= AMD_IS_APU; 3239 } 3240 break; 3241 case IP_VERSION(13, 0, 6): 3242 case IP_VERSION(13, 0, 8): 3243 case IP_VERSION(14, 0, 0): 3244 case IP_VERSION(14, 0, 1): 3245 adev->smuio.funcs = &smuio_v13_0_6_funcs; 3246 break; 3247 case IP_VERSION(14, 0, 2): 3248 adev->smuio.funcs = &smuio_v14_0_2_funcs; 3249 break; 3250 case IP_VERSION(15, 0, 0): 3251 adev->smuio.funcs = &smuio_v15_0_0_funcs; 3252 break; 3253 case IP_VERSION(15, 0, 8): 3254 adev->smuio.funcs = &smuio_v15_0_8_funcs; 3255 break; 3256 default: 3257 break; 3258 } 3259 3260 switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) { 3261 case IP_VERSION(6, 0, 0): 3262 case IP_VERSION(6, 0, 1): 3263 case IP_VERSION(6, 0, 2): 3264 case IP_VERSION(6, 0, 3): 3265 adev->lsdma.funcs = &lsdma_v6_0_funcs; 3266 break; 3267 case IP_VERSION(7, 0, 0): 3268 case IP_VERSION(7, 0, 1): 3269 adev->lsdma.funcs = &lsdma_v7_0_funcs; 3270 break; 3271 default: 3272 break; 3273 } 3274 3275 r = amdgpu_discovery_set_common_ip_blocks(adev); 3276 if (r) 3277 return r; 3278 3279 r = amdgpu_discovery_set_gmc_ip_blocks(adev); 3280 if (r) 3281 return r; 3282 3283 /* For SR-IOV, PSP needs to be initialized before IH */ 3284 if (amdgpu_sriov_vf(adev)) { 3285 r = amdgpu_discovery_set_psp_ip_blocks(adev); 3286 if (r) 3287 return r; 3288 r = amdgpu_discovery_set_ih_ip_blocks(adev); 3289 if (r) 3290 return r; 3291 } else { 3292 r = amdgpu_discovery_set_ih_ip_blocks(adev); 3293 if (r) 3294 return r; 3295 3296 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 3297 r = amdgpu_discovery_set_psp_ip_blocks(adev); 3298 if (r) 3299 return r; 3300 } 3301 } 3302 3303 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 3304 r = amdgpu_discovery_set_smu_ip_blocks(adev); 3305 if (r) 3306 return r; 3307 } 3308 3309 r = amdgpu_discovery_set_display_ip_blocks(adev); 3310 if (r) 3311 return r; 3312 3313 r = amdgpu_discovery_set_gc_ip_blocks(adev); 3314 if (r) 3315 return r; 3316 3317 r = amdgpu_discovery_set_sdma_ip_blocks(adev); 3318 if (r) 3319 return r; 3320 3321 r = amdgpu_discovery_set_ras_ip_blocks(adev); 3322 if (r) 3323 return r; 3324 3325 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 3326 !amdgpu_sriov_vf(adev) && 3327 amdgpu_dpm == 1) || 3328 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && 3329 amdgpu_dpm == 1)) { 3330 r = amdgpu_discovery_set_smu_ip_blocks(adev); 3331 if (r) 3332 return r; 3333 } 3334 3335 r = amdgpu_discovery_set_mm_ip_blocks(adev); 3336 if (r) 3337 return r; 3338 3339 r = amdgpu_discovery_set_mes_ip_blocks(adev); 3340 if (r) 3341 return r; 3342 3343 r = amdgpu_discovery_set_vpe_ip_blocks(adev); 3344 if (r) 3345 return r; 3346 3347 r = amdgpu_discovery_set_umsch_mm_ip_blocks(adev); 3348 if (r) 3349 return r; 3350 3351 r = amdgpu_discovery_set_isp_ip_blocks(adev); 3352 if (r) 3353 return r; 3354 return 0; 3355 } 3356 3357