1 /* 2 * Copyright 2018-2024 Advanced Micro Devices, Inc. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_discovery.h" 28 #include "soc15_hw_ip.h" 29 #include "discovery.h" 30 #include "amdgpu_ras.h" 31 32 #include "soc15.h" 33 #include "gfx_v9_0.h" 34 #include "gfx_v9_4_3.h" 35 #include "gmc_v9_0.h" 36 #include "df_v1_7.h" 37 #include "df_v3_6.h" 38 #include "df_v4_3.h" 39 #include "df_v4_6_2.h" 40 #include "df_v4_15.h" 41 #include "nbio_v6_1.h" 42 #include "nbio_v7_0.h" 43 #include "nbio_v7_4.h" 44 #include "nbio_v7_9.h" 45 #include "nbio_v7_11.h" 46 #include "hdp_v4_0.h" 47 #include "vega10_ih.h" 48 #include "vega20_ih.h" 49 #include "sdma_v4_0.h" 50 #include "sdma_v4_4_2.h" 51 #include "uvd_v7_0.h" 52 #include "vce_v4_0.h" 53 #include "vcn_v1_0.h" 54 #include "vcn_v2_5.h" 55 #include "jpeg_v2_5.h" 56 #include "smuio_v9_0.h" 57 #include "gmc_v10_0.h" 58 #include "gmc_v11_0.h" 59 #include "gmc_v12_0.h" 60 #include "gfxhub_v2_0.h" 61 #include "mmhub_v2_0.h" 62 #include "nbio_v2_3.h" 63 #include "nbio_v4_3.h" 64 #include "nbio_v7_2.h" 65 #include "nbio_v7_7.h" 66 #include "nbif_v6_3_1.h" 67 #include "hdp_v5_0.h" 68 #include "hdp_v5_2.h" 69 #include "hdp_v6_0.h" 70 #include "hdp_v7_0.h" 71 #include "nv.h" 72 #include "soc21.h" 73 #include "soc24.h" 74 #include "navi10_ih.h" 75 #include "ih_v6_0.h" 76 #include "ih_v6_1.h" 77 #include "ih_v7_0.h" 78 #include "gfx_v10_0.h" 79 #include "gfx_v11_0.h" 80 #include "gfx_v12_0.h" 81 #include "sdma_v5_0.h" 82 #include "sdma_v5_2.h" 83 #include "sdma_v6_0.h" 84 #include "sdma_v7_0.h" 85 #include "lsdma_v6_0.h" 86 #include "lsdma_v7_0.h" 87 #include "vcn_v2_0.h" 88 #include "jpeg_v2_0.h" 89 #include "vcn_v3_0.h" 90 #include "jpeg_v3_0.h" 91 #include "vcn_v4_0.h" 92 #include "jpeg_v4_0.h" 93 #include "vcn_v4_0_3.h" 94 #include "jpeg_v4_0_3.h" 95 #include "vcn_v4_0_5.h" 96 #include "jpeg_v4_0_5.h" 97 #include "amdgpu_vkms.h" 98 #include "mes_v11_0.h" 99 #include "mes_v12_0.h" 100 #include "smuio_v11_0.h" 101 #include "smuio_v11_0_6.h" 102 #include "smuio_v13_0.h" 103 #include "smuio_v13_0_3.h" 104 #include "smuio_v13_0_6.h" 105 #include "smuio_v14_0_2.h" 106 #include "smuio_v15_0_8.h" 107 #include "vcn_v5_0_0.h" 108 #include "vcn_v5_0_1.h" 109 #include "jpeg_v5_0_0.h" 110 #include "jpeg_v5_0_1.h" 111 #include "amdgpu_ras_mgr.h" 112 113 #include "amdgpu_vpe.h" 114 #if defined(CONFIG_DRM_AMD_ISP) 115 #include "amdgpu_isp.h" 116 #endif 117 118 MODULE_FIRMWARE("amdgpu/ip_discovery.bin"); 119 MODULE_FIRMWARE("amdgpu/vega10_ip_discovery.bin"); 120 MODULE_FIRMWARE("amdgpu/vega12_ip_discovery.bin"); 121 MODULE_FIRMWARE("amdgpu/vega20_ip_discovery.bin"); 122 MODULE_FIRMWARE("amdgpu/raven_ip_discovery.bin"); 123 MODULE_FIRMWARE("amdgpu/raven2_ip_discovery.bin"); 124 MODULE_FIRMWARE("amdgpu/picasso_ip_discovery.bin"); 125 MODULE_FIRMWARE("amdgpu/arcturus_ip_discovery.bin"); 126 MODULE_FIRMWARE("amdgpu/aldebaran_ip_discovery.bin"); 127 128 #define mmIP_DISCOVERY_VERSION 0x16A00 129 #define mmRCC_CONFIG_MEMSIZE 0xde3 130 #define mmMP0_SMN_C2PMSG_33 0x16061 131 #define mmMM_INDEX 0x0 132 #define mmMM_INDEX_HI 0x6 133 #define mmMM_DATA 0x1 134 135 static const char *hw_id_names[HW_ID_MAX] = { 136 [MP1_HWID] = "MP1", 137 [MP2_HWID] = "MP2", 138 [THM_HWID] = "THM", 139 [SMUIO_HWID] = "SMUIO", 140 [FUSE_HWID] = "FUSE", 141 [CLKA_HWID] = "CLKA", 142 [PWR_HWID] = "PWR", 143 [GC_HWID] = "GC", 144 [UVD_HWID] = "UVD", 145 [AUDIO_AZ_HWID] = "AUDIO_AZ", 146 [ACP_HWID] = "ACP", 147 [DCI_HWID] = "DCI", 148 [DMU_HWID] = "DMU", 149 [DCO_HWID] = "DCO", 150 [DIO_HWID] = "DIO", 151 [XDMA_HWID] = "XDMA", 152 [DCEAZ_HWID] = "DCEAZ", 153 [DAZ_HWID] = "DAZ", 154 [SDPMUX_HWID] = "SDPMUX", 155 [NTB_HWID] = "NTB", 156 [IOHC_HWID] = "IOHC", 157 [L2IMU_HWID] = "L2IMU", 158 [VCE_HWID] = "VCE", 159 [MMHUB_HWID] = "MMHUB", 160 [ATHUB_HWID] = "ATHUB", 161 [DBGU_NBIO_HWID] = "DBGU_NBIO", 162 [DFX_HWID] = "DFX", 163 [DBGU0_HWID] = "DBGU0", 164 [DBGU1_HWID] = "DBGU1", 165 [OSSSYS_HWID] = "OSSSYS", 166 [HDP_HWID] = "HDP", 167 [SDMA0_HWID] = "SDMA0", 168 [SDMA1_HWID] = "SDMA1", 169 [SDMA2_HWID] = "SDMA2", 170 [SDMA3_HWID] = "SDMA3", 171 [LSDMA_HWID] = "LSDMA", 172 [ISP_HWID] = "ISP", 173 [DBGU_IO_HWID] = "DBGU_IO", 174 [DF_HWID] = "DF", 175 [CLKB_HWID] = "CLKB", 176 [FCH_HWID] = "FCH", 177 [DFX_DAP_HWID] = "DFX_DAP", 178 [L1IMU_PCIE_HWID] = "L1IMU_PCIE", 179 [L1IMU_NBIF_HWID] = "L1IMU_NBIF", 180 [L1IMU_IOAGR_HWID] = "L1IMU_IOAGR", 181 [L1IMU3_HWID] = "L1IMU3", 182 [L1IMU4_HWID] = "L1IMU4", 183 [L1IMU5_HWID] = "L1IMU5", 184 [L1IMU6_HWID] = "L1IMU6", 185 [L1IMU7_HWID] = "L1IMU7", 186 [L1IMU8_HWID] = "L1IMU8", 187 [L1IMU9_HWID] = "L1IMU9", 188 [L1IMU10_HWID] = "L1IMU10", 189 [L1IMU11_HWID] = "L1IMU11", 190 [L1IMU12_HWID] = "L1IMU12", 191 [L1IMU13_HWID] = "L1IMU13", 192 [L1IMU14_HWID] = "L1IMU14", 193 [L1IMU15_HWID] = "L1IMU15", 194 [WAFLC_HWID] = "WAFLC", 195 [FCH_USB_PD_HWID] = "FCH_USB_PD", 196 [PCIE_HWID] = "PCIE", 197 [PCS_HWID] = "PCS", 198 [DDCL_HWID] = "DDCL", 199 [SST_HWID] = "SST", 200 [IOAGR_HWID] = "IOAGR", 201 [NBIF_HWID] = "NBIF", 202 [IOAPIC_HWID] = "IOAPIC", 203 [SYSTEMHUB_HWID] = "SYSTEMHUB", 204 [NTBCCP_HWID] = "NTBCCP", 205 [UMC_HWID] = "UMC", 206 [SATA_HWID] = "SATA", 207 [USB_HWID] = "USB", 208 [CCXSEC_HWID] = "CCXSEC", 209 [XGMI_HWID] = "XGMI", 210 [XGBE_HWID] = "XGBE", 211 [MP0_HWID] = "MP0", 212 [VPE_HWID] = "VPE", 213 [ATU_HWID] = "ATU", 214 [AIGC_HWID] = "AIGC", 215 }; 216 217 static int hw_id_map[MAX_HWIP] = { 218 [GC_HWIP] = GC_HWID, 219 [HDP_HWIP] = HDP_HWID, 220 [SDMA0_HWIP] = SDMA0_HWID, 221 [SDMA1_HWIP] = SDMA1_HWID, 222 [SDMA2_HWIP] = SDMA2_HWID, 223 [SDMA3_HWIP] = SDMA3_HWID, 224 [LSDMA_HWIP] = LSDMA_HWID, 225 [MMHUB_HWIP] = MMHUB_HWID, 226 [ATHUB_HWIP] = ATHUB_HWID, 227 [NBIO_HWIP] = NBIF_HWID, 228 [MP0_HWIP] = MP0_HWID, 229 [MP1_HWIP] = MP1_HWID, 230 [UVD_HWIP] = UVD_HWID, 231 [VCE_HWIP] = VCE_HWID, 232 [DF_HWIP] = DF_HWID, 233 [DCE_HWIP] = DMU_HWID, 234 [OSSSYS_HWIP] = OSSSYS_HWID, 235 [SMUIO_HWIP] = SMUIO_HWID, 236 [PWR_HWIP] = PWR_HWID, 237 [NBIF_HWIP] = NBIF_HWID, 238 [THM_HWIP] = THM_HWID, 239 [CLK_HWIP] = CLKA_HWID, 240 [UMC_HWIP] = UMC_HWID, 241 [XGMI_HWIP] = XGMI_HWID, 242 [DCI_HWIP] = DCI_HWID, 243 [PCIE_HWIP] = PCIE_HWID, 244 [VPE_HWIP] = VPE_HWID, 245 [ISP_HWIP] = ISP_HWID, 246 [ATU_HWIP] = ATU_HWID, 247 }; 248 249 static int amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device *adev, uint8_t *binary) 250 { 251 u64 tmr_offset, tmr_size, pos; 252 void *discv_regn; 253 int ret; 254 255 ret = amdgpu_acpi_get_tmr_info(adev, &tmr_offset, &tmr_size); 256 if (ret) 257 return ret; 258 259 pos = tmr_offset + tmr_size - DISCOVERY_TMR_OFFSET; 260 261 /* This region is read-only and reserved from system use */ 262 discv_regn = memremap(pos, adev->discovery.size, MEMREMAP_WC); 263 if (discv_regn) { 264 memcpy(binary, discv_regn, adev->discovery.size); 265 memunmap(discv_regn); 266 return 0; 267 } 268 269 return -ENOENT; 270 } 271 272 #define IP_DISCOVERY_V2 2 273 #define IP_DISCOVERY_V4 4 274 275 static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev, 276 uint8_t *binary) 277 { 278 bool sz_valid = true; 279 uint64_t vram_size; 280 int i, ret = 0; 281 u32 msg; 282 283 if (!amdgpu_sriov_vf(adev)) { 284 /* It can take up to two second for IFWI init to complete on some dGPUs, 285 * but generally it should be in the 60-100ms range. Normally this starts 286 * as soon as the device gets power so by the time the OS loads this has long 287 * completed. However, when a card is hotplugged via e.g., USB4, we need to 288 * wait for this to complete. Once the C2PMSG is updated, we can 289 * continue. 290 */ 291 292 for (i = 0; i < 2000; i++) { 293 msg = RREG32(mmMP0_SMN_C2PMSG_33); 294 if (msg & 0x80000000) 295 break; 296 msleep(1); 297 } 298 } 299 300 vram_size = RREG32(mmRCC_CONFIG_MEMSIZE); 301 if (!vram_size || vram_size == U32_MAX) 302 sz_valid = false; 303 else 304 vram_size <<= 20; 305 306 /* 307 * If in VRAM, discovery TMR is marked for reservation. If it is in system mem, 308 * then it is not required to be reserved. 309 */ 310 if (sz_valid) { 311 if (amdgpu_sriov_vf(adev) && adev->virt.is_dynamic_crit_regn_enabled) { 312 /* For SRIOV VFs with dynamic critical region enabled, 313 * we will get the IPD binary via below call. 314 * If dynamic critical is disabled, fall through to normal seq. 315 */ 316 if (amdgpu_virt_get_dynamic_data_info(adev, 317 AMD_SRIOV_MSG_IPD_TABLE_ID, binary, 318 &adev->discovery.size)) { 319 dev_err(adev->dev, 320 "failed to read discovery info from dynamic critical region."); 321 ret = -EINVAL; 322 goto exit; 323 } 324 } else { 325 uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET; 326 327 amdgpu_device_vram_access(adev, pos, (uint32_t *)binary, 328 adev->discovery.size, false); 329 adev->discovery.reserve_tmr = true; 330 } 331 } else { 332 ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary); 333 } 334 335 if (ret) 336 dev_err(adev->dev, 337 "failed to read discovery info from memory, vram size read: %llx", 338 vram_size); 339 exit: 340 return ret; 341 } 342 343 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, 344 uint8_t *binary, 345 const char *fw_name) 346 { 347 const struct firmware *fw; 348 int r; 349 350 r = firmware_request_nowarn(&fw, fw_name, adev->dev); 351 if (r) { 352 if (amdgpu_discovery == 2) 353 dev_err(adev->dev, "can't load firmware \"%s\"\n", fw_name); 354 else 355 drm_info(&adev->ddev, "Optional firmware \"%s\" was not found\n", fw_name); 356 return r; 357 } 358 359 memcpy((u8 *)binary, (u8 *)fw->data, fw->size); 360 release_firmware(fw); 361 362 return 0; 363 } 364 365 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size) 366 { 367 uint16_t checksum = 0; 368 int i; 369 370 for (i = 0; i < size; i++) 371 checksum += data[i]; 372 373 return checksum; 374 } 375 376 static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size, 377 uint16_t expected) 378 { 379 return !!(amdgpu_discovery_calculate_checksum(data, size) == expected); 380 } 381 382 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary) 383 { 384 struct binary_header *bhdr; 385 bhdr = (struct binary_header *)binary; 386 387 return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE); 388 } 389 390 static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev) 391 { 392 /* 393 * So far, apply this quirk only on those Navy Flounder boards which 394 * have a bad harvest table of VCN config. 395 */ 396 if ((amdgpu_ip_version(adev, UVD_HWIP, 1) == IP_VERSION(3, 0, 1)) && 397 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 2))) { 398 switch (adev->pdev->revision) { 399 case 0xC1: 400 case 0xC2: 401 case 0xC3: 402 case 0xC5: 403 case 0xC7: 404 case 0xCF: 405 case 0xDF: 406 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 407 adev->vcn.inst_mask &= ~AMDGPU_VCN_HARVEST_VCN1; 408 break; 409 default: 410 break; 411 } 412 } 413 } 414 415 static int amdgpu_discovery_verify_npsinfo(struct amdgpu_device *adev, 416 struct binary_header *bhdr) 417 { 418 uint8_t *discovery_bin = adev->discovery.bin; 419 struct table_info *info; 420 uint16_t checksum; 421 uint16_t offset; 422 423 info = &bhdr->table_list[NPS_INFO]; 424 offset = le16_to_cpu(info->offset); 425 checksum = le16_to_cpu(info->checksum); 426 427 struct nps_info_header *nhdr = 428 (struct nps_info_header *)(discovery_bin + offset); 429 430 if (le32_to_cpu(nhdr->table_id) != NPS_INFO_TABLE_ID) { 431 dev_dbg(adev->dev, "invalid ip discovery nps info table id\n"); 432 return -EINVAL; 433 } 434 435 if (!amdgpu_discovery_verify_checksum(discovery_bin + offset, 436 le32_to_cpu(nhdr->size_bytes), 437 checksum)) { 438 dev_dbg(adev->dev, "invalid nps info data table checksum\n"); 439 return -EINVAL; 440 } 441 442 return 0; 443 } 444 445 static const char *amdgpu_discovery_get_fw_name(struct amdgpu_device *adev) 446 { 447 if (amdgpu_discovery == 2) { 448 /* Assume there is valid discovery TMR in VRAM even if binary is sideloaded */ 449 adev->discovery.reserve_tmr = true; 450 return "amdgpu/ip_discovery.bin"; 451 } 452 453 switch (adev->asic_type) { 454 case CHIP_VEGA10: 455 return "amdgpu/vega10_ip_discovery.bin"; 456 case CHIP_VEGA12: 457 return "amdgpu/vega12_ip_discovery.bin"; 458 case CHIP_RAVEN: 459 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 460 return "amdgpu/raven2_ip_discovery.bin"; 461 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 462 return "amdgpu/picasso_ip_discovery.bin"; 463 else 464 return "amdgpu/raven_ip_discovery.bin"; 465 case CHIP_VEGA20: 466 return "amdgpu/vega20_ip_discovery.bin"; 467 case CHIP_ARCTURUS: 468 return "amdgpu/arcturus_ip_discovery.bin"; 469 case CHIP_ALDEBARAN: 470 return "amdgpu/aldebaran_ip_discovery.bin"; 471 default: 472 return NULL; 473 } 474 } 475 476 static int amdgpu_discovery_init(struct amdgpu_device *adev) 477 { 478 struct table_info *info; 479 struct binary_header *bhdr; 480 uint8_t *discovery_bin; 481 const char *fw_name; 482 uint16_t offset; 483 uint16_t size; 484 uint16_t checksum; 485 int r; 486 487 adev->discovery.bin = kzalloc(DISCOVERY_TMR_SIZE, GFP_KERNEL); 488 if (!adev->discovery.bin) 489 return -ENOMEM; 490 adev->discovery.size = DISCOVERY_TMR_SIZE; 491 adev->discovery.debugfs_blob.data = adev->discovery.bin; 492 adev->discovery.debugfs_blob.size = adev->discovery.size; 493 494 discovery_bin = adev->discovery.bin; 495 /* Read from file if it is the preferred option */ 496 fw_name = amdgpu_discovery_get_fw_name(adev); 497 if (fw_name != NULL) { 498 drm_dbg(&adev->ddev, "use ip discovery information from file"); 499 r = amdgpu_discovery_read_binary_from_file(adev, discovery_bin, 500 fw_name); 501 if (r) 502 goto out; 503 } else { 504 drm_dbg(&adev->ddev, "use ip discovery information from memory"); 505 r = amdgpu_discovery_read_binary_from_mem(adev, discovery_bin); 506 if (r) 507 goto out; 508 } 509 510 /* check the ip discovery binary signature */ 511 if (!amdgpu_discovery_verify_binary_signature(discovery_bin)) { 512 dev_err(adev->dev, 513 "get invalid ip discovery binary signature\n"); 514 r = -EINVAL; 515 goto out; 516 } 517 518 bhdr = (struct binary_header *)discovery_bin; 519 520 offset = offsetof(struct binary_header, binary_checksum) + 521 sizeof(bhdr->binary_checksum); 522 size = le16_to_cpu(bhdr->binary_size) - offset; 523 checksum = le16_to_cpu(bhdr->binary_checksum); 524 525 if (!amdgpu_discovery_verify_checksum(discovery_bin + offset, size, 526 checksum)) { 527 dev_err(adev->dev, "invalid ip discovery binary checksum\n"); 528 r = -EINVAL; 529 goto out; 530 } 531 532 info = &bhdr->table_list[IP_DISCOVERY]; 533 offset = le16_to_cpu(info->offset); 534 checksum = le16_to_cpu(info->checksum); 535 536 if (offset) { 537 struct ip_discovery_header *ihdr = 538 (struct ip_discovery_header *)(discovery_bin + offset); 539 if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) { 540 dev_err(adev->dev, "invalid ip discovery data table signature\n"); 541 r = -EINVAL; 542 goto out; 543 } 544 545 if (!amdgpu_discovery_verify_checksum(discovery_bin + offset, 546 le16_to_cpu(ihdr->size), 547 checksum)) { 548 dev_err(adev->dev, "invalid ip discovery data table checksum\n"); 549 r = -EINVAL; 550 goto out; 551 } 552 } 553 554 info = &bhdr->table_list[GC]; 555 offset = le16_to_cpu(info->offset); 556 checksum = le16_to_cpu(info->checksum); 557 558 if (offset) { 559 struct gpu_info_header *ghdr = 560 (struct gpu_info_header *)(discovery_bin + offset); 561 562 if (le32_to_cpu(ghdr->table_id) != GC_TABLE_ID) { 563 dev_err(adev->dev, "invalid ip discovery gc table id\n"); 564 r = -EINVAL; 565 goto out; 566 } 567 568 if (!amdgpu_discovery_verify_checksum(discovery_bin + offset, 569 le32_to_cpu(ghdr->size), 570 checksum)) { 571 dev_err(adev->dev, "invalid gc data table checksum\n"); 572 r = -EINVAL; 573 goto out; 574 } 575 } 576 577 info = &bhdr->table_list[HARVEST_INFO]; 578 offset = le16_to_cpu(info->offset); 579 checksum = le16_to_cpu(info->checksum); 580 581 if (offset) { 582 struct harvest_info_header *hhdr = 583 (struct harvest_info_header *)(discovery_bin + offset); 584 585 if (le32_to_cpu(hhdr->signature) != HARVEST_TABLE_SIGNATURE) { 586 dev_err(adev->dev, "invalid ip discovery harvest table signature\n"); 587 r = -EINVAL; 588 goto out; 589 } 590 591 if (!amdgpu_discovery_verify_checksum( 592 discovery_bin + offset, 593 sizeof(struct harvest_table), checksum)) { 594 dev_err(adev->dev, "invalid harvest data table checksum\n"); 595 r = -EINVAL; 596 goto out; 597 } 598 } 599 600 info = &bhdr->table_list[VCN_INFO]; 601 offset = le16_to_cpu(info->offset); 602 checksum = le16_to_cpu(info->checksum); 603 604 if (offset) { 605 struct vcn_info_header *vhdr = 606 (struct vcn_info_header *)(discovery_bin + offset); 607 608 if (le32_to_cpu(vhdr->table_id) != VCN_INFO_TABLE_ID) { 609 dev_err(adev->dev, "invalid ip discovery vcn table id\n"); 610 r = -EINVAL; 611 goto out; 612 } 613 614 if (!amdgpu_discovery_verify_checksum( 615 discovery_bin + offset, 616 le32_to_cpu(vhdr->size_bytes), checksum)) { 617 dev_err(adev->dev, "invalid vcn data table checksum\n"); 618 r = -EINVAL; 619 goto out; 620 } 621 } 622 623 info = &bhdr->table_list[MALL_INFO]; 624 offset = le16_to_cpu(info->offset); 625 checksum = le16_to_cpu(info->checksum); 626 627 if (0 && offset) { 628 struct mall_info_header *mhdr = 629 (struct mall_info_header *)(discovery_bin + offset); 630 631 if (le32_to_cpu(mhdr->table_id) != MALL_INFO_TABLE_ID) { 632 dev_err(adev->dev, "invalid ip discovery mall table id\n"); 633 r = -EINVAL; 634 goto out; 635 } 636 637 if (!amdgpu_discovery_verify_checksum( 638 discovery_bin + offset, 639 le32_to_cpu(mhdr->size_bytes), checksum)) { 640 dev_err(adev->dev, "invalid mall data table checksum\n"); 641 r = -EINVAL; 642 goto out; 643 } 644 } 645 646 return 0; 647 648 out: 649 kfree(adev->discovery.bin); 650 adev->discovery.bin = NULL; 651 if ((amdgpu_discovery != 2) && 652 (RREG32(mmIP_DISCOVERY_VERSION) == 4)) 653 amdgpu_ras_query_boot_status(adev, 4); 654 return r; 655 } 656 657 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev); 658 659 void amdgpu_discovery_fini(struct amdgpu_device *adev) 660 { 661 amdgpu_discovery_sysfs_fini(adev); 662 kfree(adev->discovery.bin); 663 adev->discovery.bin = NULL; 664 } 665 666 static int amdgpu_discovery_validate_ip(struct amdgpu_device *adev, 667 uint8_t instance, uint16_t hw_id) 668 { 669 if (instance >= HWIP_MAX_INSTANCE) { 670 dev_err(adev->dev, 671 "Unexpected instance_number (%d) from ip discovery blob\n", 672 instance); 673 return -EINVAL; 674 } 675 if (hw_id >= HW_ID_MAX) { 676 dev_err(adev->dev, 677 "Unexpected hw_id (%d) from ip discovery blob\n", 678 hw_id); 679 return -EINVAL; 680 } 681 682 return 0; 683 } 684 685 static void amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device *adev, 686 uint32_t *vcn_harvest_count) 687 { 688 uint8_t *discovery_bin = adev->discovery.bin; 689 struct binary_header *bhdr; 690 struct ip_discovery_header *ihdr; 691 struct die_header *dhdr; 692 struct ip *ip; 693 uint16_t die_offset, ip_offset, num_dies, num_ips; 694 uint16_t hw_id; 695 uint8_t inst; 696 int i, j; 697 698 bhdr = (struct binary_header *)discovery_bin; 699 ihdr = (struct ip_discovery_header 700 *)(discovery_bin + 701 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 702 num_dies = le16_to_cpu(ihdr->num_dies); 703 704 /* scan harvest bit of all IP data structures */ 705 for (i = 0; i < num_dies; i++) { 706 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 707 dhdr = (struct die_header *)(discovery_bin + die_offset); 708 num_ips = le16_to_cpu(dhdr->num_ips); 709 ip_offset = die_offset + sizeof(*dhdr); 710 711 for (j = 0; j < num_ips; j++) { 712 ip = (struct ip *)(discovery_bin + ip_offset); 713 inst = ip->number_instance; 714 hw_id = le16_to_cpu(ip->hw_id); 715 if (amdgpu_discovery_validate_ip(adev, inst, hw_id)) 716 goto next_ip; 717 718 if (ip->harvest == 1) { 719 switch (hw_id) { 720 case VCN_HWID: 721 (*vcn_harvest_count)++; 722 if (inst == 0) { 723 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0; 724 adev->vcn.inst_mask &= 725 ~AMDGPU_VCN_HARVEST_VCN0; 726 adev->jpeg.inst_mask &= 727 ~AMDGPU_VCN_HARVEST_VCN0; 728 } else { 729 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 730 adev->vcn.inst_mask &= 731 ~AMDGPU_VCN_HARVEST_VCN1; 732 adev->jpeg.inst_mask &= 733 ~AMDGPU_VCN_HARVEST_VCN1; 734 } 735 break; 736 case DMU_HWID: 737 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 738 break; 739 default: 740 break; 741 } 742 } 743 next_ip: 744 ip_offset += struct_size(ip, base_address, 745 ip->num_base_address); 746 } 747 } 748 } 749 750 static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev, 751 uint32_t *vcn_harvest_count, 752 uint32_t *umc_harvest_count) 753 { 754 uint8_t *discovery_bin = adev->discovery.bin; 755 struct binary_header *bhdr; 756 struct harvest_table *harvest_info; 757 u16 offset; 758 int i; 759 uint32_t umc_harvest_config = 0; 760 761 bhdr = (struct binary_header *)discovery_bin; 762 offset = le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset); 763 764 if (!offset) { 765 dev_err(adev->dev, "invalid harvest table offset\n"); 766 return; 767 } 768 769 harvest_info = (struct harvest_table *)(discovery_bin + offset); 770 771 for (i = 0; i < 32; i++) { 772 if (le16_to_cpu(harvest_info->list[i].hw_id) == 0) 773 break; 774 775 switch (le16_to_cpu(harvest_info->list[i].hw_id)) { 776 case VCN_HWID: 777 (*vcn_harvest_count)++; 778 adev->vcn.harvest_config |= 779 (1 << harvest_info->list[i].number_instance); 780 adev->jpeg.harvest_config |= 781 (1 << harvest_info->list[i].number_instance); 782 783 adev->vcn.inst_mask &= 784 ~(1U << harvest_info->list[i].number_instance); 785 adev->jpeg.inst_mask &= 786 ~(1U << harvest_info->list[i].number_instance); 787 break; 788 case DMU_HWID: 789 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 790 break; 791 case UMC_HWID: 792 umc_harvest_config |= 793 1 << (le16_to_cpu(harvest_info->list[i].number_instance)); 794 (*umc_harvest_count)++; 795 break; 796 case GC_HWID: 797 adev->gfx.xcc_mask &= 798 ~(1U << harvest_info->list[i].number_instance); 799 break; 800 case SDMA0_HWID: 801 adev->sdma.sdma_mask &= 802 ~(1U << harvest_info->list[i].number_instance); 803 break; 804 #if defined(CONFIG_DRM_AMD_ISP) 805 case ISP_HWID: 806 adev->isp.harvest_config |= 807 ~(1U << harvest_info->list[i].number_instance); 808 break; 809 #endif 810 default: 811 break; 812 } 813 } 814 815 adev->umc.active_mask = ((1 << adev->umc.node_inst_num) - 1) & 816 ~umc_harvest_config; 817 } 818 819 /* ================================================== */ 820 821 struct ip_hw_instance { 822 struct kobject kobj; /* ip_discovery/die/#die/#hw_id/#instance/<attrs...> */ 823 824 int hw_id; 825 u8 num_instance; 826 u8 major, minor, revision; 827 u8 harvest; 828 829 int num_base_addresses; 830 u32 base_addr[] __counted_by(num_base_addresses); 831 }; 832 833 struct ip_hw_id { 834 struct kset hw_id_kset; /* ip_discovery/die/#die/#hw_id/, contains ip_hw_instance */ 835 int hw_id; 836 }; 837 838 struct ip_die_entry { 839 struct kset ip_kset; /* ip_discovery/die/#die/, contains ip_hw_id */ 840 u16 num_ips; 841 }; 842 843 /* -------------------------------------------------- */ 844 845 struct ip_hw_instance_attr { 846 struct attribute attr; 847 ssize_t (*show)(struct ip_hw_instance *ip_hw_instance, char *buf); 848 }; 849 850 static ssize_t hw_id_show(struct ip_hw_instance *ip_hw_instance, char *buf) 851 { 852 return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id); 853 } 854 855 static ssize_t num_instance_show(struct ip_hw_instance *ip_hw_instance, char *buf) 856 { 857 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance); 858 } 859 860 static ssize_t major_show(struct ip_hw_instance *ip_hw_instance, char *buf) 861 { 862 return sysfs_emit(buf, "%d\n", ip_hw_instance->major); 863 } 864 865 static ssize_t minor_show(struct ip_hw_instance *ip_hw_instance, char *buf) 866 { 867 return sysfs_emit(buf, "%d\n", ip_hw_instance->minor); 868 } 869 870 static ssize_t revision_show(struct ip_hw_instance *ip_hw_instance, char *buf) 871 { 872 return sysfs_emit(buf, "%d\n", ip_hw_instance->revision); 873 } 874 875 static ssize_t harvest_show(struct ip_hw_instance *ip_hw_instance, char *buf) 876 { 877 return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest); 878 } 879 880 static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, char *buf) 881 { 882 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses); 883 } 884 885 static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf) 886 { 887 ssize_t res, at; 888 int ii; 889 890 for (res = at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) { 891 /* Here we satisfy the condition that, at + size <= PAGE_SIZE. 892 */ 893 if (at + 12 > PAGE_SIZE) 894 break; 895 res = sysfs_emit_at(buf, at, "0x%08X\n", 896 ip_hw_instance->base_addr[ii]); 897 if (res <= 0) 898 break; 899 at += res; 900 } 901 902 return res < 0 ? res : at; 903 } 904 905 static struct ip_hw_instance_attr ip_hw_attr[] = { 906 __ATTR_RO(hw_id), 907 __ATTR_RO(num_instance), 908 __ATTR_RO(major), 909 __ATTR_RO(minor), 910 __ATTR_RO(revision), 911 __ATTR_RO(harvest), 912 __ATTR_RO(num_base_addresses), 913 __ATTR_RO(base_addr), 914 }; 915 916 static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1]; 917 ATTRIBUTE_GROUPS(ip_hw_instance); 918 919 #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj) 920 #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr) 921 922 static ssize_t ip_hw_instance_attr_show(struct kobject *kobj, 923 struct attribute *attr, 924 char *buf) 925 { 926 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 927 struct ip_hw_instance_attr *ip_hw_attr = to_ip_hw_instance_attr(attr); 928 929 if (!ip_hw_attr->show) 930 return -EIO; 931 932 return ip_hw_attr->show(ip_hw_instance, buf); 933 } 934 935 static const struct sysfs_ops ip_hw_instance_sysfs_ops = { 936 .show = ip_hw_instance_attr_show, 937 }; 938 939 static void ip_hw_instance_release(struct kobject *kobj) 940 { 941 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 942 943 kfree(ip_hw_instance); 944 } 945 946 static const struct kobj_type ip_hw_instance_ktype = { 947 .release = ip_hw_instance_release, 948 .sysfs_ops = &ip_hw_instance_sysfs_ops, 949 .default_groups = ip_hw_instance_groups, 950 }; 951 952 /* -------------------------------------------------- */ 953 954 #define to_ip_hw_id(x) container_of(to_kset(x), struct ip_hw_id, hw_id_kset) 955 956 static void ip_hw_id_release(struct kobject *kobj) 957 { 958 struct ip_hw_id *ip_hw_id = to_ip_hw_id(kobj); 959 960 if (!list_empty(&ip_hw_id->hw_id_kset.list)) 961 DRM_ERROR("ip_hw_id->hw_id_kset is not empty"); 962 kfree(ip_hw_id); 963 } 964 965 static const struct kobj_type ip_hw_id_ktype = { 966 .release = ip_hw_id_release, 967 .sysfs_ops = &kobj_sysfs_ops, 968 }; 969 970 /* -------------------------------------------------- */ 971 972 static void die_kobj_release(struct kobject *kobj); 973 static void ip_disc_release(struct kobject *kobj); 974 975 struct ip_die_entry_attribute { 976 struct attribute attr; 977 ssize_t (*show)(struct ip_die_entry *ip_die_entry, char *buf); 978 }; 979 980 #define to_ip_die_entry_attr(x) container_of(x, struct ip_die_entry_attribute, attr) 981 982 static ssize_t num_ips_show(struct ip_die_entry *ip_die_entry, char *buf) 983 { 984 return sysfs_emit(buf, "%d\n", ip_die_entry->num_ips); 985 } 986 987 /* If there are more ip_die_entry attrs, other than the number of IPs, 988 * we can make this intro an array of attrs, and then initialize 989 * ip_die_entry_attrs in a loop. 990 */ 991 static struct ip_die_entry_attribute num_ips_attr = 992 __ATTR_RO(num_ips); 993 994 static struct attribute *ip_die_entry_attrs[] = { 995 &num_ips_attr.attr, 996 NULL, 997 }; 998 ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */ 999 1000 #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset) 1001 1002 static ssize_t ip_die_entry_attr_show(struct kobject *kobj, 1003 struct attribute *attr, 1004 char *buf) 1005 { 1006 struct ip_die_entry_attribute *ip_die_entry_attr = to_ip_die_entry_attr(attr); 1007 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 1008 1009 if (!ip_die_entry_attr->show) 1010 return -EIO; 1011 1012 return ip_die_entry_attr->show(ip_die_entry, buf); 1013 } 1014 1015 static void ip_die_entry_release(struct kobject *kobj) 1016 { 1017 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 1018 1019 if (!list_empty(&ip_die_entry->ip_kset.list)) 1020 DRM_ERROR("ip_die_entry->ip_kset is not empty"); 1021 kfree(ip_die_entry); 1022 } 1023 1024 static const struct sysfs_ops ip_die_entry_sysfs_ops = { 1025 .show = ip_die_entry_attr_show, 1026 }; 1027 1028 static const struct kobj_type ip_die_entry_ktype = { 1029 .release = ip_die_entry_release, 1030 .sysfs_ops = &ip_die_entry_sysfs_ops, 1031 .default_groups = ip_die_entry_groups, 1032 }; 1033 1034 static const struct kobj_type die_kobj_ktype = { 1035 .release = die_kobj_release, 1036 .sysfs_ops = &kobj_sysfs_ops, 1037 }; 1038 1039 static const struct kobj_type ip_discovery_ktype = { 1040 .release = ip_disc_release, 1041 .sysfs_ops = &kobj_sysfs_ops, 1042 }; 1043 1044 struct ip_discovery_top { 1045 struct kobject kobj; /* ip_discovery/ */ 1046 struct kset die_kset; /* ip_discovery/die/, contains ip_die_entry */ 1047 struct amdgpu_device *adev; 1048 }; 1049 1050 static void die_kobj_release(struct kobject *kobj) 1051 { 1052 struct ip_discovery_top *ip_top = container_of(to_kset(kobj), 1053 struct ip_discovery_top, 1054 die_kset); 1055 if (!list_empty(&ip_top->die_kset.list)) 1056 DRM_ERROR("ip_top->die_kset is not empty"); 1057 } 1058 1059 static void ip_disc_release(struct kobject *kobj) 1060 { 1061 struct ip_discovery_top *ip_top = container_of(kobj, struct ip_discovery_top, 1062 kobj); 1063 struct amdgpu_device *adev = ip_top->adev; 1064 1065 kfree(ip_top); 1066 adev->discovery.ip_top = NULL; 1067 } 1068 1069 static uint8_t amdgpu_discovery_get_harvest_info(struct amdgpu_device *adev, 1070 uint16_t hw_id, uint8_t inst) 1071 { 1072 uint8_t harvest = 0; 1073 1074 /* Until a uniform way is figured, get mask based on hwid */ 1075 switch (hw_id) { 1076 case VCN_HWID: 1077 /* VCN vs UVD+VCE */ 1078 if (!amdgpu_ip_version(adev, VCE_HWIP, 0)) 1079 harvest = ((1 << inst) & adev->vcn.inst_mask) == 0; 1080 break; 1081 case DMU_HWID: 1082 if (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK) 1083 harvest = 0x1; 1084 break; 1085 case UMC_HWID: 1086 /* TODO: It needs another parsing; for now, ignore.*/ 1087 break; 1088 case GC_HWID: 1089 harvest = ((1 << inst) & adev->gfx.xcc_mask) == 0; 1090 break; 1091 case SDMA0_HWID: 1092 harvest = ((1 << inst) & adev->sdma.sdma_mask) == 0; 1093 break; 1094 default: 1095 break; 1096 } 1097 1098 return harvest; 1099 } 1100 1101 static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev, 1102 struct ip_die_entry *ip_die_entry, 1103 const size_t _ip_offset, const int num_ips, 1104 bool reg_base_64) 1105 { 1106 uint8_t *discovery_bin = adev->discovery.bin; 1107 int ii, jj, kk, res; 1108 uint16_t hw_id; 1109 uint8_t inst; 1110 1111 DRM_DEBUG("num_ips:%d", num_ips); 1112 1113 /* Find all IPs of a given HW ID, and add their instance to 1114 * #die/#hw_id/#instance/<attributes> 1115 */ 1116 for (ii = 0; ii < HW_ID_MAX; ii++) { 1117 struct ip_hw_id *ip_hw_id = NULL; 1118 size_t ip_offset = _ip_offset; 1119 1120 for (jj = 0; jj < num_ips; jj++) { 1121 struct ip_v4 *ip; 1122 struct ip_hw_instance *ip_hw_instance; 1123 1124 ip = (struct ip_v4 *)(discovery_bin + ip_offset); 1125 inst = ip->instance_number; 1126 hw_id = le16_to_cpu(ip->hw_id); 1127 if (amdgpu_discovery_validate_ip(adev, inst, hw_id) || 1128 hw_id != ii) 1129 goto next_ip; 1130 1131 DRM_DEBUG("match:%d @ ip_offset:%zu", ii, ip_offset); 1132 1133 /* We have a hw_id match; register the hw 1134 * block if not yet registered. 1135 */ 1136 if (!ip_hw_id) { 1137 ip_hw_id = kzalloc(sizeof(*ip_hw_id), GFP_KERNEL); 1138 if (!ip_hw_id) 1139 return -ENOMEM; 1140 ip_hw_id->hw_id = ii; 1141 1142 kobject_set_name(&ip_hw_id->hw_id_kset.kobj, "%d", ii); 1143 ip_hw_id->hw_id_kset.kobj.kset = &ip_die_entry->ip_kset; 1144 ip_hw_id->hw_id_kset.kobj.ktype = &ip_hw_id_ktype; 1145 res = kset_register(&ip_hw_id->hw_id_kset); 1146 if (res) { 1147 DRM_ERROR("Couldn't register ip_hw_id kset"); 1148 kfree(ip_hw_id); 1149 return res; 1150 } 1151 if (hw_id_names[ii]) { 1152 res = sysfs_create_link(&ip_die_entry->ip_kset.kobj, 1153 &ip_hw_id->hw_id_kset.kobj, 1154 hw_id_names[ii]); 1155 if (res) { 1156 DRM_ERROR("Couldn't create IP link %s in IP Die:%s\n", 1157 hw_id_names[ii], 1158 kobject_name(&ip_die_entry->ip_kset.kobj)); 1159 } 1160 } 1161 } 1162 1163 /* Now register its instance. 1164 */ 1165 ip_hw_instance = kzalloc(struct_size(ip_hw_instance, 1166 base_addr, 1167 ip->num_base_address), 1168 GFP_KERNEL); 1169 if (!ip_hw_instance) { 1170 DRM_ERROR("no memory for ip_hw_instance"); 1171 return -ENOMEM; 1172 } 1173 ip_hw_instance->hw_id = le16_to_cpu(ip->hw_id); /* == ii */ 1174 ip_hw_instance->num_instance = ip->instance_number; 1175 ip_hw_instance->major = ip->major; 1176 ip_hw_instance->minor = ip->minor; 1177 ip_hw_instance->revision = ip->revision; 1178 ip_hw_instance->harvest = 1179 amdgpu_discovery_get_harvest_info( 1180 adev, ip_hw_instance->hw_id, 1181 ip_hw_instance->num_instance); 1182 ip_hw_instance->num_base_addresses = ip->num_base_address; 1183 1184 for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++) { 1185 if (reg_base_64) 1186 ip_hw_instance->base_addr[kk] = 1187 lower_32_bits(le64_to_cpu(ip->base_address_64[kk])) & 0x3FFFFFFF; 1188 else 1189 ip_hw_instance->base_addr[kk] = ip->base_address[kk]; 1190 } 1191 1192 kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype); 1193 ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset; 1194 res = kobject_add(&ip_hw_instance->kobj, NULL, 1195 "%d", ip_hw_instance->num_instance); 1196 next_ip: 1197 if (reg_base_64) 1198 ip_offset += struct_size(ip, base_address_64, 1199 ip->num_base_address); 1200 else 1201 ip_offset += struct_size(ip, base_address, 1202 ip->num_base_address); 1203 } 1204 } 1205 1206 return 0; 1207 } 1208 1209 static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev) 1210 { 1211 struct ip_discovery_top *ip_top = adev->discovery.ip_top; 1212 uint8_t *discovery_bin = adev->discovery.bin; 1213 struct binary_header *bhdr; 1214 struct ip_discovery_header *ihdr; 1215 struct die_header *dhdr; 1216 struct kset *die_kset = &ip_top->die_kset; 1217 u16 num_dies, die_offset, num_ips; 1218 size_t ip_offset; 1219 int ii, res; 1220 1221 bhdr = (struct binary_header *)discovery_bin; 1222 ihdr = (struct ip_discovery_header 1223 *)(discovery_bin + 1224 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 1225 num_dies = le16_to_cpu(ihdr->num_dies); 1226 1227 DRM_DEBUG("number of dies: %d\n", num_dies); 1228 1229 for (ii = 0; ii < num_dies; ii++) { 1230 struct ip_die_entry *ip_die_entry; 1231 1232 die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset); 1233 dhdr = (struct die_header *)(discovery_bin + die_offset); 1234 num_ips = le16_to_cpu(dhdr->num_ips); 1235 ip_offset = die_offset + sizeof(*dhdr); 1236 1237 /* Add the die to the kset. 1238 * 1239 * dhdr->die_id == ii, which was checked in 1240 * amdgpu_discovery_reg_base_init(). 1241 */ 1242 1243 ip_die_entry = kzalloc(sizeof(*ip_die_entry), GFP_KERNEL); 1244 if (!ip_die_entry) 1245 return -ENOMEM; 1246 1247 ip_die_entry->num_ips = num_ips; 1248 1249 kobject_set_name(&ip_die_entry->ip_kset.kobj, "%d", le16_to_cpu(dhdr->die_id)); 1250 ip_die_entry->ip_kset.kobj.kset = die_kset; 1251 ip_die_entry->ip_kset.kobj.ktype = &ip_die_entry_ktype; 1252 res = kset_register(&ip_die_entry->ip_kset); 1253 if (res) { 1254 DRM_ERROR("Couldn't register ip_die_entry kset"); 1255 kfree(ip_die_entry); 1256 return res; 1257 } 1258 1259 amdgpu_discovery_sysfs_ips(adev, ip_die_entry, ip_offset, num_ips, !!ihdr->base_addr_64_bit); 1260 } 1261 1262 return 0; 1263 } 1264 1265 static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev) 1266 { 1267 uint8_t *discovery_bin = adev->discovery.bin; 1268 struct ip_discovery_top *ip_top; 1269 struct kset *die_kset; 1270 int res, ii; 1271 1272 if (!discovery_bin) 1273 return -EINVAL; 1274 1275 ip_top = kzalloc(sizeof(*ip_top), GFP_KERNEL); 1276 if (!ip_top) 1277 return -ENOMEM; 1278 1279 ip_top->adev = adev; 1280 adev->discovery.ip_top = ip_top; 1281 res = kobject_init_and_add(&ip_top->kobj, &ip_discovery_ktype, 1282 &adev->dev->kobj, "ip_discovery"); 1283 if (res) { 1284 DRM_ERROR("Couldn't init and add ip_discovery/"); 1285 goto Err; 1286 } 1287 1288 die_kset = &ip_top->die_kset; 1289 kobject_set_name(&die_kset->kobj, "%s", "die"); 1290 die_kset->kobj.parent = &ip_top->kobj; 1291 die_kset->kobj.ktype = &die_kobj_ktype; 1292 res = kset_register(&ip_top->die_kset); 1293 if (res) { 1294 DRM_ERROR("Couldn't register die_kset"); 1295 goto Err; 1296 } 1297 1298 for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++) 1299 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr; 1300 ip_hw_instance_attrs[ii] = NULL; 1301 1302 res = amdgpu_discovery_sysfs_recurse(adev); 1303 1304 return res; 1305 Err: 1306 kobject_put(&ip_top->kobj); 1307 return res; 1308 } 1309 1310 /* -------------------------------------------------- */ 1311 1312 #define list_to_kobj(el) container_of(el, struct kobject, entry) 1313 1314 static void amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id *ip_hw_id) 1315 { 1316 struct list_head *el, *tmp; 1317 struct kset *hw_id_kset; 1318 1319 hw_id_kset = &ip_hw_id->hw_id_kset; 1320 spin_lock(&hw_id_kset->list_lock); 1321 list_for_each_prev_safe(el, tmp, &hw_id_kset->list) { 1322 list_del_init(el); 1323 spin_unlock(&hw_id_kset->list_lock); 1324 /* kobject is embedded in ip_hw_instance */ 1325 kobject_put(list_to_kobj(el)); 1326 spin_lock(&hw_id_kset->list_lock); 1327 } 1328 spin_unlock(&hw_id_kset->list_lock); 1329 kobject_put(&ip_hw_id->hw_id_kset.kobj); 1330 } 1331 1332 static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry) 1333 { 1334 struct list_head *el, *tmp; 1335 struct kset *ip_kset; 1336 1337 ip_kset = &ip_die_entry->ip_kset; 1338 spin_lock(&ip_kset->list_lock); 1339 list_for_each_prev_safe(el, tmp, &ip_kset->list) { 1340 list_del_init(el); 1341 spin_unlock(&ip_kset->list_lock); 1342 amdgpu_discovery_sysfs_ip_hw_free(to_ip_hw_id(list_to_kobj(el))); 1343 spin_lock(&ip_kset->list_lock); 1344 } 1345 spin_unlock(&ip_kset->list_lock); 1346 kobject_put(&ip_die_entry->ip_kset.kobj); 1347 } 1348 1349 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev) 1350 { 1351 struct ip_discovery_top *ip_top = adev->discovery.ip_top; 1352 struct list_head *el, *tmp; 1353 struct kset *die_kset; 1354 1355 die_kset = &ip_top->die_kset; 1356 spin_lock(&die_kset->list_lock); 1357 list_for_each_prev_safe(el, tmp, &die_kset->list) { 1358 list_del_init(el); 1359 spin_unlock(&die_kset->list_lock); 1360 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el))); 1361 spin_lock(&die_kset->list_lock); 1362 } 1363 spin_unlock(&die_kset->list_lock); 1364 kobject_put(&ip_top->die_kset.kobj); 1365 kobject_put(&ip_top->kobj); 1366 } 1367 1368 /* ================================================== */ 1369 1370 static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) 1371 { 1372 uint8_t num_base_address, subrev, variant; 1373 struct binary_header *bhdr; 1374 struct ip_discovery_header *ihdr; 1375 struct die_header *dhdr; 1376 uint8_t *discovery_bin; 1377 struct ip_v4 *ip; 1378 uint16_t die_offset; 1379 uint16_t ip_offset; 1380 uint16_t num_dies; 1381 uint32_t wafl_ver; 1382 uint16_t num_ips; 1383 uint16_t hw_id; 1384 uint8_t inst; 1385 int hw_ip; 1386 int i, j, k; 1387 int r; 1388 1389 r = amdgpu_discovery_init(adev); 1390 if (r) 1391 return r; 1392 discovery_bin = adev->discovery.bin; 1393 wafl_ver = 0; 1394 adev->gfx.xcc_mask = 0; 1395 adev->sdma.sdma_mask = 0; 1396 adev->vcn.inst_mask = 0; 1397 adev->jpeg.inst_mask = 0; 1398 bhdr = (struct binary_header *)discovery_bin; 1399 ihdr = (struct ip_discovery_header 1400 *)(discovery_bin + 1401 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 1402 num_dies = le16_to_cpu(ihdr->num_dies); 1403 1404 DRM_DEBUG("number of dies: %d\n", num_dies); 1405 1406 for (i = 0; i < num_dies; i++) { 1407 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 1408 dhdr = (struct die_header *)(discovery_bin + die_offset); 1409 num_ips = le16_to_cpu(dhdr->num_ips); 1410 ip_offset = die_offset + sizeof(*dhdr); 1411 1412 if (le16_to_cpu(dhdr->die_id) != i) { 1413 DRM_ERROR("invalid die id %d, expected %d\n", 1414 le16_to_cpu(dhdr->die_id), i); 1415 return -EINVAL; 1416 } 1417 1418 DRM_DEBUG("number of hardware IPs on die%d: %d\n", 1419 le16_to_cpu(dhdr->die_id), num_ips); 1420 1421 for (j = 0; j < num_ips; j++) { 1422 ip = (struct ip_v4 *)(discovery_bin + ip_offset); 1423 1424 inst = ip->instance_number; 1425 hw_id = le16_to_cpu(ip->hw_id); 1426 if (amdgpu_discovery_validate_ip(adev, inst, hw_id)) 1427 goto next_ip; 1428 1429 num_base_address = ip->num_base_address; 1430 1431 DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n", 1432 hw_id_names[le16_to_cpu(ip->hw_id)], 1433 le16_to_cpu(ip->hw_id), 1434 ip->instance_number, 1435 ip->major, ip->minor, 1436 ip->revision); 1437 1438 if (le16_to_cpu(ip->hw_id) == VCN_HWID) { 1439 /* Bit [5:0]: original revision value 1440 * Bit [7:6]: en/decode capability: 1441 * 0b00 : VCN function normally 1442 * 0b10 : encode is disabled 1443 * 0b01 : decode is disabled 1444 */ 1445 if (adev->vcn.num_vcn_inst < 1446 AMDGPU_MAX_VCN_INSTANCES) { 1447 adev->vcn.inst[adev->vcn.num_vcn_inst].vcn_config = 1448 ip->revision & 0xc0; 1449 adev->vcn.num_vcn_inst++; 1450 adev->vcn.inst_mask |= 1451 (1U << ip->instance_number); 1452 adev->jpeg.inst_mask |= 1453 (1U << ip->instance_number); 1454 } else { 1455 dev_err(adev->dev, "Too many VCN instances: %d vs %d\n", 1456 adev->vcn.num_vcn_inst + 1, 1457 AMDGPU_MAX_VCN_INSTANCES); 1458 } 1459 ip->revision &= ~0xc0; 1460 } 1461 if (le16_to_cpu(ip->hw_id) == SDMA0_HWID || 1462 le16_to_cpu(ip->hw_id) == SDMA1_HWID || 1463 le16_to_cpu(ip->hw_id) == SDMA2_HWID || 1464 le16_to_cpu(ip->hw_id) == SDMA3_HWID) { 1465 if (adev->sdma.num_instances < 1466 AMDGPU_MAX_SDMA_INSTANCES) { 1467 adev->sdma.num_instances++; 1468 adev->sdma.sdma_mask |= 1469 (1U << ip->instance_number); 1470 } else { 1471 dev_err(adev->dev, "Too many SDMA instances: %d vs %d\n", 1472 adev->sdma.num_instances + 1, 1473 AMDGPU_MAX_SDMA_INSTANCES); 1474 } 1475 } 1476 1477 if (le16_to_cpu(ip->hw_id) == VPE_HWID) { 1478 if (adev->vpe.num_instances < AMDGPU_MAX_VPE_INSTANCES) 1479 adev->vpe.num_instances++; 1480 else 1481 dev_err(adev->dev, "Too many VPE instances: %d vs %d\n", 1482 adev->vpe.num_instances + 1, 1483 AMDGPU_MAX_VPE_INSTANCES); 1484 } 1485 1486 if (le16_to_cpu(ip->hw_id) == UMC_HWID) { 1487 adev->gmc.num_umc++; 1488 adev->umc.node_inst_num++; 1489 } 1490 1491 if (le16_to_cpu(ip->hw_id) == GC_HWID) 1492 adev->gfx.xcc_mask |= 1493 (1U << ip->instance_number); 1494 1495 if (!wafl_ver && le16_to_cpu(ip->hw_id) == WAFLC_HWID) 1496 wafl_ver = IP_VERSION_FULL(ip->major, ip->minor, 1497 ip->revision, 0, 0); 1498 1499 for (k = 0; k < num_base_address; k++) { 1500 /* 1501 * convert the endianness of base addresses in place, 1502 * so that we don't need to convert them when accessing adev->reg_offset. 1503 */ 1504 if (ihdr->base_addr_64_bit) 1505 /* Truncate the 64bit base address from ip discovery 1506 * and only store lower 32bit ip base in reg_offset[]. 1507 * Bits > 32 follows ASIC specific format, thus just 1508 * discard them and handle it within specific ASIC. 1509 * By this way reg_offset[] and related helpers can 1510 * stay unchanged. 1511 * The base address is in dwords, thus clear the 1512 * highest 2 bits to store. 1513 */ 1514 ip->base_address[k] = 1515 lower_32_bits(le64_to_cpu(ip->base_address_64[k])) & 0x3FFFFFFF; 1516 else 1517 ip->base_address[k] = le32_to_cpu(ip->base_address[k]); 1518 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]); 1519 } 1520 1521 for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) { 1522 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id) && 1523 hw_id_map[hw_ip] != 0) { 1524 DRM_DEBUG("set register base offset for %s\n", 1525 hw_id_names[le16_to_cpu(ip->hw_id)]); 1526 adev->reg_offset[hw_ip][ip->instance_number] = 1527 ip->base_address; 1528 /* Instance support is somewhat inconsistent. 1529 * SDMA is a good example. Sienna cichlid has 4 total 1530 * SDMA instances, each enumerated separately (HWIDs 1531 * 42, 43, 68, 69). Arcturus has 8 total SDMA instances, 1532 * but they are enumerated as multiple instances of the 1533 * same HWIDs (4x HWID 42, 4x HWID 43). UMC is another 1534 * example. On most chips there are multiple instances 1535 * with the same HWID. 1536 */ 1537 1538 if (ihdr->version < 3) { 1539 subrev = 0; 1540 variant = 0; 1541 } else { 1542 subrev = ip->sub_revision; 1543 variant = ip->variant; 1544 } 1545 1546 adev->ip_versions[hw_ip] 1547 [ip->instance_number] = 1548 IP_VERSION_FULL(ip->major, 1549 ip->minor, 1550 ip->revision, 1551 variant, 1552 subrev); 1553 } 1554 } 1555 1556 next_ip: 1557 if (ihdr->base_addr_64_bit) 1558 ip_offset += struct_size(ip, base_address_64, ip->num_base_address); 1559 else 1560 ip_offset += struct_size(ip, base_address, ip->num_base_address); 1561 } 1562 } 1563 1564 if (wafl_ver && !adev->ip_versions[XGMI_HWIP][0]) 1565 adev->ip_versions[XGMI_HWIP][0] = wafl_ver; 1566 1567 return 0; 1568 } 1569 1570 static void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev) 1571 { 1572 uint8_t *discovery_bin = adev->discovery.bin; 1573 struct ip_discovery_header *ihdr; 1574 struct binary_header *bhdr; 1575 int vcn_harvest_count = 0; 1576 int umc_harvest_count = 0; 1577 uint16_t offset, ihdr_ver; 1578 1579 bhdr = (struct binary_header *)discovery_bin; 1580 offset = le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset); 1581 ihdr = (struct ip_discovery_header *)(discovery_bin + offset); 1582 ihdr_ver = le16_to_cpu(ihdr->version); 1583 /* 1584 * Harvest table does not fit Navi1x and legacy GPUs, 1585 * so read harvest bit per IP data structure to set 1586 * harvest configuration. 1587 */ 1588 if (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 2, 0) && 1589 ihdr_ver <= 2) { 1590 if ((adev->pdev->device == 0x731E && 1591 (adev->pdev->revision == 0xC6 || 1592 adev->pdev->revision == 0xC7)) || 1593 (adev->pdev->device == 0x7340 && 1594 adev->pdev->revision == 0xC9) || 1595 (adev->pdev->device == 0x7360 && 1596 adev->pdev->revision == 0xC7)) 1597 amdgpu_discovery_read_harvest_bit_per_ip(adev, 1598 &vcn_harvest_count); 1599 } else { 1600 amdgpu_discovery_read_from_harvest_table(adev, 1601 &vcn_harvest_count, 1602 &umc_harvest_count); 1603 } 1604 1605 amdgpu_discovery_harvest_config_quirk(adev); 1606 1607 if (vcn_harvest_count == adev->vcn.num_vcn_inst) { 1608 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK; 1609 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK; 1610 } 1611 1612 if (umc_harvest_count < adev->gmc.num_umc) { 1613 adev->gmc.num_umc -= umc_harvest_count; 1614 } 1615 } 1616 1617 union gc_info { 1618 struct gc_info_v1_0 v1; 1619 struct gc_info_v1_1 v1_1; 1620 struct gc_info_v1_2 v1_2; 1621 struct gc_info_v1_3 v1_3; 1622 struct gc_info_v2_0 v2; 1623 struct gc_info_v2_1 v2_1; 1624 }; 1625 1626 static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) 1627 { 1628 uint8_t *discovery_bin = adev->discovery.bin; 1629 struct binary_header *bhdr; 1630 union gc_info *gc_info; 1631 u16 offset; 1632 1633 if (!discovery_bin) { 1634 DRM_ERROR("ip discovery uninitialized\n"); 1635 return -EINVAL; 1636 } 1637 1638 bhdr = (struct binary_header *)discovery_bin; 1639 offset = le16_to_cpu(bhdr->table_list[GC].offset); 1640 1641 if (!offset) 1642 return 0; 1643 1644 gc_info = (union gc_info *)(discovery_bin + offset); 1645 1646 switch (le16_to_cpu(gc_info->v1.header.version_major)) { 1647 case 1: 1648 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se); 1649 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) + 1650 le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa)); 1651 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1652 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se); 1653 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c); 1654 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs); 1655 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds); 1656 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth); 1657 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth); 1658 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer); 1659 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size); 1660 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd); 1661 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu); 1662 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size); 1663 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) / 1664 le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1665 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc); 1666 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 1) { 1667 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v1_1.gc_num_tcp_per_sa); 1668 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v1_1.gc_num_sdp_interface); 1669 adev->gfx.config.gc_num_tcps = le32_to_cpu(gc_info->v1_1.gc_num_tcps); 1670 } 1671 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 2) { 1672 adev->gfx.config.gc_num_tcp_per_wpg = le32_to_cpu(gc_info->v1_2.gc_num_tcp_per_wpg); 1673 adev->gfx.config.gc_tcp_l1_size = le32_to_cpu(gc_info->v1_2.gc_tcp_l1_size); 1674 adev->gfx.config.gc_num_sqc_per_wgp = le32_to_cpu(gc_info->v1_2.gc_num_sqc_per_wgp); 1675 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_instruction_cache_size_per_sqc); 1676 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_data_cache_size_per_sqc); 1677 adev->gfx.config.gc_gl1c_per_sa = le32_to_cpu(gc_info->v1_2.gc_gl1c_per_sa); 1678 adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance); 1679 adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu); 1680 } 1681 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 3) { 1682 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v1_3.gc_tcp_size_per_cu); 1683 adev->gfx.config.gc_tcp_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcp_cache_line_size); 1684 adev->gfx.config.gc_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_size_per_sqc); 1685 adev->gfx.config.gc_instruction_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_line_size); 1686 adev->gfx.config.gc_scalar_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_size_per_sqc); 1687 adev->gfx.config.gc_scalar_data_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_line_size); 1688 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v1_3.gc_tcc_size); 1689 adev->gfx.config.gc_tcc_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcc_cache_line_size); 1690 } 1691 break; 1692 case 2: 1693 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se); 1694 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh); 1695 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1696 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se); 1697 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs); 1698 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs); 1699 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds); 1700 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth); 1701 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth); 1702 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer); 1703 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size); 1704 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd); 1705 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu); 1706 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size); 1707 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) / 1708 le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1709 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc); 1710 if (le16_to_cpu(gc_info->v2.header.version_minor) == 1) { 1711 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v2_1.gc_num_tcp_per_sh); 1712 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v2_1.gc_tcp_size_per_cu); 1713 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v2_1.gc_num_sdp_interface); /* per XCD */ 1714 adev->gfx.config.gc_num_cu_per_sqc = le32_to_cpu(gc_info->v2_1.gc_num_cu_per_sqc); 1715 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_instruction_cache_size_per_sqc); 1716 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_scalar_data_cache_size_per_sqc); 1717 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v2_1.gc_tcc_size); /* per XCD */ 1718 } 1719 break; 1720 default: 1721 dev_err(adev->dev, 1722 "Unhandled GC info table %d.%d\n", 1723 le16_to_cpu(gc_info->v1.header.version_major), 1724 le16_to_cpu(gc_info->v1.header.version_minor)); 1725 return -EINVAL; 1726 } 1727 return 0; 1728 } 1729 1730 union mall_info { 1731 struct mall_info_v1_0 v1; 1732 struct mall_info_v2_0 v2; 1733 }; 1734 1735 static int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev) 1736 { 1737 uint8_t *discovery_bin = adev->discovery.bin; 1738 struct binary_header *bhdr; 1739 union mall_info *mall_info; 1740 u32 u, mall_size_per_umc, m_s_present, half_use; 1741 u64 mall_size; 1742 u16 offset; 1743 1744 if (!discovery_bin) { 1745 DRM_ERROR("ip discovery uninitialized\n"); 1746 return -EINVAL; 1747 } 1748 1749 bhdr = (struct binary_header *)discovery_bin; 1750 offset = le16_to_cpu(bhdr->table_list[MALL_INFO].offset); 1751 1752 if (!offset) 1753 return 0; 1754 1755 mall_info = (union mall_info *)(discovery_bin + offset); 1756 1757 switch (le16_to_cpu(mall_info->v1.header.version_major)) { 1758 case 1: 1759 mall_size = 0; 1760 mall_size_per_umc = le32_to_cpu(mall_info->v1.mall_size_per_m); 1761 m_s_present = le32_to_cpu(mall_info->v1.m_s_present); 1762 half_use = le32_to_cpu(mall_info->v1.m_half_use); 1763 for (u = 0; u < adev->gmc.num_umc; u++) { 1764 if (m_s_present & (1 << u)) 1765 mall_size += mall_size_per_umc * 2; 1766 else if (half_use & (1 << u)) 1767 mall_size += mall_size_per_umc / 2; 1768 else 1769 mall_size += mall_size_per_umc; 1770 } 1771 adev->gmc.mall_size = mall_size; 1772 adev->gmc.m_half_use = half_use; 1773 break; 1774 case 2: 1775 mall_size_per_umc = le32_to_cpu(mall_info->v2.mall_size_per_umc); 1776 adev->gmc.mall_size = (uint64_t)mall_size_per_umc * adev->gmc.num_umc; 1777 break; 1778 default: 1779 dev_err(adev->dev, 1780 "Unhandled MALL info table %d.%d\n", 1781 le16_to_cpu(mall_info->v1.header.version_major), 1782 le16_to_cpu(mall_info->v1.header.version_minor)); 1783 return -EINVAL; 1784 } 1785 return 0; 1786 } 1787 1788 union vcn_info { 1789 struct vcn_info_v1_0 v1; 1790 }; 1791 1792 static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev) 1793 { 1794 uint8_t *discovery_bin = adev->discovery.bin; 1795 struct binary_header *bhdr; 1796 union vcn_info *vcn_info; 1797 u16 offset; 1798 int v; 1799 1800 if (!discovery_bin) { 1801 DRM_ERROR("ip discovery uninitialized\n"); 1802 return -EINVAL; 1803 } 1804 1805 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES 1806 * which is smaller than VCN_INFO_TABLE_MAX_NUM_INSTANCES 1807 * but that may change in the future with new GPUs so keep this 1808 * check for defensive purposes. 1809 */ 1810 if (adev->vcn.num_vcn_inst > VCN_INFO_TABLE_MAX_NUM_INSTANCES) { 1811 dev_err(adev->dev, "invalid vcn instances\n"); 1812 return -EINVAL; 1813 } 1814 1815 bhdr = (struct binary_header *)discovery_bin; 1816 offset = le16_to_cpu(bhdr->table_list[VCN_INFO].offset); 1817 1818 if (!offset) 1819 return 0; 1820 1821 vcn_info = (union vcn_info *)(discovery_bin + offset); 1822 1823 switch (le16_to_cpu(vcn_info->v1.header.version_major)) { 1824 case 1: 1825 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES 1826 * so this won't overflow. 1827 */ 1828 for (v = 0; v < adev->vcn.num_vcn_inst; v++) { 1829 adev->vcn.inst[v].vcn_codec_disable_mask = 1830 le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits); 1831 } 1832 break; 1833 default: 1834 dev_err(adev->dev, 1835 "Unhandled VCN info table %d.%d\n", 1836 le16_to_cpu(vcn_info->v1.header.version_major), 1837 le16_to_cpu(vcn_info->v1.header.version_minor)); 1838 return -EINVAL; 1839 } 1840 return 0; 1841 } 1842 1843 union nps_info { 1844 struct nps_info_v1_0 v1; 1845 }; 1846 1847 static int amdgpu_discovery_refresh_nps_info(struct amdgpu_device *adev, 1848 union nps_info *nps_data) 1849 { 1850 uint64_t vram_size, pos, offset; 1851 struct nps_info_header *nhdr; 1852 struct binary_header bhdr; 1853 uint16_t checksum; 1854 1855 vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20; 1856 pos = vram_size - DISCOVERY_TMR_OFFSET; 1857 amdgpu_device_vram_access(adev, pos, &bhdr, sizeof(bhdr), false); 1858 1859 offset = le16_to_cpu(bhdr.table_list[NPS_INFO].offset); 1860 checksum = le16_to_cpu(bhdr.table_list[NPS_INFO].checksum); 1861 1862 amdgpu_device_vram_access(adev, (pos + offset), nps_data, 1863 sizeof(*nps_data), false); 1864 1865 nhdr = (struct nps_info_header *)(nps_data); 1866 if (!amdgpu_discovery_verify_checksum((uint8_t *)nps_data, 1867 le32_to_cpu(nhdr->size_bytes), 1868 checksum)) { 1869 dev_err(adev->dev, "nps data refresh, checksum mismatch\n"); 1870 return -EINVAL; 1871 } 1872 1873 return 0; 1874 } 1875 1876 int amdgpu_discovery_get_nps_info(struct amdgpu_device *adev, 1877 uint32_t *nps_type, 1878 struct amdgpu_gmc_memrange **ranges, 1879 int *range_cnt, bool refresh) 1880 { 1881 uint8_t *discovery_bin = adev->discovery.bin; 1882 struct amdgpu_gmc_memrange *mem_ranges; 1883 struct binary_header *bhdr; 1884 union nps_info *nps_info; 1885 union nps_info nps_data; 1886 u16 offset; 1887 int i, r; 1888 1889 if (!nps_type || !range_cnt || !ranges) 1890 return -EINVAL; 1891 1892 if (refresh) { 1893 r = amdgpu_discovery_refresh_nps_info(adev, &nps_data); 1894 if (r) 1895 return r; 1896 nps_info = &nps_data; 1897 } else { 1898 if (!discovery_bin) { 1899 dev_err(adev->dev, 1900 "fetch mem range failed, ip discovery uninitialized\n"); 1901 return -EINVAL; 1902 } 1903 1904 bhdr = (struct binary_header *)discovery_bin; 1905 offset = le16_to_cpu(bhdr->table_list[NPS_INFO].offset); 1906 1907 if (!offset) 1908 return -ENOENT; 1909 1910 /* If verification fails, return as if NPS table doesn't exist */ 1911 if (amdgpu_discovery_verify_npsinfo(adev, bhdr)) 1912 return -ENOENT; 1913 1914 nps_info = (union nps_info *)(discovery_bin + offset); 1915 } 1916 1917 switch (le16_to_cpu(nps_info->v1.header.version_major)) { 1918 case 1: 1919 mem_ranges = kvcalloc(nps_info->v1.count, 1920 sizeof(*mem_ranges), 1921 GFP_KERNEL); 1922 if (!mem_ranges) 1923 return -ENOMEM; 1924 *nps_type = nps_info->v1.nps_type; 1925 *range_cnt = nps_info->v1.count; 1926 for (i = 0; i < *range_cnt; i++) { 1927 mem_ranges[i].base_address = 1928 nps_info->v1.instance_info[i].base_address; 1929 mem_ranges[i].limit_address = 1930 nps_info->v1.instance_info[i].limit_address; 1931 mem_ranges[i].nid_mask = -1; 1932 mem_ranges[i].flags = 0; 1933 } 1934 *ranges = mem_ranges; 1935 break; 1936 default: 1937 dev_err(adev->dev, "Unhandled NPS info table %d.%d\n", 1938 le16_to_cpu(nps_info->v1.header.version_major), 1939 le16_to_cpu(nps_info->v1.header.version_minor)); 1940 return -EINVAL; 1941 } 1942 1943 return 0; 1944 } 1945 1946 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev) 1947 { 1948 /* what IP to use for this? */ 1949 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1950 case IP_VERSION(9, 0, 1): 1951 case IP_VERSION(9, 1, 0): 1952 case IP_VERSION(9, 2, 1): 1953 case IP_VERSION(9, 2, 2): 1954 case IP_VERSION(9, 3, 0): 1955 case IP_VERSION(9, 4, 0): 1956 case IP_VERSION(9, 4, 1): 1957 case IP_VERSION(9, 4, 2): 1958 case IP_VERSION(9, 4, 3): 1959 case IP_VERSION(9, 4, 4): 1960 case IP_VERSION(9, 5, 0): 1961 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 1962 break; 1963 case IP_VERSION(10, 1, 10): 1964 case IP_VERSION(10, 1, 1): 1965 case IP_VERSION(10, 1, 2): 1966 case IP_VERSION(10, 1, 3): 1967 case IP_VERSION(10, 1, 4): 1968 case IP_VERSION(10, 3, 0): 1969 case IP_VERSION(10, 3, 1): 1970 case IP_VERSION(10, 3, 2): 1971 case IP_VERSION(10, 3, 3): 1972 case IP_VERSION(10, 3, 4): 1973 case IP_VERSION(10, 3, 5): 1974 case IP_VERSION(10, 3, 6): 1975 case IP_VERSION(10, 3, 7): 1976 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 1977 break; 1978 case IP_VERSION(11, 0, 0): 1979 case IP_VERSION(11, 0, 1): 1980 case IP_VERSION(11, 0, 2): 1981 case IP_VERSION(11, 0, 3): 1982 case IP_VERSION(11, 0, 4): 1983 case IP_VERSION(11, 5, 0): 1984 case IP_VERSION(11, 5, 1): 1985 case IP_VERSION(11, 5, 2): 1986 case IP_VERSION(11, 5, 3): 1987 amdgpu_device_ip_block_add(adev, &soc21_common_ip_block); 1988 break; 1989 case IP_VERSION(12, 0, 0): 1990 case IP_VERSION(12, 0, 1): 1991 amdgpu_device_ip_block_add(adev, &soc24_common_ip_block); 1992 break; 1993 default: 1994 dev_err(adev->dev, 1995 "Failed to add common ip block(GC_HWIP:0x%x)\n", 1996 amdgpu_ip_version(adev, GC_HWIP, 0)); 1997 return -EINVAL; 1998 } 1999 return 0; 2000 } 2001 2002 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev) 2003 { 2004 /* use GC or MMHUB IP version */ 2005 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2006 case IP_VERSION(9, 0, 1): 2007 case IP_VERSION(9, 1, 0): 2008 case IP_VERSION(9, 2, 1): 2009 case IP_VERSION(9, 2, 2): 2010 case IP_VERSION(9, 3, 0): 2011 case IP_VERSION(9, 4, 0): 2012 case IP_VERSION(9, 4, 1): 2013 case IP_VERSION(9, 4, 2): 2014 case IP_VERSION(9, 4, 3): 2015 case IP_VERSION(9, 4, 4): 2016 case IP_VERSION(9, 5, 0): 2017 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 2018 break; 2019 case IP_VERSION(10, 1, 10): 2020 case IP_VERSION(10, 1, 1): 2021 case IP_VERSION(10, 1, 2): 2022 case IP_VERSION(10, 1, 3): 2023 case IP_VERSION(10, 1, 4): 2024 case IP_VERSION(10, 3, 0): 2025 case IP_VERSION(10, 3, 1): 2026 case IP_VERSION(10, 3, 2): 2027 case IP_VERSION(10, 3, 3): 2028 case IP_VERSION(10, 3, 4): 2029 case IP_VERSION(10, 3, 5): 2030 case IP_VERSION(10, 3, 6): 2031 case IP_VERSION(10, 3, 7): 2032 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 2033 break; 2034 case IP_VERSION(11, 0, 0): 2035 case IP_VERSION(11, 0, 1): 2036 case IP_VERSION(11, 0, 2): 2037 case IP_VERSION(11, 0, 3): 2038 case IP_VERSION(11, 0, 4): 2039 case IP_VERSION(11, 5, 0): 2040 case IP_VERSION(11, 5, 1): 2041 case IP_VERSION(11, 5, 2): 2042 case IP_VERSION(11, 5, 3): 2043 amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block); 2044 break; 2045 case IP_VERSION(12, 0, 0): 2046 case IP_VERSION(12, 0, 1): 2047 case IP_VERSION(12, 1, 0): 2048 amdgpu_device_ip_block_add(adev, &gmc_v12_0_ip_block); 2049 break; 2050 default: 2051 dev_err(adev->dev, "Failed to add gmc ip block(GC_HWIP:0x%x)\n", 2052 amdgpu_ip_version(adev, GC_HWIP, 0)); 2053 return -EINVAL; 2054 } 2055 return 0; 2056 } 2057 2058 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev) 2059 { 2060 switch (amdgpu_ip_version(adev, OSSSYS_HWIP, 0)) { 2061 case IP_VERSION(4, 0, 0): 2062 case IP_VERSION(4, 0, 1): 2063 case IP_VERSION(4, 1, 0): 2064 case IP_VERSION(4, 1, 1): 2065 case IP_VERSION(4, 3, 0): 2066 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 2067 break; 2068 case IP_VERSION(4, 2, 0): 2069 case IP_VERSION(4, 2, 1): 2070 case IP_VERSION(4, 4, 0): 2071 case IP_VERSION(4, 4, 2): 2072 case IP_VERSION(4, 4, 5): 2073 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 2074 break; 2075 case IP_VERSION(5, 0, 0): 2076 case IP_VERSION(5, 0, 1): 2077 case IP_VERSION(5, 0, 2): 2078 case IP_VERSION(5, 0, 3): 2079 case IP_VERSION(5, 2, 0): 2080 case IP_VERSION(5, 2, 1): 2081 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 2082 break; 2083 case IP_VERSION(6, 0, 0): 2084 case IP_VERSION(6, 0, 1): 2085 case IP_VERSION(6, 0, 2): 2086 amdgpu_device_ip_block_add(adev, &ih_v6_0_ip_block); 2087 break; 2088 case IP_VERSION(6, 1, 0): 2089 amdgpu_device_ip_block_add(adev, &ih_v6_1_ip_block); 2090 break; 2091 case IP_VERSION(7, 0, 0): 2092 case IP_VERSION(7, 1, 0): 2093 amdgpu_device_ip_block_add(adev, &ih_v7_0_ip_block); 2094 break; 2095 default: 2096 dev_err(adev->dev, 2097 "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n", 2098 amdgpu_ip_version(adev, OSSSYS_HWIP, 0)); 2099 return -EINVAL; 2100 } 2101 return 0; 2102 } 2103 2104 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev) 2105 { 2106 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 2107 case IP_VERSION(9, 0, 0): 2108 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 2109 break; 2110 case IP_VERSION(10, 0, 0): 2111 case IP_VERSION(10, 0, 1): 2112 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); 2113 break; 2114 case IP_VERSION(11, 0, 0): 2115 case IP_VERSION(11, 0, 2): 2116 case IP_VERSION(11, 0, 4): 2117 case IP_VERSION(11, 0, 5): 2118 case IP_VERSION(11, 0, 9): 2119 case IP_VERSION(11, 0, 7): 2120 case IP_VERSION(11, 0, 11): 2121 case IP_VERSION(11, 0, 12): 2122 case IP_VERSION(11, 0, 13): 2123 case IP_VERSION(11, 5, 0): 2124 case IP_VERSION(11, 5, 2): 2125 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 2126 break; 2127 case IP_VERSION(11, 0, 8): 2128 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block); 2129 break; 2130 case IP_VERSION(11, 0, 3): 2131 case IP_VERSION(12, 0, 1): 2132 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); 2133 break; 2134 case IP_VERSION(13, 0, 0): 2135 case IP_VERSION(13, 0, 1): 2136 case IP_VERSION(13, 0, 2): 2137 case IP_VERSION(13, 0, 3): 2138 case IP_VERSION(13, 0, 5): 2139 case IP_VERSION(13, 0, 6): 2140 case IP_VERSION(13, 0, 7): 2141 case IP_VERSION(13, 0, 8): 2142 case IP_VERSION(13, 0, 10): 2143 case IP_VERSION(13, 0, 11): 2144 case IP_VERSION(13, 0, 12): 2145 case IP_VERSION(13, 0, 14): 2146 case IP_VERSION(14, 0, 0): 2147 case IP_VERSION(14, 0, 1): 2148 case IP_VERSION(14, 0, 4): 2149 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); 2150 break; 2151 case IP_VERSION(13, 0, 4): 2152 amdgpu_device_ip_block_add(adev, &psp_v13_0_4_ip_block); 2153 break; 2154 case IP_VERSION(14, 0, 2): 2155 case IP_VERSION(14, 0, 3): 2156 case IP_VERSION(14, 0, 5): 2157 amdgpu_device_ip_block_add(adev, &psp_v14_0_ip_block); 2158 break; 2159 case IP_VERSION(15, 0, 8): 2160 amdgpu_device_ip_block_add(adev, &psp_v15_0_8_ip_block); 2161 break; 2162 default: 2163 dev_err(adev->dev, 2164 "Failed to add psp ip block(MP0_HWIP:0x%x)\n", 2165 amdgpu_ip_version(adev, MP0_HWIP, 0)); 2166 return -EINVAL; 2167 } 2168 return 0; 2169 } 2170 2171 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev) 2172 { 2173 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2174 case IP_VERSION(9, 0, 0): 2175 case IP_VERSION(10, 0, 0): 2176 case IP_VERSION(10, 0, 1): 2177 case IP_VERSION(11, 0, 2): 2178 if (adev->asic_type == CHIP_ARCTURUS) 2179 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 2180 else 2181 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 2182 break; 2183 case IP_VERSION(11, 0, 0): 2184 case IP_VERSION(11, 0, 5): 2185 case IP_VERSION(11, 0, 9): 2186 case IP_VERSION(11, 0, 7): 2187 case IP_VERSION(11, 0, 11): 2188 case IP_VERSION(11, 0, 12): 2189 case IP_VERSION(11, 0, 13): 2190 case IP_VERSION(11, 5, 0): 2191 case IP_VERSION(11, 5, 2): 2192 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 2193 break; 2194 case IP_VERSION(11, 0, 8): 2195 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) 2196 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 2197 break; 2198 case IP_VERSION(12, 0, 0): 2199 case IP_VERSION(12, 0, 1): 2200 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); 2201 break; 2202 case IP_VERSION(13, 0, 0): 2203 case IP_VERSION(13, 0, 1): 2204 case IP_VERSION(13, 0, 2): 2205 case IP_VERSION(13, 0, 3): 2206 case IP_VERSION(13, 0, 4): 2207 case IP_VERSION(13, 0, 5): 2208 case IP_VERSION(13, 0, 6): 2209 case IP_VERSION(13, 0, 7): 2210 case IP_VERSION(13, 0, 8): 2211 case IP_VERSION(13, 0, 10): 2212 case IP_VERSION(13, 0, 11): 2213 case IP_VERSION(13, 0, 14): 2214 case IP_VERSION(13, 0, 12): 2215 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); 2216 break; 2217 case IP_VERSION(14, 0, 0): 2218 case IP_VERSION(14, 0, 1): 2219 case IP_VERSION(14, 0, 2): 2220 case IP_VERSION(14, 0, 3): 2221 case IP_VERSION(14, 0, 4): 2222 case IP_VERSION(14, 0, 5): 2223 amdgpu_device_ip_block_add(adev, &smu_v14_0_ip_block); 2224 break; 2225 default: 2226 dev_err(adev->dev, 2227 "Failed to add smu ip block(MP1_HWIP:0x%x)\n", 2228 amdgpu_ip_version(adev, MP1_HWIP, 0)); 2229 return -EINVAL; 2230 } 2231 return 0; 2232 } 2233 2234 #if defined(CONFIG_DRM_AMD_DC) 2235 static void amdgpu_discovery_set_sriov_display(struct amdgpu_device *adev) 2236 { 2237 amdgpu_device_set_sriov_virtual_display(adev); 2238 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2239 } 2240 #endif 2241 2242 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev) 2243 { 2244 if (adev->enable_virtual_display) { 2245 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2246 return 0; 2247 } 2248 2249 if (!amdgpu_device_has_dc_support(adev)) 2250 return 0; 2251 2252 #if defined(CONFIG_DRM_AMD_DC) 2253 if (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2254 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2255 case IP_VERSION(1, 0, 0): 2256 case IP_VERSION(1, 0, 1): 2257 case IP_VERSION(2, 0, 2): 2258 case IP_VERSION(2, 0, 0): 2259 case IP_VERSION(2, 0, 3): 2260 case IP_VERSION(2, 1, 0): 2261 case IP_VERSION(3, 0, 0): 2262 case IP_VERSION(3, 0, 2): 2263 case IP_VERSION(3, 0, 3): 2264 case IP_VERSION(3, 0, 1): 2265 case IP_VERSION(3, 1, 2): 2266 case IP_VERSION(3, 1, 3): 2267 case IP_VERSION(3, 1, 4): 2268 case IP_VERSION(3, 1, 5): 2269 case IP_VERSION(3, 1, 6): 2270 case IP_VERSION(3, 2, 0): 2271 case IP_VERSION(3, 2, 1): 2272 case IP_VERSION(3, 5, 0): 2273 case IP_VERSION(3, 5, 1): 2274 case IP_VERSION(3, 6, 0): 2275 case IP_VERSION(4, 1, 0): 2276 /* TODO: Fix IP version. DC code expects version 4.0.1 */ 2277 if (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(4, 1, 0)) 2278 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(4, 0, 1); 2279 2280 if (amdgpu_sriov_vf(adev)) 2281 amdgpu_discovery_set_sriov_display(adev); 2282 else 2283 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2284 break; 2285 default: 2286 dev_err(adev->dev, 2287 "Failed to add dm ip block(DCE_HWIP:0x%x)\n", 2288 amdgpu_ip_version(adev, DCE_HWIP, 0)); 2289 return -EINVAL; 2290 } 2291 } else if (amdgpu_ip_version(adev, DCI_HWIP, 0)) { 2292 switch (amdgpu_ip_version(adev, DCI_HWIP, 0)) { 2293 case IP_VERSION(12, 0, 0): 2294 case IP_VERSION(12, 0, 1): 2295 case IP_VERSION(12, 1, 0): 2296 if (amdgpu_sriov_vf(adev)) 2297 amdgpu_discovery_set_sriov_display(adev); 2298 else 2299 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2300 break; 2301 default: 2302 dev_err(adev->dev, 2303 "Failed to add dm ip block(DCI_HWIP:0x%x)\n", 2304 amdgpu_ip_version(adev, DCI_HWIP, 0)); 2305 return -EINVAL; 2306 } 2307 } 2308 #endif 2309 return 0; 2310 } 2311 2312 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) 2313 { 2314 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2315 case IP_VERSION(9, 0, 1): 2316 case IP_VERSION(9, 1, 0): 2317 case IP_VERSION(9, 2, 1): 2318 case IP_VERSION(9, 2, 2): 2319 case IP_VERSION(9, 3, 0): 2320 case IP_VERSION(9, 4, 0): 2321 case IP_VERSION(9, 4, 1): 2322 case IP_VERSION(9, 4, 2): 2323 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 2324 break; 2325 case IP_VERSION(9, 4, 3): 2326 case IP_VERSION(9, 4, 4): 2327 case IP_VERSION(9, 5, 0): 2328 amdgpu_device_ip_block_add(adev, &gfx_v9_4_3_ip_block); 2329 break; 2330 case IP_VERSION(10, 1, 10): 2331 case IP_VERSION(10, 1, 2): 2332 case IP_VERSION(10, 1, 1): 2333 case IP_VERSION(10, 1, 3): 2334 case IP_VERSION(10, 1, 4): 2335 case IP_VERSION(10, 3, 0): 2336 case IP_VERSION(10, 3, 2): 2337 case IP_VERSION(10, 3, 1): 2338 case IP_VERSION(10, 3, 4): 2339 case IP_VERSION(10, 3, 5): 2340 case IP_VERSION(10, 3, 6): 2341 case IP_VERSION(10, 3, 3): 2342 case IP_VERSION(10, 3, 7): 2343 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 2344 break; 2345 case IP_VERSION(11, 0, 0): 2346 case IP_VERSION(11, 0, 1): 2347 case IP_VERSION(11, 0, 2): 2348 case IP_VERSION(11, 0, 3): 2349 case IP_VERSION(11, 0, 4): 2350 case IP_VERSION(11, 5, 0): 2351 case IP_VERSION(11, 5, 1): 2352 case IP_VERSION(11, 5, 2): 2353 case IP_VERSION(11, 5, 3): 2354 amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block); 2355 break; 2356 case IP_VERSION(12, 0, 0): 2357 case IP_VERSION(12, 0, 1): 2358 amdgpu_device_ip_block_add(adev, &gfx_v12_0_ip_block); 2359 break; 2360 default: 2361 dev_err(adev->dev, "Failed to add gfx ip block(GC_HWIP:0x%x)\n", 2362 amdgpu_ip_version(adev, GC_HWIP, 0)); 2363 return -EINVAL; 2364 } 2365 return 0; 2366 } 2367 2368 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev) 2369 { 2370 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 2371 case IP_VERSION(4, 0, 0): 2372 case IP_VERSION(4, 0, 1): 2373 case IP_VERSION(4, 1, 0): 2374 case IP_VERSION(4, 1, 1): 2375 case IP_VERSION(4, 1, 2): 2376 case IP_VERSION(4, 2, 0): 2377 case IP_VERSION(4, 2, 2): 2378 case IP_VERSION(4, 4, 0): 2379 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 2380 break; 2381 case IP_VERSION(4, 4, 2): 2382 case IP_VERSION(4, 4, 5): 2383 case IP_VERSION(4, 4, 4): 2384 amdgpu_device_ip_block_add(adev, &sdma_v4_4_2_ip_block); 2385 break; 2386 case IP_VERSION(5, 0, 0): 2387 case IP_VERSION(5, 0, 1): 2388 case IP_VERSION(5, 0, 2): 2389 case IP_VERSION(5, 0, 5): 2390 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 2391 break; 2392 case IP_VERSION(5, 2, 0): 2393 case IP_VERSION(5, 2, 2): 2394 case IP_VERSION(5, 2, 4): 2395 case IP_VERSION(5, 2, 5): 2396 case IP_VERSION(5, 2, 6): 2397 case IP_VERSION(5, 2, 3): 2398 case IP_VERSION(5, 2, 1): 2399 case IP_VERSION(5, 2, 7): 2400 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 2401 break; 2402 case IP_VERSION(6, 0, 0): 2403 case IP_VERSION(6, 0, 1): 2404 case IP_VERSION(6, 0, 2): 2405 case IP_VERSION(6, 0, 3): 2406 case IP_VERSION(6, 1, 0): 2407 case IP_VERSION(6, 1, 1): 2408 case IP_VERSION(6, 1, 2): 2409 case IP_VERSION(6, 1, 3): 2410 amdgpu_device_ip_block_add(adev, &sdma_v6_0_ip_block); 2411 break; 2412 case IP_VERSION(7, 0, 0): 2413 case IP_VERSION(7, 0, 1): 2414 amdgpu_device_ip_block_add(adev, &sdma_v7_0_ip_block); 2415 break; 2416 default: 2417 dev_err(adev->dev, 2418 "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n", 2419 amdgpu_ip_version(adev, SDMA0_HWIP, 0)); 2420 return -EINVAL; 2421 } 2422 2423 return 0; 2424 } 2425 2426 static int amdgpu_discovery_set_ras_ip_blocks(struct amdgpu_device *adev) 2427 { 2428 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 2429 case IP_VERSION(13, 0, 6): 2430 case IP_VERSION(13, 0, 12): 2431 case IP_VERSION(13, 0, 14): 2432 amdgpu_device_ip_block_add(adev, &ras_v1_0_ip_block); 2433 break; 2434 default: 2435 break; 2436 } 2437 return 0; 2438 } 2439 2440 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) 2441 { 2442 if (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 2443 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 2444 case IP_VERSION(7, 0, 0): 2445 case IP_VERSION(7, 2, 0): 2446 /* UVD is not supported on vega20 SR-IOV */ 2447 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 2448 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); 2449 break; 2450 default: 2451 dev_err(adev->dev, 2452 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n", 2453 amdgpu_ip_version(adev, UVD_HWIP, 0)); 2454 return -EINVAL; 2455 } 2456 switch (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 2457 case IP_VERSION(4, 0, 0): 2458 case IP_VERSION(4, 1, 0): 2459 /* VCE is not supported on vega20 SR-IOV */ 2460 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 2461 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); 2462 break; 2463 default: 2464 dev_err(adev->dev, 2465 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n", 2466 amdgpu_ip_version(adev, VCE_HWIP, 0)); 2467 return -EINVAL; 2468 } 2469 } else { 2470 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 2471 case IP_VERSION(1, 0, 0): 2472 case IP_VERSION(1, 0, 1): 2473 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); 2474 break; 2475 case IP_VERSION(2, 0, 0): 2476 case IP_VERSION(2, 0, 2): 2477 case IP_VERSION(2, 2, 0): 2478 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 2479 if (!amdgpu_sriov_vf(adev)) 2480 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 2481 break; 2482 case IP_VERSION(2, 0, 3): 2483 break; 2484 case IP_VERSION(2, 5, 0): 2485 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 2486 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block); 2487 break; 2488 case IP_VERSION(2, 6, 0): 2489 amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block); 2490 amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block); 2491 break; 2492 case IP_VERSION(3, 0, 0): 2493 case IP_VERSION(3, 0, 16): 2494 case IP_VERSION(3, 1, 1): 2495 case IP_VERSION(3, 1, 2): 2496 case IP_VERSION(3, 0, 2): 2497 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 2498 if (!amdgpu_sriov_vf(adev)) 2499 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 2500 break; 2501 case IP_VERSION(3, 0, 33): 2502 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 2503 break; 2504 case IP_VERSION(4, 0, 0): 2505 case IP_VERSION(4, 0, 2): 2506 case IP_VERSION(4, 0, 4): 2507 amdgpu_device_ip_block_add(adev, &vcn_v4_0_ip_block); 2508 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block); 2509 break; 2510 case IP_VERSION(4, 0, 3): 2511 amdgpu_device_ip_block_add(adev, &vcn_v4_0_3_ip_block); 2512 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_3_ip_block); 2513 break; 2514 case IP_VERSION(4, 0, 5): 2515 case IP_VERSION(4, 0, 6): 2516 amdgpu_device_ip_block_add(adev, &vcn_v4_0_5_ip_block); 2517 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_5_ip_block); 2518 break; 2519 case IP_VERSION(5, 0, 0): 2520 amdgpu_device_ip_block_add(adev, &vcn_v5_0_0_ip_block); 2521 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_0_ip_block); 2522 break; 2523 case IP_VERSION(5, 0, 1): 2524 amdgpu_device_ip_block_add(adev, &vcn_v5_0_1_ip_block); 2525 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_1_ip_block); 2526 break; 2527 default: 2528 dev_err(adev->dev, 2529 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n", 2530 amdgpu_ip_version(adev, UVD_HWIP, 0)); 2531 return -EINVAL; 2532 } 2533 } 2534 return 0; 2535 } 2536 2537 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev) 2538 { 2539 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2540 case IP_VERSION(11, 0, 0): 2541 case IP_VERSION(11, 0, 1): 2542 case IP_VERSION(11, 0, 2): 2543 case IP_VERSION(11, 0, 3): 2544 case IP_VERSION(11, 0, 4): 2545 case IP_VERSION(11, 5, 0): 2546 case IP_VERSION(11, 5, 1): 2547 case IP_VERSION(11, 5, 2): 2548 case IP_VERSION(11, 5, 3): 2549 amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block); 2550 adev->enable_mes = true; 2551 adev->enable_mes_kiq = true; 2552 break; 2553 case IP_VERSION(12, 0, 0): 2554 case IP_VERSION(12, 0, 1): 2555 amdgpu_device_ip_block_add(adev, &mes_v12_0_ip_block); 2556 adev->enable_mes = true; 2557 adev->enable_mes_kiq = true; 2558 if (amdgpu_uni_mes) 2559 adev->enable_uni_mes = true; 2560 break; 2561 default: 2562 break; 2563 } 2564 return 0; 2565 } 2566 2567 static void amdgpu_discovery_init_soc_config(struct amdgpu_device *adev) 2568 { 2569 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2570 case IP_VERSION(9, 4, 3): 2571 case IP_VERSION(9, 4, 4): 2572 case IP_VERSION(9, 5, 0): 2573 aqua_vanjaram_init_soc_config(adev); 2574 break; 2575 default: 2576 break; 2577 } 2578 } 2579 2580 static int amdgpu_discovery_set_vpe_ip_blocks(struct amdgpu_device *adev) 2581 { 2582 switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) { 2583 case IP_VERSION(6, 1, 0): 2584 case IP_VERSION(6, 1, 1): 2585 case IP_VERSION(6, 1, 3): 2586 amdgpu_device_ip_block_add(adev, &vpe_v6_1_ip_block); 2587 break; 2588 default: 2589 break; 2590 } 2591 2592 return 0; 2593 } 2594 2595 static int amdgpu_discovery_set_umsch_mm_ip_blocks(struct amdgpu_device *adev) 2596 { 2597 switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) { 2598 case IP_VERSION(4, 0, 5): 2599 case IP_VERSION(4, 0, 6): 2600 if (amdgpu_umsch_mm & 0x1) { 2601 amdgpu_device_ip_block_add(adev, &umsch_mm_v4_0_ip_block); 2602 adev->enable_umsch_mm = true; 2603 } 2604 break; 2605 default: 2606 break; 2607 } 2608 2609 return 0; 2610 } 2611 2612 static int amdgpu_discovery_set_isp_ip_blocks(struct amdgpu_device *adev) 2613 { 2614 #if defined(CONFIG_DRM_AMD_ISP) 2615 switch (amdgpu_ip_version(adev, ISP_HWIP, 0)) { 2616 case IP_VERSION(4, 1, 0): 2617 amdgpu_device_ip_block_add(adev, &isp_v4_1_0_ip_block); 2618 break; 2619 case IP_VERSION(4, 1, 1): 2620 amdgpu_device_ip_block_add(adev, &isp_v4_1_1_ip_block); 2621 break; 2622 default: 2623 break; 2624 } 2625 #endif 2626 2627 return 0; 2628 } 2629 2630 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 2631 { 2632 int r; 2633 2634 switch (adev->asic_type) { 2635 case CHIP_VEGA10: 2636 /* This is not fatal. We only need the discovery 2637 * binary for sysfs. We don't need it for a 2638 * functional system. 2639 */ 2640 amdgpu_discovery_init(adev); 2641 vega10_reg_base_init(adev); 2642 adev->sdma.num_instances = 2; 2643 adev->sdma.sdma_mask = 3; 2644 adev->gmc.num_umc = 4; 2645 adev->gfx.xcc_mask = 1; 2646 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0); 2647 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0); 2648 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0); 2649 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0); 2650 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0); 2651 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0); 2652 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 2653 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0); 2654 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0); 2655 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 2656 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 2657 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 2658 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0); 2659 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1); 2660 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 2661 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 2662 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0); 2663 break; 2664 case CHIP_VEGA12: 2665 /* This is not fatal. We only need the discovery 2666 * binary for sysfs. We don't need it for a 2667 * functional system. 2668 */ 2669 amdgpu_discovery_init(adev); 2670 vega10_reg_base_init(adev); 2671 adev->sdma.num_instances = 2; 2672 adev->sdma.sdma_mask = 3; 2673 adev->gmc.num_umc = 4; 2674 adev->gfx.xcc_mask = 1; 2675 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0); 2676 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0); 2677 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1); 2678 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1); 2679 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1); 2680 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1); 2681 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0); 2682 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0); 2683 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0); 2684 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 2685 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 2686 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 2687 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1); 2688 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1); 2689 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 2690 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 2691 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1); 2692 break; 2693 case CHIP_RAVEN: 2694 /* This is not fatal. We only need the discovery 2695 * binary for sysfs. We don't need it for a 2696 * functional system. 2697 */ 2698 amdgpu_discovery_init(adev); 2699 vega10_reg_base_init(adev); 2700 adev->sdma.num_instances = 1; 2701 adev->sdma.sdma_mask = 1; 2702 adev->vcn.num_vcn_inst = 1; 2703 adev->gmc.num_umc = 2; 2704 adev->gfx.xcc_mask = 1; 2705 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { 2706 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0); 2707 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0); 2708 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1); 2709 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1); 2710 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1); 2711 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1); 2712 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1); 2713 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0); 2714 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1); 2715 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1); 2716 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0); 2717 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1); 2718 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2); 2719 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1); 2720 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1); 2721 adev->ip_versions[ISP_HWIP][0] = IP_VERSION(2, 0, 0); 2722 } else { 2723 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0); 2724 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0); 2725 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0); 2726 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0); 2727 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0); 2728 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 2729 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0); 2730 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0); 2731 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0); 2732 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0); 2733 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0); 2734 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0); 2735 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0); 2736 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0); 2737 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0); 2738 adev->ip_versions[ISP_HWIP][0] = IP_VERSION(2, 0, 0); 2739 } 2740 break; 2741 case CHIP_VEGA20: 2742 /* This is not fatal. We only need the discovery 2743 * binary for sysfs. We don't need it for a 2744 * functional system. 2745 */ 2746 amdgpu_discovery_init(adev); 2747 vega20_reg_base_init(adev); 2748 adev->sdma.num_instances = 2; 2749 adev->sdma.sdma_mask = 3; 2750 adev->gmc.num_umc = 8; 2751 adev->gfx.xcc_mask = 1; 2752 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2753 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2754 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0); 2755 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0); 2756 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0); 2757 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0); 2758 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0); 2759 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0); 2760 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1); 2761 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2); 2762 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2763 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2); 2764 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2); 2765 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0); 2766 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0); 2767 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0); 2768 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0); 2769 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0); 2770 break; 2771 case CHIP_ARCTURUS: 2772 /* This is not fatal. We only need the discovery 2773 * binary for sysfs. We don't need it for a 2774 * functional system. 2775 */ 2776 amdgpu_discovery_init(adev); 2777 arct_reg_base_init(adev); 2778 adev->sdma.num_instances = 8; 2779 adev->sdma.sdma_mask = 0xff; 2780 adev->vcn.num_vcn_inst = 2; 2781 adev->gmc.num_umc = 8; 2782 adev->gfx.xcc_mask = 1; 2783 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2784 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2785 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1); 2786 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1); 2787 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2); 2788 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2); 2789 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2); 2790 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2); 2791 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2); 2792 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2); 2793 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2); 2794 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2); 2795 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1); 2796 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1); 2797 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2); 2798 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4); 2799 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2800 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3); 2801 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3); 2802 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1); 2803 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0); 2804 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0); 2805 break; 2806 case CHIP_ALDEBARAN: 2807 /* This is not fatal. We only need the discovery 2808 * binary for sysfs. We don't need it for a 2809 * functional system. 2810 */ 2811 amdgpu_discovery_init(adev); 2812 aldebaran_reg_base_init(adev); 2813 adev->sdma.num_instances = 5; 2814 adev->sdma.sdma_mask = 0x1f; 2815 adev->vcn.num_vcn_inst = 2; 2816 adev->gmc.num_umc = 4; 2817 adev->gfx.xcc_mask = 1; 2818 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2819 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2820 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0); 2821 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0); 2822 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0); 2823 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0); 2824 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0); 2825 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0); 2826 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0); 2827 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2); 2828 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4); 2829 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0); 2830 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2); 2831 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2); 2832 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2); 2833 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2); 2834 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2); 2835 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0); 2836 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0); 2837 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0); 2838 break; 2839 case CHIP_CYAN_SKILLFISH: 2840 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 2841 r = amdgpu_discovery_reg_base_init(adev); 2842 if (r) 2843 return -EINVAL; 2844 2845 amdgpu_discovery_harvest_ip(adev); 2846 amdgpu_discovery_get_gfx_info(adev); 2847 amdgpu_discovery_get_mall_info(adev); 2848 amdgpu_discovery_get_vcn_info(adev); 2849 } else { 2850 cyan_skillfish_reg_base_init(adev); 2851 adev->sdma.num_instances = 2; 2852 adev->sdma.sdma_mask = 3; 2853 adev->gfx.xcc_mask = 1; 2854 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(2, 0, 3); 2855 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(2, 0, 3); 2856 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(5, 0, 1); 2857 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(5, 0, 1); 2858 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(5, 0, 1); 2859 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(5, 0, 1); 2860 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 5, 0); 2861 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(2, 1, 1); 2862 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(8, 1, 1); 2863 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 8); 2864 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 8); 2865 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 1); 2866 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 8); 2867 adev->ip_versions[GC_HWIP][0] = IP_VERSION(10, 1, 3); 2868 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 0, 3); 2869 } 2870 break; 2871 default: 2872 r = amdgpu_discovery_reg_base_init(adev); 2873 if (r) { 2874 drm_err(&adev->ddev, "discovery failed: %d\n", r); 2875 return r; 2876 } 2877 2878 amdgpu_discovery_harvest_ip(adev); 2879 amdgpu_discovery_get_gfx_info(adev); 2880 amdgpu_discovery_get_mall_info(adev); 2881 amdgpu_discovery_get_vcn_info(adev); 2882 break; 2883 } 2884 2885 amdgpu_discovery_init_soc_config(adev); 2886 amdgpu_discovery_sysfs_init(adev); 2887 2888 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2889 case IP_VERSION(9, 0, 1): 2890 case IP_VERSION(9, 2, 1): 2891 case IP_VERSION(9, 4, 0): 2892 case IP_VERSION(9, 4, 1): 2893 case IP_VERSION(9, 4, 2): 2894 case IP_VERSION(9, 4, 3): 2895 case IP_VERSION(9, 4, 4): 2896 case IP_VERSION(9, 5, 0): 2897 adev->family = AMDGPU_FAMILY_AI; 2898 break; 2899 case IP_VERSION(9, 1, 0): 2900 case IP_VERSION(9, 2, 2): 2901 case IP_VERSION(9, 3, 0): 2902 adev->family = AMDGPU_FAMILY_RV; 2903 break; 2904 case IP_VERSION(10, 1, 10): 2905 case IP_VERSION(10, 1, 1): 2906 case IP_VERSION(10, 1, 2): 2907 case IP_VERSION(10, 1, 3): 2908 case IP_VERSION(10, 1, 4): 2909 case IP_VERSION(10, 3, 0): 2910 case IP_VERSION(10, 3, 2): 2911 case IP_VERSION(10, 3, 4): 2912 case IP_VERSION(10, 3, 5): 2913 adev->family = AMDGPU_FAMILY_NV; 2914 break; 2915 case IP_VERSION(10, 3, 1): 2916 adev->family = AMDGPU_FAMILY_VGH; 2917 adev->apu_flags |= AMD_APU_IS_VANGOGH; 2918 break; 2919 case IP_VERSION(10, 3, 3): 2920 adev->family = AMDGPU_FAMILY_YC; 2921 break; 2922 case IP_VERSION(10, 3, 6): 2923 adev->family = AMDGPU_FAMILY_GC_10_3_6; 2924 break; 2925 case IP_VERSION(10, 3, 7): 2926 adev->family = AMDGPU_FAMILY_GC_10_3_7; 2927 break; 2928 case IP_VERSION(11, 0, 0): 2929 case IP_VERSION(11, 0, 2): 2930 case IP_VERSION(11, 0, 3): 2931 adev->family = AMDGPU_FAMILY_GC_11_0_0; 2932 break; 2933 case IP_VERSION(11, 0, 1): 2934 case IP_VERSION(11, 0, 4): 2935 adev->family = AMDGPU_FAMILY_GC_11_0_1; 2936 break; 2937 case IP_VERSION(11, 5, 0): 2938 case IP_VERSION(11, 5, 1): 2939 case IP_VERSION(11, 5, 2): 2940 case IP_VERSION(11, 5, 3): 2941 adev->family = AMDGPU_FAMILY_GC_11_5_0; 2942 break; 2943 case IP_VERSION(12, 0, 0): 2944 case IP_VERSION(12, 0, 1): 2945 adev->family = AMDGPU_FAMILY_GC_12_0_0; 2946 break; 2947 default: 2948 return -EINVAL; 2949 } 2950 2951 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2952 case IP_VERSION(9, 1, 0): 2953 case IP_VERSION(9, 2, 2): 2954 case IP_VERSION(9, 3, 0): 2955 case IP_VERSION(10, 1, 3): 2956 case IP_VERSION(10, 1, 4): 2957 case IP_VERSION(10, 3, 1): 2958 case IP_VERSION(10, 3, 3): 2959 case IP_VERSION(10, 3, 6): 2960 case IP_VERSION(10, 3, 7): 2961 case IP_VERSION(11, 0, 1): 2962 case IP_VERSION(11, 0, 4): 2963 case IP_VERSION(11, 5, 0): 2964 case IP_VERSION(11, 5, 1): 2965 case IP_VERSION(11, 5, 2): 2966 case IP_VERSION(11, 5, 3): 2967 adev->flags |= AMD_IS_APU; 2968 break; 2969 default: 2970 break; 2971 } 2972 2973 /* set NBIO version */ 2974 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { 2975 case IP_VERSION(6, 1, 0): 2976 case IP_VERSION(6, 2, 0): 2977 adev->nbio.funcs = &nbio_v6_1_funcs; 2978 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; 2979 break; 2980 case IP_VERSION(7, 0, 0): 2981 case IP_VERSION(7, 0, 1): 2982 case IP_VERSION(2, 5, 0): 2983 adev->nbio.funcs = &nbio_v7_0_funcs; 2984 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; 2985 break; 2986 case IP_VERSION(7, 4, 0): 2987 case IP_VERSION(7, 4, 1): 2988 case IP_VERSION(7, 4, 4): 2989 adev->nbio.funcs = &nbio_v7_4_funcs; 2990 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; 2991 break; 2992 case IP_VERSION(7, 9, 0): 2993 case IP_VERSION(7, 9, 1): 2994 adev->nbio.funcs = &nbio_v7_9_funcs; 2995 adev->nbio.hdp_flush_reg = &nbio_v7_9_hdp_flush_reg; 2996 break; 2997 case IP_VERSION(7, 11, 0): 2998 case IP_VERSION(7, 11, 1): 2999 case IP_VERSION(7, 11, 2): 3000 case IP_VERSION(7, 11, 3): 3001 adev->nbio.funcs = &nbio_v7_11_funcs; 3002 adev->nbio.hdp_flush_reg = &nbio_v7_11_hdp_flush_reg; 3003 break; 3004 case IP_VERSION(7, 2, 0): 3005 case IP_VERSION(7, 2, 1): 3006 case IP_VERSION(7, 3, 0): 3007 case IP_VERSION(7, 5, 0): 3008 case IP_VERSION(7, 5, 1): 3009 adev->nbio.funcs = &nbio_v7_2_funcs; 3010 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; 3011 break; 3012 case IP_VERSION(2, 1, 1): 3013 case IP_VERSION(2, 3, 0): 3014 case IP_VERSION(2, 3, 1): 3015 case IP_VERSION(2, 3, 2): 3016 case IP_VERSION(3, 3, 0): 3017 case IP_VERSION(3, 3, 1): 3018 case IP_VERSION(3, 3, 2): 3019 case IP_VERSION(3, 3, 3): 3020 adev->nbio.funcs = &nbio_v2_3_funcs; 3021 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 3022 break; 3023 case IP_VERSION(4, 3, 0): 3024 case IP_VERSION(4, 3, 1): 3025 if (amdgpu_sriov_vf(adev)) 3026 adev->nbio.funcs = &nbio_v4_3_sriov_funcs; 3027 else 3028 adev->nbio.funcs = &nbio_v4_3_funcs; 3029 adev->nbio.hdp_flush_reg = &nbio_v4_3_hdp_flush_reg; 3030 break; 3031 case IP_VERSION(7, 7, 0): 3032 case IP_VERSION(7, 7, 1): 3033 adev->nbio.funcs = &nbio_v7_7_funcs; 3034 adev->nbio.hdp_flush_reg = &nbio_v7_7_hdp_flush_reg; 3035 break; 3036 case IP_VERSION(6, 3, 1): 3037 adev->nbio.funcs = &nbif_v6_3_1_funcs; 3038 adev->nbio.hdp_flush_reg = &nbif_v6_3_1_hdp_flush_reg; 3039 break; 3040 default: 3041 break; 3042 } 3043 3044 switch (amdgpu_ip_version(adev, HDP_HWIP, 0)) { 3045 case IP_VERSION(4, 0, 0): 3046 case IP_VERSION(4, 0, 1): 3047 case IP_VERSION(4, 1, 0): 3048 case IP_VERSION(4, 1, 1): 3049 case IP_VERSION(4, 1, 2): 3050 case IP_VERSION(4, 2, 0): 3051 case IP_VERSION(4, 2, 1): 3052 case IP_VERSION(4, 4, 0): 3053 case IP_VERSION(4, 4, 2): 3054 case IP_VERSION(4, 4, 5): 3055 adev->hdp.funcs = &hdp_v4_0_funcs; 3056 break; 3057 case IP_VERSION(5, 0, 0): 3058 case IP_VERSION(5, 0, 1): 3059 case IP_VERSION(5, 0, 2): 3060 case IP_VERSION(5, 0, 3): 3061 case IP_VERSION(5, 0, 4): 3062 case IP_VERSION(5, 2, 0): 3063 adev->hdp.funcs = &hdp_v5_0_funcs; 3064 break; 3065 case IP_VERSION(5, 2, 1): 3066 adev->hdp.funcs = &hdp_v5_2_funcs; 3067 break; 3068 case IP_VERSION(6, 0, 0): 3069 case IP_VERSION(6, 0, 1): 3070 case IP_VERSION(6, 1, 0): 3071 adev->hdp.funcs = &hdp_v6_0_funcs; 3072 break; 3073 case IP_VERSION(7, 0, 0): 3074 adev->hdp.funcs = &hdp_v7_0_funcs; 3075 break; 3076 default: 3077 break; 3078 } 3079 3080 switch (amdgpu_ip_version(adev, DF_HWIP, 0)) { 3081 case IP_VERSION(3, 6, 0): 3082 case IP_VERSION(3, 6, 1): 3083 case IP_VERSION(3, 6, 2): 3084 adev->df.funcs = &df_v3_6_funcs; 3085 break; 3086 case IP_VERSION(2, 1, 0): 3087 case IP_VERSION(2, 1, 1): 3088 case IP_VERSION(2, 5, 0): 3089 case IP_VERSION(3, 5, 1): 3090 case IP_VERSION(3, 5, 2): 3091 adev->df.funcs = &df_v1_7_funcs; 3092 break; 3093 case IP_VERSION(4, 3, 0): 3094 adev->df.funcs = &df_v4_3_funcs; 3095 break; 3096 case IP_VERSION(4, 6, 2): 3097 adev->df.funcs = &df_v4_6_2_funcs; 3098 break; 3099 case IP_VERSION(4, 15, 0): 3100 case IP_VERSION(4, 15, 1): 3101 adev->df.funcs = &df_v4_15_funcs; 3102 break; 3103 default: 3104 break; 3105 } 3106 3107 switch (amdgpu_ip_version(adev, SMUIO_HWIP, 0)) { 3108 case IP_VERSION(9, 0, 0): 3109 case IP_VERSION(9, 0, 1): 3110 case IP_VERSION(10, 0, 0): 3111 case IP_VERSION(10, 0, 1): 3112 case IP_VERSION(10, 0, 2): 3113 adev->smuio.funcs = &smuio_v9_0_funcs; 3114 break; 3115 case IP_VERSION(11, 0, 0): 3116 case IP_VERSION(11, 0, 2): 3117 case IP_VERSION(11, 0, 3): 3118 case IP_VERSION(11, 0, 4): 3119 case IP_VERSION(11, 0, 7): 3120 case IP_VERSION(11, 0, 8): 3121 adev->smuio.funcs = &smuio_v11_0_funcs; 3122 break; 3123 case IP_VERSION(11, 0, 6): 3124 case IP_VERSION(11, 0, 10): 3125 case IP_VERSION(11, 0, 11): 3126 case IP_VERSION(11, 5, 0): 3127 case IP_VERSION(11, 5, 2): 3128 case IP_VERSION(13, 0, 1): 3129 case IP_VERSION(13, 0, 9): 3130 case IP_VERSION(13, 0, 10): 3131 adev->smuio.funcs = &smuio_v11_0_6_funcs; 3132 break; 3133 case IP_VERSION(13, 0, 2): 3134 adev->smuio.funcs = &smuio_v13_0_funcs; 3135 break; 3136 case IP_VERSION(13, 0, 3): 3137 case IP_VERSION(13, 0, 11): 3138 adev->smuio.funcs = &smuio_v13_0_3_funcs; 3139 if (adev->smuio.funcs->get_pkg_type(adev) == AMDGPU_PKG_TYPE_APU) { 3140 adev->flags |= AMD_IS_APU; 3141 } 3142 break; 3143 case IP_VERSION(13, 0, 6): 3144 case IP_VERSION(13, 0, 8): 3145 case IP_VERSION(14, 0, 0): 3146 case IP_VERSION(14, 0, 1): 3147 adev->smuio.funcs = &smuio_v13_0_6_funcs; 3148 break; 3149 case IP_VERSION(14, 0, 2): 3150 adev->smuio.funcs = &smuio_v14_0_2_funcs; 3151 break; 3152 case IP_VERSION(15, 0, 8): 3153 adev->smuio.funcs = &smuio_v15_0_8_funcs; 3154 break; 3155 default: 3156 break; 3157 } 3158 3159 switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) { 3160 case IP_VERSION(6, 0, 0): 3161 case IP_VERSION(6, 0, 1): 3162 case IP_VERSION(6, 0, 2): 3163 case IP_VERSION(6, 0, 3): 3164 adev->lsdma.funcs = &lsdma_v6_0_funcs; 3165 break; 3166 case IP_VERSION(7, 0, 0): 3167 case IP_VERSION(7, 0, 1): 3168 adev->lsdma.funcs = &lsdma_v7_0_funcs; 3169 break; 3170 default: 3171 break; 3172 } 3173 3174 r = amdgpu_discovery_set_common_ip_blocks(adev); 3175 if (r) 3176 return r; 3177 3178 r = amdgpu_discovery_set_gmc_ip_blocks(adev); 3179 if (r) 3180 return r; 3181 3182 /* For SR-IOV, PSP needs to be initialized before IH */ 3183 if (amdgpu_sriov_vf(adev)) { 3184 r = amdgpu_discovery_set_psp_ip_blocks(adev); 3185 if (r) 3186 return r; 3187 r = amdgpu_discovery_set_ih_ip_blocks(adev); 3188 if (r) 3189 return r; 3190 } else { 3191 r = amdgpu_discovery_set_ih_ip_blocks(adev); 3192 if (r) 3193 return r; 3194 3195 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 3196 r = amdgpu_discovery_set_psp_ip_blocks(adev); 3197 if (r) 3198 return r; 3199 } 3200 } 3201 3202 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 3203 r = amdgpu_discovery_set_smu_ip_blocks(adev); 3204 if (r) 3205 return r; 3206 } 3207 3208 r = amdgpu_discovery_set_display_ip_blocks(adev); 3209 if (r) 3210 return r; 3211 3212 r = amdgpu_discovery_set_gc_ip_blocks(adev); 3213 if (r) 3214 return r; 3215 3216 r = amdgpu_discovery_set_sdma_ip_blocks(adev); 3217 if (r) 3218 return r; 3219 3220 r = amdgpu_discovery_set_ras_ip_blocks(adev); 3221 if (r) 3222 return r; 3223 3224 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 3225 !amdgpu_sriov_vf(adev) && 3226 amdgpu_dpm == 1) || 3227 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && 3228 amdgpu_dpm == 1)) { 3229 r = amdgpu_discovery_set_smu_ip_blocks(adev); 3230 if (r) 3231 return r; 3232 } 3233 3234 r = amdgpu_discovery_set_mm_ip_blocks(adev); 3235 if (r) 3236 return r; 3237 3238 r = amdgpu_discovery_set_mes_ip_blocks(adev); 3239 if (r) 3240 return r; 3241 3242 r = amdgpu_discovery_set_vpe_ip_blocks(adev); 3243 if (r) 3244 return r; 3245 3246 r = amdgpu_discovery_set_umsch_mm_ip_blocks(adev); 3247 if (r) 3248 return r; 3249 3250 r = amdgpu_discovery_set_isp_ip_blocks(adev); 3251 if (r) 3252 return r; 3253 return 0; 3254 } 3255 3256