1 /* 2 * Copyright 2018-2024 Advanced Micro Devices, Inc. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_discovery.h" 28 #include "soc15_hw_ip.h" 29 #include "discovery.h" 30 #include "amdgpu_ras.h" 31 32 #include "soc15.h" 33 #include "gfx_v9_0.h" 34 #include "gfx_v9_4_3.h" 35 #include "gmc_v9_0.h" 36 #include "df_v1_7.h" 37 #include "df_v3_6.h" 38 #include "df_v4_3.h" 39 #include "df_v4_6_2.h" 40 #include "df_v4_15.h" 41 #include "nbio_v6_1.h" 42 #include "nbio_v7_0.h" 43 #include "nbio_v7_4.h" 44 #include "nbio_v7_9.h" 45 #include "nbio_v7_11.h" 46 #include "hdp_v4_0.h" 47 #include "vega10_ih.h" 48 #include "vega20_ih.h" 49 #include "sdma_v4_0.h" 50 #include "sdma_v4_4_2.h" 51 #include "uvd_v7_0.h" 52 #include "vce_v4_0.h" 53 #include "vcn_v1_0.h" 54 #include "vcn_v2_5.h" 55 #include "jpeg_v2_5.h" 56 #include "smuio_v9_0.h" 57 #include "gmc_v10_0.h" 58 #include "gmc_v11_0.h" 59 #include "gmc_v12_0.h" 60 #include "gfxhub_v2_0.h" 61 #include "mmhub_v2_0.h" 62 #include "nbio_v2_3.h" 63 #include "nbio_v4_3.h" 64 #include "nbio_v7_2.h" 65 #include "nbio_v7_7.h" 66 #include "nbif_v6_3_1.h" 67 #include "hdp_v5_0.h" 68 #include "hdp_v5_2.h" 69 #include "hdp_v6_0.h" 70 #include "hdp_v7_0.h" 71 #include "nv.h" 72 #include "soc21.h" 73 #include "soc24.h" 74 #include "navi10_ih.h" 75 #include "ih_v6_0.h" 76 #include "ih_v6_1.h" 77 #include "ih_v7_0.h" 78 #include "gfx_v10_0.h" 79 #include "gfx_v11_0.h" 80 #include "gfx_v12_0.h" 81 #include "sdma_v5_0.h" 82 #include "sdma_v5_2.h" 83 #include "sdma_v6_0.h" 84 #include "sdma_v7_0.h" 85 #include "lsdma_v6_0.h" 86 #include "lsdma_v7_0.h" 87 #include "vcn_v2_0.h" 88 #include "jpeg_v2_0.h" 89 #include "vcn_v3_0.h" 90 #include "jpeg_v3_0.h" 91 #include "vcn_v4_0.h" 92 #include "jpeg_v4_0.h" 93 #include "vcn_v4_0_3.h" 94 #include "jpeg_v4_0_3.h" 95 #include "vcn_v4_0_5.h" 96 #include "jpeg_v4_0_5.h" 97 #include "amdgpu_vkms.h" 98 #include "mes_v11_0.h" 99 #include "mes_v12_0.h" 100 #include "smuio_v11_0.h" 101 #include "smuio_v11_0_6.h" 102 #include "smuio_v13_0.h" 103 #include "smuio_v13_0_3.h" 104 #include "smuio_v13_0_6.h" 105 #include "smuio_v14_0_2.h" 106 #include "vcn_v5_0_0.h" 107 #include "vcn_v5_0_1.h" 108 #include "jpeg_v5_0_0.h" 109 #include "jpeg_v5_0_1.h" 110 #include "amdgpu_ras_mgr.h" 111 112 #include "amdgpu_vpe.h" 113 #if defined(CONFIG_DRM_AMD_ISP) 114 #include "amdgpu_isp.h" 115 #endif 116 117 MODULE_FIRMWARE("amdgpu/ip_discovery.bin"); 118 MODULE_FIRMWARE("amdgpu/vega10_ip_discovery.bin"); 119 MODULE_FIRMWARE("amdgpu/vega12_ip_discovery.bin"); 120 MODULE_FIRMWARE("amdgpu/vega20_ip_discovery.bin"); 121 MODULE_FIRMWARE("amdgpu/raven_ip_discovery.bin"); 122 MODULE_FIRMWARE("amdgpu/raven2_ip_discovery.bin"); 123 MODULE_FIRMWARE("amdgpu/picasso_ip_discovery.bin"); 124 MODULE_FIRMWARE("amdgpu/arcturus_ip_discovery.bin"); 125 MODULE_FIRMWARE("amdgpu/aldebaran_ip_discovery.bin"); 126 127 #define mmIP_DISCOVERY_VERSION 0x16A00 128 #define mmRCC_CONFIG_MEMSIZE 0xde3 129 #define mmMP0_SMN_C2PMSG_33 0x16061 130 #define mmMM_INDEX 0x0 131 #define mmMM_INDEX_HI 0x6 132 #define mmMM_DATA 0x1 133 134 static const char *hw_id_names[HW_ID_MAX] = { 135 [MP1_HWID] = "MP1", 136 [MP2_HWID] = "MP2", 137 [THM_HWID] = "THM", 138 [SMUIO_HWID] = "SMUIO", 139 [FUSE_HWID] = "FUSE", 140 [CLKA_HWID] = "CLKA", 141 [PWR_HWID] = "PWR", 142 [GC_HWID] = "GC", 143 [UVD_HWID] = "UVD", 144 [AUDIO_AZ_HWID] = "AUDIO_AZ", 145 [ACP_HWID] = "ACP", 146 [DCI_HWID] = "DCI", 147 [DMU_HWID] = "DMU", 148 [DCO_HWID] = "DCO", 149 [DIO_HWID] = "DIO", 150 [XDMA_HWID] = "XDMA", 151 [DCEAZ_HWID] = "DCEAZ", 152 [DAZ_HWID] = "DAZ", 153 [SDPMUX_HWID] = "SDPMUX", 154 [NTB_HWID] = "NTB", 155 [IOHC_HWID] = "IOHC", 156 [L2IMU_HWID] = "L2IMU", 157 [VCE_HWID] = "VCE", 158 [MMHUB_HWID] = "MMHUB", 159 [ATHUB_HWID] = "ATHUB", 160 [DBGU_NBIO_HWID] = "DBGU_NBIO", 161 [DFX_HWID] = "DFX", 162 [DBGU0_HWID] = "DBGU0", 163 [DBGU1_HWID] = "DBGU1", 164 [OSSSYS_HWID] = "OSSSYS", 165 [HDP_HWID] = "HDP", 166 [SDMA0_HWID] = "SDMA0", 167 [SDMA1_HWID] = "SDMA1", 168 [SDMA2_HWID] = "SDMA2", 169 [SDMA3_HWID] = "SDMA3", 170 [LSDMA_HWID] = "LSDMA", 171 [ISP_HWID] = "ISP", 172 [DBGU_IO_HWID] = "DBGU_IO", 173 [DF_HWID] = "DF", 174 [CLKB_HWID] = "CLKB", 175 [FCH_HWID] = "FCH", 176 [DFX_DAP_HWID] = "DFX_DAP", 177 [L1IMU_PCIE_HWID] = "L1IMU_PCIE", 178 [L1IMU_NBIF_HWID] = "L1IMU_NBIF", 179 [L1IMU_IOAGR_HWID] = "L1IMU_IOAGR", 180 [L1IMU3_HWID] = "L1IMU3", 181 [L1IMU4_HWID] = "L1IMU4", 182 [L1IMU5_HWID] = "L1IMU5", 183 [L1IMU6_HWID] = "L1IMU6", 184 [L1IMU7_HWID] = "L1IMU7", 185 [L1IMU8_HWID] = "L1IMU8", 186 [L1IMU9_HWID] = "L1IMU9", 187 [L1IMU10_HWID] = "L1IMU10", 188 [L1IMU11_HWID] = "L1IMU11", 189 [L1IMU12_HWID] = "L1IMU12", 190 [L1IMU13_HWID] = "L1IMU13", 191 [L1IMU14_HWID] = "L1IMU14", 192 [L1IMU15_HWID] = "L1IMU15", 193 [WAFLC_HWID] = "WAFLC", 194 [FCH_USB_PD_HWID] = "FCH_USB_PD", 195 [PCIE_HWID] = "PCIE", 196 [PCS_HWID] = "PCS", 197 [DDCL_HWID] = "DDCL", 198 [SST_HWID] = "SST", 199 [IOAGR_HWID] = "IOAGR", 200 [NBIF_HWID] = "NBIF", 201 [IOAPIC_HWID] = "IOAPIC", 202 [SYSTEMHUB_HWID] = "SYSTEMHUB", 203 [NTBCCP_HWID] = "NTBCCP", 204 [UMC_HWID] = "UMC", 205 [SATA_HWID] = "SATA", 206 [USB_HWID] = "USB", 207 [CCXSEC_HWID] = "CCXSEC", 208 [XGMI_HWID] = "XGMI", 209 [XGBE_HWID] = "XGBE", 210 [MP0_HWID] = "MP0", 211 [VPE_HWID] = "VPE", 212 [ATU_HWID] = "ATU", 213 [AIGC_HWID] = "AIGC", 214 }; 215 216 static int hw_id_map[MAX_HWIP] = { 217 [GC_HWIP] = GC_HWID, 218 [HDP_HWIP] = HDP_HWID, 219 [SDMA0_HWIP] = SDMA0_HWID, 220 [SDMA1_HWIP] = SDMA1_HWID, 221 [SDMA2_HWIP] = SDMA2_HWID, 222 [SDMA3_HWIP] = SDMA3_HWID, 223 [LSDMA_HWIP] = LSDMA_HWID, 224 [MMHUB_HWIP] = MMHUB_HWID, 225 [ATHUB_HWIP] = ATHUB_HWID, 226 [NBIO_HWIP] = NBIF_HWID, 227 [MP0_HWIP] = MP0_HWID, 228 [MP1_HWIP] = MP1_HWID, 229 [UVD_HWIP] = UVD_HWID, 230 [VCE_HWIP] = VCE_HWID, 231 [DF_HWIP] = DF_HWID, 232 [DCE_HWIP] = DMU_HWID, 233 [OSSSYS_HWIP] = OSSSYS_HWID, 234 [SMUIO_HWIP] = SMUIO_HWID, 235 [PWR_HWIP] = PWR_HWID, 236 [NBIF_HWIP] = NBIF_HWID, 237 [THM_HWIP] = THM_HWID, 238 [CLK_HWIP] = CLKA_HWID, 239 [UMC_HWIP] = UMC_HWID, 240 [XGMI_HWIP] = XGMI_HWID, 241 [DCI_HWIP] = DCI_HWID, 242 [PCIE_HWIP] = PCIE_HWID, 243 [VPE_HWIP] = VPE_HWID, 244 [ISP_HWIP] = ISP_HWID, 245 [ATU_HWIP] = ATU_HWID, 246 }; 247 248 static int amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device *adev, uint8_t *binary) 249 { 250 u64 tmr_offset, tmr_size, pos; 251 void *discv_regn; 252 int ret; 253 254 ret = amdgpu_acpi_get_tmr_info(adev, &tmr_offset, &tmr_size); 255 if (ret) 256 return ret; 257 258 pos = tmr_offset + tmr_size - DISCOVERY_TMR_OFFSET; 259 260 /* This region is read-only and reserved from system use */ 261 discv_regn = memremap(pos, adev->discovery.size, MEMREMAP_WC); 262 if (discv_regn) { 263 memcpy(binary, discv_regn, adev->discovery.size); 264 memunmap(discv_regn); 265 return 0; 266 } 267 268 return -ENOENT; 269 } 270 271 #define IP_DISCOVERY_V2 2 272 #define IP_DISCOVERY_V4 4 273 274 static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev, 275 uint8_t *binary) 276 { 277 bool sz_valid = true; 278 uint64_t vram_size; 279 int i, ret = 0; 280 u32 msg; 281 282 if (!amdgpu_sriov_vf(adev)) { 283 /* It can take up to two second for IFWI init to complete on some dGPUs, 284 * but generally it should be in the 60-100ms range. Normally this starts 285 * as soon as the device gets power so by the time the OS loads this has long 286 * completed. However, when a card is hotplugged via e.g., USB4, we need to 287 * wait for this to complete. Once the C2PMSG is updated, we can 288 * continue. 289 */ 290 291 for (i = 0; i < 2000; i++) { 292 msg = RREG32(mmMP0_SMN_C2PMSG_33); 293 if (msg & 0x80000000) 294 break; 295 msleep(1); 296 } 297 } 298 299 vram_size = RREG32(mmRCC_CONFIG_MEMSIZE); 300 if (!vram_size || vram_size == U32_MAX) 301 sz_valid = false; 302 else 303 vram_size <<= 20; 304 305 /* 306 * If in VRAM, discovery TMR is marked for reservation. If it is in system mem, 307 * then it is not required to be reserved. 308 */ 309 if (sz_valid) { 310 if (amdgpu_sriov_vf(adev) && adev->virt.is_dynamic_crit_regn_enabled) { 311 /* For SRIOV VFs with dynamic critical region enabled, 312 * we will get the IPD binary via below call. 313 * If dynamic critical is disabled, fall through to normal seq. 314 */ 315 if (amdgpu_virt_get_dynamic_data_info(adev, 316 AMD_SRIOV_MSG_IPD_TABLE_ID, binary, 317 &adev->discovery.size)) { 318 dev_err(adev->dev, 319 "failed to read discovery info from dynamic critical region."); 320 ret = -EINVAL; 321 goto exit; 322 } 323 } else { 324 uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET; 325 326 amdgpu_device_vram_access(adev, pos, (uint32_t *)binary, 327 adev->discovery.size, false); 328 adev->discovery.reserve_tmr = true; 329 } 330 } else { 331 ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary); 332 } 333 334 if (ret) 335 dev_err(adev->dev, 336 "failed to read discovery info from memory, vram size read: %llx", 337 vram_size); 338 exit: 339 return ret; 340 } 341 342 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, 343 uint8_t *binary, 344 const char *fw_name) 345 { 346 const struct firmware *fw; 347 int r; 348 349 r = firmware_request_nowarn(&fw, fw_name, adev->dev); 350 if (r) { 351 if (amdgpu_discovery == 2) 352 dev_err(adev->dev, "can't load firmware \"%s\"\n", fw_name); 353 else 354 drm_info(&adev->ddev, "Optional firmware \"%s\" was not found\n", fw_name); 355 return r; 356 } 357 358 memcpy((u8 *)binary, (u8 *)fw->data, fw->size); 359 release_firmware(fw); 360 361 return 0; 362 } 363 364 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size) 365 { 366 uint16_t checksum = 0; 367 int i; 368 369 for (i = 0; i < size; i++) 370 checksum += data[i]; 371 372 return checksum; 373 } 374 375 static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size, 376 uint16_t expected) 377 { 378 return !!(amdgpu_discovery_calculate_checksum(data, size) == expected); 379 } 380 381 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary) 382 { 383 struct binary_header *bhdr; 384 bhdr = (struct binary_header *)binary; 385 386 return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE); 387 } 388 389 static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev) 390 { 391 /* 392 * So far, apply this quirk only on those Navy Flounder boards which 393 * have a bad harvest table of VCN config. 394 */ 395 if ((amdgpu_ip_version(adev, UVD_HWIP, 1) == IP_VERSION(3, 0, 1)) && 396 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 2))) { 397 switch (adev->pdev->revision) { 398 case 0xC1: 399 case 0xC2: 400 case 0xC3: 401 case 0xC5: 402 case 0xC7: 403 case 0xCF: 404 case 0xDF: 405 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 406 adev->vcn.inst_mask &= ~AMDGPU_VCN_HARVEST_VCN1; 407 break; 408 default: 409 break; 410 } 411 } 412 } 413 414 static int amdgpu_discovery_verify_npsinfo(struct amdgpu_device *adev, 415 struct binary_header *bhdr) 416 { 417 uint8_t *discovery_bin = adev->discovery.bin; 418 struct table_info *info; 419 uint16_t checksum; 420 uint16_t offset; 421 422 info = &bhdr->table_list[NPS_INFO]; 423 offset = le16_to_cpu(info->offset); 424 checksum = le16_to_cpu(info->checksum); 425 426 struct nps_info_header *nhdr = 427 (struct nps_info_header *)(discovery_bin + offset); 428 429 if (le32_to_cpu(nhdr->table_id) != NPS_INFO_TABLE_ID) { 430 dev_dbg(adev->dev, "invalid ip discovery nps info table id\n"); 431 return -EINVAL; 432 } 433 434 if (!amdgpu_discovery_verify_checksum(discovery_bin + offset, 435 le32_to_cpu(nhdr->size_bytes), 436 checksum)) { 437 dev_dbg(adev->dev, "invalid nps info data table checksum\n"); 438 return -EINVAL; 439 } 440 441 return 0; 442 } 443 444 static const char *amdgpu_discovery_get_fw_name(struct amdgpu_device *adev) 445 { 446 if (amdgpu_discovery == 2) { 447 /* Assume there is valid discovery TMR in VRAM even if binary is sideloaded */ 448 adev->discovery.reserve_tmr = true; 449 return "amdgpu/ip_discovery.bin"; 450 } 451 452 switch (adev->asic_type) { 453 case CHIP_VEGA10: 454 return "amdgpu/vega10_ip_discovery.bin"; 455 case CHIP_VEGA12: 456 return "amdgpu/vega12_ip_discovery.bin"; 457 case CHIP_RAVEN: 458 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 459 return "amdgpu/raven2_ip_discovery.bin"; 460 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 461 return "amdgpu/picasso_ip_discovery.bin"; 462 else 463 return "amdgpu/raven_ip_discovery.bin"; 464 case CHIP_VEGA20: 465 return "amdgpu/vega20_ip_discovery.bin"; 466 case CHIP_ARCTURUS: 467 return "amdgpu/arcturus_ip_discovery.bin"; 468 case CHIP_ALDEBARAN: 469 return "amdgpu/aldebaran_ip_discovery.bin"; 470 default: 471 return NULL; 472 } 473 } 474 475 static int amdgpu_discovery_init(struct amdgpu_device *adev) 476 { 477 struct table_info *info; 478 struct binary_header *bhdr; 479 uint8_t *discovery_bin; 480 const char *fw_name; 481 uint16_t offset; 482 uint16_t size; 483 uint16_t checksum; 484 int r; 485 486 adev->discovery.bin = kzalloc(DISCOVERY_TMR_SIZE, GFP_KERNEL); 487 if (!adev->discovery.bin) 488 return -ENOMEM; 489 adev->discovery.size = DISCOVERY_TMR_SIZE; 490 adev->discovery.debugfs_blob.data = adev->discovery.bin; 491 adev->discovery.debugfs_blob.size = adev->discovery.size; 492 493 discovery_bin = adev->discovery.bin; 494 /* Read from file if it is the preferred option */ 495 fw_name = amdgpu_discovery_get_fw_name(adev); 496 if (fw_name != NULL) { 497 drm_dbg(&adev->ddev, "use ip discovery information from file"); 498 r = amdgpu_discovery_read_binary_from_file(adev, discovery_bin, 499 fw_name); 500 if (r) 501 goto out; 502 } else { 503 drm_dbg(&adev->ddev, "use ip discovery information from memory"); 504 r = amdgpu_discovery_read_binary_from_mem(adev, discovery_bin); 505 if (r) 506 goto out; 507 } 508 509 /* check the ip discovery binary signature */ 510 if (!amdgpu_discovery_verify_binary_signature(discovery_bin)) { 511 dev_err(adev->dev, 512 "get invalid ip discovery binary signature\n"); 513 r = -EINVAL; 514 goto out; 515 } 516 517 bhdr = (struct binary_header *)discovery_bin; 518 519 offset = offsetof(struct binary_header, binary_checksum) + 520 sizeof(bhdr->binary_checksum); 521 size = le16_to_cpu(bhdr->binary_size) - offset; 522 checksum = le16_to_cpu(bhdr->binary_checksum); 523 524 if (!amdgpu_discovery_verify_checksum(discovery_bin + offset, size, 525 checksum)) { 526 dev_err(adev->dev, "invalid ip discovery binary checksum\n"); 527 r = -EINVAL; 528 goto out; 529 } 530 531 info = &bhdr->table_list[IP_DISCOVERY]; 532 offset = le16_to_cpu(info->offset); 533 checksum = le16_to_cpu(info->checksum); 534 535 if (offset) { 536 struct ip_discovery_header *ihdr = 537 (struct ip_discovery_header *)(discovery_bin + offset); 538 if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) { 539 dev_err(adev->dev, "invalid ip discovery data table signature\n"); 540 r = -EINVAL; 541 goto out; 542 } 543 544 if (!amdgpu_discovery_verify_checksum(discovery_bin + offset, 545 le16_to_cpu(ihdr->size), 546 checksum)) { 547 dev_err(adev->dev, "invalid ip discovery data table checksum\n"); 548 r = -EINVAL; 549 goto out; 550 } 551 } 552 553 info = &bhdr->table_list[GC]; 554 offset = le16_to_cpu(info->offset); 555 checksum = le16_to_cpu(info->checksum); 556 557 if (offset) { 558 struct gpu_info_header *ghdr = 559 (struct gpu_info_header *)(discovery_bin + offset); 560 561 if (le32_to_cpu(ghdr->table_id) != GC_TABLE_ID) { 562 dev_err(adev->dev, "invalid ip discovery gc table id\n"); 563 r = -EINVAL; 564 goto out; 565 } 566 567 if (!amdgpu_discovery_verify_checksum(discovery_bin + offset, 568 le32_to_cpu(ghdr->size), 569 checksum)) { 570 dev_err(adev->dev, "invalid gc data table checksum\n"); 571 r = -EINVAL; 572 goto out; 573 } 574 } 575 576 info = &bhdr->table_list[HARVEST_INFO]; 577 offset = le16_to_cpu(info->offset); 578 checksum = le16_to_cpu(info->checksum); 579 580 if (offset) { 581 struct harvest_info_header *hhdr = 582 (struct harvest_info_header *)(discovery_bin + offset); 583 584 if (le32_to_cpu(hhdr->signature) != HARVEST_TABLE_SIGNATURE) { 585 dev_err(adev->dev, "invalid ip discovery harvest table signature\n"); 586 r = -EINVAL; 587 goto out; 588 } 589 590 if (!amdgpu_discovery_verify_checksum( 591 discovery_bin + offset, 592 sizeof(struct harvest_table), checksum)) { 593 dev_err(adev->dev, "invalid harvest data table checksum\n"); 594 r = -EINVAL; 595 goto out; 596 } 597 } 598 599 info = &bhdr->table_list[VCN_INFO]; 600 offset = le16_to_cpu(info->offset); 601 checksum = le16_to_cpu(info->checksum); 602 603 if (offset) { 604 struct vcn_info_header *vhdr = 605 (struct vcn_info_header *)(discovery_bin + offset); 606 607 if (le32_to_cpu(vhdr->table_id) != VCN_INFO_TABLE_ID) { 608 dev_err(adev->dev, "invalid ip discovery vcn table id\n"); 609 r = -EINVAL; 610 goto out; 611 } 612 613 if (!amdgpu_discovery_verify_checksum( 614 discovery_bin + offset, 615 le32_to_cpu(vhdr->size_bytes), checksum)) { 616 dev_err(adev->dev, "invalid vcn data table checksum\n"); 617 r = -EINVAL; 618 goto out; 619 } 620 } 621 622 info = &bhdr->table_list[MALL_INFO]; 623 offset = le16_to_cpu(info->offset); 624 checksum = le16_to_cpu(info->checksum); 625 626 if (0 && offset) { 627 struct mall_info_header *mhdr = 628 (struct mall_info_header *)(discovery_bin + offset); 629 630 if (le32_to_cpu(mhdr->table_id) != MALL_INFO_TABLE_ID) { 631 dev_err(adev->dev, "invalid ip discovery mall table id\n"); 632 r = -EINVAL; 633 goto out; 634 } 635 636 if (!amdgpu_discovery_verify_checksum( 637 discovery_bin + offset, 638 le32_to_cpu(mhdr->size_bytes), checksum)) { 639 dev_err(adev->dev, "invalid mall data table checksum\n"); 640 r = -EINVAL; 641 goto out; 642 } 643 } 644 645 return 0; 646 647 out: 648 kfree(adev->discovery.bin); 649 adev->discovery.bin = NULL; 650 if ((amdgpu_discovery != 2) && 651 (RREG32(mmIP_DISCOVERY_VERSION) == 4)) 652 amdgpu_ras_query_boot_status(adev, 4); 653 return r; 654 } 655 656 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev); 657 658 void amdgpu_discovery_fini(struct amdgpu_device *adev) 659 { 660 amdgpu_discovery_sysfs_fini(adev); 661 kfree(adev->discovery.bin); 662 adev->discovery.bin = NULL; 663 } 664 665 static int amdgpu_discovery_validate_ip(struct amdgpu_device *adev, 666 uint8_t instance, uint16_t hw_id) 667 { 668 if (instance >= HWIP_MAX_INSTANCE) { 669 dev_err(adev->dev, 670 "Unexpected instance_number (%d) from ip discovery blob\n", 671 instance); 672 return -EINVAL; 673 } 674 if (hw_id >= HW_ID_MAX) { 675 dev_err(adev->dev, 676 "Unexpected hw_id (%d) from ip discovery blob\n", 677 hw_id); 678 return -EINVAL; 679 } 680 681 return 0; 682 } 683 684 static void amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device *adev, 685 uint32_t *vcn_harvest_count) 686 { 687 uint8_t *discovery_bin = adev->discovery.bin; 688 struct binary_header *bhdr; 689 struct ip_discovery_header *ihdr; 690 struct die_header *dhdr; 691 struct ip *ip; 692 uint16_t die_offset, ip_offset, num_dies, num_ips; 693 uint16_t hw_id; 694 uint8_t inst; 695 int i, j; 696 697 bhdr = (struct binary_header *)discovery_bin; 698 ihdr = (struct ip_discovery_header 699 *)(discovery_bin + 700 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 701 num_dies = le16_to_cpu(ihdr->num_dies); 702 703 /* scan harvest bit of all IP data structures */ 704 for (i = 0; i < num_dies; i++) { 705 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 706 dhdr = (struct die_header *)(discovery_bin + die_offset); 707 num_ips = le16_to_cpu(dhdr->num_ips); 708 ip_offset = die_offset + sizeof(*dhdr); 709 710 for (j = 0; j < num_ips; j++) { 711 ip = (struct ip *)(discovery_bin + ip_offset); 712 inst = ip->number_instance; 713 hw_id = le16_to_cpu(ip->hw_id); 714 if (amdgpu_discovery_validate_ip(adev, inst, hw_id)) 715 goto next_ip; 716 717 if (ip->harvest == 1) { 718 switch (hw_id) { 719 case VCN_HWID: 720 (*vcn_harvest_count)++; 721 if (inst == 0) { 722 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0; 723 adev->vcn.inst_mask &= 724 ~AMDGPU_VCN_HARVEST_VCN0; 725 adev->jpeg.inst_mask &= 726 ~AMDGPU_VCN_HARVEST_VCN0; 727 } else { 728 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 729 adev->vcn.inst_mask &= 730 ~AMDGPU_VCN_HARVEST_VCN1; 731 adev->jpeg.inst_mask &= 732 ~AMDGPU_VCN_HARVEST_VCN1; 733 } 734 break; 735 case DMU_HWID: 736 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 737 break; 738 default: 739 break; 740 } 741 } 742 next_ip: 743 ip_offset += struct_size(ip, base_address, 744 ip->num_base_address); 745 } 746 } 747 } 748 749 static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev, 750 uint32_t *vcn_harvest_count, 751 uint32_t *umc_harvest_count) 752 { 753 uint8_t *discovery_bin = adev->discovery.bin; 754 struct binary_header *bhdr; 755 struct harvest_table *harvest_info; 756 u16 offset; 757 int i; 758 uint32_t umc_harvest_config = 0; 759 760 bhdr = (struct binary_header *)discovery_bin; 761 offset = le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset); 762 763 if (!offset) { 764 dev_err(adev->dev, "invalid harvest table offset\n"); 765 return; 766 } 767 768 harvest_info = (struct harvest_table *)(discovery_bin + offset); 769 770 for (i = 0; i < 32; i++) { 771 if (le16_to_cpu(harvest_info->list[i].hw_id) == 0) 772 break; 773 774 switch (le16_to_cpu(harvest_info->list[i].hw_id)) { 775 case VCN_HWID: 776 (*vcn_harvest_count)++; 777 adev->vcn.harvest_config |= 778 (1 << harvest_info->list[i].number_instance); 779 adev->jpeg.harvest_config |= 780 (1 << harvest_info->list[i].number_instance); 781 782 adev->vcn.inst_mask &= 783 ~(1U << harvest_info->list[i].number_instance); 784 adev->jpeg.inst_mask &= 785 ~(1U << harvest_info->list[i].number_instance); 786 break; 787 case DMU_HWID: 788 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 789 break; 790 case UMC_HWID: 791 umc_harvest_config |= 792 1 << (le16_to_cpu(harvest_info->list[i].number_instance)); 793 (*umc_harvest_count)++; 794 break; 795 case GC_HWID: 796 adev->gfx.xcc_mask &= 797 ~(1U << harvest_info->list[i].number_instance); 798 break; 799 case SDMA0_HWID: 800 adev->sdma.sdma_mask &= 801 ~(1U << harvest_info->list[i].number_instance); 802 break; 803 #if defined(CONFIG_DRM_AMD_ISP) 804 case ISP_HWID: 805 adev->isp.harvest_config |= 806 ~(1U << harvest_info->list[i].number_instance); 807 break; 808 #endif 809 default: 810 break; 811 } 812 } 813 814 adev->umc.active_mask = ((1 << adev->umc.node_inst_num) - 1) & 815 ~umc_harvest_config; 816 } 817 818 /* ================================================== */ 819 820 struct ip_hw_instance { 821 struct kobject kobj; /* ip_discovery/die/#die/#hw_id/#instance/<attrs...> */ 822 823 int hw_id; 824 u8 num_instance; 825 u8 major, minor, revision; 826 u8 harvest; 827 828 int num_base_addresses; 829 u32 base_addr[] __counted_by(num_base_addresses); 830 }; 831 832 struct ip_hw_id { 833 struct kset hw_id_kset; /* ip_discovery/die/#die/#hw_id/, contains ip_hw_instance */ 834 int hw_id; 835 }; 836 837 struct ip_die_entry { 838 struct kset ip_kset; /* ip_discovery/die/#die/, contains ip_hw_id */ 839 u16 num_ips; 840 }; 841 842 /* -------------------------------------------------- */ 843 844 struct ip_hw_instance_attr { 845 struct attribute attr; 846 ssize_t (*show)(struct ip_hw_instance *ip_hw_instance, char *buf); 847 }; 848 849 static ssize_t hw_id_show(struct ip_hw_instance *ip_hw_instance, char *buf) 850 { 851 return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id); 852 } 853 854 static ssize_t num_instance_show(struct ip_hw_instance *ip_hw_instance, char *buf) 855 { 856 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance); 857 } 858 859 static ssize_t major_show(struct ip_hw_instance *ip_hw_instance, char *buf) 860 { 861 return sysfs_emit(buf, "%d\n", ip_hw_instance->major); 862 } 863 864 static ssize_t minor_show(struct ip_hw_instance *ip_hw_instance, char *buf) 865 { 866 return sysfs_emit(buf, "%d\n", ip_hw_instance->minor); 867 } 868 869 static ssize_t revision_show(struct ip_hw_instance *ip_hw_instance, char *buf) 870 { 871 return sysfs_emit(buf, "%d\n", ip_hw_instance->revision); 872 } 873 874 static ssize_t harvest_show(struct ip_hw_instance *ip_hw_instance, char *buf) 875 { 876 return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest); 877 } 878 879 static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, char *buf) 880 { 881 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses); 882 } 883 884 static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf) 885 { 886 ssize_t res, at; 887 int ii; 888 889 for (res = at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) { 890 /* Here we satisfy the condition that, at + size <= PAGE_SIZE. 891 */ 892 if (at + 12 > PAGE_SIZE) 893 break; 894 res = sysfs_emit_at(buf, at, "0x%08X\n", 895 ip_hw_instance->base_addr[ii]); 896 if (res <= 0) 897 break; 898 at += res; 899 } 900 901 return res < 0 ? res : at; 902 } 903 904 static struct ip_hw_instance_attr ip_hw_attr[] = { 905 __ATTR_RO(hw_id), 906 __ATTR_RO(num_instance), 907 __ATTR_RO(major), 908 __ATTR_RO(minor), 909 __ATTR_RO(revision), 910 __ATTR_RO(harvest), 911 __ATTR_RO(num_base_addresses), 912 __ATTR_RO(base_addr), 913 }; 914 915 static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1]; 916 ATTRIBUTE_GROUPS(ip_hw_instance); 917 918 #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj) 919 #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr) 920 921 static ssize_t ip_hw_instance_attr_show(struct kobject *kobj, 922 struct attribute *attr, 923 char *buf) 924 { 925 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 926 struct ip_hw_instance_attr *ip_hw_attr = to_ip_hw_instance_attr(attr); 927 928 if (!ip_hw_attr->show) 929 return -EIO; 930 931 return ip_hw_attr->show(ip_hw_instance, buf); 932 } 933 934 static const struct sysfs_ops ip_hw_instance_sysfs_ops = { 935 .show = ip_hw_instance_attr_show, 936 }; 937 938 static void ip_hw_instance_release(struct kobject *kobj) 939 { 940 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 941 942 kfree(ip_hw_instance); 943 } 944 945 static const struct kobj_type ip_hw_instance_ktype = { 946 .release = ip_hw_instance_release, 947 .sysfs_ops = &ip_hw_instance_sysfs_ops, 948 .default_groups = ip_hw_instance_groups, 949 }; 950 951 /* -------------------------------------------------- */ 952 953 #define to_ip_hw_id(x) container_of(to_kset(x), struct ip_hw_id, hw_id_kset) 954 955 static void ip_hw_id_release(struct kobject *kobj) 956 { 957 struct ip_hw_id *ip_hw_id = to_ip_hw_id(kobj); 958 959 if (!list_empty(&ip_hw_id->hw_id_kset.list)) 960 DRM_ERROR("ip_hw_id->hw_id_kset is not empty"); 961 kfree(ip_hw_id); 962 } 963 964 static const struct kobj_type ip_hw_id_ktype = { 965 .release = ip_hw_id_release, 966 .sysfs_ops = &kobj_sysfs_ops, 967 }; 968 969 /* -------------------------------------------------- */ 970 971 static void die_kobj_release(struct kobject *kobj); 972 static void ip_disc_release(struct kobject *kobj); 973 974 struct ip_die_entry_attribute { 975 struct attribute attr; 976 ssize_t (*show)(struct ip_die_entry *ip_die_entry, char *buf); 977 }; 978 979 #define to_ip_die_entry_attr(x) container_of(x, struct ip_die_entry_attribute, attr) 980 981 static ssize_t num_ips_show(struct ip_die_entry *ip_die_entry, char *buf) 982 { 983 return sysfs_emit(buf, "%d\n", ip_die_entry->num_ips); 984 } 985 986 /* If there are more ip_die_entry attrs, other than the number of IPs, 987 * we can make this intro an array of attrs, and then initialize 988 * ip_die_entry_attrs in a loop. 989 */ 990 static struct ip_die_entry_attribute num_ips_attr = 991 __ATTR_RO(num_ips); 992 993 static struct attribute *ip_die_entry_attrs[] = { 994 &num_ips_attr.attr, 995 NULL, 996 }; 997 ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */ 998 999 #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset) 1000 1001 static ssize_t ip_die_entry_attr_show(struct kobject *kobj, 1002 struct attribute *attr, 1003 char *buf) 1004 { 1005 struct ip_die_entry_attribute *ip_die_entry_attr = to_ip_die_entry_attr(attr); 1006 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 1007 1008 if (!ip_die_entry_attr->show) 1009 return -EIO; 1010 1011 return ip_die_entry_attr->show(ip_die_entry, buf); 1012 } 1013 1014 static void ip_die_entry_release(struct kobject *kobj) 1015 { 1016 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 1017 1018 if (!list_empty(&ip_die_entry->ip_kset.list)) 1019 DRM_ERROR("ip_die_entry->ip_kset is not empty"); 1020 kfree(ip_die_entry); 1021 } 1022 1023 static const struct sysfs_ops ip_die_entry_sysfs_ops = { 1024 .show = ip_die_entry_attr_show, 1025 }; 1026 1027 static const struct kobj_type ip_die_entry_ktype = { 1028 .release = ip_die_entry_release, 1029 .sysfs_ops = &ip_die_entry_sysfs_ops, 1030 .default_groups = ip_die_entry_groups, 1031 }; 1032 1033 static const struct kobj_type die_kobj_ktype = { 1034 .release = die_kobj_release, 1035 .sysfs_ops = &kobj_sysfs_ops, 1036 }; 1037 1038 static const struct kobj_type ip_discovery_ktype = { 1039 .release = ip_disc_release, 1040 .sysfs_ops = &kobj_sysfs_ops, 1041 }; 1042 1043 struct ip_discovery_top { 1044 struct kobject kobj; /* ip_discovery/ */ 1045 struct kset die_kset; /* ip_discovery/die/, contains ip_die_entry */ 1046 struct amdgpu_device *adev; 1047 }; 1048 1049 static void die_kobj_release(struct kobject *kobj) 1050 { 1051 struct ip_discovery_top *ip_top = container_of(to_kset(kobj), 1052 struct ip_discovery_top, 1053 die_kset); 1054 if (!list_empty(&ip_top->die_kset.list)) 1055 DRM_ERROR("ip_top->die_kset is not empty"); 1056 } 1057 1058 static void ip_disc_release(struct kobject *kobj) 1059 { 1060 struct ip_discovery_top *ip_top = container_of(kobj, struct ip_discovery_top, 1061 kobj); 1062 struct amdgpu_device *adev = ip_top->adev; 1063 1064 kfree(ip_top); 1065 adev->discovery.ip_top = NULL; 1066 } 1067 1068 static uint8_t amdgpu_discovery_get_harvest_info(struct amdgpu_device *adev, 1069 uint16_t hw_id, uint8_t inst) 1070 { 1071 uint8_t harvest = 0; 1072 1073 /* Until a uniform way is figured, get mask based on hwid */ 1074 switch (hw_id) { 1075 case VCN_HWID: 1076 /* VCN vs UVD+VCE */ 1077 if (!amdgpu_ip_version(adev, VCE_HWIP, 0)) 1078 harvest = ((1 << inst) & adev->vcn.inst_mask) == 0; 1079 break; 1080 case DMU_HWID: 1081 if (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK) 1082 harvest = 0x1; 1083 break; 1084 case UMC_HWID: 1085 /* TODO: It needs another parsing; for now, ignore.*/ 1086 break; 1087 case GC_HWID: 1088 harvest = ((1 << inst) & adev->gfx.xcc_mask) == 0; 1089 break; 1090 case SDMA0_HWID: 1091 harvest = ((1 << inst) & adev->sdma.sdma_mask) == 0; 1092 break; 1093 default: 1094 break; 1095 } 1096 1097 return harvest; 1098 } 1099 1100 static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev, 1101 struct ip_die_entry *ip_die_entry, 1102 const size_t _ip_offset, const int num_ips, 1103 bool reg_base_64) 1104 { 1105 uint8_t *discovery_bin = adev->discovery.bin; 1106 int ii, jj, kk, res; 1107 uint16_t hw_id; 1108 uint8_t inst; 1109 1110 DRM_DEBUG("num_ips:%d", num_ips); 1111 1112 /* Find all IPs of a given HW ID, and add their instance to 1113 * #die/#hw_id/#instance/<attributes> 1114 */ 1115 for (ii = 0; ii < HW_ID_MAX; ii++) { 1116 struct ip_hw_id *ip_hw_id = NULL; 1117 size_t ip_offset = _ip_offset; 1118 1119 for (jj = 0; jj < num_ips; jj++) { 1120 struct ip_v4 *ip; 1121 struct ip_hw_instance *ip_hw_instance; 1122 1123 ip = (struct ip_v4 *)(discovery_bin + ip_offset); 1124 inst = ip->instance_number; 1125 hw_id = le16_to_cpu(ip->hw_id); 1126 if (amdgpu_discovery_validate_ip(adev, inst, hw_id) || 1127 hw_id != ii) 1128 goto next_ip; 1129 1130 DRM_DEBUG("match:%d @ ip_offset:%zu", ii, ip_offset); 1131 1132 /* We have a hw_id match; register the hw 1133 * block if not yet registered. 1134 */ 1135 if (!ip_hw_id) { 1136 ip_hw_id = kzalloc(sizeof(*ip_hw_id), GFP_KERNEL); 1137 if (!ip_hw_id) 1138 return -ENOMEM; 1139 ip_hw_id->hw_id = ii; 1140 1141 kobject_set_name(&ip_hw_id->hw_id_kset.kobj, "%d", ii); 1142 ip_hw_id->hw_id_kset.kobj.kset = &ip_die_entry->ip_kset; 1143 ip_hw_id->hw_id_kset.kobj.ktype = &ip_hw_id_ktype; 1144 res = kset_register(&ip_hw_id->hw_id_kset); 1145 if (res) { 1146 DRM_ERROR("Couldn't register ip_hw_id kset"); 1147 kfree(ip_hw_id); 1148 return res; 1149 } 1150 if (hw_id_names[ii]) { 1151 res = sysfs_create_link(&ip_die_entry->ip_kset.kobj, 1152 &ip_hw_id->hw_id_kset.kobj, 1153 hw_id_names[ii]); 1154 if (res) { 1155 DRM_ERROR("Couldn't create IP link %s in IP Die:%s\n", 1156 hw_id_names[ii], 1157 kobject_name(&ip_die_entry->ip_kset.kobj)); 1158 } 1159 } 1160 } 1161 1162 /* Now register its instance. 1163 */ 1164 ip_hw_instance = kzalloc(struct_size(ip_hw_instance, 1165 base_addr, 1166 ip->num_base_address), 1167 GFP_KERNEL); 1168 if (!ip_hw_instance) { 1169 DRM_ERROR("no memory for ip_hw_instance"); 1170 return -ENOMEM; 1171 } 1172 ip_hw_instance->hw_id = le16_to_cpu(ip->hw_id); /* == ii */ 1173 ip_hw_instance->num_instance = ip->instance_number; 1174 ip_hw_instance->major = ip->major; 1175 ip_hw_instance->minor = ip->minor; 1176 ip_hw_instance->revision = ip->revision; 1177 ip_hw_instance->harvest = 1178 amdgpu_discovery_get_harvest_info( 1179 adev, ip_hw_instance->hw_id, 1180 ip_hw_instance->num_instance); 1181 ip_hw_instance->num_base_addresses = ip->num_base_address; 1182 1183 for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++) { 1184 if (reg_base_64) 1185 ip_hw_instance->base_addr[kk] = 1186 lower_32_bits(le64_to_cpu(ip->base_address_64[kk])) & 0x3FFFFFFF; 1187 else 1188 ip_hw_instance->base_addr[kk] = ip->base_address[kk]; 1189 } 1190 1191 kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype); 1192 ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset; 1193 res = kobject_add(&ip_hw_instance->kobj, NULL, 1194 "%d", ip_hw_instance->num_instance); 1195 next_ip: 1196 if (reg_base_64) 1197 ip_offset += struct_size(ip, base_address_64, 1198 ip->num_base_address); 1199 else 1200 ip_offset += struct_size(ip, base_address, 1201 ip->num_base_address); 1202 } 1203 } 1204 1205 return 0; 1206 } 1207 1208 static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev) 1209 { 1210 struct ip_discovery_top *ip_top = adev->discovery.ip_top; 1211 uint8_t *discovery_bin = adev->discovery.bin; 1212 struct binary_header *bhdr; 1213 struct ip_discovery_header *ihdr; 1214 struct die_header *dhdr; 1215 struct kset *die_kset = &ip_top->die_kset; 1216 u16 num_dies, die_offset, num_ips; 1217 size_t ip_offset; 1218 int ii, res; 1219 1220 bhdr = (struct binary_header *)discovery_bin; 1221 ihdr = (struct ip_discovery_header 1222 *)(discovery_bin + 1223 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 1224 num_dies = le16_to_cpu(ihdr->num_dies); 1225 1226 DRM_DEBUG("number of dies: %d\n", num_dies); 1227 1228 for (ii = 0; ii < num_dies; ii++) { 1229 struct ip_die_entry *ip_die_entry; 1230 1231 die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset); 1232 dhdr = (struct die_header *)(discovery_bin + die_offset); 1233 num_ips = le16_to_cpu(dhdr->num_ips); 1234 ip_offset = die_offset + sizeof(*dhdr); 1235 1236 /* Add the die to the kset. 1237 * 1238 * dhdr->die_id == ii, which was checked in 1239 * amdgpu_discovery_reg_base_init(). 1240 */ 1241 1242 ip_die_entry = kzalloc(sizeof(*ip_die_entry), GFP_KERNEL); 1243 if (!ip_die_entry) 1244 return -ENOMEM; 1245 1246 ip_die_entry->num_ips = num_ips; 1247 1248 kobject_set_name(&ip_die_entry->ip_kset.kobj, "%d", le16_to_cpu(dhdr->die_id)); 1249 ip_die_entry->ip_kset.kobj.kset = die_kset; 1250 ip_die_entry->ip_kset.kobj.ktype = &ip_die_entry_ktype; 1251 res = kset_register(&ip_die_entry->ip_kset); 1252 if (res) { 1253 DRM_ERROR("Couldn't register ip_die_entry kset"); 1254 kfree(ip_die_entry); 1255 return res; 1256 } 1257 1258 amdgpu_discovery_sysfs_ips(adev, ip_die_entry, ip_offset, num_ips, !!ihdr->base_addr_64_bit); 1259 } 1260 1261 return 0; 1262 } 1263 1264 static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev) 1265 { 1266 uint8_t *discovery_bin = adev->discovery.bin; 1267 struct ip_discovery_top *ip_top; 1268 struct kset *die_kset; 1269 int res, ii; 1270 1271 if (!discovery_bin) 1272 return -EINVAL; 1273 1274 ip_top = kzalloc(sizeof(*ip_top), GFP_KERNEL); 1275 if (!ip_top) 1276 return -ENOMEM; 1277 1278 ip_top->adev = adev; 1279 adev->discovery.ip_top = ip_top; 1280 res = kobject_init_and_add(&ip_top->kobj, &ip_discovery_ktype, 1281 &adev->dev->kobj, "ip_discovery"); 1282 if (res) { 1283 DRM_ERROR("Couldn't init and add ip_discovery/"); 1284 goto Err; 1285 } 1286 1287 die_kset = &ip_top->die_kset; 1288 kobject_set_name(&die_kset->kobj, "%s", "die"); 1289 die_kset->kobj.parent = &ip_top->kobj; 1290 die_kset->kobj.ktype = &die_kobj_ktype; 1291 res = kset_register(&ip_top->die_kset); 1292 if (res) { 1293 DRM_ERROR("Couldn't register die_kset"); 1294 goto Err; 1295 } 1296 1297 for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++) 1298 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr; 1299 ip_hw_instance_attrs[ii] = NULL; 1300 1301 res = amdgpu_discovery_sysfs_recurse(adev); 1302 1303 return res; 1304 Err: 1305 kobject_put(&ip_top->kobj); 1306 return res; 1307 } 1308 1309 /* -------------------------------------------------- */ 1310 1311 #define list_to_kobj(el) container_of(el, struct kobject, entry) 1312 1313 static void amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id *ip_hw_id) 1314 { 1315 struct list_head *el, *tmp; 1316 struct kset *hw_id_kset; 1317 1318 hw_id_kset = &ip_hw_id->hw_id_kset; 1319 spin_lock(&hw_id_kset->list_lock); 1320 list_for_each_prev_safe(el, tmp, &hw_id_kset->list) { 1321 list_del_init(el); 1322 spin_unlock(&hw_id_kset->list_lock); 1323 /* kobject is embedded in ip_hw_instance */ 1324 kobject_put(list_to_kobj(el)); 1325 spin_lock(&hw_id_kset->list_lock); 1326 } 1327 spin_unlock(&hw_id_kset->list_lock); 1328 kobject_put(&ip_hw_id->hw_id_kset.kobj); 1329 } 1330 1331 static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry) 1332 { 1333 struct list_head *el, *tmp; 1334 struct kset *ip_kset; 1335 1336 ip_kset = &ip_die_entry->ip_kset; 1337 spin_lock(&ip_kset->list_lock); 1338 list_for_each_prev_safe(el, tmp, &ip_kset->list) { 1339 list_del_init(el); 1340 spin_unlock(&ip_kset->list_lock); 1341 amdgpu_discovery_sysfs_ip_hw_free(to_ip_hw_id(list_to_kobj(el))); 1342 spin_lock(&ip_kset->list_lock); 1343 } 1344 spin_unlock(&ip_kset->list_lock); 1345 kobject_put(&ip_die_entry->ip_kset.kobj); 1346 } 1347 1348 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev) 1349 { 1350 struct ip_discovery_top *ip_top = adev->discovery.ip_top; 1351 struct list_head *el, *tmp; 1352 struct kset *die_kset; 1353 1354 die_kset = &ip_top->die_kset; 1355 spin_lock(&die_kset->list_lock); 1356 list_for_each_prev_safe(el, tmp, &die_kset->list) { 1357 list_del_init(el); 1358 spin_unlock(&die_kset->list_lock); 1359 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el))); 1360 spin_lock(&die_kset->list_lock); 1361 } 1362 spin_unlock(&die_kset->list_lock); 1363 kobject_put(&ip_top->die_kset.kobj); 1364 kobject_put(&ip_top->kobj); 1365 } 1366 1367 /* ================================================== */ 1368 1369 static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) 1370 { 1371 uint8_t num_base_address, subrev, variant; 1372 struct binary_header *bhdr; 1373 struct ip_discovery_header *ihdr; 1374 struct die_header *dhdr; 1375 uint8_t *discovery_bin; 1376 struct ip_v4 *ip; 1377 uint16_t die_offset; 1378 uint16_t ip_offset; 1379 uint16_t num_dies; 1380 uint32_t wafl_ver; 1381 uint16_t num_ips; 1382 uint16_t hw_id; 1383 uint8_t inst; 1384 int hw_ip; 1385 int i, j, k; 1386 int r; 1387 1388 r = amdgpu_discovery_init(adev); 1389 if (r) 1390 return r; 1391 discovery_bin = adev->discovery.bin; 1392 wafl_ver = 0; 1393 adev->gfx.xcc_mask = 0; 1394 adev->sdma.sdma_mask = 0; 1395 adev->vcn.inst_mask = 0; 1396 adev->jpeg.inst_mask = 0; 1397 bhdr = (struct binary_header *)discovery_bin; 1398 ihdr = (struct ip_discovery_header 1399 *)(discovery_bin + 1400 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 1401 num_dies = le16_to_cpu(ihdr->num_dies); 1402 1403 DRM_DEBUG("number of dies: %d\n", num_dies); 1404 1405 for (i = 0; i < num_dies; i++) { 1406 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 1407 dhdr = (struct die_header *)(discovery_bin + die_offset); 1408 num_ips = le16_to_cpu(dhdr->num_ips); 1409 ip_offset = die_offset + sizeof(*dhdr); 1410 1411 if (le16_to_cpu(dhdr->die_id) != i) { 1412 DRM_ERROR("invalid die id %d, expected %d\n", 1413 le16_to_cpu(dhdr->die_id), i); 1414 return -EINVAL; 1415 } 1416 1417 DRM_DEBUG("number of hardware IPs on die%d: %d\n", 1418 le16_to_cpu(dhdr->die_id), num_ips); 1419 1420 for (j = 0; j < num_ips; j++) { 1421 ip = (struct ip_v4 *)(discovery_bin + ip_offset); 1422 1423 inst = ip->instance_number; 1424 hw_id = le16_to_cpu(ip->hw_id); 1425 if (amdgpu_discovery_validate_ip(adev, inst, hw_id)) 1426 goto next_ip; 1427 1428 num_base_address = ip->num_base_address; 1429 1430 DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n", 1431 hw_id_names[le16_to_cpu(ip->hw_id)], 1432 le16_to_cpu(ip->hw_id), 1433 ip->instance_number, 1434 ip->major, ip->minor, 1435 ip->revision); 1436 1437 if (le16_to_cpu(ip->hw_id) == VCN_HWID) { 1438 /* Bit [5:0]: original revision value 1439 * Bit [7:6]: en/decode capability: 1440 * 0b00 : VCN function normally 1441 * 0b10 : encode is disabled 1442 * 0b01 : decode is disabled 1443 */ 1444 if (adev->vcn.num_vcn_inst < 1445 AMDGPU_MAX_VCN_INSTANCES) { 1446 adev->vcn.inst[adev->vcn.num_vcn_inst].vcn_config = 1447 ip->revision & 0xc0; 1448 adev->vcn.num_vcn_inst++; 1449 adev->vcn.inst_mask |= 1450 (1U << ip->instance_number); 1451 adev->jpeg.inst_mask |= 1452 (1U << ip->instance_number); 1453 } else { 1454 dev_err(adev->dev, "Too many VCN instances: %d vs %d\n", 1455 adev->vcn.num_vcn_inst + 1, 1456 AMDGPU_MAX_VCN_INSTANCES); 1457 } 1458 ip->revision &= ~0xc0; 1459 } 1460 if (le16_to_cpu(ip->hw_id) == SDMA0_HWID || 1461 le16_to_cpu(ip->hw_id) == SDMA1_HWID || 1462 le16_to_cpu(ip->hw_id) == SDMA2_HWID || 1463 le16_to_cpu(ip->hw_id) == SDMA3_HWID) { 1464 if (adev->sdma.num_instances < 1465 AMDGPU_MAX_SDMA_INSTANCES) { 1466 adev->sdma.num_instances++; 1467 adev->sdma.sdma_mask |= 1468 (1U << ip->instance_number); 1469 } else { 1470 dev_err(adev->dev, "Too many SDMA instances: %d vs %d\n", 1471 adev->sdma.num_instances + 1, 1472 AMDGPU_MAX_SDMA_INSTANCES); 1473 } 1474 } 1475 1476 if (le16_to_cpu(ip->hw_id) == VPE_HWID) { 1477 if (adev->vpe.num_instances < AMDGPU_MAX_VPE_INSTANCES) 1478 adev->vpe.num_instances++; 1479 else 1480 dev_err(adev->dev, "Too many VPE instances: %d vs %d\n", 1481 adev->vpe.num_instances + 1, 1482 AMDGPU_MAX_VPE_INSTANCES); 1483 } 1484 1485 if (le16_to_cpu(ip->hw_id) == UMC_HWID) { 1486 adev->gmc.num_umc++; 1487 adev->umc.node_inst_num++; 1488 } 1489 1490 if (le16_to_cpu(ip->hw_id) == GC_HWID) 1491 adev->gfx.xcc_mask |= 1492 (1U << ip->instance_number); 1493 1494 if (!wafl_ver && le16_to_cpu(ip->hw_id) == WAFLC_HWID) 1495 wafl_ver = IP_VERSION_FULL(ip->major, ip->minor, 1496 ip->revision, 0, 0); 1497 1498 for (k = 0; k < num_base_address; k++) { 1499 /* 1500 * convert the endianness of base addresses in place, 1501 * so that we don't need to convert them when accessing adev->reg_offset. 1502 */ 1503 if (ihdr->base_addr_64_bit) 1504 /* Truncate the 64bit base address from ip discovery 1505 * and only store lower 32bit ip base in reg_offset[]. 1506 * Bits > 32 follows ASIC specific format, thus just 1507 * discard them and handle it within specific ASIC. 1508 * By this way reg_offset[] and related helpers can 1509 * stay unchanged. 1510 * The base address is in dwords, thus clear the 1511 * highest 2 bits to store. 1512 */ 1513 ip->base_address[k] = 1514 lower_32_bits(le64_to_cpu(ip->base_address_64[k])) & 0x3FFFFFFF; 1515 else 1516 ip->base_address[k] = le32_to_cpu(ip->base_address[k]); 1517 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]); 1518 } 1519 1520 for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) { 1521 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id) && 1522 hw_id_map[hw_ip] != 0) { 1523 DRM_DEBUG("set register base offset for %s\n", 1524 hw_id_names[le16_to_cpu(ip->hw_id)]); 1525 adev->reg_offset[hw_ip][ip->instance_number] = 1526 ip->base_address; 1527 /* Instance support is somewhat inconsistent. 1528 * SDMA is a good example. Sienna cichlid has 4 total 1529 * SDMA instances, each enumerated separately (HWIDs 1530 * 42, 43, 68, 69). Arcturus has 8 total SDMA instances, 1531 * but they are enumerated as multiple instances of the 1532 * same HWIDs (4x HWID 42, 4x HWID 43). UMC is another 1533 * example. On most chips there are multiple instances 1534 * with the same HWID. 1535 */ 1536 1537 if (ihdr->version < 3) { 1538 subrev = 0; 1539 variant = 0; 1540 } else { 1541 subrev = ip->sub_revision; 1542 variant = ip->variant; 1543 } 1544 1545 adev->ip_versions[hw_ip] 1546 [ip->instance_number] = 1547 IP_VERSION_FULL(ip->major, 1548 ip->minor, 1549 ip->revision, 1550 variant, 1551 subrev); 1552 } 1553 } 1554 1555 next_ip: 1556 if (ihdr->base_addr_64_bit) 1557 ip_offset += struct_size(ip, base_address_64, ip->num_base_address); 1558 else 1559 ip_offset += struct_size(ip, base_address, ip->num_base_address); 1560 } 1561 } 1562 1563 if (wafl_ver && !adev->ip_versions[XGMI_HWIP][0]) 1564 adev->ip_versions[XGMI_HWIP][0] = wafl_ver; 1565 1566 return 0; 1567 } 1568 1569 static void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev) 1570 { 1571 uint8_t *discovery_bin = adev->discovery.bin; 1572 struct ip_discovery_header *ihdr; 1573 struct binary_header *bhdr; 1574 int vcn_harvest_count = 0; 1575 int umc_harvest_count = 0; 1576 uint16_t offset, ihdr_ver; 1577 1578 bhdr = (struct binary_header *)discovery_bin; 1579 offset = le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset); 1580 ihdr = (struct ip_discovery_header *)(discovery_bin + offset); 1581 ihdr_ver = le16_to_cpu(ihdr->version); 1582 /* 1583 * Harvest table does not fit Navi1x and legacy GPUs, 1584 * so read harvest bit per IP data structure to set 1585 * harvest configuration. 1586 */ 1587 if (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 2, 0) && 1588 ihdr_ver <= 2) { 1589 if ((adev->pdev->device == 0x731E && 1590 (adev->pdev->revision == 0xC6 || 1591 adev->pdev->revision == 0xC7)) || 1592 (adev->pdev->device == 0x7340 && 1593 adev->pdev->revision == 0xC9) || 1594 (adev->pdev->device == 0x7360 && 1595 adev->pdev->revision == 0xC7)) 1596 amdgpu_discovery_read_harvest_bit_per_ip(adev, 1597 &vcn_harvest_count); 1598 } else { 1599 amdgpu_discovery_read_from_harvest_table(adev, 1600 &vcn_harvest_count, 1601 &umc_harvest_count); 1602 } 1603 1604 amdgpu_discovery_harvest_config_quirk(adev); 1605 1606 if (vcn_harvest_count == adev->vcn.num_vcn_inst) { 1607 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK; 1608 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK; 1609 } 1610 1611 if (umc_harvest_count < adev->gmc.num_umc) { 1612 adev->gmc.num_umc -= umc_harvest_count; 1613 } 1614 } 1615 1616 union gc_info { 1617 struct gc_info_v1_0 v1; 1618 struct gc_info_v1_1 v1_1; 1619 struct gc_info_v1_2 v1_2; 1620 struct gc_info_v1_3 v1_3; 1621 struct gc_info_v2_0 v2; 1622 struct gc_info_v2_1 v2_1; 1623 }; 1624 1625 static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) 1626 { 1627 uint8_t *discovery_bin = adev->discovery.bin; 1628 struct binary_header *bhdr; 1629 union gc_info *gc_info; 1630 u16 offset; 1631 1632 if (!discovery_bin) { 1633 DRM_ERROR("ip discovery uninitialized\n"); 1634 return -EINVAL; 1635 } 1636 1637 bhdr = (struct binary_header *)discovery_bin; 1638 offset = le16_to_cpu(bhdr->table_list[GC].offset); 1639 1640 if (!offset) 1641 return 0; 1642 1643 gc_info = (union gc_info *)(discovery_bin + offset); 1644 1645 switch (le16_to_cpu(gc_info->v1.header.version_major)) { 1646 case 1: 1647 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se); 1648 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) + 1649 le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa)); 1650 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1651 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se); 1652 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c); 1653 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs); 1654 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds); 1655 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth); 1656 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth); 1657 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer); 1658 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size); 1659 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd); 1660 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu); 1661 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size); 1662 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) / 1663 le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1664 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc); 1665 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 1) { 1666 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v1_1.gc_num_tcp_per_sa); 1667 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v1_1.gc_num_sdp_interface); 1668 adev->gfx.config.gc_num_tcps = le32_to_cpu(gc_info->v1_1.gc_num_tcps); 1669 } 1670 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 2) { 1671 adev->gfx.config.gc_num_tcp_per_wpg = le32_to_cpu(gc_info->v1_2.gc_num_tcp_per_wpg); 1672 adev->gfx.config.gc_tcp_l1_size = le32_to_cpu(gc_info->v1_2.gc_tcp_l1_size); 1673 adev->gfx.config.gc_num_sqc_per_wgp = le32_to_cpu(gc_info->v1_2.gc_num_sqc_per_wgp); 1674 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_instruction_cache_size_per_sqc); 1675 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_data_cache_size_per_sqc); 1676 adev->gfx.config.gc_gl1c_per_sa = le32_to_cpu(gc_info->v1_2.gc_gl1c_per_sa); 1677 adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance); 1678 adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu); 1679 } 1680 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 3) { 1681 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v1_3.gc_tcp_size_per_cu); 1682 adev->gfx.config.gc_tcp_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcp_cache_line_size); 1683 adev->gfx.config.gc_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_size_per_sqc); 1684 adev->gfx.config.gc_instruction_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_line_size); 1685 adev->gfx.config.gc_scalar_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_size_per_sqc); 1686 adev->gfx.config.gc_scalar_data_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_line_size); 1687 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v1_3.gc_tcc_size); 1688 adev->gfx.config.gc_tcc_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcc_cache_line_size); 1689 } 1690 break; 1691 case 2: 1692 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se); 1693 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh); 1694 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1695 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se); 1696 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs); 1697 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs); 1698 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds); 1699 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth); 1700 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth); 1701 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer); 1702 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size); 1703 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd); 1704 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu); 1705 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size); 1706 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) / 1707 le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1708 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc); 1709 if (le16_to_cpu(gc_info->v2.header.version_minor) == 1) { 1710 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v2_1.gc_num_tcp_per_sh); 1711 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v2_1.gc_tcp_size_per_cu); 1712 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v2_1.gc_num_sdp_interface); /* per XCD */ 1713 adev->gfx.config.gc_num_cu_per_sqc = le32_to_cpu(gc_info->v2_1.gc_num_cu_per_sqc); 1714 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_instruction_cache_size_per_sqc); 1715 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_scalar_data_cache_size_per_sqc); 1716 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v2_1.gc_tcc_size); /* per XCD */ 1717 } 1718 break; 1719 default: 1720 dev_err(adev->dev, 1721 "Unhandled GC info table %d.%d\n", 1722 le16_to_cpu(gc_info->v1.header.version_major), 1723 le16_to_cpu(gc_info->v1.header.version_minor)); 1724 return -EINVAL; 1725 } 1726 return 0; 1727 } 1728 1729 union mall_info { 1730 struct mall_info_v1_0 v1; 1731 struct mall_info_v2_0 v2; 1732 }; 1733 1734 static int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev) 1735 { 1736 uint8_t *discovery_bin = adev->discovery.bin; 1737 struct binary_header *bhdr; 1738 union mall_info *mall_info; 1739 u32 u, mall_size_per_umc, m_s_present, half_use; 1740 u64 mall_size; 1741 u16 offset; 1742 1743 if (!discovery_bin) { 1744 DRM_ERROR("ip discovery uninitialized\n"); 1745 return -EINVAL; 1746 } 1747 1748 bhdr = (struct binary_header *)discovery_bin; 1749 offset = le16_to_cpu(bhdr->table_list[MALL_INFO].offset); 1750 1751 if (!offset) 1752 return 0; 1753 1754 mall_info = (union mall_info *)(discovery_bin + offset); 1755 1756 switch (le16_to_cpu(mall_info->v1.header.version_major)) { 1757 case 1: 1758 mall_size = 0; 1759 mall_size_per_umc = le32_to_cpu(mall_info->v1.mall_size_per_m); 1760 m_s_present = le32_to_cpu(mall_info->v1.m_s_present); 1761 half_use = le32_to_cpu(mall_info->v1.m_half_use); 1762 for (u = 0; u < adev->gmc.num_umc; u++) { 1763 if (m_s_present & (1 << u)) 1764 mall_size += mall_size_per_umc * 2; 1765 else if (half_use & (1 << u)) 1766 mall_size += mall_size_per_umc / 2; 1767 else 1768 mall_size += mall_size_per_umc; 1769 } 1770 adev->gmc.mall_size = mall_size; 1771 adev->gmc.m_half_use = half_use; 1772 break; 1773 case 2: 1774 mall_size_per_umc = le32_to_cpu(mall_info->v2.mall_size_per_umc); 1775 adev->gmc.mall_size = (uint64_t)mall_size_per_umc * adev->gmc.num_umc; 1776 break; 1777 default: 1778 dev_err(adev->dev, 1779 "Unhandled MALL info table %d.%d\n", 1780 le16_to_cpu(mall_info->v1.header.version_major), 1781 le16_to_cpu(mall_info->v1.header.version_minor)); 1782 return -EINVAL; 1783 } 1784 return 0; 1785 } 1786 1787 union vcn_info { 1788 struct vcn_info_v1_0 v1; 1789 }; 1790 1791 static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev) 1792 { 1793 uint8_t *discovery_bin = adev->discovery.bin; 1794 struct binary_header *bhdr; 1795 union vcn_info *vcn_info; 1796 u16 offset; 1797 int v; 1798 1799 if (!discovery_bin) { 1800 DRM_ERROR("ip discovery uninitialized\n"); 1801 return -EINVAL; 1802 } 1803 1804 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES 1805 * which is smaller than VCN_INFO_TABLE_MAX_NUM_INSTANCES 1806 * but that may change in the future with new GPUs so keep this 1807 * check for defensive purposes. 1808 */ 1809 if (adev->vcn.num_vcn_inst > VCN_INFO_TABLE_MAX_NUM_INSTANCES) { 1810 dev_err(adev->dev, "invalid vcn instances\n"); 1811 return -EINVAL; 1812 } 1813 1814 bhdr = (struct binary_header *)discovery_bin; 1815 offset = le16_to_cpu(bhdr->table_list[VCN_INFO].offset); 1816 1817 if (!offset) 1818 return 0; 1819 1820 vcn_info = (union vcn_info *)(discovery_bin + offset); 1821 1822 switch (le16_to_cpu(vcn_info->v1.header.version_major)) { 1823 case 1: 1824 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES 1825 * so this won't overflow. 1826 */ 1827 for (v = 0; v < adev->vcn.num_vcn_inst; v++) { 1828 adev->vcn.inst[v].vcn_codec_disable_mask = 1829 le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits); 1830 } 1831 break; 1832 default: 1833 dev_err(adev->dev, 1834 "Unhandled VCN info table %d.%d\n", 1835 le16_to_cpu(vcn_info->v1.header.version_major), 1836 le16_to_cpu(vcn_info->v1.header.version_minor)); 1837 return -EINVAL; 1838 } 1839 return 0; 1840 } 1841 1842 union nps_info { 1843 struct nps_info_v1_0 v1; 1844 }; 1845 1846 static int amdgpu_discovery_refresh_nps_info(struct amdgpu_device *adev, 1847 union nps_info *nps_data) 1848 { 1849 uint64_t vram_size, pos, offset; 1850 struct nps_info_header *nhdr; 1851 struct binary_header bhdr; 1852 uint16_t checksum; 1853 1854 vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20; 1855 pos = vram_size - DISCOVERY_TMR_OFFSET; 1856 amdgpu_device_vram_access(adev, pos, &bhdr, sizeof(bhdr), false); 1857 1858 offset = le16_to_cpu(bhdr.table_list[NPS_INFO].offset); 1859 checksum = le16_to_cpu(bhdr.table_list[NPS_INFO].checksum); 1860 1861 amdgpu_device_vram_access(adev, (pos + offset), nps_data, 1862 sizeof(*nps_data), false); 1863 1864 nhdr = (struct nps_info_header *)(nps_data); 1865 if (!amdgpu_discovery_verify_checksum((uint8_t *)nps_data, 1866 le32_to_cpu(nhdr->size_bytes), 1867 checksum)) { 1868 dev_err(adev->dev, "nps data refresh, checksum mismatch\n"); 1869 return -EINVAL; 1870 } 1871 1872 return 0; 1873 } 1874 1875 int amdgpu_discovery_get_nps_info(struct amdgpu_device *adev, 1876 uint32_t *nps_type, 1877 struct amdgpu_gmc_memrange **ranges, 1878 int *range_cnt, bool refresh) 1879 { 1880 uint8_t *discovery_bin = adev->discovery.bin; 1881 struct amdgpu_gmc_memrange *mem_ranges; 1882 struct binary_header *bhdr; 1883 union nps_info *nps_info; 1884 union nps_info nps_data; 1885 u16 offset; 1886 int i, r; 1887 1888 if (!nps_type || !range_cnt || !ranges) 1889 return -EINVAL; 1890 1891 if (refresh) { 1892 r = amdgpu_discovery_refresh_nps_info(adev, &nps_data); 1893 if (r) 1894 return r; 1895 nps_info = &nps_data; 1896 } else { 1897 if (!discovery_bin) { 1898 dev_err(adev->dev, 1899 "fetch mem range failed, ip discovery uninitialized\n"); 1900 return -EINVAL; 1901 } 1902 1903 bhdr = (struct binary_header *)discovery_bin; 1904 offset = le16_to_cpu(bhdr->table_list[NPS_INFO].offset); 1905 1906 if (!offset) 1907 return -ENOENT; 1908 1909 /* If verification fails, return as if NPS table doesn't exist */ 1910 if (amdgpu_discovery_verify_npsinfo(adev, bhdr)) 1911 return -ENOENT; 1912 1913 nps_info = (union nps_info *)(discovery_bin + offset); 1914 } 1915 1916 switch (le16_to_cpu(nps_info->v1.header.version_major)) { 1917 case 1: 1918 mem_ranges = kvcalloc(nps_info->v1.count, 1919 sizeof(*mem_ranges), 1920 GFP_KERNEL); 1921 if (!mem_ranges) 1922 return -ENOMEM; 1923 *nps_type = nps_info->v1.nps_type; 1924 *range_cnt = nps_info->v1.count; 1925 for (i = 0; i < *range_cnt; i++) { 1926 mem_ranges[i].base_address = 1927 nps_info->v1.instance_info[i].base_address; 1928 mem_ranges[i].limit_address = 1929 nps_info->v1.instance_info[i].limit_address; 1930 mem_ranges[i].nid_mask = -1; 1931 mem_ranges[i].flags = 0; 1932 } 1933 *ranges = mem_ranges; 1934 break; 1935 default: 1936 dev_err(adev->dev, "Unhandled NPS info table %d.%d\n", 1937 le16_to_cpu(nps_info->v1.header.version_major), 1938 le16_to_cpu(nps_info->v1.header.version_minor)); 1939 return -EINVAL; 1940 } 1941 1942 return 0; 1943 } 1944 1945 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev) 1946 { 1947 /* what IP to use for this? */ 1948 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1949 case IP_VERSION(9, 0, 1): 1950 case IP_VERSION(9, 1, 0): 1951 case IP_VERSION(9, 2, 1): 1952 case IP_VERSION(9, 2, 2): 1953 case IP_VERSION(9, 3, 0): 1954 case IP_VERSION(9, 4, 0): 1955 case IP_VERSION(9, 4, 1): 1956 case IP_VERSION(9, 4, 2): 1957 case IP_VERSION(9, 4, 3): 1958 case IP_VERSION(9, 4, 4): 1959 case IP_VERSION(9, 5, 0): 1960 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 1961 break; 1962 case IP_VERSION(10, 1, 10): 1963 case IP_VERSION(10, 1, 1): 1964 case IP_VERSION(10, 1, 2): 1965 case IP_VERSION(10, 1, 3): 1966 case IP_VERSION(10, 1, 4): 1967 case IP_VERSION(10, 3, 0): 1968 case IP_VERSION(10, 3, 1): 1969 case IP_VERSION(10, 3, 2): 1970 case IP_VERSION(10, 3, 3): 1971 case IP_VERSION(10, 3, 4): 1972 case IP_VERSION(10, 3, 5): 1973 case IP_VERSION(10, 3, 6): 1974 case IP_VERSION(10, 3, 7): 1975 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 1976 break; 1977 case IP_VERSION(11, 0, 0): 1978 case IP_VERSION(11, 0, 1): 1979 case IP_VERSION(11, 0, 2): 1980 case IP_VERSION(11, 0, 3): 1981 case IP_VERSION(11, 0, 4): 1982 case IP_VERSION(11, 5, 0): 1983 case IP_VERSION(11, 5, 1): 1984 case IP_VERSION(11, 5, 2): 1985 case IP_VERSION(11, 5, 3): 1986 amdgpu_device_ip_block_add(adev, &soc21_common_ip_block); 1987 break; 1988 case IP_VERSION(12, 0, 0): 1989 case IP_VERSION(12, 0, 1): 1990 amdgpu_device_ip_block_add(adev, &soc24_common_ip_block); 1991 break; 1992 default: 1993 dev_err(adev->dev, 1994 "Failed to add common ip block(GC_HWIP:0x%x)\n", 1995 amdgpu_ip_version(adev, GC_HWIP, 0)); 1996 return -EINVAL; 1997 } 1998 return 0; 1999 } 2000 2001 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev) 2002 { 2003 /* use GC or MMHUB IP version */ 2004 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2005 case IP_VERSION(9, 0, 1): 2006 case IP_VERSION(9, 1, 0): 2007 case IP_VERSION(9, 2, 1): 2008 case IP_VERSION(9, 2, 2): 2009 case IP_VERSION(9, 3, 0): 2010 case IP_VERSION(9, 4, 0): 2011 case IP_VERSION(9, 4, 1): 2012 case IP_VERSION(9, 4, 2): 2013 case IP_VERSION(9, 4, 3): 2014 case IP_VERSION(9, 4, 4): 2015 case IP_VERSION(9, 5, 0): 2016 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 2017 break; 2018 case IP_VERSION(10, 1, 10): 2019 case IP_VERSION(10, 1, 1): 2020 case IP_VERSION(10, 1, 2): 2021 case IP_VERSION(10, 1, 3): 2022 case IP_VERSION(10, 1, 4): 2023 case IP_VERSION(10, 3, 0): 2024 case IP_VERSION(10, 3, 1): 2025 case IP_VERSION(10, 3, 2): 2026 case IP_VERSION(10, 3, 3): 2027 case IP_VERSION(10, 3, 4): 2028 case IP_VERSION(10, 3, 5): 2029 case IP_VERSION(10, 3, 6): 2030 case IP_VERSION(10, 3, 7): 2031 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 2032 break; 2033 case IP_VERSION(11, 0, 0): 2034 case IP_VERSION(11, 0, 1): 2035 case IP_VERSION(11, 0, 2): 2036 case IP_VERSION(11, 0, 3): 2037 case IP_VERSION(11, 0, 4): 2038 case IP_VERSION(11, 5, 0): 2039 case IP_VERSION(11, 5, 1): 2040 case IP_VERSION(11, 5, 2): 2041 case IP_VERSION(11, 5, 3): 2042 amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block); 2043 break; 2044 case IP_VERSION(12, 0, 0): 2045 case IP_VERSION(12, 0, 1): 2046 amdgpu_device_ip_block_add(adev, &gmc_v12_0_ip_block); 2047 break; 2048 default: 2049 dev_err(adev->dev, "Failed to add gmc ip block(GC_HWIP:0x%x)\n", 2050 amdgpu_ip_version(adev, GC_HWIP, 0)); 2051 return -EINVAL; 2052 } 2053 return 0; 2054 } 2055 2056 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev) 2057 { 2058 switch (amdgpu_ip_version(adev, OSSSYS_HWIP, 0)) { 2059 case IP_VERSION(4, 0, 0): 2060 case IP_VERSION(4, 0, 1): 2061 case IP_VERSION(4, 1, 0): 2062 case IP_VERSION(4, 1, 1): 2063 case IP_VERSION(4, 3, 0): 2064 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 2065 break; 2066 case IP_VERSION(4, 2, 0): 2067 case IP_VERSION(4, 2, 1): 2068 case IP_VERSION(4, 4, 0): 2069 case IP_VERSION(4, 4, 2): 2070 case IP_VERSION(4, 4, 5): 2071 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 2072 break; 2073 case IP_VERSION(5, 0, 0): 2074 case IP_VERSION(5, 0, 1): 2075 case IP_VERSION(5, 0, 2): 2076 case IP_VERSION(5, 0, 3): 2077 case IP_VERSION(5, 2, 0): 2078 case IP_VERSION(5, 2, 1): 2079 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 2080 break; 2081 case IP_VERSION(6, 0, 0): 2082 case IP_VERSION(6, 0, 1): 2083 case IP_VERSION(6, 0, 2): 2084 amdgpu_device_ip_block_add(adev, &ih_v6_0_ip_block); 2085 break; 2086 case IP_VERSION(6, 1, 0): 2087 amdgpu_device_ip_block_add(adev, &ih_v6_1_ip_block); 2088 break; 2089 case IP_VERSION(7, 0, 0): 2090 amdgpu_device_ip_block_add(adev, &ih_v7_0_ip_block); 2091 break; 2092 default: 2093 dev_err(adev->dev, 2094 "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n", 2095 amdgpu_ip_version(adev, OSSSYS_HWIP, 0)); 2096 return -EINVAL; 2097 } 2098 return 0; 2099 } 2100 2101 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev) 2102 { 2103 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 2104 case IP_VERSION(9, 0, 0): 2105 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 2106 break; 2107 case IP_VERSION(10, 0, 0): 2108 case IP_VERSION(10, 0, 1): 2109 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); 2110 break; 2111 case IP_VERSION(11, 0, 0): 2112 case IP_VERSION(11, 0, 2): 2113 case IP_VERSION(11, 0, 4): 2114 case IP_VERSION(11, 0, 5): 2115 case IP_VERSION(11, 0, 9): 2116 case IP_VERSION(11, 0, 7): 2117 case IP_VERSION(11, 0, 11): 2118 case IP_VERSION(11, 0, 12): 2119 case IP_VERSION(11, 0, 13): 2120 case IP_VERSION(11, 5, 0): 2121 case IP_VERSION(11, 5, 2): 2122 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 2123 break; 2124 case IP_VERSION(11, 0, 8): 2125 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block); 2126 break; 2127 case IP_VERSION(11, 0, 3): 2128 case IP_VERSION(12, 0, 1): 2129 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); 2130 break; 2131 case IP_VERSION(13, 0, 0): 2132 case IP_VERSION(13, 0, 1): 2133 case IP_VERSION(13, 0, 2): 2134 case IP_VERSION(13, 0, 3): 2135 case IP_VERSION(13, 0, 5): 2136 case IP_VERSION(13, 0, 6): 2137 case IP_VERSION(13, 0, 7): 2138 case IP_VERSION(13, 0, 8): 2139 case IP_VERSION(13, 0, 10): 2140 case IP_VERSION(13, 0, 11): 2141 case IP_VERSION(13, 0, 12): 2142 case IP_VERSION(13, 0, 14): 2143 case IP_VERSION(14, 0, 0): 2144 case IP_VERSION(14, 0, 1): 2145 case IP_VERSION(14, 0, 4): 2146 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); 2147 break; 2148 case IP_VERSION(13, 0, 4): 2149 amdgpu_device_ip_block_add(adev, &psp_v13_0_4_ip_block); 2150 break; 2151 case IP_VERSION(14, 0, 2): 2152 case IP_VERSION(14, 0, 3): 2153 case IP_VERSION(14, 0, 5): 2154 amdgpu_device_ip_block_add(adev, &psp_v14_0_ip_block); 2155 break; 2156 default: 2157 dev_err(adev->dev, 2158 "Failed to add psp ip block(MP0_HWIP:0x%x)\n", 2159 amdgpu_ip_version(adev, MP0_HWIP, 0)); 2160 return -EINVAL; 2161 } 2162 return 0; 2163 } 2164 2165 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev) 2166 { 2167 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2168 case IP_VERSION(9, 0, 0): 2169 case IP_VERSION(10, 0, 0): 2170 case IP_VERSION(10, 0, 1): 2171 case IP_VERSION(11, 0, 2): 2172 if (adev->asic_type == CHIP_ARCTURUS) 2173 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 2174 else 2175 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 2176 break; 2177 case IP_VERSION(11, 0, 0): 2178 case IP_VERSION(11, 0, 5): 2179 case IP_VERSION(11, 0, 9): 2180 case IP_VERSION(11, 0, 7): 2181 case IP_VERSION(11, 0, 11): 2182 case IP_VERSION(11, 0, 12): 2183 case IP_VERSION(11, 0, 13): 2184 case IP_VERSION(11, 5, 0): 2185 case IP_VERSION(11, 5, 2): 2186 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 2187 break; 2188 case IP_VERSION(11, 0, 8): 2189 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) 2190 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 2191 break; 2192 case IP_VERSION(12, 0, 0): 2193 case IP_VERSION(12, 0, 1): 2194 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); 2195 break; 2196 case IP_VERSION(13, 0, 0): 2197 case IP_VERSION(13, 0, 1): 2198 case IP_VERSION(13, 0, 2): 2199 case IP_VERSION(13, 0, 3): 2200 case IP_VERSION(13, 0, 4): 2201 case IP_VERSION(13, 0, 5): 2202 case IP_VERSION(13, 0, 6): 2203 case IP_VERSION(13, 0, 7): 2204 case IP_VERSION(13, 0, 8): 2205 case IP_VERSION(13, 0, 10): 2206 case IP_VERSION(13, 0, 11): 2207 case IP_VERSION(13, 0, 14): 2208 case IP_VERSION(13, 0, 12): 2209 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); 2210 break; 2211 case IP_VERSION(14, 0, 0): 2212 case IP_VERSION(14, 0, 1): 2213 case IP_VERSION(14, 0, 2): 2214 case IP_VERSION(14, 0, 3): 2215 case IP_VERSION(14, 0, 4): 2216 case IP_VERSION(14, 0, 5): 2217 amdgpu_device_ip_block_add(adev, &smu_v14_0_ip_block); 2218 break; 2219 default: 2220 dev_err(adev->dev, 2221 "Failed to add smu ip block(MP1_HWIP:0x%x)\n", 2222 amdgpu_ip_version(adev, MP1_HWIP, 0)); 2223 return -EINVAL; 2224 } 2225 return 0; 2226 } 2227 2228 #if defined(CONFIG_DRM_AMD_DC) 2229 static void amdgpu_discovery_set_sriov_display(struct amdgpu_device *adev) 2230 { 2231 amdgpu_device_set_sriov_virtual_display(adev); 2232 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2233 } 2234 #endif 2235 2236 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev) 2237 { 2238 if (adev->enable_virtual_display) { 2239 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2240 return 0; 2241 } 2242 2243 if (!amdgpu_device_has_dc_support(adev)) 2244 return 0; 2245 2246 #if defined(CONFIG_DRM_AMD_DC) 2247 if (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2248 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2249 case IP_VERSION(1, 0, 0): 2250 case IP_VERSION(1, 0, 1): 2251 case IP_VERSION(2, 0, 2): 2252 case IP_VERSION(2, 0, 0): 2253 case IP_VERSION(2, 0, 3): 2254 case IP_VERSION(2, 1, 0): 2255 case IP_VERSION(3, 0, 0): 2256 case IP_VERSION(3, 0, 2): 2257 case IP_VERSION(3, 0, 3): 2258 case IP_VERSION(3, 0, 1): 2259 case IP_VERSION(3, 1, 2): 2260 case IP_VERSION(3, 1, 3): 2261 case IP_VERSION(3, 1, 4): 2262 case IP_VERSION(3, 1, 5): 2263 case IP_VERSION(3, 1, 6): 2264 case IP_VERSION(3, 2, 0): 2265 case IP_VERSION(3, 2, 1): 2266 case IP_VERSION(3, 5, 0): 2267 case IP_VERSION(3, 5, 1): 2268 case IP_VERSION(3, 6, 0): 2269 case IP_VERSION(4, 1, 0): 2270 /* TODO: Fix IP version. DC code expects version 4.0.1 */ 2271 if (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(4, 1, 0)) 2272 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(4, 0, 1); 2273 2274 if (amdgpu_sriov_vf(adev)) 2275 amdgpu_discovery_set_sriov_display(adev); 2276 else 2277 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2278 break; 2279 default: 2280 dev_err(adev->dev, 2281 "Failed to add dm ip block(DCE_HWIP:0x%x)\n", 2282 amdgpu_ip_version(adev, DCE_HWIP, 0)); 2283 return -EINVAL; 2284 } 2285 } else if (amdgpu_ip_version(adev, DCI_HWIP, 0)) { 2286 switch (amdgpu_ip_version(adev, DCI_HWIP, 0)) { 2287 case IP_VERSION(12, 0, 0): 2288 case IP_VERSION(12, 0, 1): 2289 case IP_VERSION(12, 1, 0): 2290 if (amdgpu_sriov_vf(adev)) 2291 amdgpu_discovery_set_sriov_display(adev); 2292 else 2293 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2294 break; 2295 default: 2296 dev_err(adev->dev, 2297 "Failed to add dm ip block(DCI_HWIP:0x%x)\n", 2298 amdgpu_ip_version(adev, DCI_HWIP, 0)); 2299 return -EINVAL; 2300 } 2301 } 2302 #endif 2303 return 0; 2304 } 2305 2306 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) 2307 { 2308 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2309 case IP_VERSION(9, 0, 1): 2310 case IP_VERSION(9, 1, 0): 2311 case IP_VERSION(9, 2, 1): 2312 case IP_VERSION(9, 2, 2): 2313 case IP_VERSION(9, 3, 0): 2314 case IP_VERSION(9, 4, 0): 2315 case IP_VERSION(9, 4, 1): 2316 case IP_VERSION(9, 4, 2): 2317 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 2318 break; 2319 case IP_VERSION(9, 4, 3): 2320 case IP_VERSION(9, 4, 4): 2321 case IP_VERSION(9, 5, 0): 2322 amdgpu_device_ip_block_add(adev, &gfx_v9_4_3_ip_block); 2323 break; 2324 case IP_VERSION(10, 1, 10): 2325 case IP_VERSION(10, 1, 2): 2326 case IP_VERSION(10, 1, 1): 2327 case IP_VERSION(10, 1, 3): 2328 case IP_VERSION(10, 1, 4): 2329 case IP_VERSION(10, 3, 0): 2330 case IP_VERSION(10, 3, 2): 2331 case IP_VERSION(10, 3, 1): 2332 case IP_VERSION(10, 3, 4): 2333 case IP_VERSION(10, 3, 5): 2334 case IP_VERSION(10, 3, 6): 2335 case IP_VERSION(10, 3, 3): 2336 case IP_VERSION(10, 3, 7): 2337 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 2338 break; 2339 case IP_VERSION(11, 0, 0): 2340 case IP_VERSION(11, 0, 1): 2341 case IP_VERSION(11, 0, 2): 2342 case IP_VERSION(11, 0, 3): 2343 case IP_VERSION(11, 0, 4): 2344 case IP_VERSION(11, 5, 0): 2345 case IP_VERSION(11, 5, 1): 2346 case IP_VERSION(11, 5, 2): 2347 case IP_VERSION(11, 5, 3): 2348 amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block); 2349 break; 2350 case IP_VERSION(12, 0, 0): 2351 case IP_VERSION(12, 0, 1): 2352 amdgpu_device_ip_block_add(adev, &gfx_v12_0_ip_block); 2353 break; 2354 default: 2355 dev_err(adev->dev, "Failed to add gfx ip block(GC_HWIP:0x%x)\n", 2356 amdgpu_ip_version(adev, GC_HWIP, 0)); 2357 return -EINVAL; 2358 } 2359 return 0; 2360 } 2361 2362 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev) 2363 { 2364 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 2365 case IP_VERSION(4, 0, 0): 2366 case IP_VERSION(4, 0, 1): 2367 case IP_VERSION(4, 1, 0): 2368 case IP_VERSION(4, 1, 1): 2369 case IP_VERSION(4, 1, 2): 2370 case IP_VERSION(4, 2, 0): 2371 case IP_VERSION(4, 2, 2): 2372 case IP_VERSION(4, 4, 0): 2373 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 2374 break; 2375 case IP_VERSION(4, 4, 2): 2376 case IP_VERSION(4, 4, 5): 2377 case IP_VERSION(4, 4, 4): 2378 amdgpu_device_ip_block_add(adev, &sdma_v4_4_2_ip_block); 2379 break; 2380 case IP_VERSION(5, 0, 0): 2381 case IP_VERSION(5, 0, 1): 2382 case IP_VERSION(5, 0, 2): 2383 case IP_VERSION(5, 0, 5): 2384 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 2385 break; 2386 case IP_VERSION(5, 2, 0): 2387 case IP_VERSION(5, 2, 2): 2388 case IP_VERSION(5, 2, 4): 2389 case IP_VERSION(5, 2, 5): 2390 case IP_VERSION(5, 2, 6): 2391 case IP_VERSION(5, 2, 3): 2392 case IP_VERSION(5, 2, 1): 2393 case IP_VERSION(5, 2, 7): 2394 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 2395 break; 2396 case IP_VERSION(6, 0, 0): 2397 case IP_VERSION(6, 0, 1): 2398 case IP_VERSION(6, 0, 2): 2399 case IP_VERSION(6, 0, 3): 2400 case IP_VERSION(6, 1, 0): 2401 case IP_VERSION(6, 1, 1): 2402 case IP_VERSION(6, 1, 2): 2403 case IP_VERSION(6, 1, 3): 2404 amdgpu_device_ip_block_add(adev, &sdma_v6_0_ip_block); 2405 break; 2406 case IP_VERSION(7, 0, 0): 2407 case IP_VERSION(7, 0, 1): 2408 amdgpu_device_ip_block_add(adev, &sdma_v7_0_ip_block); 2409 break; 2410 default: 2411 dev_err(adev->dev, 2412 "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n", 2413 amdgpu_ip_version(adev, SDMA0_HWIP, 0)); 2414 return -EINVAL; 2415 } 2416 2417 return 0; 2418 } 2419 2420 static int amdgpu_discovery_set_ras_ip_blocks(struct amdgpu_device *adev) 2421 { 2422 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 2423 case IP_VERSION(13, 0, 6): 2424 case IP_VERSION(13, 0, 12): 2425 case IP_VERSION(13, 0, 14): 2426 amdgpu_device_ip_block_add(adev, &ras_v1_0_ip_block); 2427 break; 2428 default: 2429 break; 2430 } 2431 return 0; 2432 } 2433 2434 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) 2435 { 2436 if (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 2437 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 2438 case IP_VERSION(7, 0, 0): 2439 case IP_VERSION(7, 2, 0): 2440 /* UVD is not supported on vega20 SR-IOV */ 2441 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 2442 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); 2443 break; 2444 default: 2445 dev_err(adev->dev, 2446 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n", 2447 amdgpu_ip_version(adev, UVD_HWIP, 0)); 2448 return -EINVAL; 2449 } 2450 switch (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 2451 case IP_VERSION(4, 0, 0): 2452 case IP_VERSION(4, 1, 0): 2453 /* VCE is not supported on vega20 SR-IOV */ 2454 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 2455 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); 2456 break; 2457 default: 2458 dev_err(adev->dev, 2459 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n", 2460 amdgpu_ip_version(adev, VCE_HWIP, 0)); 2461 return -EINVAL; 2462 } 2463 } else { 2464 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 2465 case IP_VERSION(1, 0, 0): 2466 case IP_VERSION(1, 0, 1): 2467 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); 2468 break; 2469 case IP_VERSION(2, 0, 0): 2470 case IP_VERSION(2, 0, 2): 2471 case IP_VERSION(2, 2, 0): 2472 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 2473 if (!amdgpu_sriov_vf(adev)) 2474 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 2475 break; 2476 case IP_VERSION(2, 0, 3): 2477 break; 2478 case IP_VERSION(2, 5, 0): 2479 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 2480 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block); 2481 break; 2482 case IP_VERSION(2, 6, 0): 2483 amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block); 2484 amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block); 2485 break; 2486 case IP_VERSION(3, 0, 0): 2487 case IP_VERSION(3, 0, 16): 2488 case IP_VERSION(3, 1, 1): 2489 case IP_VERSION(3, 1, 2): 2490 case IP_VERSION(3, 0, 2): 2491 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 2492 if (!amdgpu_sriov_vf(adev)) 2493 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 2494 break; 2495 case IP_VERSION(3, 0, 33): 2496 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 2497 break; 2498 case IP_VERSION(4, 0, 0): 2499 case IP_VERSION(4, 0, 2): 2500 case IP_VERSION(4, 0, 4): 2501 amdgpu_device_ip_block_add(adev, &vcn_v4_0_ip_block); 2502 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block); 2503 break; 2504 case IP_VERSION(4, 0, 3): 2505 amdgpu_device_ip_block_add(adev, &vcn_v4_0_3_ip_block); 2506 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_3_ip_block); 2507 break; 2508 case IP_VERSION(4, 0, 5): 2509 case IP_VERSION(4, 0, 6): 2510 amdgpu_device_ip_block_add(adev, &vcn_v4_0_5_ip_block); 2511 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_5_ip_block); 2512 break; 2513 case IP_VERSION(5, 0, 0): 2514 amdgpu_device_ip_block_add(adev, &vcn_v5_0_0_ip_block); 2515 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_0_ip_block); 2516 break; 2517 case IP_VERSION(5, 0, 1): 2518 amdgpu_device_ip_block_add(adev, &vcn_v5_0_1_ip_block); 2519 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_1_ip_block); 2520 break; 2521 default: 2522 dev_err(adev->dev, 2523 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n", 2524 amdgpu_ip_version(adev, UVD_HWIP, 0)); 2525 return -EINVAL; 2526 } 2527 } 2528 return 0; 2529 } 2530 2531 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev) 2532 { 2533 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2534 case IP_VERSION(11, 0, 0): 2535 case IP_VERSION(11, 0, 1): 2536 case IP_VERSION(11, 0, 2): 2537 case IP_VERSION(11, 0, 3): 2538 case IP_VERSION(11, 0, 4): 2539 case IP_VERSION(11, 5, 0): 2540 case IP_VERSION(11, 5, 1): 2541 case IP_VERSION(11, 5, 2): 2542 case IP_VERSION(11, 5, 3): 2543 amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block); 2544 adev->enable_mes = true; 2545 adev->enable_mes_kiq = true; 2546 break; 2547 case IP_VERSION(12, 0, 0): 2548 case IP_VERSION(12, 0, 1): 2549 amdgpu_device_ip_block_add(adev, &mes_v12_0_ip_block); 2550 adev->enable_mes = true; 2551 adev->enable_mes_kiq = true; 2552 if (amdgpu_uni_mes) 2553 adev->enable_uni_mes = true; 2554 break; 2555 default: 2556 break; 2557 } 2558 return 0; 2559 } 2560 2561 static void amdgpu_discovery_init_soc_config(struct amdgpu_device *adev) 2562 { 2563 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2564 case IP_VERSION(9, 4, 3): 2565 case IP_VERSION(9, 4, 4): 2566 case IP_VERSION(9, 5, 0): 2567 aqua_vanjaram_init_soc_config(adev); 2568 break; 2569 default: 2570 break; 2571 } 2572 } 2573 2574 static int amdgpu_discovery_set_vpe_ip_blocks(struct amdgpu_device *adev) 2575 { 2576 switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) { 2577 case IP_VERSION(6, 1, 0): 2578 case IP_VERSION(6, 1, 1): 2579 case IP_VERSION(6, 1, 3): 2580 amdgpu_device_ip_block_add(adev, &vpe_v6_1_ip_block); 2581 break; 2582 default: 2583 break; 2584 } 2585 2586 return 0; 2587 } 2588 2589 static int amdgpu_discovery_set_umsch_mm_ip_blocks(struct amdgpu_device *adev) 2590 { 2591 switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) { 2592 case IP_VERSION(4, 0, 5): 2593 case IP_VERSION(4, 0, 6): 2594 if (amdgpu_umsch_mm & 0x1) { 2595 amdgpu_device_ip_block_add(adev, &umsch_mm_v4_0_ip_block); 2596 adev->enable_umsch_mm = true; 2597 } 2598 break; 2599 default: 2600 break; 2601 } 2602 2603 return 0; 2604 } 2605 2606 static int amdgpu_discovery_set_isp_ip_blocks(struct amdgpu_device *adev) 2607 { 2608 #if defined(CONFIG_DRM_AMD_ISP) 2609 switch (amdgpu_ip_version(adev, ISP_HWIP, 0)) { 2610 case IP_VERSION(4, 1, 0): 2611 amdgpu_device_ip_block_add(adev, &isp_v4_1_0_ip_block); 2612 break; 2613 case IP_VERSION(4, 1, 1): 2614 amdgpu_device_ip_block_add(adev, &isp_v4_1_1_ip_block); 2615 break; 2616 default: 2617 break; 2618 } 2619 #endif 2620 2621 return 0; 2622 } 2623 2624 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 2625 { 2626 int r; 2627 2628 switch (adev->asic_type) { 2629 case CHIP_VEGA10: 2630 /* This is not fatal. We only need the discovery 2631 * binary for sysfs. We don't need it for a 2632 * functional system. 2633 */ 2634 amdgpu_discovery_init(adev); 2635 vega10_reg_base_init(adev); 2636 adev->sdma.num_instances = 2; 2637 adev->sdma.sdma_mask = 3; 2638 adev->gmc.num_umc = 4; 2639 adev->gfx.xcc_mask = 1; 2640 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0); 2641 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0); 2642 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0); 2643 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0); 2644 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0); 2645 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0); 2646 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 2647 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0); 2648 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0); 2649 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 2650 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 2651 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 2652 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0); 2653 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1); 2654 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 2655 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 2656 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0); 2657 break; 2658 case CHIP_VEGA12: 2659 /* This is not fatal. We only need the discovery 2660 * binary for sysfs. We don't need it for a 2661 * functional system. 2662 */ 2663 amdgpu_discovery_init(adev); 2664 vega10_reg_base_init(adev); 2665 adev->sdma.num_instances = 2; 2666 adev->sdma.sdma_mask = 3; 2667 adev->gmc.num_umc = 4; 2668 adev->gfx.xcc_mask = 1; 2669 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0); 2670 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0); 2671 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1); 2672 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1); 2673 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1); 2674 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1); 2675 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0); 2676 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0); 2677 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0); 2678 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 2679 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 2680 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 2681 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1); 2682 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1); 2683 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 2684 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 2685 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1); 2686 break; 2687 case CHIP_RAVEN: 2688 /* This is not fatal. We only need the discovery 2689 * binary for sysfs. We don't need it for a 2690 * functional system. 2691 */ 2692 amdgpu_discovery_init(adev); 2693 vega10_reg_base_init(adev); 2694 adev->sdma.num_instances = 1; 2695 adev->sdma.sdma_mask = 1; 2696 adev->vcn.num_vcn_inst = 1; 2697 adev->gmc.num_umc = 2; 2698 adev->gfx.xcc_mask = 1; 2699 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { 2700 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0); 2701 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0); 2702 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1); 2703 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1); 2704 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1); 2705 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1); 2706 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1); 2707 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0); 2708 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1); 2709 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1); 2710 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0); 2711 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1); 2712 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2); 2713 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1); 2714 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1); 2715 adev->ip_versions[ISP_HWIP][0] = IP_VERSION(2, 0, 0); 2716 } else { 2717 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0); 2718 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0); 2719 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0); 2720 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0); 2721 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0); 2722 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 2723 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0); 2724 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0); 2725 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0); 2726 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0); 2727 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0); 2728 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0); 2729 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0); 2730 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0); 2731 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0); 2732 adev->ip_versions[ISP_HWIP][0] = IP_VERSION(2, 0, 0); 2733 } 2734 break; 2735 case CHIP_VEGA20: 2736 /* This is not fatal. We only need the discovery 2737 * binary for sysfs. We don't need it for a 2738 * functional system. 2739 */ 2740 amdgpu_discovery_init(adev); 2741 vega20_reg_base_init(adev); 2742 adev->sdma.num_instances = 2; 2743 adev->sdma.sdma_mask = 3; 2744 adev->gmc.num_umc = 8; 2745 adev->gfx.xcc_mask = 1; 2746 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2747 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2748 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0); 2749 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0); 2750 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0); 2751 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0); 2752 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0); 2753 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0); 2754 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1); 2755 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2); 2756 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2757 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2); 2758 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2); 2759 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0); 2760 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0); 2761 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0); 2762 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0); 2763 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0); 2764 break; 2765 case CHIP_ARCTURUS: 2766 /* This is not fatal. We only need the discovery 2767 * binary for sysfs. We don't need it for a 2768 * functional system. 2769 */ 2770 amdgpu_discovery_init(adev); 2771 arct_reg_base_init(adev); 2772 adev->sdma.num_instances = 8; 2773 adev->sdma.sdma_mask = 0xff; 2774 adev->vcn.num_vcn_inst = 2; 2775 adev->gmc.num_umc = 8; 2776 adev->gfx.xcc_mask = 1; 2777 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2778 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2779 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1); 2780 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1); 2781 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2); 2782 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2); 2783 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2); 2784 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2); 2785 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2); 2786 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2); 2787 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2); 2788 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2); 2789 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1); 2790 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1); 2791 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2); 2792 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4); 2793 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2794 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3); 2795 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3); 2796 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1); 2797 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0); 2798 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0); 2799 break; 2800 case CHIP_ALDEBARAN: 2801 /* This is not fatal. We only need the discovery 2802 * binary for sysfs. We don't need it for a 2803 * functional system. 2804 */ 2805 amdgpu_discovery_init(adev); 2806 aldebaran_reg_base_init(adev); 2807 adev->sdma.num_instances = 5; 2808 adev->sdma.sdma_mask = 0x1f; 2809 adev->vcn.num_vcn_inst = 2; 2810 adev->gmc.num_umc = 4; 2811 adev->gfx.xcc_mask = 1; 2812 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2813 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2814 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0); 2815 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0); 2816 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0); 2817 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0); 2818 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0); 2819 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0); 2820 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0); 2821 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2); 2822 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4); 2823 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0); 2824 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2); 2825 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2); 2826 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2); 2827 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2); 2828 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2); 2829 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0); 2830 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0); 2831 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0); 2832 break; 2833 case CHIP_CYAN_SKILLFISH: 2834 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 2835 r = amdgpu_discovery_reg_base_init(adev); 2836 if (r) 2837 return -EINVAL; 2838 2839 amdgpu_discovery_harvest_ip(adev); 2840 amdgpu_discovery_get_gfx_info(adev); 2841 amdgpu_discovery_get_mall_info(adev); 2842 amdgpu_discovery_get_vcn_info(adev); 2843 } else { 2844 cyan_skillfish_reg_base_init(adev); 2845 adev->sdma.num_instances = 2; 2846 adev->sdma.sdma_mask = 3; 2847 adev->gfx.xcc_mask = 1; 2848 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(2, 0, 3); 2849 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(2, 0, 3); 2850 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(5, 0, 1); 2851 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(5, 0, 1); 2852 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(5, 0, 1); 2853 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(5, 0, 1); 2854 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 5, 0); 2855 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(2, 1, 1); 2856 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(8, 1, 1); 2857 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 8); 2858 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 8); 2859 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 1); 2860 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 8); 2861 adev->ip_versions[GC_HWIP][0] = IP_VERSION(10, 1, 3); 2862 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 0, 3); 2863 } 2864 break; 2865 default: 2866 r = amdgpu_discovery_reg_base_init(adev); 2867 if (r) { 2868 drm_err(&adev->ddev, "discovery failed: %d\n", r); 2869 return r; 2870 } 2871 2872 amdgpu_discovery_harvest_ip(adev); 2873 amdgpu_discovery_get_gfx_info(adev); 2874 amdgpu_discovery_get_mall_info(adev); 2875 amdgpu_discovery_get_vcn_info(adev); 2876 break; 2877 } 2878 2879 amdgpu_discovery_init_soc_config(adev); 2880 amdgpu_discovery_sysfs_init(adev); 2881 2882 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2883 case IP_VERSION(9, 0, 1): 2884 case IP_VERSION(9, 2, 1): 2885 case IP_VERSION(9, 4, 0): 2886 case IP_VERSION(9, 4, 1): 2887 case IP_VERSION(9, 4, 2): 2888 case IP_VERSION(9, 4, 3): 2889 case IP_VERSION(9, 4, 4): 2890 case IP_VERSION(9, 5, 0): 2891 adev->family = AMDGPU_FAMILY_AI; 2892 break; 2893 case IP_VERSION(9, 1, 0): 2894 case IP_VERSION(9, 2, 2): 2895 case IP_VERSION(9, 3, 0): 2896 adev->family = AMDGPU_FAMILY_RV; 2897 break; 2898 case IP_VERSION(10, 1, 10): 2899 case IP_VERSION(10, 1, 1): 2900 case IP_VERSION(10, 1, 2): 2901 case IP_VERSION(10, 1, 3): 2902 case IP_VERSION(10, 1, 4): 2903 case IP_VERSION(10, 3, 0): 2904 case IP_VERSION(10, 3, 2): 2905 case IP_VERSION(10, 3, 4): 2906 case IP_VERSION(10, 3, 5): 2907 adev->family = AMDGPU_FAMILY_NV; 2908 break; 2909 case IP_VERSION(10, 3, 1): 2910 adev->family = AMDGPU_FAMILY_VGH; 2911 adev->apu_flags |= AMD_APU_IS_VANGOGH; 2912 break; 2913 case IP_VERSION(10, 3, 3): 2914 adev->family = AMDGPU_FAMILY_YC; 2915 break; 2916 case IP_VERSION(10, 3, 6): 2917 adev->family = AMDGPU_FAMILY_GC_10_3_6; 2918 break; 2919 case IP_VERSION(10, 3, 7): 2920 adev->family = AMDGPU_FAMILY_GC_10_3_7; 2921 break; 2922 case IP_VERSION(11, 0, 0): 2923 case IP_VERSION(11, 0, 2): 2924 case IP_VERSION(11, 0, 3): 2925 adev->family = AMDGPU_FAMILY_GC_11_0_0; 2926 break; 2927 case IP_VERSION(11, 0, 1): 2928 case IP_VERSION(11, 0, 4): 2929 adev->family = AMDGPU_FAMILY_GC_11_0_1; 2930 break; 2931 case IP_VERSION(11, 5, 0): 2932 case IP_VERSION(11, 5, 1): 2933 case IP_VERSION(11, 5, 2): 2934 case IP_VERSION(11, 5, 3): 2935 adev->family = AMDGPU_FAMILY_GC_11_5_0; 2936 break; 2937 case IP_VERSION(12, 0, 0): 2938 case IP_VERSION(12, 0, 1): 2939 adev->family = AMDGPU_FAMILY_GC_12_0_0; 2940 break; 2941 default: 2942 return -EINVAL; 2943 } 2944 2945 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2946 case IP_VERSION(9, 1, 0): 2947 case IP_VERSION(9, 2, 2): 2948 case IP_VERSION(9, 3, 0): 2949 case IP_VERSION(10, 1, 3): 2950 case IP_VERSION(10, 1, 4): 2951 case IP_VERSION(10, 3, 1): 2952 case IP_VERSION(10, 3, 3): 2953 case IP_VERSION(10, 3, 6): 2954 case IP_VERSION(10, 3, 7): 2955 case IP_VERSION(11, 0, 1): 2956 case IP_VERSION(11, 0, 4): 2957 case IP_VERSION(11, 5, 0): 2958 case IP_VERSION(11, 5, 1): 2959 case IP_VERSION(11, 5, 2): 2960 case IP_VERSION(11, 5, 3): 2961 adev->flags |= AMD_IS_APU; 2962 break; 2963 default: 2964 break; 2965 } 2966 2967 /* set NBIO version */ 2968 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { 2969 case IP_VERSION(6, 1, 0): 2970 case IP_VERSION(6, 2, 0): 2971 adev->nbio.funcs = &nbio_v6_1_funcs; 2972 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; 2973 break; 2974 case IP_VERSION(7, 0, 0): 2975 case IP_VERSION(7, 0, 1): 2976 case IP_VERSION(2, 5, 0): 2977 adev->nbio.funcs = &nbio_v7_0_funcs; 2978 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; 2979 break; 2980 case IP_VERSION(7, 4, 0): 2981 case IP_VERSION(7, 4, 1): 2982 case IP_VERSION(7, 4, 4): 2983 adev->nbio.funcs = &nbio_v7_4_funcs; 2984 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; 2985 break; 2986 case IP_VERSION(7, 9, 0): 2987 case IP_VERSION(7, 9, 1): 2988 adev->nbio.funcs = &nbio_v7_9_funcs; 2989 adev->nbio.hdp_flush_reg = &nbio_v7_9_hdp_flush_reg; 2990 break; 2991 case IP_VERSION(7, 11, 0): 2992 case IP_VERSION(7, 11, 1): 2993 case IP_VERSION(7, 11, 2): 2994 case IP_VERSION(7, 11, 3): 2995 adev->nbio.funcs = &nbio_v7_11_funcs; 2996 adev->nbio.hdp_flush_reg = &nbio_v7_11_hdp_flush_reg; 2997 break; 2998 case IP_VERSION(7, 2, 0): 2999 case IP_VERSION(7, 2, 1): 3000 case IP_VERSION(7, 3, 0): 3001 case IP_VERSION(7, 5, 0): 3002 case IP_VERSION(7, 5, 1): 3003 adev->nbio.funcs = &nbio_v7_2_funcs; 3004 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; 3005 break; 3006 case IP_VERSION(2, 1, 1): 3007 case IP_VERSION(2, 3, 0): 3008 case IP_VERSION(2, 3, 1): 3009 case IP_VERSION(2, 3, 2): 3010 case IP_VERSION(3, 3, 0): 3011 case IP_VERSION(3, 3, 1): 3012 case IP_VERSION(3, 3, 2): 3013 case IP_VERSION(3, 3, 3): 3014 adev->nbio.funcs = &nbio_v2_3_funcs; 3015 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 3016 break; 3017 case IP_VERSION(4, 3, 0): 3018 case IP_VERSION(4, 3, 1): 3019 if (amdgpu_sriov_vf(adev)) 3020 adev->nbio.funcs = &nbio_v4_3_sriov_funcs; 3021 else 3022 adev->nbio.funcs = &nbio_v4_3_funcs; 3023 adev->nbio.hdp_flush_reg = &nbio_v4_3_hdp_flush_reg; 3024 break; 3025 case IP_VERSION(7, 7, 0): 3026 case IP_VERSION(7, 7, 1): 3027 adev->nbio.funcs = &nbio_v7_7_funcs; 3028 adev->nbio.hdp_flush_reg = &nbio_v7_7_hdp_flush_reg; 3029 break; 3030 case IP_VERSION(6, 3, 1): 3031 adev->nbio.funcs = &nbif_v6_3_1_funcs; 3032 adev->nbio.hdp_flush_reg = &nbif_v6_3_1_hdp_flush_reg; 3033 break; 3034 default: 3035 break; 3036 } 3037 3038 switch (amdgpu_ip_version(adev, HDP_HWIP, 0)) { 3039 case IP_VERSION(4, 0, 0): 3040 case IP_VERSION(4, 0, 1): 3041 case IP_VERSION(4, 1, 0): 3042 case IP_VERSION(4, 1, 1): 3043 case IP_VERSION(4, 1, 2): 3044 case IP_VERSION(4, 2, 0): 3045 case IP_VERSION(4, 2, 1): 3046 case IP_VERSION(4, 4, 0): 3047 case IP_VERSION(4, 4, 2): 3048 case IP_VERSION(4, 4, 5): 3049 adev->hdp.funcs = &hdp_v4_0_funcs; 3050 break; 3051 case IP_VERSION(5, 0, 0): 3052 case IP_VERSION(5, 0, 1): 3053 case IP_VERSION(5, 0, 2): 3054 case IP_VERSION(5, 0, 3): 3055 case IP_VERSION(5, 0, 4): 3056 case IP_VERSION(5, 2, 0): 3057 adev->hdp.funcs = &hdp_v5_0_funcs; 3058 break; 3059 case IP_VERSION(5, 2, 1): 3060 adev->hdp.funcs = &hdp_v5_2_funcs; 3061 break; 3062 case IP_VERSION(6, 0, 0): 3063 case IP_VERSION(6, 0, 1): 3064 case IP_VERSION(6, 1, 0): 3065 adev->hdp.funcs = &hdp_v6_0_funcs; 3066 break; 3067 case IP_VERSION(7, 0, 0): 3068 adev->hdp.funcs = &hdp_v7_0_funcs; 3069 break; 3070 default: 3071 break; 3072 } 3073 3074 switch (amdgpu_ip_version(adev, DF_HWIP, 0)) { 3075 case IP_VERSION(3, 6, 0): 3076 case IP_VERSION(3, 6, 1): 3077 case IP_VERSION(3, 6, 2): 3078 adev->df.funcs = &df_v3_6_funcs; 3079 break; 3080 case IP_VERSION(2, 1, 0): 3081 case IP_VERSION(2, 1, 1): 3082 case IP_VERSION(2, 5, 0): 3083 case IP_VERSION(3, 5, 1): 3084 case IP_VERSION(3, 5, 2): 3085 adev->df.funcs = &df_v1_7_funcs; 3086 break; 3087 case IP_VERSION(4, 3, 0): 3088 adev->df.funcs = &df_v4_3_funcs; 3089 break; 3090 case IP_VERSION(4, 6, 2): 3091 adev->df.funcs = &df_v4_6_2_funcs; 3092 break; 3093 case IP_VERSION(4, 15, 0): 3094 case IP_VERSION(4, 15, 1): 3095 adev->df.funcs = &df_v4_15_funcs; 3096 break; 3097 default: 3098 break; 3099 } 3100 3101 switch (amdgpu_ip_version(adev, SMUIO_HWIP, 0)) { 3102 case IP_VERSION(9, 0, 0): 3103 case IP_VERSION(9, 0, 1): 3104 case IP_VERSION(10, 0, 0): 3105 case IP_VERSION(10, 0, 1): 3106 case IP_VERSION(10, 0, 2): 3107 adev->smuio.funcs = &smuio_v9_0_funcs; 3108 break; 3109 case IP_VERSION(11, 0, 0): 3110 case IP_VERSION(11, 0, 2): 3111 case IP_VERSION(11, 0, 3): 3112 case IP_VERSION(11, 0, 4): 3113 case IP_VERSION(11, 0, 7): 3114 case IP_VERSION(11, 0, 8): 3115 adev->smuio.funcs = &smuio_v11_0_funcs; 3116 break; 3117 case IP_VERSION(11, 0, 6): 3118 case IP_VERSION(11, 0, 10): 3119 case IP_VERSION(11, 0, 11): 3120 case IP_VERSION(11, 5, 0): 3121 case IP_VERSION(11, 5, 2): 3122 case IP_VERSION(13, 0, 1): 3123 case IP_VERSION(13, 0, 9): 3124 case IP_VERSION(13, 0, 10): 3125 adev->smuio.funcs = &smuio_v11_0_6_funcs; 3126 break; 3127 case IP_VERSION(13, 0, 2): 3128 adev->smuio.funcs = &smuio_v13_0_funcs; 3129 break; 3130 case IP_VERSION(13, 0, 3): 3131 case IP_VERSION(13, 0, 11): 3132 adev->smuio.funcs = &smuio_v13_0_3_funcs; 3133 if (adev->smuio.funcs->get_pkg_type(adev) == AMDGPU_PKG_TYPE_APU) { 3134 adev->flags |= AMD_IS_APU; 3135 } 3136 break; 3137 case IP_VERSION(13, 0, 6): 3138 case IP_VERSION(13, 0, 8): 3139 case IP_VERSION(14, 0, 0): 3140 case IP_VERSION(14, 0, 1): 3141 adev->smuio.funcs = &smuio_v13_0_6_funcs; 3142 break; 3143 case IP_VERSION(14, 0, 2): 3144 adev->smuio.funcs = &smuio_v14_0_2_funcs; 3145 break; 3146 default: 3147 break; 3148 } 3149 3150 switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) { 3151 case IP_VERSION(6, 0, 0): 3152 case IP_VERSION(6, 0, 1): 3153 case IP_VERSION(6, 0, 2): 3154 case IP_VERSION(6, 0, 3): 3155 adev->lsdma.funcs = &lsdma_v6_0_funcs; 3156 break; 3157 case IP_VERSION(7, 0, 0): 3158 case IP_VERSION(7, 0, 1): 3159 adev->lsdma.funcs = &lsdma_v7_0_funcs; 3160 break; 3161 default: 3162 break; 3163 } 3164 3165 r = amdgpu_discovery_set_common_ip_blocks(adev); 3166 if (r) 3167 return r; 3168 3169 r = amdgpu_discovery_set_gmc_ip_blocks(adev); 3170 if (r) 3171 return r; 3172 3173 /* For SR-IOV, PSP needs to be initialized before IH */ 3174 if (amdgpu_sriov_vf(adev)) { 3175 r = amdgpu_discovery_set_psp_ip_blocks(adev); 3176 if (r) 3177 return r; 3178 r = amdgpu_discovery_set_ih_ip_blocks(adev); 3179 if (r) 3180 return r; 3181 } else { 3182 r = amdgpu_discovery_set_ih_ip_blocks(adev); 3183 if (r) 3184 return r; 3185 3186 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 3187 r = amdgpu_discovery_set_psp_ip_blocks(adev); 3188 if (r) 3189 return r; 3190 } 3191 } 3192 3193 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 3194 r = amdgpu_discovery_set_smu_ip_blocks(adev); 3195 if (r) 3196 return r; 3197 } 3198 3199 r = amdgpu_discovery_set_display_ip_blocks(adev); 3200 if (r) 3201 return r; 3202 3203 r = amdgpu_discovery_set_gc_ip_blocks(adev); 3204 if (r) 3205 return r; 3206 3207 r = amdgpu_discovery_set_sdma_ip_blocks(adev); 3208 if (r) 3209 return r; 3210 3211 r = amdgpu_discovery_set_ras_ip_blocks(adev); 3212 if (r) 3213 return r; 3214 3215 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 3216 !amdgpu_sriov_vf(adev) && 3217 amdgpu_dpm == 1) || 3218 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && 3219 amdgpu_dpm == 1)) { 3220 r = amdgpu_discovery_set_smu_ip_blocks(adev); 3221 if (r) 3222 return r; 3223 } 3224 3225 r = amdgpu_discovery_set_mm_ip_blocks(adev); 3226 if (r) 3227 return r; 3228 3229 r = amdgpu_discovery_set_mes_ip_blocks(adev); 3230 if (r) 3231 return r; 3232 3233 r = amdgpu_discovery_set_vpe_ip_blocks(adev); 3234 if (r) 3235 return r; 3236 3237 r = amdgpu_discovery_set_umsch_mm_ip_blocks(adev); 3238 if (r) 3239 return r; 3240 3241 r = amdgpu_discovery_set_isp_ip_blocks(adev); 3242 if (r) 3243 return r; 3244 return 0; 3245 } 3246 3247