1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_discovery.h" 28 #include "soc15_hw_ip.h" 29 #include "discovery.h" 30 #include "amdgpu_ras.h" 31 32 #include "soc15.h" 33 #include "gfx_v9_0.h" 34 #include "gfx_v9_4_3.h" 35 #include "gmc_v9_0.h" 36 #include "df_v1_7.h" 37 #include "df_v3_6.h" 38 #include "df_v4_3.h" 39 #include "df_v4_6_2.h" 40 #include "nbio_v6_1.h" 41 #include "nbio_v7_0.h" 42 #include "nbio_v7_4.h" 43 #include "nbio_v7_9.h" 44 #include "nbio_v7_11.h" 45 #include "hdp_v4_0.h" 46 #include "vega10_ih.h" 47 #include "vega20_ih.h" 48 #include "sdma_v4_0.h" 49 #include "sdma_v4_4_2.h" 50 #include "uvd_v7_0.h" 51 #include "vce_v4_0.h" 52 #include "vcn_v1_0.h" 53 #include "vcn_v2_5.h" 54 #include "jpeg_v2_5.h" 55 #include "smuio_v9_0.h" 56 #include "gmc_v10_0.h" 57 #include "gmc_v11_0.h" 58 #include "gmc_v12_0.h" 59 #include "gfxhub_v2_0.h" 60 #include "mmhub_v2_0.h" 61 #include "nbio_v2_3.h" 62 #include "nbio_v4_3.h" 63 #include "nbio_v7_2.h" 64 #include "nbio_v7_7.h" 65 #include "nbif_v6_3_1.h" 66 #include "hdp_v5_0.h" 67 #include "hdp_v5_2.h" 68 #include "hdp_v6_0.h" 69 #include "hdp_v7_0.h" 70 #include "nv.h" 71 #include "soc21.h" 72 #include "soc24.h" 73 #include "navi10_ih.h" 74 #include "ih_v6_0.h" 75 #include "ih_v6_1.h" 76 #include "ih_v7_0.h" 77 #include "gfx_v10_0.h" 78 #include "gfx_v11_0.h" 79 #include "gfx_v12_0.h" 80 #include "sdma_v5_0.h" 81 #include "sdma_v5_2.h" 82 #include "sdma_v6_0.h" 83 #include "sdma_v7_0.h" 84 #include "lsdma_v6_0.h" 85 #include "lsdma_v7_0.h" 86 #include "vcn_v2_0.h" 87 #include "jpeg_v2_0.h" 88 #include "vcn_v3_0.h" 89 #include "jpeg_v3_0.h" 90 #include "vcn_v4_0.h" 91 #include "jpeg_v4_0.h" 92 #include "vcn_v4_0_3.h" 93 #include "jpeg_v4_0_3.h" 94 #include "vcn_v4_0_5.h" 95 #include "jpeg_v4_0_5.h" 96 #include "amdgpu_vkms.h" 97 #include "mes_v11_0.h" 98 #include "mes_v12_0.h" 99 #include "smuio_v11_0.h" 100 #include "smuio_v11_0_6.h" 101 #include "smuio_v13_0.h" 102 #include "smuio_v13_0_3.h" 103 #include "smuio_v13_0_6.h" 104 #include "smuio_v14_0_2.h" 105 #include "vcn_v5_0_0.h" 106 #include "jpeg_v5_0_0.h" 107 108 #include "amdgpu_vpe.h" 109 110 #define FIRMWARE_IP_DISCOVERY "amdgpu/ip_discovery.bin" 111 MODULE_FIRMWARE(FIRMWARE_IP_DISCOVERY); 112 113 #define mmIP_DISCOVERY_VERSION 0x16A00 114 #define mmRCC_CONFIG_MEMSIZE 0xde3 115 #define mmMP0_SMN_C2PMSG_33 0x16061 116 #define mmMM_INDEX 0x0 117 #define mmMM_INDEX_HI 0x6 118 #define mmMM_DATA 0x1 119 120 static const char *hw_id_names[HW_ID_MAX] = { 121 [MP1_HWID] = "MP1", 122 [MP2_HWID] = "MP2", 123 [THM_HWID] = "THM", 124 [SMUIO_HWID] = "SMUIO", 125 [FUSE_HWID] = "FUSE", 126 [CLKA_HWID] = "CLKA", 127 [PWR_HWID] = "PWR", 128 [GC_HWID] = "GC", 129 [UVD_HWID] = "UVD", 130 [AUDIO_AZ_HWID] = "AUDIO_AZ", 131 [ACP_HWID] = "ACP", 132 [DCI_HWID] = "DCI", 133 [DMU_HWID] = "DMU", 134 [DCO_HWID] = "DCO", 135 [DIO_HWID] = "DIO", 136 [XDMA_HWID] = "XDMA", 137 [DCEAZ_HWID] = "DCEAZ", 138 [DAZ_HWID] = "DAZ", 139 [SDPMUX_HWID] = "SDPMUX", 140 [NTB_HWID] = "NTB", 141 [IOHC_HWID] = "IOHC", 142 [L2IMU_HWID] = "L2IMU", 143 [VCE_HWID] = "VCE", 144 [MMHUB_HWID] = "MMHUB", 145 [ATHUB_HWID] = "ATHUB", 146 [DBGU_NBIO_HWID] = "DBGU_NBIO", 147 [DFX_HWID] = "DFX", 148 [DBGU0_HWID] = "DBGU0", 149 [DBGU1_HWID] = "DBGU1", 150 [OSSSYS_HWID] = "OSSSYS", 151 [HDP_HWID] = "HDP", 152 [SDMA0_HWID] = "SDMA0", 153 [SDMA1_HWID] = "SDMA1", 154 [SDMA2_HWID] = "SDMA2", 155 [SDMA3_HWID] = "SDMA3", 156 [LSDMA_HWID] = "LSDMA", 157 [ISP_HWID] = "ISP", 158 [DBGU_IO_HWID] = "DBGU_IO", 159 [DF_HWID] = "DF", 160 [CLKB_HWID] = "CLKB", 161 [FCH_HWID] = "FCH", 162 [DFX_DAP_HWID] = "DFX_DAP", 163 [L1IMU_PCIE_HWID] = "L1IMU_PCIE", 164 [L1IMU_NBIF_HWID] = "L1IMU_NBIF", 165 [L1IMU_IOAGR_HWID] = "L1IMU_IOAGR", 166 [L1IMU3_HWID] = "L1IMU3", 167 [L1IMU4_HWID] = "L1IMU4", 168 [L1IMU5_HWID] = "L1IMU5", 169 [L1IMU6_HWID] = "L1IMU6", 170 [L1IMU7_HWID] = "L1IMU7", 171 [L1IMU8_HWID] = "L1IMU8", 172 [L1IMU9_HWID] = "L1IMU9", 173 [L1IMU10_HWID] = "L1IMU10", 174 [L1IMU11_HWID] = "L1IMU11", 175 [L1IMU12_HWID] = "L1IMU12", 176 [L1IMU13_HWID] = "L1IMU13", 177 [L1IMU14_HWID] = "L1IMU14", 178 [L1IMU15_HWID] = "L1IMU15", 179 [WAFLC_HWID] = "WAFLC", 180 [FCH_USB_PD_HWID] = "FCH_USB_PD", 181 [PCIE_HWID] = "PCIE", 182 [PCS_HWID] = "PCS", 183 [DDCL_HWID] = "DDCL", 184 [SST_HWID] = "SST", 185 [IOAGR_HWID] = "IOAGR", 186 [NBIF_HWID] = "NBIF", 187 [IOAPIC_HWID] = "IOAPIC", 188 [SYSTEMHUB_HWID] = "SYSTEMHUB", 189 [NTBCCP_HWID] = "NTBCCP", 190 [UMC_HWID] = "UMC", 191 [SATA_HWID] = "SATA", 192 [USB_HWID] = "USB", 193 [CCXSEC_HWID] = "CCXSEC", 194 [XGMI_HWID] = "XGMI", 195 [XGBE_HWID] = "XGBE", 196 [MP0_HWID] = "MP0", 197 [VPE_HWID] = "VPE", 198 }; 199 200 static int hw_id_map[MAX_HWIP] = { 201 [GC_HWIP] = GC_HWID, 202 [HDP_HWIP] = HDP_HWID, 203 [SDMA0_HWIP] = SDMA0_HWID, 204 [SDMA1_HWIP] = SDMA1_HWID, 205 [SDMA2_HWIP] = SDMA2_HWID, 206 [SDMA3_HWIP] = SDMA3_HWID, 207 [LSDMA_HWIP] = LSDMA_HWID, 208 [MMHUB_HWIP] = MMHUB_HWID, 209 [ATHUB_HWIP] = ATHUB_HWID, 210 [NBIO_HWIP] = NBIF_HWID, 211 [MP0_HWIP] = MP0_HWID, 212 [MP1_HWIP] = MP1_HWID, 213 [UVD_HWIP] = UVD_HWID, 214 [VCE_HWIP] = VCE_HWID, 215 [DF_HWIP] = DF_HWID, 216 [DCE_HWIP] = DMU_HWID, 217 [OSSSYS_HWIP] = OSSSYS_HWID, 218 [SMUIO_HWIP] = SMUIO_HWID, 219 [PWR_HWIP] = PWR_HWID, 220 [NBIF_HWIP] = NBIF_HWID, 221 [THM_HWIP] = THM_HWID, 222 [CLK_HWIP] = CLKA_HWID, 223 [UMC_HWIP] = UMC_HWID, 224 [XGMI_HWIP] = XGMI_HWID, 225 [DCI_HWIP] = DCI_HWID, 226 [PCIE_HWIP] = PCIE_HWID, 227 [VPE_HWIP] = VPE_HWID, 228 }; 229 230 static int amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device *adev, uint8_t *binary) 231 { 232 u64 tmr_offset, tmr_size, pos; 233 void *discv_regn; 234 int ret; 235 236 ret = amdgpu_acpi_get_tmr_info(adev, &tmr_offset, &tmr_size); 237 if (ret) 238 return ret; 239 240 pos = tmr_offset + tmr_size - DISCOVERY_TMR_OFFSET; 241 242 /* This region is read-only and reserved from system use */ 243 discv_regn = memremap(pos, adev->mman.discovery_tmr_size, MEMREMAP_WC); 244 if (discv_regn) { 245 memcpy(binary, discv_regn, adev->mman.discovery_tmr_size); 246 memunmap(discv_regn); 247 return 0; 248 } 249 250 return -ENOENT; 251 } 252 253 #define IP_DISCOVERY_V2 2 254 #define IP_DISCOVERY_V4 4 255 256 static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev, 257 uint8_t *binary) 258 { 259 uint64_t vram_size; 260 u32 msg; 261 int i, ret = 0; 262 263 /* It can take up to a second for IFWI init to complete on some dGPUs, 264 * but generally it should be in the 60-100ms range. Normally this starts 265 * as soon as the device gets power so by the time the OS loads this has long 266 * completed. However, when a card is hotplugged via e.g., USB4, we need to 267 * wait for this to complete. Once the C2PMSG is updated, we can 268 * continue. 269 */ 270 271 for (i = 0; i < 1000; i++) { 272 msg = RREG32(mmMP0_SMN_C2PMSG_33); 273 if (msg & 0x80000000) 274 break; 275 usleep_range(1000, 1100); 276 } 277 278 vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20; 279 280 if (vram_size) { 281 uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET; 282 amdgpu_device_vram_access(adev, pos, (uint32_t *)binary, 283 adev->mman.discovery_tmr_size, false); 284 } else { 285 ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary); 286 } 287 288 return ret; 289 } 290 291 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, uint8_t *binary) 292 { 293 const struct firmware *fw; 294 const char *fw_name; 295 int r; 296 297 switch (amdgpu_discovery) { 298 case 2: 299 fw_name = FIRMWARE_IP_DISCOVERY; 300 break; 301 default: 302 dev_warn(adev->dev, "amdgpu_discovery is not set properly\n"); 303 return -EINVAL; 304 } 305 306 r = request_firmware(&fw, fw_name, adev->dev); 307 if (r) { 308 dev_err(adev->dev, "can't load firmware \"%s\"\n", 309 fw_name); 310 return r; 311 } 312 313 memcpy((u8 *)binary, (u8 *)fw->data, fw->size); 314 release_firmware(fw); 315 316 return 0; 317 } 318 319 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size) 320 { 321 uint16_t checksum = 0; 322 int i; 323 324 for (i = 0; i < size; i++) 325 checksum += data[i]; 326 327 return checksum; 328 } 329 330 static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size, 331 uint16_t expected) 332 { 333 return !!(amdgpu_discovery_calculate_checksum(data, size) == expected); 334 } 335 336 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary) 337 { 338 struct binary_header *bhdr; 339 bhdr = (struct binary_header *)binary; 340 341 return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE); 342 } 343 344 static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev) 345 { 346 /* 347 * So far, apply this quirk only on those Navy Flounder boards which 348 * have a bad harvest table of VCN config. 349 */ 350 if ((amdgpu_ip_version(adev, UVD_HWIP, 1) == IP_VERSION(3, 0, 1)) && 351 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 2))) { 352 switch (adev->pdev->revision) { 353 case 0xC1: 354 case 0xC2: 355 case 0xC3: 356 case 0xC5: 357 case 0xC7: 358 case 0xCF: 359 case 0xDF: 360 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 361 adev->vcn.inst_mask &= ~AMDGPU_VCN_HARVEST_VCN1; 362 break; 363 default: 364 break; 365 } 366 } 367 } 368 369 static int amdgpu_discovery_verify_npsinfo(struct amdgpu_device *adev, 370 struct binary_header *bhdr) 371 { 372 struct table_info *info; 373 uint16_t checksum; 374 uint16_t offset; 375 376 info = &bhdr->table_list[NPS_INFO]; 377 offset = le16_to_cpu(info->offset); 378 checksum = le16_to_cpu(info->checksum); 379 380 struct nps_info_header *nhdr = 381 (struct nps_info_header *)(adev->mman.discovery_bin + offset); 382 383 if (le32_to_cpu(nhdr->table_id) != NPS_INFO_TABLE_ID) { 384 dev_dbg(adev->dev, "invalid ip discovery nps info table id\n"); 385 return -EINVAL; 386 } 387 388 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 389 le32_to_cpu(nhdr->size_bytes), 390 checksum)) { 391 dev_dbg(adev->dev, "invalid nps info data table checksum\n"); 392 return -EINVAL; 393 } 394 395 return 0; 396 } 397 398 static int amdgpu_discovery_init(struct amdgpu_device *adev) 399 { 400 struct table_info *info; 401 struct binary_header *bhdr; 402 uint16_t offset; 403 uint16_t size; 404 uint16_t checksum; 405 int r; 406 407 adev->mman.discovery_tmr_size = DISCOVERY_TMR_SIZE; 408 adev->mman.discovery_bin = kzalloc(adev->mman.discovery_tmr_size, GFP_KERNEL); 409 if (!adev->mman.discovery_bin) 410 return -ENOMEM; 411 412 /* Read from file if it is the preferred option */ 413 if (amdgpu_discovery == 2) { 414 dev_info(adev->dev, "use ip discovery information from file"); 415 r = amdgpu_discovery_read_binary_from_file(adev, adev->mman.discovery_bin); 416 417 if (r) { 418 dev_err(adev->dev, "failed to read ip discovery binary from file\n"); 419 r = -EINVAL; 420 goto out; 421 } 422 423 } else { 424 r = amdgpu_discovery_read_binary_from_mem( 425 adev, adev->mman.discovery_bin); 426 if (r) 427 goto out; 428 } 429 430 /* check the ip discovery binary signature */ 431 if (!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) { 432 dev_err(adev->dev, 433 "get invalid ip discovery binary signature\n"); 434 r = -EINVAL; 435 goto out; 436 } 437 438 bhdr = (struct binary_header *)adev->mman.discovery_bin; 439 440 offset = offsetof(struct binary_header, binary_checksum) + 441 sizeof(bhdr->binary_checksum); 442 size = le16_to_cpu(bhdr->binary_size) - offset; 443 checksum = le16_to_cpu(bhdr->binary_checksum); 444 445 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 446 size, checksum)) { 447 dev_err(adev->dev, "invalid ip discovery binary checksum\n"); 448 r = -EINVAL; 449 goto out; 450 } 451 452 info = &bhdr->table_list[IP_DISCOVERY]; 453 offset = le16_to_cpu(info->offset); 454 checksum = le16_to_cpu(info->checksum); 455 456 if (offset) { 457 struct ip_discovery_header *ihdr = 458 (struct ip_discovery_header *)(adev->mman.discovery_bin + offset); 459 if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) { 460 dev_err(adev->dev, "invalid ip discovery data table signature\n"); 461 r = -EINVAL; 462 goto out; 463 } 464 465 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 466 le16_to_cpu(ihdr->size), checksum)) { 467 dev_err(adev->dev, "invalid ip discovery data table checksum\n"); 468 r = -EINVAL; 469 goto out; 470 } 471 } 472 473 info = &bhdr->table_list[GC]; 474 offset = le16_to_cpu(info->offset); 475 checksum = le16_to_cpu(info->checksum); 476 477 if (offset) { 478 struct gpu_info_header *ghdr = 479 (struct gpu_info_header *)(adev->mman.discovery_bin + offset); 480 481 if (le32_to_cpu(ghdr->table_id) != GC_TABLE_ID) { 482 dev_err(adev->dev, "invalid ip discovery gc table id\n"); 483 r = -EINVAL; 484 goto out; 485 } 486 487 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 488 le32_to_cpu(ghdr->size), checksum)) { 489 dev_err(adev->dev, "invalid gc data table checksum\n"); 490 r = -EINVAL; 491 goto out; 492 } 493 } 494 495 info = &bhdr->table_list[HARVEST_INFO]; 496 offset = le16_to_cpu(info->offset); 497 checksum = le16_to_cpu(info->checksum); 498 499 if (offset) { 500 struct harvest_info_header *hhdr = 501 (struct harvest_info_header *)(adev->mman.discovery_bin + offset); 502 503 if (le32_to_cpu(hhdr->signature) != HARVEST_TABLE_SIGNATURE) { 504 dev_err(adev->dev, "invalid ip discovery harvest table signature\n"); 505 r = -EINVAL; 506 goto out; 507 } 508 509 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 510 sizeof(struct harvest_table), checksum)) { 511 dev_err(adev->dev, "invalid harvest data table checksum\n"); 512 r = -EINVAL; 513 goto out; 514 } 515 } 516 517 info = &bhdr->table_list[VCN_INFO]; 518 offset = le16_to_cpu(info->offset); 519 checksum = le16_to_cpu(info->checksum); 520 521 if (offset) { 522 struct vcn_info_header *vhdr = 523 (struct vcn_info_header *)(adev->mman.discovery_bin + offset); 524 525 if (le32_to_cpu(vhdr->table_id) != VCN_INFO_TABLE_ID) { 526 dev_err(adev->dev, "invalid ip discovery vcn table id\n"); 527 r = -EINVAL; 528 goto out; 529 } 530 531 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 532 le32_to_cpu(vhdr->size_bytes), checksum)) { 533 dev_err(adev->dev, "invalid vcn data table checksum\n"); 534 r = -EINVAL; 535 goto out; 536 } 537 } 538 539 info = &bhdr->table_list[MALL_INFO]; 540 offset = le16_to_cpu(info->offset); 541 checksum = le16_to_cpu(info->checksum); 542 543 if (0 && offset) { 544 struct mall_info_header *mhdr = 545 (struct mall_info_header *)(adev->mman.discovery_bin + offset); 546 547 if (le32_to_cpu(mhdr->table_id) != MALL_INFO_TABLE_ID) { 548 dev_err(adev->dev, "invalid ip discovery mall table id\n"); 549 r = -EINVAL; 550 goto out; 551 } 552 553 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 554 le32_to_cpu(mhdr->size_bytes), checksum)) { 555 dev_err(adev->dev, "invalid mall data table checksum\n"); 556 r = -EINVAL; 557 goto out; 558 } 559 } 560 561 return 0; 562 563 out: 564 kfree(adev->mman.discovery_bin); 565 adev->mman.discovery_bin = NULL; 566 if ((amdgpu_discovery != 2) && 567 (RREG32(mmIP_DISCOVERY_VERSION) == 4)) 568 amdgpu_ras_query_boot_status(adev, 4); 569 return r; 570 } 571 572 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev); 573 574 void amdgpu_discovery_fini(struct amdgpu_device *adev) 575 { 576 amdgpu_discovery_sysfs_fini(adev); 577 kfree(adev->mman.discovery_bin); 578 adev->mman.discovery_bin = NULL; 579 } 580 581 static int amdgpu_discovery_validate_ip(const struct ip_v4 *ip) 582 { 583 if (ip->instance_number >= HWIP_MAX_INSTANCE) { 584 DRM_ERROR("Unexpected instance_number (%d) from ip discovery blob\n", 585 ip->instance_number); 586 return -EINVAL; 587 } 588 if (le16_to_cpu(ip->hw_id) >= HW_ID_MAX) { 589 DRM_ERROR("Unexpected hw_id (%d) from ip discovery blob\n", 590 le16_to_cpu(ip->hw_id)); 591 return -EINVAL; 592 } 593 594 return 0; 595 } 596 597 static void amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device *adev, 598 uint32_t *vcn_harvest_count) 599 { 600 struct binary_header *bhdr; 601 struct ip_discovery_header *ihdr; 602 struct die_header *dhdr; 603 struct ip_v4 *ip; 604 uint16_t die_offset, ip_offset, num_dies, num_ips; 605 int i, j; 606 607 bhdr = (struct binary_header *)adev->mman.discovery_bin; 608 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 609 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 610 num_dies = le16_to_cpu(ihdr->num_dies); 611 612 /* scan harvest bit of all IP data structures */ 613 for (i = 0; i < num_dies; i++) { 614 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 615 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 616 num_ips = le16_to_cpu(dhdr->num_ips); 617 ip_offset = die_offset + sizeof(*dhdr); 618 619 for (j = 0; j < num_ips; j++) { 620 ip = (struct ip_v4 *)(adev->mman.discovery_bin + ip_offset); 621 622 if (amdgpu_discovery_validate_ip(ip)) 623 goto next_ip; 624 625 if (le16_to_cpu(ip->variant) == 1) { 626 switch (le16_to_cpu(ip->hw_id)) { 627 case VCN_HWID: 628 (*vcn_harvest_count)++; 629 if (ip->instance_number == 0) { 630 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0; 631 adev->vcn.inst_mask &= 632 ~AMDGPU_VCN_HARVEST_VCN0; 633 adev->jpeg.inst_mask &= 634 ~AMDGPU_VCN_HARVEST_VCN0; 635 } else { 636 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 637 adev->vcn.inst_mask &= 638 ~AMDGPU_VCN_HARVEST_VCN1; 639 adev->jpeg.inst_mask &= 640 ~AMDGPU_VCN_HARVEST_VCN1; 641 } 642 break; 643 case DMU_HWID: 644 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 645 break; 646 default: 647 break; 648 } 649 } 650 next_ip: 651 if (ihdr->base_addr_64_bit) 652 ip_offset += struct_size(ip, base_address_64, ip->num_base_address); 653 else 654 ip_offset += struct_size(ip, base_address, ip->num_base_address); 655 } 656 } 657 } 658 659 static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev, 660 uint32_t *vcn_harvest_count, 661 uint32_t *umc_harvest_count) 662 { 663 struct binary_header *bhdr; 664 struct harvest_table *harvest_info; 665 u16 offset; 666 int i; 667 uint32_t umc_harvest_config = 0; 668 669 bhdr = (struct binary_header *)adev->mman.discovery_bin; 670 offset = le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset); 671 672 if (!offset) { 673 dev_err(adev->dev, "invalid harvest table offset\n"); 674 return; 675 } 676 677 harvest_info = (struct harvest_table *)(adev->mman.discovery_bin + offset); 678 679 for (i = 0; i < 32; i++) { 680 if (le16_to_cpu(harvest_info->list[i].hw_id) == 0) 681 break; 682 683 switch (le16_to_cpu(harvest_info->list[i].hw_id)) { 684 case VCN_HWID: 685 (*vcn_harvest_count)++; 686 adev->vcn.harvest_config |= 687 (1 << harvest_info->list[i].number_instance); 688 adev->jpeg.harvest_config |= 689 (1 << harvest_info->list[i].number_instance); 690 691 adev->vcn.inst_mask &= 692 ~(1U << harvest_info->list[i].number_instance); 693 adev->jpeg.inst_mask &= 694 ~(1U << harvest_info->list[i].number_instance); 695 break; 696 case DMU_HWID: 697 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 698 break; 699 case UMC_HWID: 700 umc_harvest_config |= 701 1 << (le16_to_cpu(harvest_info->list[i].number_instance)); 702 (*umc_harvest_count)++; 703 break; 704 case GC_HWID: 705 adev->gfx.xcc_mask &= 706 ~(1U << harvest_info->list[i].number_instance); 707 break; 708 case SDMA0_HWID: 709 adev->sdma.sdma_mask &= 710 ~(1U << harvest_info->list[i].number_instance); 711 break; 712 default: 713 break; 714 } 715 } 716 717 adev->umc.active_mask = ((1 << adev->umc.node_inst_num) - 1) & 718 ~umc_harvest_config; 719 } 720 721 /* ================================================== */ 722 723 struct ip_hw_instance { 724 struct kobject kobj; /* ip_discovery/die/#die/#hw_id/#instance/<attrs...> */ 725 726 int hw_id; 727 u8 num_instance; 728 u8 major, minor, revision; 729 u8 harvest; 730 731 int num_base_addresses; 732 u32 base_addr[] __counted_by(num_base_addresses); 733 }; 734 735 struct ip_hw_id { 736 struct kset hw_id_kset; /* ip_discovery/die/#die/#hw_id/, contains ip_hw_instance */ 737 int hw_id; 738 }; 739 740 struct ip_die_entry { 741 struct kset ip_kset; /* ip_discovery/die/#die/, contains ip_hw_id */ 742 u16 num_ips; 743 }; 744 745 /* -------------------------------------------------- */ 746 747 struct ip_hw_instance_attr { 748 struct attribute attr; 749 ssize_t (*show)(struct ip_hw_instance *ip_hw_instance, char *buf); 750 }; 751 752 static ssize_t hw_id_show(struct ip_hw_instance *ip_hw_instance, char *buf) 753 { 754 return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id); 755 } 756 757 static ssize_t num_instance_show(struct ip_hw_instance *ip_hw_instance, char *buf) 758 { 759 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance); 760 } 761 762 static ssize_t major_show(struct ip_hw_instance *ip_hw_instance, char *buf) 763 { 764 return sysfs_emit(buf, "%d\n", ip_hw_instance->major); 765 } 766 767 static ssize_t minor_show(struct ip_hw_instance *ip_hw_instance, char *buf) 768 { 769 return sysfs_emit(buf, "%d\n", ip_hw_instance->minor); 770 } 771 772 static ssize_t revision_show(struct ip_hw_instance *ip_hw_instance, char *buf) 773 { 774 return sysfs_emit(buf, "%d\n", ip_hw_instance->revision); 775 } 776 777 static ssize_t harvest_show(struct ip_hw_instance *ip_hw_instance, char *buf) 778 { 779 return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest); 780 } 781 782 static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, char *buf) 783 { 784 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses); 785 } 786 787 static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf) 788 { 789 ssize_t res, at; 790 int ii; 791 792 for (res = at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) { 793 /* Here we satisfy the condition that, at + size <= PAGE_SIZE. 794 */ 795 if (at + 12 > PAGE_SIZE) 796 break; 797 res = sysfs_emit_at(buf, at, "0x%08X\n", 798 ip_hw_instance->base_addr[ii]); 799 if (res <= 0) 800 break; 801 at += res; 802 } 803 804 return res < 0 ? res : at; 805 } 806 807 static struct ip_hw_instance_attr ip_hw_attr[] = { 808 __ATTR_RO(hw_id), 809 __ATTR_RO(num_instance), 810 __ATTR_RO(major), 811 __ATTR_RO(minor), 812 __ATTR_RO(revision), 813 __ATTR_RO(harvest), 814 __ATTR_RO(num_base_addresses), 815 __ATTR_RO(base_addr), 816 }; 817 818 static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1]; 819 ATTRIBUTE_GROUPS(ip_hw_instance); 820 821 #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj) 822 #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr) 823 824 static ssize_t ip_hw_instance_attr_show(struct kobject *kobj, 825 struct attribute *attr, 826 char *buf) 827 { 828 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 829 struct ip_hw_instance_attr *ip_hw_attr = to_ip_hw_instance_attr(attr); 830 831 if (!ip_hw_attr->show) 832 return -EIO; 833 834 return ip_hw_attr->show(ip_hw_instance, buf); 835 } 836 837 static const struct sysfs_ops ip_hw_instance_sysfs_ops = { 838 .show = ip_hw_instance_attr_show, 839 }; 840 841 static void ip_hw_instance_release(struct kobject *kobj) 842 { 843 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 844 845 kfree(ip_hw_instance); 846 } 847 848 static const struct kobj_type ip_hw_instance_ktype = { 849 .release = ip_hw_instance_release, 850 .sysfs_ops = &ip_hw_instance_sysfs_ops, 851 .default_groups = ip_hw_instance_groups, 852 }; 853 854 /* -------------------------------------------------- */ 855 856 #define to_ip_hw_id(x) container_of(to_kset(x), struct ip_hw_id, hw_id_kset) 857 858 static void ip_hw_id_release(struct kobject *kobj) 859 { 860 struct ip_hw_id *ip_hw_id = to_ip_hw_id(kobj); 861 862 if (!list_empty(&ip_hw_id->hw_id_kset.list)) 863 DRM_ERROR("ip_hw_id->hw_id_kset is not empty"); 864 kfree(ip_hw_id); 865 } 866 867 static const struct kobj_type ip_hw_id_ktype = { 868 .release = ip_hw_id_release, 869 .sysfs_ops = &kobj_sysfs_ops, 870 }; 871 872 /* -------------------------------------------------- */ 873 874 static void die_kobj_release(struct kobject *kobj); 875 static void ip_disc_release(struct kobject *kobj); 876 877 struct ip_die_entry_attribute { 878 struct attribute attr; 879 ssize_t (*show)(struct ip_die_entry *ip_die_entry, char *buf); 880 }; 881 882 #define to_ip_die_entry_attr(x) container_of(x, struct ip_die_entry_attribute, attr) 883 884 static ssize_t num_ips_show(struct ip_die_entry *ip_die_entry, char *buf) 885 { 886 return sysfs_emit(buf, "%d\n", ip_die_entry->num_ips); 887 } 888 889 /* If there are more ip_die_entry attrs, other than the number of IPs, 890 * we can make this intro an array of attrs, and then initialize 891 * ip_die_entry_attrs in a loop. 892 */ 893 static struct ip_die_entry_attribute num_ips_attr = 894 __ATTR_RO(num_ips); 895 896 static struct attribute *ip_die_entry_attrs[] = { 897 &num_ips_attr.attr, 898 NULL, 899 }; 900 ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */ 901 902 #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset) 903 904 static ssize_t ip_die_entry_attr_show(struct kobject *kobj, 905 struct attribute *attr, 906 char *buf) 907 { 908 struct ip_die_entry_attribute *ip_die_entry_attr = to_ip_die_entry_attr(attr); 909 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 910 911 if (!ip_die_entry_attr->show) 912 return -EIO; 913 914 return ip_die_entry_attr->show(ip_die_entry, buf); 915 } 916 917 static void ip_die_entry_release(struct kobject *kobj) 918 { 919 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 920 921 if (!list_empty(&ip_die_entry->ip_kset.list)) 922 DRM_ERROR("ip_die_entry->ip_kset is not empty"); 923 kfree(ip_die_entry); 924 } 925 926 static const struct sysfs_ops ip_die_entry_sysfs_ops = { 927 .show = ip_die_entry_attr_show, 928 }; 929 930 static const struct kobj_type ip_die_entry_ktype = { 931 .release = ip_die_entry_release, 932 .sysfs_ops = &ip_die_entry_sysfs_ops, 933 .default_groups = ip_die_entry_groups, 934 }; 935 936 static const struct kobj_type die_kobj_ktype = { 937 .release = die_kobj_release, 938 .sysfs_ops = &kobj_sysfs_ops, 939 }; 940 941 static const struct kobj_type ip_discovery_ktype = { 942 .release = ip_disc_release, 943 .sysfs_ops = &kobj_sysfs_ops, 944 }; 945 946 struct ip_discovery_top { 947 struct kobject kobj; /* ip_discovery/ */ 948 struct kset die_kset; /* ip_discovery/die/, contains ip_die_entry */ 949 struct amdgpu_device *adev; 950 }; 951 952 static void die_kobj_release(struct kobject *kobj) 953 { 954 struct ip_discovery_top *ip_top = container_of(to_kset(kobj), 955 struct ip_discovery_top, 956 die_kset); 957 if (!list_empty(&ip_top->die_kset.list)) 958 DRM_ERROR("ip_top->die_kset is not empty"); 959 } 960 961 static void ip_disc_release(struct kobject *kobj) 962 { 963 struct ip_discovery_top *ip_top = container_of(kobj, struct ip_discovery_top, 964 kobj); 965 struct amdgpu_device *adev = ip_top->adev; 966 967 adev->ip_top = NULL; 968 kfree(ip_top); 969 } 970 971 static uint8_t amdgpu_discovery_get_harvest_info(struct amdgpu_device *adev, 972 uint16_t hw_id, uint8_t inst) 973 { 974 uint8_t harvest = 0; 975 976 /* Until a uniform way is figured, get mask based on hwid */ 977 switch (hw_id) { 978 case VCN_HWID: 979 harvest = ((1 << inst) & adev->vcn.inst_mask) == 0; 980 break; 981 case DMU_HWID: 982 if (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK) 983 harvest = 0x1; 984 break; 985 case UMC_HWID: 986 /* TODO: It needs another parsing; for now, ignore.*/ 987 break; 988 case GC_HWID: 989 harvest = ((1 << inst) & adev->gfx.xcc_mask) == 0; 990 break; 991 case SDMA0_HWID: 992 harvest = ((1 << inst) & adev->sdma.sdma_mask) == 0; 993 break; 994 default: 995 break; 996 } 997 998 return harvest; 999 } 1000 1001 static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev, 1002 struct ip_die_entry *ip_die_entry, 1003 const size_t _ip_offset, const int num_ips, 1004 bool reg_base_64) 1005 { 1006 int ii, jj, kk, res; 1007 1008 DRM_DEBUG("num_ips:%d", num_ips); 1009 1010 /* Find all IPs of a given HW ID, and add their instance to 1011 * #die/#hw_id/#instance/<attributes> 1012 */ 1013 for (ii = 0; ii < HW_ID_MAX; ii++) { 1014 struct ip_hw_id *ip_hw_id = NULL; 1015 size_t ip_offset = _ip_offset; 1016 1017 for (jj = 0; jj < num_ips; jj++) { 1018 struct ip_v4 *ip; 1019 struct ip_hw_instance *ip_hw_instance; 1020 1021 ip = (struct ip_v4 *)(adev->mman.discovery_bin + ip_offset); 1022 if (amdgpu_discovery_validate_ip(ip) || 1023 le16_to_cpu(ip->hw_id) != ii) 1024 goto next_ip; 1025 1026 DRM_DEBUG("match:%d @ ip_offset:%zu", ii, ip_offset); 1027 1028 /* We have a hw_id match; register the hw 1029 * block if not yet registered. 1030 */ 1031 if (!ip_hw_id) { 1032 ip_hw_id = kzalloc(sizeof(*ip_hw_id), GFP_KERNEL); 1033 if (!ip_hw_id) 1034 return -ENOMEM; 1035 ip_hw_id->hw_id = ii; 1036 1037 kobject_set_name(&ip_hw_id->hw_id_kset.kobj, "%d", ii); 1038 ip_hw_id->hw_id_kset.kobj.kset = &ip_die_entry->ip_kset; 1039 ip_hw_id->hw_id_kset.kobj.ktype = &ip_hw_id_ktype; 1040 res = kset_register(&ip_hw_id->hw_id_kset); 1041 if (res) { 1042 DRM_ERROR("Couldn't register ip_hw_id kset"); 1043 kfree(ip_hw_id); 1044 return res; 1045 } 1046 if (hw_id_names[ii]) { 1047 res = sysfs_create_link(&ip_die_entry->ip_kset.kobj, 1048 &ip_hw_id->hw_id_kset.kobj, 1049 hw_id_names[ii]); 1050 if (res) { 1051 DRM_ERROR("Couldn't create IP link %s in IP Die:%s\n", 1052 hw_id_names[ii], 1053 kobject_name(&ip_die_entry->ip_kset.kobj)); 1054 } 1055 } 1056 } 1057 1058 /* Now register its instance. 1059 */ 1060 ip_hw_instance = kzalloc(struct_size(ip_hw_instance, 1061 base_addr, 1062 ip->num_base_address), 1063 GFP_KERNEL); 1064 if (!ip_hw_instance) { 1065 DRM_ERROR("no memory for ip_hw_instance"); 1066 return -ENOMEM; 1067 } 1068 ip_hw_instance->hw_id = le16_to_cpu(ip->hw_id); /* == ii */ 1069 ip_hw_instance->num_instance = ip->instance_number; 1070 ip_hw_instance->major = ip->major; 1071 ip_hw_instance->minor = ip->minor; 1072 ip_hw_instance->revision = ip->revision; 1073 ip_hw_instance->harvest = 1074 amdgpu_discovery_get_harvest_info( 1075 adev, ip_hw_instance->hw_id, 1076 ip_hw_instance->num_instance); 1077 ip_hw_instance->num_base_addresses = ip->num_base_address; 1078 1079 for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++) { 1080 if (reg_base_64) 1081 ip_hw_instance->base_addr[kk] = 1082 lower_32_bits(le64_to_cpu(ip->base_address_64[kk])) & 0x3FFFFFFF; 1083 else 1084 ip_hw_instance->base_addr[kk] = ip->base_address[kk]; 1085 } 1086 1087 kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype); 1088 ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset; 1089 res = kobject_add(&ip_hw_instance->kobj, NULL, 1090 "%d", ip_hw_instance->num_instance); 1091 next_ip: 1092 if (reg_base_64) 1093 ip_offset += struct_size(ip, base_address_64, 1094 ip->num_base_address); 1095 else 1096 ip_offset += struct_size(ip, base_address, 1097 ip->num_base_address); 1098 } 1099 } 1100 1101 return 0; 1102 } 1103 1104 static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev) 1105 { 1106 struct binary_header *bhdr; 1107 struct ip_discovery_header *ihdr; 1108 struct die_header *dhdr; 1109 struct kset *die_kset = &adev->ip_top->die_kset; 1110 u16 num_dies, die_offset, num_ips; 1111 size_t ip_offset; 1112 int ii, res; 1113 1114 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1115 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 1116 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 1117 num_dies = le16_to_cpu(ihdr->num_dies); 1118 1119 DRM_DEBUG("number of dies: %d\n", num_dies); 1120 1121 for (ii = 0; ii < num_dies; ii++) { 1122 struct ip_die_entry *ip_die_entry; 1123 1124 die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset); 1125 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 1126 num_ips = le16_to_cpu(dhdr->num_ips); 1127 ip_offset = die_offset + sizeof(*dhdr); 1128 1129 /* Add the die to the kset. 1130 * 1131 * dhdr->die_id == ii, which was checked in 1132 * amdgpu_discovery_reg_base_init(). 1133 */ 1134 1135 ip_die_entry = kzalloc(sizeof(*ip_die_entry), GFP_KERNEL); 1136 if (!ip_die_entry) 1137 return -ENOMEM; 1138 1139 ip_die_entry->num_ips = num_ips; 1140 1141 kobject_set_name(&ip_die_entry->ip_kset.kobj, "%d", le16_to_cpu(dhdr->die_id)); 1142 ip_die_entry->ip_kset.kobj.kset = die_kset; 1143 ip_die_entry->ip_kset.kobj.ktype = &ip_die_entry_ktype; 1144 res = kset_register(&ip_die_entry->ip_kset); 1145 if (res) { 1146 DRM_ERROR("Couldn't register ip_die_entry kset"); 1147 kfree(ip_die_entry); 1148 return res; 1149 } 1150 1151 amdgpu_discovery_sysfs_ips(adev, ip_die_entry, ip_offset, num_ips, !!ihdr->base_addr_64_bit); 1152 } 1153 1154 return 0; 1155 } 1156 1157 static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev) 1158 { 1159 struct kset *die_kset; 1160 int res, ii; 1161 1162 if (!adev->mman.discovery_bin) 1163 return -EINVAL; 1164 1165 adev->ip_top = kzalloc(sizeof(*adev->ip_top), GFP_KERNEL); 1166 if (!adev->ip_top) 1167 return -ENOMEM; 1168 1169 adev->ip_top->adev = adev; 1170 1171 res = kobject_init_and_add(&adev->ip_top->kobj, &ip_discovery_ktype, 1172 &adev->dev->kobj, "ip_discovery"); 1173 if (res) { 1174 DRM_ERROR("Couldn't init and add ip_discovery/"); 1175 goto Err; 1176 } 1177 1178 die_kset = &adev->ip_top->die_kset; 1179 kobject_set_name(&die_kset->kobj, "%s", "die"); 1180 die_kset->kobj.parent = &adev->ip_top->kobj; 1181 die_kset->kobj.ktype = &die_kobj_ktype; 1182 res = kset_register(&adev->ip_top->die_kset); 1183 if (res) { 1184 DRM_ERROR("Couldn't register die_kset"); 1185 goto Err; 1186 } 1187 1188 for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++) 1189 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr; 1190 ip_hw_instance_attrs[ii] = NULL; 1191 1192 res = amdgpu_discovery_sysfs_recurse(adev); 1193 1194 return res; 1195 Err: 1196 kobject_put(&adev->ip_top->kobj); 1197 return res; 1198 } 1199 1200 /* -------------------------------------------------- */ 1201 1202 #define list_to_kobj(el) container_of(el, struct kobject, entry) 1203 1204 static void amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id *ip_hw_id) 1205 { 1206 struct list_head *el, *tmp; 1207 struct kset *hw_id_kset; 1208 1209 hw_id_kset = &ip_hw_id->hw_id_kset; 1210 spin_lock(&hw_id_kset->list_lock); 1211 list_for_each_prev_safe(el, tmp, &hw_id_kset->list) { 1212 list_del_init(el); 1213 spin_unlock(&hw_id_kset->list_lock); 1214 /* kobject is embedded in ip_hw_instance */ 1215 kobject_put(list_to_kobj(el)); 1216 spin_lock(&hw_id_kset->list_lock); 1217 } 1218 spin_unlock(&hw_id_kset->list_lock); 1219 kobject_put(&ip_hw_id->hw_id_kset.kobj); 1220 } 1221 1222 static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry) 1223 { 1224 struct list_head *el, *tmp; 1225 struct kset *ip_kset; 1226 1227 ip_kset = &ip_die_entry->ip_kset; 1228 spin_lock(&ip_kset->list_lock); 1229 list_for_each_prev_safe(el, tmp, &ip_kset->list) { 1230 list_del_init(el); 1231 spin_unlock(&ip_kset->list_lock); 1232 amdgpu_discovery_sysfs_ip_hw_free(to_ip_hw_id(list_to_kobj(el))); 1233 spin_lock(&ip_kset->list_lock); 1234 } 1235 spin_unlock(&ip_kset->list_lock); 1236 kobject_put(&ip_die_entry->ip_kset.kobj); 1237 } 1238 1239 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev) 1240 { 1241 struct list_head *el, *tmp; 1242 struct kset *die_kset; 1243 1244 die_kset = &adev->ip_top->die_kset; 1245 spin_lock(&die_kset->list_lock); 1246 list_for_each_prev_safe(el, tmp, &die_kset->list) { 1247 list_del_init(el); 1248 spin_unlock(&die_kset->list_lock); 1249 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el))); 1250 spin_lock(&die_kset->list_lock); 1251 } 1252 spin_unlock(&die_kset->list_lock); 1253 kobject_put(&adev->ip_top->die_kset.kobj); 1254 kobject_put(&adev->ip_top->kobj); 1255 } 1256 1257 /* ================================================== */ 1258 1259 static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) 1260 { 1261 uint8_t num_base_address, subrev, variant; 1262 struct binary_header *bhdr; 1263 struct ip_discovery_header *ihdr; 1264 struct die_header *dhdr; 1265 struct ip_v4 *ip; 1266 uint16_t die_offset; 1267 uint16_t ip_offset; 1268 uint16_t num_dies; 1269 uint16_t num_ips; 1270 int hw_ip; 1271 int i, j, k; 1272 int r; 1273 1274 r = amdgpu_discovery_init(adev); 1275 if (r) { 1276 DRM_ERROR("amdgpu_discovery_init failed\n"); 1277 return r; 1278 } 1279 1280 adev->gfx.xcc_mask = 0; 1281 adev->sdma.sdma_mask = 0; 1282 adev->vcn.inst_mask = 0; 1283 adev->jpeg.inst_mask = 0; 1284 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1285 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 1286 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 1287 num_dies = le16_to_cpu(ihdr->num_dies); 1288 1289 DRM_DEBUG("number of dies: %d\n", num_dies); 1290 1291 for (i = 0; i < num_dies; i++) { 1292 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 1293 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 1294 num_ips = le16_to_cpu(dhdr->num_ips); 1295 ip_offset = die_offset + sizeof(*dhdr); 1296 1297 if (le16_to_cpu(dhdr->die_id) != i) { 1298 DRM_ERROR("invalid die id %d, expected %d\n", 1299 le16_to_cpu(dhdr->die_id), i); 1300 return -EINVAL; 1301 } 1302 1303 DRM_DEBUG("number of hardware IPs on die%d: %d\n", 1304 le16_to_cpu(dhdr->die_id), num_ips); 1305 1306 for (j = 0; j < num_ips; j++) { 1307 ip = (struct ip_v4 *)(adev->mman.discovery_bin + ip_offset); 1308 1309 if (amdgpu_discovery_validate_ip(ip)) 1310 goto next_ip; 1311 1312 num_base_address = ip->num_base_address; 1313 1314 DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n", 1315 hw_id_names[le16_to_cpu(ip->hw_id)], 1316 le16_to_cpu(ip->hw_id), 1317 ip->instance_number, 1318 ip->major, ip->minor, 1319 ip->revision); 1320 1321 if (le16_to_cpu(ip->hw_id) == VCN_HWID) { 1322 /* Bit [5:0]: original revision value 1323 * Bit [7:6]: en/decode capability: 1324 * 0b00 : VCN function normally 1325 * 0b10 : encode is disabled 1326 * 0b01 : decode is disabled 1327 */ 1328 if (adev->vcn.num_vcn_inst < 1329 AMDGPU_MAX_VCN_INSTANCES) { 1330 adev->vcn.vcn_config[adev->vcn.num_vcn_inst] = 1331 ip->revision & 0xc0; 1332 adev->vcn.num_vcn_inst++; 1333 adev->vcn.inst_mask |= 1334 (1U << ip->instance_number); 1335 adev->jpeg.inst_mask |= 1336 (1U << ip->instance_number); 1337 } else { 1338 dev_err(adev->dev, "Too many VCN instances: %d vs %d\n", 1339 adev->vcn.num_vcn_inst + 1, 1340 AMDGPU_MAX_VCN_INSTANCES); 1341 } 1342 ip->revision &= ~0xc0; 1343 } 1344 if (le16_to_cpu(ip->hw_id) == SDMA0_HWID || 1345 le16_to_cpu(ip->hw_id) == SDMA1_HWID || 1346 le16_to_cpu(ip->hw_id) == SDMA2_HWID || 1347 le16_to_cpu(ip->hw_id) == SDMA3_HWID) { 1348 if (adev->sdma.num_instances < 1349 AMDGPU_MAX_SDMA_INSTANCES) { 1350 adev->sdma.num_instances++; 1351 adev->sdma.sdma_mask |= 1352 (1U << ip->instance_number); 1353 } else { 1354 dev_err(adev->dev, "Too many SDMA instances: %d vs %d\n", 1355 adev->sdma.num_instances + 1, 1356 AMDGPU_MAX_SDMA_INSTANCES); 1357 } 1358 } 1359 1360 if (le16_to_cpu(ip->hw_id) == VPE_HWID) { 1361 if (adev->vpe.num_instances < AMDGPU_MAX_VPE_INSTANCES) 1362 adev->vpe.num_instances++; 1363 else 1364 dev_err(adev->dev, "Too many VPE instances: %d vs %d\n", 1365 adev->vpe.num_instances + 1, 1366 AMDGPU_MAX_VPE_INSTANCES); 1367 } 1368 1369 if (le16_to_cpu(ip->hw_id) == UMC_HWID) { 1370 adev->gmc.num_umc++; 1371 adev->umc.node_inst_num++; 1372 } 1373 1374 if (le16_to_cpu(ip->hw_id) == GC_HWID) 1375 adev->gfx.xcc_mask |= 1376 (1U << ip->instance_number); 1377 1378 for (k = 0; k < num_base_address; k++) { 1379 /* 1380 * convert the endianness of base addresses in place, 1381 * so that we don't need to convert them when accessing adev->reg_offset. 1382 */ 1383 if (ihdr->base_addr_64_bit) 1384 /* Truncate the 64bit base address from ip discovery 1385 * and only store lower 32bit ip base in reg_offset[]. 1386 * Bits > 32 follows ASIC specific format, thus just 1387 * discard them and handle it within specific ASIC. 1388 * By this way reg_offset[] and related helpers can 1389 * stay unchanged. 1390 * The base address is in dwords, thus clear the 1391 * highest 2 bits to store. 1392 */ 1393 ip->base_address[k] = 1394 lower_32_bits(le64_to_cpu(ip->base_address_64[k])) & 0x3FFFFFFF; 1395 else 1396 ip->base_address[k] = le32_to_cpu(ip->base_address[k]); 1397 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]); 1398 } 1399 1400 for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) { 1401 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id) && 1402 hw_id_map[hw_ip] != 0) { 1403 DRM_DEBUG("set register base offset for %s\n", 1404 hw_id_names[le16_to_cpu(ip->hw_id)]); 1405 adev->reg_offset[hw_ip][ip->instance_number] = 1406 ip->base_address; 1407 /* Instance support is somewhat inconsistent. 1408 * SDMA is a good example. Sienna cichlid has 4 total 1409 * SDMA instances, each enumerated separately (HWIDs 1410 * 42, 43, 68, 69). Arcturus has 8 total SDMA instances, 1411 * but they are enumerated as multiple instances of the 1412 * same HWIDs (4x HWID 42, 4x HWID 43). UMC is another 1413 * example. On most chips there are multiple instances 1414 * with the same HWID. 1415 */ 1416 1417 if (ihdr->version < 3) { 1418 subrev = 0; 1419 variant = 0; 1420 } else { 1421 subrev = ip->sub_revision; 1422 variant = ip->variant; 1423 } 1424 1425 adev->ip_versions[hw_ip] 1426 [ip->instance_number] = 1427 IP_VERSION_FULL(ip->major, 1428 ip->minor, 1429 ip->revision, 1430 variant, 1431 subrev); 1432 } 1433 } 1434 1435 next_ip: 1436 if (ihdr->base_addr_64_bit) 1437 ip_offset += struct_size(ip, base_address_64, ip->num_base_address); 1438 else 1439 ip_offset += struct_size(ip, base_address, ip->num_base_address); 1440 } 1441 } 1442 1443 return 0; 1444 } 1445 1446 static void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev) 1447 { 1448 int vcn_harvest_count = 0; 1449 int umc_harvest_count = 0; 1450 1451 /* 1452 * Harvest table does not fit Navi1x and legacy GPUs, 1453 * so read harvest bit per IP data structure to set 1454 * harvest configuration. 1455 */ 1456 if (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 2, 0) && 1457 amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 3) && 1458 amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 4)) { 1459 if ((adev->pdev->device == 0x731E && 1460 (adev->pdev->revision == 0xC6 || 1461 adev->pdev->revision == 0xC7)) || 1462 (adev->pdev->device == 0x7340 && 1463 adev->pdev->revision == 0xC9) || 1464 (adev->pdev->device == 0x7360 && 1465 adev->pdev->revision == 0xC7)) 1466 amdgpu_discovery_read_harvest_bit_per_ip(adev, 1467 &vcn_harvest_count); 1468 } else { 1469 amdgpu_discovery_read_from_harvest_table(adev, 1470 &vcn_harvest_count, 1471 &umc_harvest_count); 1472 } 1473 1474 amdgpu_discovery_harvest_config_quirk(adev); 1475 1476 if (vcn_harvest_count == adev->vcn.num_vcn_inst) { 1477 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK; 1478 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK; 1479 } 1480 1481 if (umc_harvest_count < adev->gmc.num_umc) { 1482 adev->gmc.num_umc -= umc_harvest_count; 1483 } 1484 } 1485 1486 union gc_info { 1487 struct gc_info_v1_0 v1; 1488 struct gc_info_v1_1 v1_1; 1489 struct gc_info_v1_2 v1_2; 1490 struct gc_info_v2_0 v2; 1491 struct gc_info_v2_1 v2_1; 1492 }; 1493 1494 static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) 1495 { 1496 struct binary_header *bhdr; 1497 union gc_info *gc_info; 1498 u16 offset; 1499 1500 if (!adev->mman.discovery_bin) { 1501 DRM_ERROR("ip discovery uninitialized\n"); 1502 return -EINVAL; 1503 } 1504 1505 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1506 offset = le16_to_cpu(bhdr->table_list[GC].offset); 1507 1508 if (!offset) 1509 return 0; 1510 1511 gc_info = (union gc_info *)(adev->mman.discovery_bin + offset); 1512 1513 switch (le16_to_cpu(gc_info->v1.header.version_major)) { 1514 case 1: 1515 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se); 1516 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) + 1517 le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa)); 1518 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1519 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se); 1520 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c); 1521 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs); 1522 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds); 1523 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth); 1524 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth); 1525 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer); 1526 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size); 1527 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd); 1528 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu); 1529 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size); 1530 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) / 1531 le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1532 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc); 1533 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 1) { 1534 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v1_1.gc_num_tcp_per_sa); 1535 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v1_1.gc_num_sdp_interface); 1536 adev->gfx.config.gc_num_tcps = le32_to_cpu(gc_info->v1_1.gc_num_tcps); 1537 } 1538 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 2) { 1539 adev->gfx.config.gc_num_tcp_per_wpg = le32_to_cpu(gc_info->v1_2.gc_num_tcp_per_wpg); 1540 adev->gfx.config.gc_tcp_l1_size = le32_to_cpu(gc_info->v1_2.gc_tcp_l1_size); 1541 adev->gfx.config.gc_num_sqc_per_wgp = le32_to_cpu(gc_info->v1_2.gc_num_sqc_per_wgp); 1542 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_instruction_cache_size_per_sqc); 1543 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_data_cache_size_per_sqc); 1544 adev->gfx.config.gc_gl1c_per_sa = le32_to_cpu(gc_info->v1_2.gc_gl1c_per_sa); 1545 adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance); 1546 adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu); 1547 } 1548 break; 1549 case 2: 1550 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se); 1551 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh); 1552 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1553 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se); 1554 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs); 1555 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs); 1556 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds); 1557 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth); 1558 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth); 1559 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer); 1560 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size); 1561 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd); 1562 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu); 1563 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size); 1564 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) / 1565 le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1566 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc); 1567 if (le16_to_cpu(gc_info->v2.header.version_minor) == 1) { 1568 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v2_1.gc_num_tcp_per_sh); 1569 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v2_1.gc_tcp_size_per_cu); 1570 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v2_1.gc_num_sdp_interface); /* per XCD */ 1571 adev->gfx.config.gc_num_cu_per_sqc = le32_to_cpu(gc_info->v2_1.gc_num_cu_per_sqc); 1572 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_instruction_cache_size_per_sqc); 1573 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_scalar_data_cache_size_per_sqc); 1574 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v2_1.gc_tcc_size); /* per XCD */ 1575 } 1576 break; 1577 default: 1578 dev_err(adev->dev, 1579 "Unhandled GC info table %d.%d\n", 1580 le16_to_cpu(gc_info->v1.header.version_major), 1581 le16_to_cpu(gc_info->v1.header.version_minor)); 1582 return -EINVAL; 1583 } 1584 return 0; 1585 } 1586 1587 union mall_info { 1588 struct mall_info_v1_0 v1; 1589 struct mall_info_v2_0 v2; 1590 }; 1591 1592 static int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev) 1593 { 1594 struct binary_header *bhdr; 1595 union mall_info *mall_info; 1596 u32 u, mall_size_per_umc, m_s_present, half_use; 1597 u64 mall_size; 1598 u16 offset; 1599 1600 if (!adev->mman.discovery_bin) { 1601 DRM_ERROR("ip discovery uninitialized\n"); 1602 return -EINVAL; 1603 } 1604 1605 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1606 offset = le16_to_cpu(bhdr->table_list[MALL_INFO].offset); 1607 1608 if (!offset) 1609 return 0; 1610 1611 mall_info = (union mall_info *)(adev->mman.discovery_bin + offset); 1612 1613 switch (le16_to_cpu(mall_info->v1.header.version_major)) { 1614 case 1: 1615 mall_size = 0; 1616 mall_size_per_umc = le32_to_cpu(mall_info->v1.mall_size_per_m); 1617 m_s_present = le32_to_cpu(mall_info->v1.m_s_present); 1618 half_use = le32_to_cpu(mall_info->v1.m_half_use); 1619 for (u = 0; u < adev->gmc.num_umc; u++) { 1620 if (m_s_present & (1 << u)) 1621 mall_size += mall_size_per_umc * 2; 1622 else if (half_use & (1 << u)) 1623 mall_size += mall_size_per_umc / 2; 1624 else 1625 mall_size += mall_size_per_umc; 1626 } 1627 adev->gmc.mall_size = mall_size; 1628 adev->gmc.m_half_use = half_use; 1629 break; 1630 case 2: 1631 mall_size_per_umc = le32_to_cpu(mall_info->v2.mall_size_per_umc); 1632 adev->gmc.mall_size = mall_size_per_umc * adev->gmc.num_umc; 1633 break; 1634 default: 1635 dev_err(adev->dev, 1636 "Unhandled MALL info table %d.%d\n", 1637 le16_to_cpu(mall_info->v1.header.version_major), 1638 le16_to_cpu(mall_info->v1.header.version_minor)); 1639 return -EINVAL; 1640 } 1641 return 0; 1642 } 1643 1644 union vcn_info { 1645 struct vcn_info_v1_0 v1; 1646 }; 1647 1648 static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev) 1649 { 1650 struct binary_header *bhdr; 1651 union vcn_info *vcn_info; 1652 u16 offset; 1653 int v; 1654 1655 if (!adev->mman.discovery_bin) { 1656 DRM_ERROR("ip discovery uninitialized\n"); 1657 return -EINVAL; 1658 } 1659 1660 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES 1661 * which is smaller than VCN_INFO_TABLE_MAX_NUM_INSTANCES 1662 * but that may change in the future with new GPUs so keep this 1663 * check for defensive purposes. 1664 */ 1665 if (adev->vcn.num_vcn_inst > VCN_INFO_TABLE_MAX_NUM_INSTANCES) { 1666 dev_err(adev->dev, "invalid vcn instances\n"); 1667 return -EINVAL; 1668 } 1669 1670 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1671 offset = le16_to_cpu(bhdr->table_list[VCN_INFO].offset); 1672 1673 if (!offset) 1674 return 0; 1675 1676 vcn_info = (union vcn_info *)(adev->mman.discovery_bin + offset); 1677 1678 switch (le16_to_cpu(vcn_info->v1.header.version_major)) { 1679 case 1: 1680 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES 1681 * so this won't overflow. 1682 */ 1683 for (v = 0; v < adev->vcn.num_vcn_inst; v++) { 1684 adev->vcn.vcn_codec_disable_mask[v] = 1685 le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits); 1686 } 1687 break; 1688 default: 1689 dev_err(adev->dev, 1690 "Unhandled VCN info table %d.%d\n", 1691 le16_to_cpu(vcn_info->v1.header.version_major), 1692 le16_to_cpu(vcn_info->v1.header.version_minor)); 1693 return -EINVAL; 1694 } 1695 return 0; 1696 } 1697 1698 union nps_info { 1699 struct nps_info_v1_0 v1; 1700 }; 1701 1702 int amdgpu_discovery_get_nps_info(struct amdgpu_device *adev, 1703 uint32_t *nps_type, 1704 struct amdgpu_gmc_memrange **ranges, 1705 int *range_cnt) 1706 { 1707 struct amdgpu_gmc_memrange *mem_ranges; 1708 struct binary_header *bhdr; 1709 union nps_info *nps_info; 1710 u16 offset; 1711 int i; 1712 1713 if (!nps_type || !range_cnt || !ranges) 1714 return -EINVAL; 1715 1716 if (!adev->mman.discovery_bin) { 1717 dev_err(adev->dev, 1718 "fetch mem range failed, ip discovery uninitialized\n"); 1719 return -EINVAL; 1720 } 1721 1722 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1723 offset = le16_to_cpu(bhdr->table_list[NPS_INFO].offset); 1724 1725 if (!offset) 1726 return -ENOENT; 1727 1728 /* If verification fails, return as if NPS table doesn't exist */ 1729 if (amdgpu_discovery_verify_npsinfo(adev, bhdr)) 1730 return -ENOENT; 1731 1732 nps_info = (union nps_info *)(adev->mman.discovery_bin + offset); 1733 1734 switch (le16_to_cpu(nps_info->v1.header.version_major)) { 1735 case 1: 1736 *nps_type = nps_info->v1.nps_type; 1737 *range_cnt = nps_info->v1.count; 1738 mem_ranges = kvzalloc( 1739 *range_cnt * sizeof(struct amdgpu_gmc_memrange), 1740 GFP_KERNEL); 1741 for (i = 0; i < *range_cnt; i++) { 1742 mem_ranges[i].base_address = 1743 nps_info->v1.instance_info[i].base_address; 1744 mem_ranges[i].limit_address = 1745 nps_info->v1.instance_info[i].limit_address; 1746 mem_ranges[i].nid_mask = -1; 1747 mem_ranges[i].flags = 0; 1748 } 1749 *ranges = mem_ranges; 1750 break; 1751 default: 1752 dev_err(adev->dev, "Unhandled NPS info table %d.%d\n", 1753 le16_to_cpu(nps_info->v1.header.version_major), 1754 le16_to_cpu(nps_info->v1.header.version_minor)); 1755 return -EINVAL; 1756 } 1757 1758 return 0; 1759 } 1760 1761 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev) 1762 { 1763 /* what IP to use for this? */ 1764 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1765 case IP_VERSION(9, 0, 1): 1766 case IP_VERSION(9, 1, 0): 1767 case IP_VERSION(9, 2, 1): 1768 case IP_VERSION(9, 2, 2): 1769 case IP_VERSION(9, 3, 0): 1770 case IP_VERSION(9, 4, 0): 1771 case IP_VERSION(9, 4, 1): 1772 case IP_VERSION(9, 4, 2): 1773 case IP_VERSION(9, 4, 3): 1774 case IP_VERSION(9, 4, 4): 1775 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 1776 break; 1777 case IP_VERSION(10, 1, 10): 1778 case IP_VERSION(10, 1, 1): 1779 case IP_VERSION(10, 1, 2): 1780 case IP_VERSION(10, 1, 3): 1781 case IP_VERSION(10, 1, 4): 1782 case IP_VERSION(10, 3, 0): 1783 case IP_VERSION(10, 3, 1): 1784 case IP_VERSION(10, 3, 2): 1785 case IP_VERSION(10, 3, 3): 1786 case IP_VERSION(10, 3, 4): 1787 case IP_VERSION(10, 3, 5): 1788 case IP_VERSION(10, 3, 6): 1789 case IP_VERSION(10, 3, 7): 1790 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 1791 break; 1792 case IP_VERSION(11, 0, 0): 1793 case IP_VERSION(11, 0, 1): 1794 case IP_VERSION(11, 0, 2): 1795 case IP_VERSION(11, 0, 3): 1796 case IP_VERSION(11, 0, 4): 1797 case IP_VERSION(11, 5, 0): 1798 case IP_VERSION(11, 5, 1): 1799 amdgpu_device_ip_block_add(adev, &soc21_common_ip_block); 1800 break; 1801 case IP_VERSION(12, 0, 0): 1802 case IP_VERSION(12, 0, 1): 1803 amdgpu_device_ip_block_add(adev, &soc24_common_ip_block); 1804 break; 1805 default: 1806 dev_err(adev->dev, 1807 "Failed to add common ip block(GC_HWIP:0x%x)\n", 1808 amdgpu_ip_version(adev, GC_HWIP, 0)); 1809 return -EINVAL; 1810 } 1811 return 0; 1812 } 1813 1814 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev) 1815 { 1816 /* use GC or MMHUB IP version */ 1817 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1818 case IP_VERSION(9, 0, 1): 1819 case IP_VERSION(9, 1, 0): 1820 case IP_VERSION(9, 2, 1): 1821 case IP_VERSION(9, 2, 2): 1822 case IP_VERSION(9, 3, 0): 1823 case IP_VERSION(9, 4, 0): 1824 case IP_VERSION(9, 4, 1): 1825 case IP_VERSION(9, 4, 2): 1826 case IP_VERSION(9, 4, 3): 1827 case IP_VERSION(9, 4, 4): 1828 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 1829 break; 1830 case IP_VERSION(10, 1, 10): 1831 case IP_VERSION(10, 1, 1): 1832 case IP_VERSION(10, 1, 2): 1833 case IP_VERSION(10, 1, 3): 1834 case IP_VERSION(10, 1, 4): 1835 case IP_VERSION(10, 3, 0): 1836 case IP_VERSION(10, 3, 1): 1837 case IP_VERSION(10, 3, 2): 1838 case IP_VERSION(10, 3, 3): 1839 case IP_VERSION(10, 3, 4): 1840 case IP_VERSION(10, 3, 5): 1841 case IP_VERSION(10, 3, 6): 1842 case IP_VERSION(10, 3, 7): 1843 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 1844 break; 1845 case IP_VERSION(11, 0, 0): 1846 case IP_VERSION(11, 0, 1): 1847 case IP_VERSION(11, 0, 2): 1848 case IP_VERSION(11, 0, 3): 1849 case IP_VERSION(11, 0, 4): 1850 case IP_VERSION(11, 5, 0): 1851 case IP_VERSION(11, 5, 1): 1852 amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block); 1853 break; 1854 case IP_VERSION(12, 0, 0): 1855 case IP_VERSION(12, 0, 1): 1856 amdgpu_device_ip_block_add(adev, &gmc_v12_0_ip_block); 1857 break; 1858 default: 1859 dev_err(adev->dev, "Failed to add gmc ip block(GC_HWIP:0x%x)\n", 1860 amdgpu_ip_version(adev, GC_HWIP, 0)); 1861 return -EINVAL; 1862 } 1863 return 0; 1864 } 1865 1866 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev) 1867 { 1868 switch (amdgpu_ip_version(adev, OSSSYS_HWIP, 0)) { 1869 case IP_VERSION(4, 0, 0): 1870 case IP_VERSION(4, 0, 1): 1871 case IP_VERSION(4, 1, 0): 1872 case IP_VERSION(4, 1, 1): 1873 case IP_VERSION(4, 3, 0): 1874 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 1875 break; 1876 case IP_VERSION(4, 2, 0): 1877 case IP_VERSION(4, 2, 1): 1878 case IP_VERSION(4, 4, 0): 1879 case IP_VERSION(4, 4, 2): 1880 case IP_VERSION(4, 4, 5): 1881 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 1882 break; 1883 case IP_VERSION(5, 0, 0): 1884 case IP_VERSION(5, 0, 1): 1885 case IP_VERSION(5, 0, 2): 1886 case IP_VERSION(5, 0, 3): 1887 case IP_VERSION(5, 2, 0): 1888 case IP_VERSION(5, 2, 1): 1889 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 1890 break; 1891 case IP_VERSION(6, 0, 0): 1892 case IP_VERSION(6, 0, 1): 1893 case IP_VERSION(6, 0, 2): 1894 amdgpu_device_ip_block_add(adev, &ih_v6_0_ip_block); 1895 break; 1896 case IP_VERSION(6, 1, 0): 1897 amdgpu_device_ip_block_add(adev, &ih_v6_1_ip_block); 1898 break; 1899 case IP_VERSION(7, 0, 0): 1900 amdgpu_device_ip_block_add(adev, &ih_v7_0_ip_block); 1901 break; 1902 default: 1903 dev_err(adev->dev, 1904 "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n", 1905 amdgpu_ip_version(adev, OSSSYS_HWIP, 0)); 1906 return -EINVAL; 1907 } 1908 return 0; 1909 } 1910 1911 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev) 1912 { 1913 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 1914 case IP_VERSION(9, 0, 0): 1915 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 1916 break; 1917 case IP_VERSION(10, 0, 0): 1918 case IP_VERSION(10, 0, 1): 1919 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); 1920 break; 1921 case IP_VERSION(11, 0, 0): 1922 case IP_VERSION(11, 0, 2): 1923 case IP_VERSION(11, 0, 4): 1924 case IP_VERSION(11, 0, 5): 1925 case IP_VERSION(11, 0, 9): 1926 case IP_VERSION(11, 0, 7): 1927 case IP_VERSION(11, 0, 11): 1928 case IP_VERSION(11, 0, 12): 1929 case IP_VERSION(11, 0, 13): 1930 case IP_VERSION(11, 5, 0): 1931 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 1932 break; 1933 case IP_VERSION(11, 0, 8): 1934 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block); 1935 break; 1936 case IP_VERSION(11, 0, 3): 1937 case IP_VERSION(12, 0, 1): 1938 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); 1939 break; 1940 case IP_VERSION(13, 0, 0): 1941 case IP_VERSION(13, 0, 1): 1942 case IP_VERSION(13, 0, 2): 1943 case IP_VERSION(13, 0, 3): 1944 case IP_VERSION(13, 0, 5): 1945 case IP_VERSION(13, 0, 6): 1946 case IP_VERSION(13, 0, 7): 1947 case IP_VERSION(13, 0, 8): 1948 case IP_VERSION(13, 0, 10): 1949 case IP_VERSION(13, 0, 11): 1950 case IP_VERSION(13, 0, 14): 1951 case IP_VERSION(14, 0, 0): 1952 case IP_VERSION(14, 0, 1): 1953 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); 1954 break; 1955 case IP_VERSION(13, 0, 4): 1956 amdgpu_device_ip_block_add(adev, &psp_v13_0_4_ip_block); 1957 break; 1958 case IP_VERSION(14, 0, 2): 1959 case IP_VERSION(14, 0, 3): 1960 amdgpu_device_ip_block_add(adev, &psp_v14_0_ip_block); 1961 break; 1962 default: 1963 dev_err(adev->dev, 1964 "Failed to add psp ip block(MP0_HWIP:0x%x)\n", 1965 amdgpu_ip_version(adev, MP0_HWIP, 0)); 1966 return -EINVAL; 1967 } 1968 return 0; 1969 } 1970 1971 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev) 1972 { 1973 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1974 case IP_VERSION(9, 0, 0): 1975 case IP_VERSION(10, 0, 0): 1976 case IP_VERSION(10, 0, 1): 1977 case IP_VERSION(11, 0, 2): 1978 if (adev->asic_type == CHIP_ARCTURUS) 1979 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 1980 else 1981 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 1982 break; 1983 case IP_VERSION(11, 0, 0): 1984 case IP_VERSION(11, 0, 5): 1985 case IP_VERSION(11, 0, 9): 1986 case IP_VERSION(11, 0, 7): 1987 case IP_VERSION(11, 0, 8): 1988 case IP_VERSION(11, 0, 11): 1989 case IP_VERSION(11, 0, 12): 1990 case IP_VERSION(11, 0, 13): 1991 case IP_VERSION(11, 5, 0): 1992 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 1993 break; 1994 case IP_VERSION(12, 0, 0): 1995 case IP_VERSION(12, 0, 1): 1996 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); 1997 break; 1998 case IP_VERSION(13, 0, 0): 1999 case IP_VERSION(13, 0, 1): 2000 case IP_VERSION(13, 0, 2): 2001 case IP_VERSION(13, 0, 3): 2002 case IP_VERSION(13, 0, 4): 2003 case IP_VERSION(13, 0, 5): 2004 case IP_VERSION(13, 0, 6): 2005 case IP_VERSION(13, 0, 7): 2006 case IP_VERSION(13, 0, 8): 2007 case IP_VERSION(13, 0, 10): 2008 case IP_VERSION(13, 0, 11): 2009 case IP_VERSION(13, 0, 14): 2010 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); 2011 break; 2012 case IP_VERSION(14, 0, 0): 2013 case IP_VERSION(14, 0, 1): 2014 case IP_VERSION(14, 0, 2): 2015 case IP_VERSION(14, 0, 3): 2016 amdgpu_device_ip_block_add(adev, &smu_v14_0_ip_block); 2017 break; 2018 default: 2019 dev_err(adev->dev, 2020 "Failed to add smu ip block(MP1_HWIP:0x%x)\n", 2021 amdgpu_ip_version(adev, MP1_HWIP, 0)); 2022 return -EINVAL; 2023 } 2024 return 0; 2025 } 2026 2027 #if defined(CONFIG_DRM_AMD_DC) 2028 static void amdgpu_discovery_set_sriov_display(struct amdgpu_device *adev) 2029 { 2030 amdgpu_device_set_sriov_virtual_display(adev); 2031 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2032 } 2033 #endif 2034 2035 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev) 2036 { 2037 if (adev->enable_virtual_display) { 2038 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2039 return 0; 2040 } 2041 2042 if (!amdgpu_device_has_dc_support(adev)) 2043 return 0; 2044 2045 #if defined(CONFIG_DRM_AMD_DC) 2046 if (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2047 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2048 case IP_VERSION(1, 0, 0): 2049 case IP_VERSION(1, 0, 1): 2050 case IP_VERSION(2, 0, 2): 2051 case IP_VERSION(2, 0, 0): 2052 case IP_VERSION(2, 0, 3): 2053 case IP_VERSION(2, 1, 0): 2054 case IP_VERSION(3, 0, 0): 2055 case IP_VERSION(3, 0, 2): 2056 case IP_VERSION(3, 0, 3): 2057 case IP_VERSION(3, 0, 1): 2058 case IP_VERSION(3, 1, 2): 2059 case IP_VERSION(3, 1, 3): 2060 case IP_VERSION(3, 1, 4): 2061 case IP_VERSION(3, 1, 5): 2062 case IP_VERSION(3, 1, 6): 2063 case IP_VERSION(3, 2, 0): 2064 case IP_VERSION(3, 2, 1): 2065 case IP_VERSION(3, 5, 0): 2066 case IP_VERSION(3, 5, 1): 2067 case IP_VERSION(4, 1, 0): 2068 /* TODO: Fix IP version. DC code expects version 4.0.1 */ 2069 if (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(4, 1, 0)) 2070 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(4, 0, 1); 2071 2072 if (amdgpu_sriov_vf(adev)) 2073 amdgpu_discovery_set_sriov_display(adev); 2074 else 2075 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2076 break; 2077 default: 2078 dev_err(adev->dev, 2079 "Failed to add dm ip block(DCE_HWIP:0x%x)\n", 2080 amdgpu_ip_version(adev, DCE_HWIP, 0)); 2081 return -EINVAL; 2082 } 2083 } else if (amdgpu_ip_version(adev, DCI_HWIP, 0)) { 2084 switch (amdgpu_ip_version(adev, DCI_HWIP, 0)) { 2085 case IP_VERSION(12, 0, 0): 2086 case IP_VERSION(12, 0, 1): 2087 case IP_VERSION(12, 1, 0): 2088 if (amdgpu_sriov_vf(adev)) 2089 amdgpu_discovery_set_sriov_display(adev); 2090 else 2091 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2092 break; 2093 default: 2094 dev_err(adev->dev, 2095 "Failed to add dm ip block(DCI_HWIP:0x%x)\n", 2096 amdgpu_ip_version(adev, DCI_HWIP, 0)); 2097 return -EINVAL; 2098 } 2099 } 2100 #endif 2101 return 0; 2102 } 2103 2104 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) 2105 { 2106 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2107 case IP_VERSION(9, 0, 1): 2108 case IP_VERSION(9, 1, 0): 2109 case IP_VERSION(9, 2, 1): 2110 case IP_VERSION(9, 2, 2): 2111 case IP_VERSION(9, 3, 0): 2112 case IP_VERSION(9, 4, 0): 2113 case IP_VERSION(9, 4, 1): 2114 case IP_VERSION(9, 4, 2): 2115 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 2116 break; 2117 case IP_VERSION(9, 4, 3): 2118 case IP_VERSION(9, 4, 4): 2119 amdgpu_device_ip_block_add(adev, &gfx_v9_4_3_ip_block); 2120 break; 2121 case IP_VERSION(10, 1, 10): 2122 case IP_VERSION(10, 1, 2): 2123 case IP_VERSION(10, 1, 1): 2124 case IP_VERSION(10, 1, 3): 2125 case IP_VERSION(10, 1, 4): 2126 case IP_VERSION(10, 3, 0): 2127 case IP_VERSION(10, 3, 2): 2128 case IP_VERSION(10, 3, 1): 2129 case IP_VERSION(10, 3, 4): 2130 case IP_VERSION(10, 3, 5): 2131 case IP_VERSION(10, 3, 6): 2132 case IP_VERSION(10, 3, 3): 2133 case IP_VERSION(10, 3, 7): 2134 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 2135 break; 2136 case IP_VERSION(11, 0, 0): 2137 case IP_VERSION(11, 0, 1): 2138 case IP_VERSION(11, 0, 2): 2139 case IP_VERSION(11, 0, 3): 2140 case IP_VERSION(11, 0, 4): 2141 case IP_VERSION(11, 5, 0): 2142 case IP_VERSION(11, 5, 1): 2143 amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block); 2144 break; 2145 case IP_VERSION(12, 0, 0): 2146 case IP_VERSION(12, 0, 1): 2147 if (!amdgpu_exp_hw_support) 2148 return -EINVAL; 2149 amdgpu_device_ip_block_add(adev, &gfx_v12_0_ip_block); 2150 break; 2151 default: 2152 dev_err(adev->dev, "Failed to add gfx ip block(GC_HWIP:0x%x)\n", 2153 amdgpu_ip_version(adev, GC_HWIP, 0)); 2154 return -EINVAL; 2155 } 2156 return 0; 2157 } 2158 2159 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev) 2160 { 2161 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 2162 case IP_VERSION(4, 0, 0): 2163 case IP_VERSION(4, 0, 1): 2164 case IP_VERSION(4, 1, 0): 2165 case IP_VERSION(4, 1, 1): 2166 case IP_VERSION(4, 1, 2): 2167 case IP_VERSION(4, 2, 0): 2168 case IP_VERSION(4, 2, 2): 2169 case IP_VERSION(4, 4, 0): 2170 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 2171 break; 2172 case IP_VERSION(4, 4, 2): 2173 case IP_VERSION(4, 4, 5): 2174 amdgpu_device_ip_block_add(adev, &sdma_v4_4_2_ip_block); 2175 break; 2176 case IP_VERSION(5, 0, 0): 2177 case IP_VERSION(5, 0, 1): 2178 case IP_VERSION(5, 0, 2): 2179 case IP_VERSION(5, 0, 5): 2180 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 2181 break; 2182 case IP_VERSION(5, 2, 0): 2183 case IP_VERSION(5, 2, 2): 2184 case IP_VERSION(5, 2, 4): 2185 case IP_VERSION(5, 2, 5): 2186 case IP_VERSION(5, 2, 6): 2187 case IP_VERSION(5, 2, 3): 2188 case IP_VERSION(5, 2, 1): 2189 case IP_VERSION(5, 2, 7): 2190 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 2191 break; 2192 case IP_VERSION(6, 0, 0): 2193 case IP_VERSION(6, 0, 1): 2194 case IP_VERSION(6, 0, 2): 2195 case IP_VERSION(6, 0, 3): 2196 case IP_VERSION(6, 1, 0): 2197 case IP_VERSION(6, 1, 1): 2198 amdgpu_device_ip_block_add(adev, &sdma_v6_0_ip_block); 2199 break; 2200 case IP_VERSION(7, 0, 0): 2201 case IP_VERSION(7, 0, 1): 2202 amdgpu_device_ip_block_add(adev, &sdma_v7_0_ip_block); 2203 break; 2204 default: 2205 dev_err(adev->dev, 2206 "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n", 2207 amdgpu_ip_version(adev, SDMA0_HWIP, 0)); 2208 return -EINVAL; 2209 } 2210 return 0; 2211 } 2212 2213 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) 2214 { 2215 if (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 2216 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 2217 case IP_VERSION(7, 0, 0): 2218 case IP_VERSION(7, 2, 0): 2219 /* UVD is not supported on vega20 SR-IOV */ 2220 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 2221 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); 2222 break; 2223 default: 2224 dev_err(adev->dev, 2225 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n", 2226 amdgpu_ip_version(adev, UVD_HWIP, 0)); 2227 return -EINVAL; 2228 } 2229 switch (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 2230 case IP_VERSION(4, 0, 0): 2231 case IP_VERSION(4, 1, 0): 2232 /* VCE is not supported on vega20 SR-IOV */ 2233 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 2234 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); 2235 break; 2236 default: 2237 dev_err(adev->dev, 2238 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n", 2239 amdgpu_ip_version(adev, VCE_HWIP, 0)); 2240 return -EINVAL; 2241 } 2242 } else { 2243 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 2244 case IP_VERSION(1, 0, 0): 2245 case IP_VERSION(1, 0, 1): 2246 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); 2247 break; 2248 case IP_VERSION(2, 0, 0): 2249 case IP_VERSION(2, 0, 2): 2250 case IP_VERSION(2, 2, 0): 2251 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 2252 if (!amdgpu_sriov_vf(adev)) 2253 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 2254 break; 2255 case IP_VERSION(2, 0, 3): 2256 break; 2257 case IP_VERSION(2, 5, 0): 2258 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 2259 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block); 2260 break; 2261 case IP_VERSION(2, 6, 0): 2262 amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block); 2263 amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block); 2264 break; 2265 case IP_VERSION(3, 0, 0): 2266 case IP_VERSION(3, 0, 16): 2267 case IP_VERSION(3, 1, 1): 2268 case IP_VERSION(3, 1, 2): 2269 case IP_VERSION(3, 0, 2): 2270 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 2271 if (!amdgpu_sriov_vf(adev)) 2272 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 2273 break; 2274 case IP_VERSION(3, 0, 33): 2275 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 2276 break; 2277 case IP_VERSION(4, 0, 0): 2278 case IP_VERSION(4, 0, 2): 2279 case IP_VERSION(4, 0, 4): 2280 amdgpu_device_ip_block_add(adev, &vcn_v4_0_ip_block); 2281 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block); 2282 break; 2283 case IP_VERSION(4, 0, 3): 2284 amdgpu_device_ip_block_add(adev, &vcn_v4_0_3_ip_block); 2285 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_3_ip_block); 2286 break; 2287 case IP_VERSION(4, 0, 5): 2288 case IP_VERSION(4, 0, 6): 2289 amdgpu_device_ip_block_add(adev, &vcn_v4_0_5_ip_block); 2290 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_5_ip_block); 2291 break; 2292 case IP_VERSION(5, 0, 0): 2293 amdgpu_device_ip_block_add(adev, &vcn_v5_0_0_ip_block); 2294 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_0_ip_block); 2295 if (amdgpu_jpeg_test) 2296 adev->enable_jpeg_test = true; 2297 break; 2298 default: 2299 dev_err(adev->dev, 2300 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n", 2301 amdgpu_ip_version(adev, UVD_HWIP, 0)); 2302 return -EINVAL; 2303 } 2304 } 2305 return 0; 2306 } 2307 2308 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev) 2309 { 2310 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2311 case IP_VERSION(11, 0, 0): 2312 case IP_VERSION(11, 0, 1): 2313 case IP_VERSION(11, 0, 2): 2314 case IP_VERSION(11, 0, 3): 2315 case IP_VERSION(11, 0, 4): 2316 case IP_VERSION(11, 5, 0): 2317 case IP_VERSION(11, 5, 1): 2318 amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block); 2319 adev->enable_mes = true; 2320 adev->enable_mes_kiq = true; 2321 break; 2322 case IP_VERSION(12, 0, 0): 2323 case IP_VERSION(12, 0, 1): 2324 amdgpu_device_ip_block_add(adev, &mes_v12_0_ip_block); 2325 adev->enable_mes = true; 2326 adev->enable_mes_kiq = true; 2327 if (amdgpu_uni_mes) 2328 adev->enable_uni_mes = true; 2329 break; 2330 default: 2331 break; 2332 } 2333 return 0; 2334 } 2335 2336 static void amdgpu_discovery_init_soc_config(struct amdgpu_device *adev) 2337 { 2338 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2339 case IP_VERSION(9, 4, 3): 2340 case IP_VERSION(9, 4, 4): 2341 aqua_vanjaram_init_soc_config(adev); 2342 break; 2343 default: 2344 break; 2345 } 2346 } 2347 2348 static int amdgpu_discovery_set_vpe_ip_blocks(struct amdgpu_device *adev) 2349 { 2350 switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) { 2351 case IP_VERSION(6, 1, 0): 2352 case IP_VERSION(6, 1, 1): 2353 amdgpu_device_ip_block_add(adev, &vpe_v6_1_ip_block); 2354 break; 2355 default: 2356 break; 2357 } 2358 2359 return 0; 2360 } 2361 2362 static int amdgpu_discovery_set_umsch_mm_ip_blocks(struct amdgpu_device *adev) 2363 { 2364 switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) { 2365 case IP_VERSION(4, 0, 5): 2366 case IP_VERSION(4, 0, 6): 2367 if (amdgpu_umsch_mm & 0x1) { 2368 amdgpu_device_ip_block_add(adev, &umsch_mm_v4_0_ip_block); 2369 adev->enable_umsch_mm = true; 2370 } 2371 break; 2372 default: 2373 break; 2374 } 2375 2376 return 0; 2377 } 2378 2379 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 2380 { 2381 int r; 2382 2383 switch (adev->asic_type) { 2384 case CHIP_VEGA10: 2385 vega10_reg_base_init(adev); 2386 adev->sdma.num_instances = 2; 2387 adev->gmc.num_umc = 4; 2388 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0); 2389 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0); 2390 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0); 2391 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0); 2392 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0); 2393 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0); 2394 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 2395 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0); 2396 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0); 2397 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 2398 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 2399 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 2400 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0); 2401 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1); 2402 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 2403 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 2404 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0); 2405 break; 2406 case CHIP_VEGA12: 2407 vega10_reg_base_init(adev); 2408 adev->sdma.num_instances = 2; 2409 adev->gmc.num_umc = 4; 2410 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0); 2411 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0); 2412 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1); 2413 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1); 2414 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1); 2415 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1); 2416 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0); 2417 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0); 2418 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0); 2419 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 2420 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 2421 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 2422 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1); 2423 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1); 2424 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 2425 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 2426 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1); 2427 break; 2428 case CHIP_RAVEN: 2429 vega10_reg_base_init(adev); 2430 adev->sdma.num_instances = 1; 2431 adev->vcn.num_vcn_inst = 1; 2432 adev->gmc.num_umc = 2; 2433 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { 2434 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0); 2435 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0); 2436 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1); 2437 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1); 2438 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1); 2439 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1); 2440 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1); 2441 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0); 2442 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1); 2443 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1); 2444 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0); 2445 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1); 2446 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2); 2447 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1); 2448 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1); 2449 } else { 2450 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0); 2451 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0); 2452 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0); 2453 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0); 2454 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0); 2455 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 2456 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0); 2457 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0); 2458 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0); 2459 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0); 2460 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0); 2461 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0); 2462 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0); 2463 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0); 2464 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0); 2465 } 2466 break; 2467 case CHIP_VEGA20: 2468 vega20_reg_base_init(adev); 2469 adev->sdma.num_instances = 2; 2470 adev->gmc.num_umc = 8; 2471 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2472 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2473 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0); 2474 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0); 2475 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0); 2476 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0); 2477 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0); 2478 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0); 2479 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1); 2480 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2); 2481 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2482 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2); 2483 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2); 2484 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0); 2485 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0); 2486 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0); 2487 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0); 2488 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0); 2489 break; 2490 case CHIP_ARCTURUS: 2491 arct_reg_base_init(adev); 2492 adev->sdma.num_instances = 8; 2493 adev->vcn.num_vcn_inst = 2; 2494 adev->gmc.num_umc = 8; 2495 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2496 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2497 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1); 2498 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1); 2499 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2); 2500 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2); 2501 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2); 2502 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2); 2503 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2); 2504 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2); 2505 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2); 2506 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2); 2507 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1); 2508 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1); 2509 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2); 2510 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4); 2511 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2512 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3); 2513 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3); 2514 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1); 2515 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0); 2516 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0); 2517 break; 2518 case CHIP_ALDEBARAN: 2519 aldebaran_reg_base_init(adev); 2520 adev->sdma.num_instances = 5; 2521 adev->vcn.num_vcn_inst = 2; 2522 adev->gmc.num_umc = 4; 2523 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2524 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2525 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0); 2526 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0); 2527 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0); 2528 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0); 2529 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0); 2530 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0); 2531 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0); 2532 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2); 2533 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4); 2534 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0); 2535 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2); 2536 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2); 2537 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2); 2538 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2); 2539 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2); 2540 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0); 2541 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0); 2542 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0); 2543 break; 2544 default: 2545 r = amdgpu_discovery_reg_base_init(adev); 2546 if (r) 2547 return -EINVAL; 2548 2549 amdgpu_discovery_harvest_ip(adev); 2550 amdgpu_discovery_get_gfx_info(adev); 2551 amdgpu_discovery_get_mall_info(adev); 2552 amdgpu_discovery_get_vcn_info(adev); 2553 break; 2554 } 2555 2556 amdgpu_discovery_init_soc_config(adev); 2557 amdgpu_discovery_sysfs_init(adev); 2558 2559 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2560 case IP_VERSION(9, 0, 1): 2561 case IP_VERSION(9, 2, 1): 2562 case IP_VERSION(9, 4, 0): 2563 case IP_VERSION(9, 4, 1): 2564 case IP_VERSION(9, 4, 2): 2565 case IP_VERSION(9, 4, 3): 2566 case IP_VERSION(9, 4, 4): 2567 adev->family = AMDGPU_FAMILY_AI; 2568 break; 2569 case IP_VERSION(9, 1, 0): 2570 case IP_VERSION(9, 2, 2): 2571 case IP_VERSION(9, 3, 0): 2572 adev->family = AMDGPU_FAMILY_RV; 2573 break; 2574 case IP_VERSION(10, 1, 10): 2575 case IP_VERSION(10, 1, 1): 2576 case IP_VERSION(10, 1, 2): 2577 case IP_VERSION(10, 1, 3): 2578 case IP_VERSION(10, 1, 4): 2579 case IP_VERSION(10, 3, 0): 2580 case IP_VERSION(10, 3, 2): 2581 case IP_VERSION(10, 3, 4): 2582 case IP_VERSION(10, 3, 5): 2583 adev->family = AMDGPU_FAMILY_NV; 2584 break; 2585 case IP_VERSION(10, 3, 1): 2586 adev->family = AMDGPU_FAMILY_VGH; 2587 adev->apu_flags |= AMD_APU_IS_VANGOGH; 2588 break; 2589 case IP_VERSION(10, 3, 3): 2590 adev->family = AMDGPU_FAMILY_YC; 2591 break; 2592 case IP_VERSION(10, 3, 6): 2593 adev->family = AMDGPU_FAMILY_GC_10_3_6; 2594 break; 2595 case IP_VERSION(10, 3, 7): 2596 adev->family = AMDGPU_FAMILY_GC_10_3_7; 2597 break; 2598 case IP_VERSION(11, 0, 0): 2599 case IP_VERSION(11, 0, 2): 2600 case IP_VERSION(11, 0, 3): 2601 adev->family = AMDGPU_FAMILY_GC_11_0_0; 2602 break; 2603 case IP_VERSION(11, 0, 1): 2604 case IP_VERSION(11, 0, 4): 2605 adev->family = AMDGPU_FAMILY_GC_11_0_1; 2606 break; 2607 case IP_VERSION(11, 5, 0): 2608 case IP_VERSION(11, 5, 1): 2609 adev->family = AMDGPU_FAMILY_GC_11_5_0; 2610 break; 2611 case IP_VERSION(12, 0, 0): 2612 case IP_VERSION(12, 0, 1): 2613 adev->family = AMDGPU_FAMILY_GC_12_0_0; 2614 break; 2615 default: 2616 return -EINVAL; 2617 } 2618 2619 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2620 case IP_VERSION(9, 1, 0): 2621 case IP_VERSION(9, 2, 2): 2622 case IP_VERSION(9, 3, 0): 2623 case IP_VERSION(10, 1, 3): 2624 case IP_VERSION(10, 1, 4): 2625 case IP_VERSION(10, 3, 1): 2626 case IP_VERSION(10, 3, 3): 2627 case IP_VERSION(10, 3, 6): 2628 case IP_VERSION(10, 3, 7): 2629 case IP_VERSION(11, 0, 1): 2630 case IP_VERSION(11, 0, 4): 2631 case IP_VERSION(11, 5, 0): 2632 case IP_VERSION(11, 5, 1): 2633 adev->flags |= AMD_IS_APU; 2634 break; 2635 default: 2636 break; 2637 } 2638 2639 if (amdgpu_ip_version(adev, XGMI_HWIP, 0) == IP_VERSION(4, 8, 0)) 2640 adev->gmc.xgmi.supported = true; 2641 2642 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 2643 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) 2644 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 4, 0); 2645 2646 /* set NBIO version */ 2647 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { 2648 case IP_VERSION(6, 1, 0): 2649 case IP_VERSION(6, 2, 0): 2650 adev->nbio.funcs = &nbio_v6_1_funcs; 2651 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; 2652 break; 2653 case IP_VERSION(7, 0, 0): 2654 case IP_VERSION(7, 0, 1): 2655 case IP_VERSION(2, 5, 0): 2656 adev->nbio.funcs = &nbio_v7_0_funcs; 2657 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; 2658 break; 2659 case IP_VERSION(7, 4, 0): 2660 case IP_VERSION(7, 4, 1): 2661 case IP_VERSION(7, 4, 4): 2662 adev->nbio.funcs = &nbio_v7_4_funcs; 2663 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; 2664 break; 2665 case IP_VERSION(7, 9, 0): 2666 adev->nbio.funcs = &nbio_v7_9_funcs; 2667 adev->nbio.hdp_flush_reg = &nbio_v7_9_hdp_flush_reg; 2668 break; 2669 case IP_VERSION(7, 11, 0): 2670 case IP_VERSION(7, 11, 1): 2671 adev->nbio.funcs = &nbio_v7_11_funcs; 2672 adev->nbio.hdp_flush_reg = &nbio_v7_11_hdp_flush_reg; 2673 break; 2674 case IP_VERSION(7, 2, 0): 2675 case IP_VERSION(7, 2, 1): 2676 case IP_VERSION(7, 3, 0): 2677 case IP_VERSION(7, 5, 0): 2678 case IP_VERSION(7, 5, 1): 2679 adev->nbio.funcs = &nbio_v7_2_funcs; 2680 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; 2681 break; 2682 case IP_VERSION(2, 1, 1): 2683 case IP_VERSION(2, 3, 0): 2684 case IP_VERSION(2, 3, 1): 2685 case IP_VERSION(2, 3, 2): 2686 case IP_VERSION(3, 3, 0): 2687 case IP_VERSION(3, 3, 1): 2688 case IP_VERSION(3, 3, 2): 2689 case IP_VERSION(3, 3, 3): 2690 adev->nbio.funcs = &nbio_v2_3_funcs; 2691 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 2692 break; 2693 case IP_VERSION(4, 3, 0): 2694 case IP_VERSION(4, 3, 1): 2695 if (amdgpu_sriov_vf(adev)) 2696 adev->nbio.funcs = &nbio_v4_3_sriov_funcs; 2697 else 2698 adev->nbio.funcs = &nbio_v4_3_funcs; 2699 adev->nbio.hdp_flush_reg = &nbio_v4_3_hdp_flush_reg; 2700 break; 2701 case IP_VERSION(7, 7, 0): 2702 case IP_VERSION(7, 7, 1): 2703 adev->nbio.funcs = &nbio_v7_7_funcs; 2704 adev->nbio.hdp_flush_reg = &nbio_v7_7_hdp_flush_reg; 2705 break; 2706 case IP_VERSION(6, 3, 1): 2707 adev->nbio.funcs = &nbif_v6_3_1_funcs; 2708 adev->nbio.hdp_flush_reg = &nbif_v6_3_1_hdp_flush_reg; 2709 break; 2710 default: 2711 break; 2712 } 2713 2714 switch (amdgpu_ip_version(adev, HDP_HWIP, 0)) { 2715 case IP_VERSION(4, 0, 0): 2716 case IP_VERSION(4, 0, 1): 2717 case IP_VERSION(4, 1, 0): 2718 case IP_VERSION(4, 1, 1): 2719 case IP_VERSION(4, 1, 2): 2720 case IP_VERSION(4, 2, 0): 2721 case IP_VERSION(4, 2, 1): 2722 case IP_VERSION(4, 4, 0): 2723 case IP_VERSION(4, 4, 2): 2724 case IP_VERSION(4, 4, 5): 2725 adev->hdp.funcs = &hdp_v4_0_funcs; 2726 break; 2727 case IP_VERSION(5, 0, 0): 2728 case IP_VERSION(5, 0, 1): 2729 case IP_VERSION(5, 0, 2): 2730 case IP_VERSION(5, 0, 3): 2731 case IP_VERSION(5, 0, 4): 2732 case IP_VERSION(5, 2, 0): 2733 adev->hdp.funcs = &hdp_v5_0_funcs; 2734 break; 2735 case IP_VERSION(5, 2, 1): 2736 adev->hdp.funcs = &hdp_v5_2_funcs; 2737 break; 2738 case IP_VERSION(6, 0, 0): 2739 case IP_VERSION(6, 0, 1): 2740 case IP_VERSION(6, 1, 0): 2741 adev->hdp.funcs = &hdp_v6_0_funcs; 2742 break; 2743 case IP_VERSION(7, 0, 0): 2744 adev->hdp.funcs = &hdp_v7_0_funcs; 2745 break; 2746 default: 2747 break; 2748 } 2749 2750 switch (amdgpu_ip_version(adev, DF_HWIP, 0)) { 2751 case IP_VERSION(3, 6, 0): 2752 case IP_VERSION(3, 6, 1): 2753 case IP_VERSION(3, 6, 2): 2754 adev->df.funcs = &df_v3_6_funcs; 2755 break; 2756 case IP_VERSION(2, 1, 0): 2757 case IP_VERSION(2, 1, 1): 2758 case IP_VERSION(2, 5, 0): 2759 case IP_VERSION(3, 5, 1): 2760 case IP_VERSION(3, 5, 2): 2761 adev->df.funcs = &df_v1_7_funcs; 2762 break; 2763 case IP_VERSION(4, 3, 0): 2764 adev->df.funcs = &df_v4_3_funcs; 2765 break; 2766 case IP_VERSION(4, 6, 2): 2767 adev->df.funcs = &df_v4_6_2_funcs; 2768 break; 2769 default: 2770 break; 2771 } 2772 2773 switch (amdgpu_ip_version(adev, SMUIO_HWIP, 0)) { 2774 case IP_VERSION(9, 0, 0): 2775 case IP_VERSION(9, 0, 1): 2776 case IP_VERSION(10, 0, 0): 2777 case IP_VERSION(10, 0, 1): 2778 case IP_VERSION(10, 0, 2): 2779 adev->smuio.funcs = &smuio_v9_0_funcs; 2780 break; 2781 case IP_VERSION(11, 0, 0): 2782 case IP_VERSION(11, 0, 2): 2783 case IP_VERSION(11, 0, 3): 2784 case IP_VERSION(11, 0, 4): 2785 case IP_VERSION(11, 0, 7): 2786 case IP_VERSION(11, 0, 8): 2787 adev->smuio.funcs = &smuio_v11_0_funcs; 2788 break; 2789 case IP_VERSION(11, 0, 6): 2790 case IP_VERSION(11, 0, 10): 2791 case IP_VERSION(11, 0, 11): 2792 case IP_VERSION(11, 5, 0): 2793 case IP_VERSION(13, 0, 1): 2794 case IP_VERSION(13, 0, 9): 2795 case IP_VERSION(13, 0, 10): 2796 adev->smuio.funcs = &smuio_v11_0_6_funcs; 2797 break; 2798 case IP_VERSION(13, 0, 2): 2799 adev->smuio.funcs = &smuio_v13_0_funcs; 2800 break; 2801 case IP_VERSION(13, 0, 3): 2802 adev->smuio.funcs = &smuio_v13_0_3_funcs; 2803 if (adev->smuio.funcs->get_pkg_type(adev) == AMDGPU_PKG_TYPE_APU) { 2804 adev->flags |= AMD_IS_APU; 2805 } 2806 break; 2807 case IP_VERSION(13, 0, 6): 2808 case IP_VERSION(13, 0, 8): 2809 case IP_VERSION(14, 0, 0): 2810 case IP_VERSION(14, 0, 1): 2811 adev->smuio.funcs = &smuio_v13_0_6_funcs; 2812 break; 2813 case IP_VERSION(14, 0, 2): 2814 adev->smuio.funcs = &smuio_v14_0_2_funcs; 2815 break; 2816 default: 2817 break; 2818 } 2819 2820 switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) { 2821 case IP_VERSION(6, 0, 0): 2822 case IP_VERSION(6, 0, 1): 2823 case IP_VERSION(6, 0, 2): 2824 case IP_VERSION(6, 0, 3): 2825 adev->lsdma.funcs = &lsdma_v6_0_funcs; 2826 break; 2827 case IP_VERSION(7, 0, 0): 2828 case IP_VERSION(7, 0, 1): 2829 adev->lsdma.funcs = &lsdma_v7_0_funcs; 2830 break; 2831 default: 2832 break; 2833 } 2834 2835 r = amdgpu_discovery_set_common_ip_blocks(adev); 2836 if (r) 2837 return r; 2838 2839 r = amdgpu_discovery_set_gmc_ip_blocks(adev); 2840 if (r) 2841 return r; 2842 2843 /* For SR-IOV, PSP needs to be initialized before IH */ 2844 if (amdgpu_sriov_vf(adev)) { 2845 r = amdgpu_discovery_set_psp_ip_blocks(adev); 2846 if (r) 2847 return r; 2848 r = amdgpu_discovery_set_ih_ip_blocks(adev); 2849 if (r) 2850 return r; 2851 } else { 2852 r = amdgpu_discovery_set_ih_ip_blocks(adev); 2853 if (r) 2854 return r; 2855 2856 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 2857 r = amdgpu_discovery_set_psp_ip_blocks(adev); 2858 if (r) 2859 return r; 2860 } 2861 } 2862 2863 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 2864 r = amdgpu_discovery_set_smu_ip_blocks(adev); 2865 if (r) 2866 return r; 2867 } 2868 2869 r = amdgpu_discovery_set_display_ip_blocks(adev); 2870 if (r) 2871 return r; 2872 2873 r = amdgpu_discovery_set_gc_ip_blocks(adev); 2874 if (r) 2875 return r; 2876 2877 r = amdgpu_discovery_set_sdma_ip_blocks(adev); 2878 if (r) 2879 return r; 2880 2881 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 2882 !amdgpu_sriov_vf(adev)) || 2883 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) { 2884 r = amdgpu_discovery_set_smu_ip_blocks(adev); 2885 if (r) 2886 return r; 2887 } 2888 2889 r = amdgpu_discovery_set_mm_ip_blocks(adev); 2890 if (r) 2891 return r; 2892 2893 r = amdgpu_discovery_set_mes_ip_blocks(adev); 2894 if (r) 2895 return r; 2896 2897 r = amdgpu_discovery_set_vpe_ip_blocks(adev); 2898 if (r) 2899 return r; 2900 2901 r = amdgpu_discovery_set_umsch_mm_ip_blocks(adev); 2902 if (r) 2903 return r; 2904 2905 return 0; 2906 } 2907 2908