1 /* 2 * Copyright 2018-2024 Advanced Micro Devices, Inc. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/kernfs.h> 26 27 #include "amdgpu.h" 28 #include "amdgpu_discovery.h" 29 #include "soc15_hw_ip.h" 30 #include "discovery.h" 31 #include "amdgpu_ras.h" 32 33 #include "soc15.h" 34 #include "gfx_v9_0.h" 35 #include "gfx_v9_4_3.h" 36 #include "gmc_v9_0.h" 37 #include "df_v1_7.h" 38 #include "df_v3_6.h" 39 #include "df_v4_3.h" 40 #include "df_v4_6_2.h" 41 #include "df_v4_15.h" 42 #include "nbio_v6_1.h" 43 #include "nbio_v7_0.h" 44 #include "nbio_v7_4.h" 45 #include "nbio_v7_9.h" 46 #include "nbio_v7_11.h" 47 #include "hdp_v4_0.h" 48 #include "vega10_ih.h" 49 #include "vega20_ih.h" 50 #include "sdma_v4_0.h" 51 #include "sdma_v4_4_2.h" 52 #include "uvd_v7_0.h" 53 #include "vce_v4_0.h" 54 #include "vcn_v1_0.h" 55 #include "vcn_v2_5.h" 56 #include "jpeg_v2_5.h" 57 #include "smuio_v9_0.h" 58 #include "gmc_v10_0.h" 59 #include "gmc_v11_0.h" 60 #include "gmc_v12_0.h" 61 #include "gfxhub_v2_0.h" 62 #include "mmhub_v2_0.h" 63 #include "nbio_v2_3.h" 64 #include "nbio_v4_3.h" 65 #include "nbio_v7_2.h" 66 #include "nbio_v7_7.h" 67 #include "nbif_v6_3_1.h" 68 #include "nbio_v6_3_2.h" 69 #include "hdp_v5_0.h" 70 #include "hdp_v5_2.h" 71 #include "hdp_v6_0.h" 72 #include "hdp_v7_0.h" 73 #include "nv.h" 74 #include "soc21.h" 75 #include "soc24.h" 76 #include "soc_v1_0.h" 77 #include "navi10_ih.h" 78 #include "ih_v6_0.h" 79 #include "ih_v6_1.h" 80 #include "ih_v7_0.h" 81 #include "gfx_v10_0.h" 82 #include "gfx_v11_0.h" 83 #include "gfx_v12_0.h" 84 #include "gfx_v12_1.h" 85 #include "sdma_v5_0.h" 86 #include "sdma_v5_2.h" 87 #include "sdma_v6_0.h" 88 #include "sdma_v7_0.h" 89 #include "sdma_v7_1.h" 90 #include "lsdma_v6_0.h" 91 #include "lsdma_v7_0.h" 92 #include "lsdma_v7_1.h" 93 #include "vcn_v2_0.h" 94 #include "jpeg_v2_0.h" 95 #include "vcn_v3_0.h" 96 #include "jpeg_v3_0.h" 97 #include "vcn_v4_0.h" 98 #include "jpeg_v4_0.h" 99 #include "vcn_v4_0_3.h" 100 #include "jpeg_v4_0_3.h" 101 #include "vcn_v4_0_5.h" 102 #include "jpeg_v4_0_5.h" 103 #include "amdgpu_vkms.h" 104 #include "mes_v11_0.h" 105 #include "mes_v12_0.h" 106 #include "mes_v12_1.h" 107 #include "smuio_v11_0.h" 108 #include "smuio_v11_0_6.h" 109 #include "smuio_v13_0.h" 110 #include "smuio_v13_0_3.h" 111 #include "smuio_v13_0_6.h" 112 #include "smuio_v14_0_2.h" 113 #include "smuio_v15_0_0.h" 114 #include "smuio_v15_0_8.h" 115 #include "vcn_v5_0_0.h" 116 #include "vcn_v5_0_1.h" 117 #include "vcn_v5_0_2.h" 118 #include "jpeg_v5_0_0.h" 119 #include "jpeg_v5_0_1.h" 120 #include "jpeg_v5_0_2.h" 121 #include "jpeg_v5_3_0.h" 122 123 #include "amdgpu_ras_mgr.h" 124 125 #include "amdgpu_vpe.h" 126 #if defined(CONFIG_DRM_AMD_ISP) 127 #include "amdgpu_isp.h" 128 #endif 129 130 MODULE_FIRMWARE("amdgpu/ip_discovery.bin"); 131 MODULE_FIRMWARE("amdgpu/vega10_ip_discovery.bin"); 132 MODULE_FIRMWARE("amdgpu/vega12_ip_discovery.bin"); 133 MODULE_FIRMWARE("amdgpu/vega20_ip_discovery.bin"); 134 MODULE_FIRMWARE("amdgpu/raven_ip_discovery.bin"); 135 MODULE_FIRMWARE("amdgpu/raven2_ip_discovery.bin"); 136 MODULE_FIRMWARE("amdgpu/picasso_ip_discovery.bin"); 137 MODULE_FIRMWARE("amdgpu/arcturus_ip_discovery.bin"); 138 MODULE_FIRMWARE("amdgpu/aldebaran_ip_discovery.bin"); 139 140 /* Note: These registers are consistent across all the SOCs */ 141 #define mmIP_DISCOVERY_VERSION 0x16A00 142 #define mmRCC_CONFIG_MEMSIZE 0xde3 143 #define mmMP0_SMN_C2PMSG_33 0x16061 144 #define mmMM_INDEX 0x0 145 #define mmMM_INDEX_HI 0x6 146 #define mmMM_DATA 0x1 147 148 #define mmDRIVER_SCRATCH_0 0x94 149 #define mmDRIVER_SCRATCH_1 0x95 150 #define mmDRIVER_SCRATCH_2 0x96 151 152 struct ip_discovery_top { 153 struct kobject kobj; 154 struct kset die_kset; 155 struct pci_dev *pdev; 156 struct amdgpu_device *adev; 157 uint8_t *discovery_bin; 158 uint32_t bin_size; 159 bool standalone_mode; 160 }; 161 162 /* List to track early-initialized ip_discovery_top entries */ 163 struct early_ip_discovery { 164 struct list_head list; 165 struct pci_dev *pdev; 166 struct ip_discovery_top *ip_top; 167 }; 168 169 static LIST_HEAD(early_ip_discovery_list); 170 static DEFINE_MUTEX(early_ip_discovery_mutex); 171 172 static const char *hw_id_names[HW_ID_MAX] = { 173 [MP1_HWID] = "MP1", 174 [MP2_HWID] = "MP2", 175 [THM_HWID] = "THM", 176 [SMUIO_HWID] = "SMUIO", 177 [FUSE_HWID] = "FUSE", 178 [CLKA_HWID] = "CLKA", 179 [PWR_HWID] = "PWR", 180 [GC_HWID] = "GC", 181 [UVD_HWID] = "UVD", 182 [AUDIO_AZ_HWID] = "AUDIO_AZ", 183 [ACP_HWID] = "ACP", 184 [DCI_HWID] = "DCI", 185 [DMU_HWID] = "DMU", 186 [DCO_HWID] = "DCO", 187 [DIO_HWID] = "DIO", 188 [XDMA_HWID] = "XDMA", 189 [DCEAZ_HWID] = "DCEAZ", 190 [DAZ_HWID] = "DAZ", 191 [SDPMUX_HWID] = "SDPMUX", 192 [NTB_HWID] = "NTB", 193 [IOHC_HWID] = "IOHC", 194 [L2IMU_HWID] = "L2IMU", 195 [VCE_HWID] = "VCE", 196 [MMHUB_HWID] = "MMHUB", 197 [ATHUB_HWID] = "ATHUB", 198 [DBGU_NBIO_HWID] = "DBGU_NBIO", 199 [DFX_HWID] = "DFX", 200 [DBGU0_HWID] = "DBGU0", 201 [DBGU1_HWID] = "DBGU1", 202 [OSSSYS_HWID] = "OSSSYS", 203 [HDP_HWID] = "HDP", 204 [SDMA0_HWID] = "SDMA0", 205 [SDMA1_HWID] = "SDMA1", 206 [SDMA2_HWID] = "SDMA2", 207 [SDMA3_HWID] = "SDMA3", 208 [LSDMA_HWID] = "LSDMA", 209 [ISP_HWID] = "ISP", 210 [DBGU_IO_HWID] = "DBGU_IO", 211 [DF_HWID] = "DF", 212 [CLKB_HWID] = "CLKB", 213 [FCH_HWID] = "FCH", 214 [DFX_DAP_HWID] = "DFX_DAP", 215 [L1IMU_PCIE_HWID] = "L1IMU_PCIE", 216 [L1IMU_NBIF_HWID] = "L1IMU_NBIF", 217 [L1IMU_IOAGR_HWID] = "L1IMU_IOAGR", 218 [L1IMU3_HWID] = "L1IMU3", 219 [L1IMU4_HWID] = "L1IMU4", 220 [L1IMU5_HWID] = "L1IMU5", 221 [L1IMU6_HWID] = "L1IMU6", 222 [L1IMU7_HWID] = "L1IMU7", 223 [L1IMU8_HWID] = "L1IMU8", 224 [L1IMU9_HWID] = "L1IMU9", 225 [L1IMU10_HWID] = "L1IMU10", 226 [L1IMU11_HWID] = "L1IMU11", 227 [L1IMU12_HWID] = "L1IMU12", 228 [L1IMU13_HWID] = "L1IMU13", 229 [L1IMU14_HWID] = "L1IMU14", 230 [L1IMU15_HWID] = "L1IMU15", 231 [WAFLC_HWID] = "WAFLC", 232 [FCH_USB_PD_HWID] = "FCH_USB_PD", 233 [PCIE_HWID] = "PCIE", 234 [PCS_HWID] = "PCS", 235 [DDCL_HWID] = "DDCL", 236 [SST_HWID] = "SST", 237 [IOAGR_HWID] = "IOAGR", 238 [NBIF_HWID] = "NBIF", 239 [IOAPIC_HWID] = "IOAPIC", 240 [SYSTEMHUB_HWID] = "SYSTEMHUB", 241 [NTBCCP_HWID] = "NTBCCP", 242 [UMC_HWID] = "UMC", 243 [SATA_HWID] = "SATA", 244 [USB_HWID] = "USB", 245 [CCXSEC_HWID] = "CCXSEC", 246 [XGMI_HWID] = "XGMI", 247 [XGBE_HWID] = "XGBE", 248 [MP0_HWID] = "MP0", 249 [VPE_HWID] = "VPE", 250 [UMSCH_HWID] = "UMSCH", 251 [ATU_HWID] = "ATU", 252 [AIGC_HWID] = "AIGC", 253 }; 254 255 static int hw_id_map[MAX_HWIP] = { 256 [GC_HWIP] = GC_HWID, 257 [HDP_HWIP] = HDP_HWID, 258 [SDMA0_HWIP] = SDMA0_HWID, 259 [SDMA1_HWIP] = SDMA1_HWID, 260 [SDMA2_HWIP] = SDMA2_HWID, 261 [SDMA3_HWIP] = SDMA3_HWID, 262 [LSDMA_HWIP] = LSDMA_HWID, 263 [MMHUB_HWIP] = MMHUB_HWID, 264 [ATHUB_HWIP] = ATHUB_HWID, 265 [NBIO_HWIP] = NBIF_HWID, 266 [MP0_HWIP] = MP0_HWID, 267 [MP1_HWIP] = MP1_HWID, 268 [UVD_HWIP] = UVD_HWID, 269 [VCE_HWIP] = VCE_HWID, 270 [DF_HWIP] = DF_HWID, 271 [DCE_HWIP] = DMU_HWID, 272 [OSSSYS_HWIP] = OSSSYS_HWID, 273 [SMUIO_HWIP] = SMUIO_HWID, 274 [PWR_HWIP] = PWR_HWID, 275 [NBIF_HWIP] = NBIF_HWID, 276 [THM_HWIP] = THM_HWID, 277 [CLK_HWIP] = CLKA_HWID, 278 [UMC_HWIP] = UMC_HWID, 279 [XGMI_HWIP] = XGMI_HWID, 280 [DCI_HWIP] = DCI_HWID, 281 [PCIE_HWIP] = PCIE_HWID, 282 [VPE_HWIP] = VPE_HWID, 283 [UMSCH_HWIP] = UMSCH_HWID, 284 [ISP_HWIP] = ISP_HWID, 285 [ATU_HWIP] = ATU_HWID, 286 }; 287 288 static int amdgpu_discovery_get_tmr_info(struct amdgpu_device *adev, 289 bool *is_tmr_in_sysmem) 290 { 291 u64 vram_size, tmr_offset, tmr_size; 292 u32 msg, tmr_offset_lo, tmr_offset_hi; 293 int i, ret; 294 295 if (!amdgpu_sriov_vf(adev)) { 296 /* It can take up to two second for IFWI init to complete on some dGPUs, 297 * but generally it should be in the 60-100ms range. Normally this starts 298 * as soon as the device gets power so by the time the OS loads this has long 299 * completed. However, when a card is hotplugged via e.g., USB4, we need to 300 * wait for this to complete. Once the C2PMSG is updated, we can 301 * continue. 302 */ 303 304 for (i = 0; i < 2000; i++) { 305 msg = RREG32(mmMP0_SMN_C2PMSG_33); 306 if (msg & 0x80000000) 307 break; 308 msleep(1); 309 } 310 } 311 312 vram_size = RREG32(mmRCC_CONFIG_MEMSIZE); 313 if (vram_size == U32_MAX) 314 return -ENXIO; 315 else if (!vram_size) 316 *is_tmr_in_sysmem = true; 317 else 318 *is_tmr_in_sysmem = false; 319 320 /* init the default tmr size and offset */ 321 adev->discovery.size = DISCOVERY_TMR_SIZE; 322 if (vram_size) 323 adev->discovery.offset = (vram_size << 20) - DISCOVERY_TMR_OFFSET; 324 325 if (amdgpu_sriov_vf(adev)) { 326 if (adev->virt.is_dynamic_crit_regn_enabled) { 327 adev->discovery.offset = 328 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].offset; 329 adev->discovery.size = 330 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].size_kb << 10; 331 if (!adev->discovery.size) 332 return -EINVAL; 333 } else { 334 goto out; 335 } 336 } else { 337 tmr_size = RREG32(mmDRIVER_SCRATCH_2); 338 if (tmr_size) { 339 /* It's preferred to transition to PSP mailbox reg interface 340 * for both bare-metal and passthrough if available */ 341 adev->discovery.size = (u32)tmr_size; 342 tmr_offset_lo = RREG32(mmDRIVER_SCRATCH_0); 343 tmr_offset_hi = RREG32(mmDRIVER_SCRATCH_1); 344 adev->discovery.offset = ((u64)le32_to_cpu(tmr_offset_hi) << 32 | 345 le32_to_cpu(tmr_offset_lo)); 346 } else if (!vram_size) { 347 /* fall back to apci approach to query tmr offset if vram_size is 0 */ 348 ret = amdgpu_acpi_get_tmr_info(adev, &tmr_offset, &tmr_size); 349 if (ret) 350 return ret; 351 adev->discovery.size = DISCOVERY_TMR_SIZE; 352 adev->discovery.offset = tmr_offset + tmr_size - DISCOVERY_TMR_OFFSET; 353 } 354 } 355 out: 356 adev->discovery.bin = kzalloc(adev->discovery.size, GFP_KERNEL); 357 if (!adev->discovery.bin) 358 return -ENOMEM; 359 adev->discovery.debugfs_blob.data = adev->discovery.bin; 360 adev->discovery.debugfs_blob.size = adev->discovery.size; 361 362 return 0; 363 } 364 365 static int amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device *adev, uint8_t *binary) 366 { 367 void *discv_regn; 368 369 /* This region is read-only and reserved from system use */ 370 discv_regn = memremap(adev->discovery.offset, adev->discovery.size, MEMREMAP_WC); 371 if (discv_regn) { 372 memcpy(binary, discv_regn, adev->discovery.size); 373 memunmap(discv_regn); 374 return 0; 375 } 376 377 return -ENOENT; 378 } 379 380 #define IP_DISCOVERY_V2 2 381 #define IP_DISCOVERY_V4 4 382 383 static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev, 384 uint8_t *binary, 385 bool is_tmr_in_sysmem) 386 { 387 int ret = 0; 388 389 if (!is_tmr_in_sysmem) { 390 if (amdgpu_sriov_vf(adev) && 391 amdgpu_sriov_xgmi_connected_to_cpu(adev)) { 392 ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary); 393 } else { 394 amdgpu_device_vram_access(adev, adev->discovery.offset, 395 (uint32_t *)binary, 396 adev->discovery.size, false); 397 adev->discovery.reserve_tmr = true; 398 } 399 } else { 400 ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary); 401 } 402 403 return ret; 404 } 405 406 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, 407 uint8_t *binary, 408 const char *fw_name) 409 { 410 const struct firmware *fw; 411 int r; 412 413 r = firmware_request_nowarn(&fw, fw_name, adev->dev); 414 if (r) { 415 if (amdgpu_discovery == 2) 416 dev_err(adev->dev, "can't load firmware \"%s\"\n", fw_name); 417 else 418 drm_info(&adev->ddev, "Optional firmware \"%s\" was not found\n", fw_name); 419 return r; 420 } 421 422 if (fw->size > adev->discovery.size) { 423 dev_err(adev->dev, 424 "ip discovery firmware \"%s\" too large (%zu > %u)\n", 425 fw_name, fw->size, adev->discovery.size); 426 release_firmware(fw); 427 return -EINVAL; 428 } 429 430 /* Ensure the firmware is at least large enough to contain the 431 * binary header fields. 432 */ 433 if (fw->size < offsetof(struct binary_header, binary_size) + 434 sizeof(((struct binary_header *)0)->binary_size)) { 435 dev_err(adev->dev, 436 "ip discovery firmware \"%s\" too small (%zu)\n", 437 fw_name, fw->size); 438 release_firmware(fw); 439 return -EINVAL; 440 } 441 442 memcpy((u8 *)binary, (u8 *)fw->data, fw->size); 443 release_firmware(fw); 444 445 return 0; 446 } 447 448 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size) 449 { 450 uint16_t checksum = 0; 451 int i; 452 453 for (i = 0; i < size; i++) 454 checksum += data[i]; 455 456 return checksum; 457 } 458 459 static inline bool amdgpu_discovery_verify_checksum(struct amdgpu_device *adev, 460 uint8_t *data, uint32_t size, 461 uint16_t expected) 462 { 463 uint16_t calculated; 464 465 calculated = amdgpu_discovery_calculate_checksum(data, size); 466 467 if (calculated != expected) { 468 dev_err(adev->dev, "Discovery checksum failed: calc 0x%04x != exp 0x%04x, size %u.\n", 469 calculated, expected, size); 470 return false; 471 } 472 473 return true; 474 } 475 476 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary) 477 { 478 struct binary_header *bhdr; 479 bhdr = (struct binary_header *)binary; 480 481 return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE); 482 } 483 484 static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev) 485 { 486 /* 487 * So far, apply this quirk only on those Navy Flounder boards which 488 * have a bad harvest table of VCN config. 489 */ 490 if ((amdgpu_ip_version(adev, UVD_HWIP, 1) == IP_VERSION(3, 0, 1)) && 491 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 2))) { 492 switch (adev->pdev->revision) { 493 case 0xC1: 494 case 0xC2: 495 case 0xC3: 496 case 0xC5: 497 case 0xC7: 498 case 0xCF: 499 case 0xDF: 500 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 501 adev->vcn.inst_mask &= ~AMDGPU_VCN_HARVEST_VCN1; 502 break; 503 default: 504 break; 505 } 506 } 507 } 508 509 static int amdgpu_discovery_verify_npsinfo(struct amdgpu_device *adev, 510 struct table_info *info) 511 { 512 uint8_t *discovery_bin = adev->discovery.bin; 513 uint16_t checksum; 514 uint16_t offset; 515 516 offset = le16_to_cpu(info->offset); 517 checksum = le16_to_cpu(info->checksum); 518 519 struct nps_info_header *nhdr = 520 (struct nps_info_header *)(discovery_bin + offset); 521 522 if (le32_to_cpu(nhdr->table_id) != NPS_INFO_TABLE_ID) { 523 dev_dbg(adev->dev, "invalid ip discovery nps info table id\n"); 524 return -EINVAL; 525 } 526 527 if (!amdgpu_discovery_verify_checksum(adev, discovery_bin + offset, 528 le32_to_cpu(nhdr->size_bytes), 529 checksum)) { 530 dev_dbg(adev->dev, "invalid nps info data table checksum\n"); 531 return -EINVAL; 532 } 533 534 return 0; 535 } 536 537 static const char *amdgpu_discovery_get_fw_name(struct amdgpu_device *adev) 538 { 539 if (amdgpu_discovery == 2) { 540 /* Assume there is valid discovery TMR in VRAM even if binary is sideloaded */ 541 adev->discovery.reserve_tmr = true; 542 return "amdgpu/ip_discovery.bin"; 543 } 544 545 switch (adev->asic_type) { 546 case CHIP_VEGA10: 547 return "amdgpu/vega10_ip_discovery.bin"; 548 case CHIP_VEGA12: 549 return "amdgpu/vega12_ip_discovery.bin"; 550 case CHIP_RAVEN: 551 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 552 return "amdgpu/raven2_ip_discovery.bin"; 553 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 554 return "amdgpu/picasso_ip_discovery.bin"; 555 else 556 return "amdgpu/raven_ip_discovery.bin"; 557 case CHIP_VEGA20: 558 return "amdgpu/vega20_ip_discovery.bin"; 559 case CHIP_ARCTURUS: 560 return "amdgpu/arcturus_ip_discovery.bin"; 561 case CHIP_ALDEBARAN: 562 return "amdgpu/aldebaran_ip_discovery.bin"; 563 default: 564 return NULL; 565 } 566 } 567 568 static struct table_info * 569 amdgpu_discovery_get_table_info_from_bin(uint8_t *discovery_bin, 570 uint16_t table_id) 571 { 572 struct binary_header *bhdr = (struct binary_header *)discovery_bin; 573 struct binary_header_v2 *bhdrv2; 574 575 switch (bhdr->version_major) { 576 case 2: 577 bhdrv2 = (struct binary_header_v2 *)discovery_bin; 578 return &bhdrv2->table_list[table_id]; 579 case 1: 580 case 0: 581 return &bhdr->table_list[table_id]; 582 default: 583 return NULL; 584 } 585 } 586 587 static int amdgpu_discovery_get_table_info(struct amdgpu_device *adev, 588 struct table_info **info, 589 uint16_t table_id) 590 { 591 struct binary_header *bhdr = 592 (struct binary_header *)adev->discovery.bin; 593 594 *info = amdgpu_discovery_get_table_info_from_bin(adev->discovery.bin, 595 table_id); 596 if (!*info) { 597 dev_err(adev->dev, "Invalid ip discovery table version %d\n", 598 bhdr->version_major); 599 return -EINVAL; 600 } 601 602 return 0; 603 } 604 605 static int amdgpu_discovery_table_check(struct amdgpu_device *adev, 606 uint8_t *discovery_bin, 607 uint16_t table_id) 608 { 609 int r, act_val, exp_val, table_size; 610 uint16_t offset, checksum; 611 struct table_info *info; 612 bool check_table = true; 613 char *table_name; 614 615 r = amdgpu_discovery_get_table_info(adev, &info, table_id); 616 if (r) 617 return r; 618 offset = le16_to_cpu(info->offset); 619 checksum = le16_to_cpu(info->checksum); 620 621 switch (table_id) { 622 case IP_DISCOVERY: { 623 struct ip_discovery_header *ihdr = 624 (struct ip_discovery_header *)(discovery_bin + offset); 625 act_val = le32_to_cpu(ihdr->signature); 626 exp_val = DISCOVERY_TABLE_SIGNATURE; 627 table_size = le16_to_cpu(ihdr->size); 628 table_name = "data table"; 629 break; 630 } 631 case GC: { 632 struct gpu_info_header *ghdr = 633 (struct gpu_info_header *)(discovery_bin + offset); 634 act_val = le32_to_cpu(ghdr->table_id); 635 exp_val = GC_TABLE_ID; 636 table_size = le16_to_cpu(ghdr->size); 637 table_name = "gc table"; 638 break; 639 } 640 case HARVEST_INFO: { 641 struct harvest_info_header *hhdr = 642 (struct harvest_info_header *)(discovery_bin + offset); 643 act_val = le32_to_cpu(hhdr->signature); 644 exp_val = HARVEST_TABLE_SIGNATURE; 645 table_size = sizeof(struct harvest_table); 646 table_name = "harvest table"; 647 break; 648 } 649 case VCN_INFO: { 650 struct vcn_info_header *vhdr = 651 (struct vcn_info_header *)(discovery_bin + offset); 652 act_val = le32_to_cpu(vhdr->table_id); 653 exp_val = VCN_INFO_TABLE_ID; 654 table_size = le32_to_cpu(vhdr->size_bytes); 655 table_name = "vcn table"; 656 break; 657 } 658 case MALL_INFO: { 659 struct mall_info_header *mhdr = 660 (struct mall_info_header *)(discovery_bin + offset); 661 act_val = le32_to_cpu(mhdr->table_id); 662 exp_val = MALL_INFO_TABLE_ID; 663 table_size = le32_to_cpu(mhdr->size_bytes); 664 table_name = "mall table"; 665 check_table = false; 666 break; 667 } 668 default: 669 dev_err(adev->dev, "invalid ip discovery table id %d specified\n", table_id); 670 check_table = false; 671 break; 672 } 673 674 if (check_table && offset) { 675 if (act_val != exp_val) { 676 dev_err(adev->dev, "invalid ip discovery %s signature\n", table_name); 677 return -EINVAL; 678 } 679 680 if (!amdgpu_discovery_verify_checksum(adev, discovery_bin + offset, 681 table_size, checksum)) { 682 dev_err(adev->dev, "invalid ip discovery %s checksum\n", table_name); 683 return -EINVAL; 684 } 685 } 686 687 return 0; 688 } 689 690 static int amdgpu_discovery_init(struct amdgpu_device *adev) 691 { 692 struct binary_header *bhdr; 693 uint8_t *discovery_bin; 694 const char *fw_name; 695 uint16_t offset; 696 uint16_t size; 697 uint16_t checksum; 698 uint16_t table_id; 699 bool is_tmr_in_sysmem; 700 int r; 701 702 r = amdgpu_discovery_get_tmr_info(adev, &is_tmr_in_sysmem); 703 if (r) 704 return r; 705 706 discovery_bin = adev->discovery.bin; 707 /* Read from file if it is the preferred option */ 708 fw_name = amdgpu_discovery_get_fw_name(adev); 709 if (fw_name != NULL) { 710 drm_dbg(&adev->ddev, "use ip discovery information from file"); 711 r = amdgpu_discovery_read_binary_from_file(adev, discovery_bin, 712 fw_name); 713 if (r) 714 goto out; 715 } else { 716 drm_dbg(&adev->ddev, "use ip discovery information from memory"); 717 r = amdgpu_discovery_read_binary_from_mem(adev, discovery_bin, 718 is_tmr_in_sysmem); 719 if (r) 720 goto out; 721 } 722 723 /* check the ip discovery binary signature */ 724 if (!amdgpu_discovery_verify_binary_signature(discovery_bin)) { 725 dev_err(adev->dev, 726 "get invalid ip discovery binary signature\n"); 727 r = -EINVAL; 728 goto out; 729 } 730 731 bhdr = (struct binary_header *)discovery_bin; 732 733 offset = offsetof(struct binary_header, binary_checksum) + 734 sizeof(bhdr->binary_checksum); 735 size = le16_to_cpu(bhdr->binary_size) - offset; 736 checksum = le16_to_cpu(bhdr->binary_checksum); 737 738 if (!amdgpu_discovery_verify_checksum(adev, discovery_bin + offset, size, 739 checksum)) { 740 dev_err(adev->dev, "invalid ip discovery binary checksum\n"); 741 r = -EINVAL; 742 goto out; 743 } 744 745 for (table_id = 0; table_id <= MALL_INFO; table_id++) { 746 r = amdgpu_discovery_table_check(adev, discovery_bin, table_id); 747 if (r) 748 goto out; 749 } 750 751 return 0; 752 753 out: 754 kfree(adev->discovery.bin); 755 adev->discovery.bin = NULL; 756 if ((amdgpu_discovery != 2) && 757 (RREG32(mmIP_DISCOVERY_VERSION) == 4)) 758 amdgpu_ras_query_boot_status(adev, 4); 759 return r; 760 } 761 762 void amdgpu_discovery_fini(struct amdgpu_device *adev) 763 { 764 if (adev->discovery.ip_top && !adev->discovery.ip_top->standalone_mode) 765 amdgpu_discovery_sysfs_fini(adev); 766 767 kfree(adev->discovery.bin); 768 adev->discovery.bin = NULL; 769 } 770 771 static int amdgpu_discovery_validate_ip(struct amdgpu_device *adev, 772 uint8_t instance, uint16_t hw_id) 773 { 774 if (instance >= HWIP_MAX_INSTANCE) { 775 if (adev) 776 dev_err(adev->dev, 777 "Unexpected instance_number (%d) from ip discovery blob\n", 778 instance); 779 return -EINVAL; 780 } 781 if (hw_id >= HW_ID_MAX) { 782 if (adev) 783 dev_err(adev->dev, 784 "Unexpected hw_id (%d) from ip discovery blob\n", 785 hw_id); 786 return -EINVAL; 787 } 788 789 return 0; 790 } 791 792 static void amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device *adev, 793 uint32_t *vcn_harvest_count) 794 { 795 uint8_t *discovery_bin = adev->discovery.bin; 796 struct binary_header *bhdr; 797 struct ip_discovery_header *ihdr; 798 struct die_header *dhdr; 799 struct ip *ip; 800 uint16_t die_offset, ip_offset, num_dies, num_ips; 801 uint16_t hw_id; 802 uint8_t inst; 803 int i, j; 804 805 bhdr = (struct binary_header *)discovery_bin; 806 ihdr = (struct ip_discovery_header 807 *)(discovery_bin + 808 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 809 num_dies = le16_to_cpu(ihdr->num_dies); 810 811 /* scan harvest bit of all IP data structures */ 812 for (i = 0; i < num_dies; i++) { 813 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 814 dhdr = (struct die_header *)(discovery_bin + die_offset); 815 num_ips = le16_to_cpu(dhdr->num_ips); 816 ip_offset = die_offset + sizeof(*dhdr); 817 818 for (j = 0; j < num_ips; j++) { 819 ip = (struct ip *)(discovery_bin + ip_offset); 820 inst = ip->number_instance; 821 hw_id = le16_to_cpu(ip->hw_id); 822 if (amdgpu_discovery_validate_ip(adev, inst, hw_id)) 823 goto next_ip; 824 825 if (ip->harvest == 1) { 826 switch (hw_id) { 827 case VCN_HWID: 828 (*vcn_harvest_count)++; 829 if (inst == 0) { 830 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0; 831 adev->vcn.inst_mask &= 832 ~AMDGPU_VCN_HARVEST_VCN0; 833 adev->jpeg.inst_mask &= 834 ~AMDGPU_VCN_HARVEST_VCN0; 835 } else { 836 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 837 adev->vcn.inst_mask &= 838 ~AMDGPU_VCN_HARVEST_VCN1; 839 adev->jpeg.inst_mask &= 840 ~AMDGPU_VCN_HARVEST_VCN1; 841 } 842 break; 843 case DMU_HWID: 844 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 845 break; 846 default: 847 break; 848 } 849 } 850 next_ip: 851 ip_offset += struct_size(ip, base_address, 852 ip->num_base_address); 853 } 854 } 855 } 856 857 static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev, 858 uint32_t *vcn_harvest_count, 859 uint32_t *umc_harvest_count) 860 { 861 uint8_t *discovery_bin = adev->discovery.bin; 862 struct table_info *info; 863 struct harvest_table *harvest_info; 864 u16 offset; 865 int i; 866 u64 umc_harvest_config = 0; 867 868 if (amdgpu_discovery_get_table_info(adev, &info, HARVEST_INFO)) 869 return; 870 offset = le16_to_cpu(info->offset); 871 872 if (!offset) { 873 dev_err(adev->dev, "invalid harvest table offset\n"); 874 return; 875 } 876 877 harvest_info = (struct harvest_table *)(discovery_bin + offset); 878 879 for (i = 0; i < 32; i++) { 880 u16 hw_id = le16_to_cpu(harvest_info->list[i].hw_id); 881 u8 inst = harvest_info->list[i].number_instance; 882 883 if (hw_id == 0) 884 break; 885 886 if (inst >= 32) { 887 dev_warn(adev->dev, 888 "bogus harvest instance %u for hw_id %u\n", 889 inst, hw_id); 890 continue; 891 } 892 893 switch (hw_id) { 894 case VCN_HWID: 895 (*vcn_harvest_count)++; 896 adev->vcn.harvest_config |= BIT(inst); 897 adev->jpeg.harvest_config |= BIT(inst); 898 899 adev->vcn.inst_mask &= ~BIT(inst); 900 adev->jpeg.inst_mask &= ~BIT(inst); 901 break; 902 case DMU_HWID: 903 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 904 break; 905 case UMC_HWID: 906 umc_harvest_config |= BIT_ULL(inst); 907 (*umc_harvest_count)++; 908 break; 909 case GC_HWID: 910 adev->gfx.xcc_mask &= ~BIT(inst); 911 break; 912 case SDMA0_HWID: 913 adev->sdma.sdma_mask &= ~BIT(inst); 914 break; 915 #if defined(CONFIG_DRM_AMD_ISP) 916 case ISP_HWID: 917 adev->isp.harvest_config |= ~BIT(inst); 918 break; 919 #endif 920 default: 921 break; 922 } 923 } 924 925 adev->umc.active_mask = ((1ULL << adev->umc.node_inst_num) - 1ULL) & 926 ~umc_harvest_config; 927 } 928 929 /* ================================================== */ 930 931 struct ip_hw_instance { 932 struct kobject kobj; /* ip_discovery/die/#die/#hw_id/#instance/<attrs...> */ 933 934 int hw_id; 935 u8 num_instance; 936 u8 major, minor, revision; 937 u8 harvest; 938 939 int num_base_addresses; 940 u32 base_addr[] __counted_by(num_base_addresses); 941 }; 942 943 struct ip_hw_id { 944 struct kset hw_id_kset; /* ip_discovery/die/#die/#hw_id/, contains ip_hw_instance */ 945 int hw_id; 946 }; 947 948 struct ip_die_entry { 949 struct kset ip_kset; /* ip_discovery/die/#die/, contains ip_hw_id */ 950 u16 num_ips; 951 }; 952 953 /* -------------------------------------------------- */ 954 955 struct ip_hw_instance_attr { 956 struct attribute attr; 957 ssize_t (*show)(struct ip_hw_instance *ip_hw_instance, char *buf); 958 }; 959 960 static ssize_t hw_id_show(struct ip_hw_instance *ip_hw_instance, char *buf) 961 { 962 return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id); 963 } 964 965 static ssize_t num_instance_show(struct ip_hw_instance *ip_hw_instance, char *buf) 966 { 967 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance); 968 } 969 970 static ssize_t major_show(struct ip_hw_instance *ip_hw_instance, char *buf) 971 { 972 return sysfs_emit(buf, "%d\n", ip_hw_instance->major); 973 } 974 975 static ssize_t minor_show(struct ip_hw_instance *ip_hw_instance, char *buf) 976 { 977 return sysfs_emit(buf, "%d\n", ip_hw_instance->minor); 978 } 979 980 static ssize_t revision_show(struct ip_hw_instance *ip_hw_instance, char *buf) 981 { 982 return sysfs_emit(buf, "%d\n", ip_hw_instance->revision); 983 } 984 985 static ssize_t harvest_show(struct ip_hw_instance *ip_hw_instance, char *buf) 986 { 987 return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest); 988 } 989 990 static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, char *buf) 991 { 992 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses); 993 } 994 995 static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf) 996 { 997 ssize_t at; 998 int ii; 999 1000 for (at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) { 1001 /* Here we satisfy the condition that, at + size <= PAGE_SIZE. 1002 */ 1003 if (at + 12 > PAGE_SIZE) 1004 break; 1005 at += sysfs_emit_at(buf, at, "0x%08X\n", 1006 ip_hw_instance->base_addr[ii]); 1007 } 1008 1009 return at; 1010 } 1011 1012 static struct ip_hw_instance_attr ip_hw_attr[] = { 1013 __ATTR_RO(hw_id), 1014 __ATTR_RO(num_instance), 1015 __ATTR_RO(major), 1016 __ATTR_RO(minor), 1017 __ATTR_RO(revision), 1018 __ATTR_RO(harvest), 1019 __ATTR_RO(num_base_addresses), 1020 __ATTR_RO(base_addr), 1021 }; 1022 1023 static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1]; 1024 ATTRIBUTE_GROUPS(ip_hw_instance); 1025 1026 #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj) 1027 #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr) 1028 1029 static ssize_t ip_hw_instance_attr_show(struct kobject *kobj, 1030 struct attribute *attr, 1031 char *buf) 1032 { 1033 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 1034 struct ip_hw_instance_attr *ip_hw_attr = to_ip_hw_instance_attr(attr); 1035 1036 if (!ip_hw_attr->show) 1037 return -EIO; 1038 1039 return ip_hw_attr->show(ip_hw_instance, buf); 1040 } 1041 1042 static const struct sysfs_ops ip_hw_instance_sysfs_ops = { 1043 .show = ip_hw_instance_attr_show, 1044 }; 1045 1046 static void ip_hw_instance_release(struct kobject *kobj) 1047 { 1048 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 1049 1050 kfree(ip_hw_instance); 1051 } 1052 1053 static const struct kobj_type ip_hw_instance_ktype = { 1054 .release = ip_hw_instance_release, 1055 .sysfs_ops = &ip_hw_instance_sysfs_ops, 1056 .default_groups = ip_hw_instance_groups, 1057 }; 1058 1059 /* -------------------------------------------------- */ 1060 1061 #define to_ip_hw_id(x) container_of(to_kset(x), struct ip_hw_id, hw_id_kset) 1062 1063 static void ip_hw_id_release(struct kobject *kobj) 1064 { 1065 struct ip_hw_id *ip_hw_id = to_ip_hw_id(kobj); 1066 1067 if (!list_empty(&ip_hw_id->hw_id_kset.list)) 1068 DRM_ERROR("ip_hw_id->hw_id_kset is not empty"); 1069 kfree(ip_hw_id); 1070 } 1071 1072 static const struct kobj_type ip_hw_id_ktype = { 1073 .release = ip_hw_id_release, 1074 .sysfs_ops = &kobj_sysfs_ops, 1075 }; 1076 1077 /* -------------------------------------------------- */ 1078 1079 static void die_kobj_release(struct kobject *kobj); 1080 static void ip_disc_release(struct kobject *kobj); 1081 1082 struct ip_die_entry_attribute { 1083 struct attribute attr; 1084 ssize_t (*show)(struct ip_die_entry *ip_die_entry, char *buf); 1085 }; 1086 1087 #define to_ip_die_entry_attr(x) container_of(x, struct ip_die_entry_attribute, attr) 1088 1089 static ssize_t num_ips_show(struct ip_die_entry *ip_die_entry, char *buf) 1090 { 1091 return sysfs_emit(buf, "%d\n", ip_die_entry->num_ips); 1092 } 1093 1094 /* If there are more ip_die_entry attrs, other than the number of IPs, 1095 * we can make this intro an array of attrs, and then initialize 1096 * ip_die_entry_attrs in a loop. 1097 */ 1098 static struct ip_die_entry_attribute num_ips_attr = 1099 __ATTR_RO(num_ips); 1100 1101 static struct attribute *ip_die_entry_attrs[] = { 1102 &num_ips_attr.attr, 1103 NULL, 1104 }; 1105 ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */ 1106 1107 #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset) 1108 1109 static ssize_t ip_die_entry_attr_show(struct kobject *kobj, 1110 struct attribute *attr, 1111 char *buf) 1112 { 1113 struct ip_die_entry_attribute *ip_die_entry_attr = to_ip_die_entry_attr(attr); 1114 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 1115 1116 if (!ip_die_entry_attr->show) 1117 return -EIO; 1118 1119 return ip_die_entry_attr->show(ip_die_entry, buf); 1120 } 1121 1122 static void ip_die_entry_release(struct kobject *kobj) 1123 { 1124 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 1125 1126 if (!list_empty(&ip_die_entry->ip_kset.list)) 1127 DRM_ERROR("ip_die_entry->ip_kset is not empty"); 1128 kfree(ip_die_entry); 1129 } 1130 1131 static const struct sysfs_ops ip_die_entry_sysfs_ops = { 1132 .show = ip_die_entry_attr_show, 1133 }; 1134 1135 static const struct kobj_type ip_die_entry_ktype = { 1136 .release = ip_die_entry_release, 1137 .sysfs_ops = &ip_die_entry_sysfs_ops, 1138 .default_groups = ip_die_entry_groups, 1139 }; 1140 1141 static const struct kobj_type die_kobj_ktype = { 1142 .release = die_kobj_release, 1143 .sysfs_ops = &kobj_sysfs_ops, 1144 }; 1145 1146 static const struct kobj_type ip_discovery_ktype = { 1147 .release = ip_disc_release, 1148 .sysfs_ops = &kobj_sysfs_ops, 1149 }; 1150 1151 static void die_kobj_release(struct kobject *kobj) 1152 { 1153 struct ip_discovery_top *ip_top = container_of(to_kset(kobj), 1154 struct ip_discovery_top, 1155 die_kset); 1156 if (!list_empty(&ip_top->die_kset.list)) 1157 DRM_ERROR("ip_top->die_kset is not empty"); 1158 } 1159 1160 static void ip_disc_release(struct kobject *kobj) 1161 { 1162 struct ip_discovery_top *ip_top = container_of(kobj, struct ip_discovery_top, 1163 kobj); 1164 struct amdgpu_device *adev = ip_top->adev; 1165 1166 /* In standalone mode, discovery_bin is managed by devm and will be 1167 * freed automatically when the PCI device is removed. Do not manually 1168 * free it here to avoid double-free. 1169 */ 1170 1171 kfree(ip_top); 1172 if (adev) 1173 adev->discovery.ip_top = NULL; 1174 } 1175 1176 static uint8_t amdgpu_discovery_get_harvest_info(struct amdgpu_device *adev, 1177 uint16_t hw_id, uint8_t inst) 1178 { 1179 uint8_t harvest = 0; 1180 1181 /* In early init mode (adev == NULL), harvest info is not available */ 1182 if (!adev) 1183 return 0; 1184 1185 /* Until a uniform way is figured, get mask based on hwid */ 1186 switch (hw_id) { 1187 case VCN_HWID: 1188 /* VCN vs UVD+VCE */ 1189 if (!amdgpu_ip_version(adev, VCE_HWIP, 0)) 1190 harvest = ((1 << inst) & adev->vcn.inst_mask) == 0; 1191 break; 1192 case DMU_HWID: 1193 if (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK) 1194 harvest = 0x1; 1195 break; 1196 case UMC_HWID: 1197 /* TODO: It needs another parsing; for now, ignore.*/ 1198 break; 1199 case GC_HWID: 1200 harvest = ((1 << inst) & adev->gfx.xcc_mask) == 0; 1201 break; 1202 case SDMA0_HWID: 1203 harvest = ((1 << inst) & adev->sdma.sdma_mask) == 0; 1204 break; 1205 default: 1206 break; 1207 } 1208 1209 return harvest; 1210 } 1211 1212 static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev, 1213 struct ip_discovery_top *ip_top, 1214 struct ip_die_entry *ip_die_entry, 1215 const size_t _ip_offset, const int num_ips, 1216 bool reg_base_64) 1217 { 1218 uint8_t *discovery_bin = ip_top->standalone_mode ? 1219 ip_top->discovery_bin : 1220 adev->discovery.bin; 1221 int ii, jj, kk, res; 1222 uint16_t hw_id; 1223 uint8_t inst; 1224 1225 DRM_DEBUG("num_ips:%d", num_ips); 1226 1227 /* Find all IPs of a given HW ID, and add their instance to 1228 * #die/#hw_id/#instance/<attributes> 1229 */ 1230 for (ii = 0; ii < HW_ID_MAX; ii++) { 1231 struct ip_hw_id *ip_hw_id = NULL; 1232 size_t ip_offset = _ip_offset; 1233 1234 for (jj = 0; jj < num_ips; jj++) { 1235 struct ip_v4 *ip; 1236 struct ip_hw_instance *ip_hw_instance; 1237 1238 ip = (struct ip_v4 *)(discovery_bin + ip_offset); 1239 inst = ip->instance_number; 1240 hw_id = le16_to_cpu(ip->hw_id); 1241 if (amdgpu_discovery_validate_ip(adev, inst, hw_id) || 1242 hw_id != ii) 1243 goto next_ip; 1244 1245 DRM_DEBUG("match:%d @ ip_offset:%zu", ii, ip_offset); 1246 1247 /* We have a hw_id match; register the hw 1248 * block if not yet registered. 1249 */ 1250 if (!ip_hw_id) { 1251 ip_hw_id = kzalloc_obj(*ip_hw_id); 1252 if (!ip_hw_id) 1253 return -ENOMEM; 1254 ip_hw_id->hw_id = ii; 1255 1256 kobject_set_name(&ip_hw_id->hw_id_kset.kobj, "%d", ii); 1257 ip_hw_id->hw_id_kset.kobj.kset = &ip_die_entry->ip_kset; 1258 ip_hw_id->hw_id_kset.kobj.ktype = &ip_hw_id_ktype; 1259 res = kset_register(&ip_hw_id->hw_id_kset); 1260 if (res) { 1261 DRM_ERROR("Couldn't register ip_hw_id kset"); 1262 kfree(ip_hw_id); 1263 return res; 1264 } 1265 if (hw_id_names[ii]) { 1266 res = sysfs_create_link(&ip_die_entry->ip_kset.kobj, 1267 &ip_hw_id->hw_id_kset.kobj, 1268 hw_id_names[ii]); 1269 if (res) { 1270 DRM_ERROR("Couldn't create IP link %s in IP Die:%s\n", 1271 hw_id_names[ii], 1272 kobject_name(&ip_die_entry->ip_kset.kobj)); 1273 } 1274 } 1275 } 1276 1277 /* Now register its instance. 1278 */ 1279 ip_hw_instance = kzalloc_flex(*ip_hw_instance, 1280 base_addr, 1281 ip->num_base_address); 1282 if (!ip_hw_instance) { 1283 DRM_ERROR("no memory for ip_hw_instance"); 1284 return -ENOMEM; 1285 } 1286 ip_hw_instance->hw_id = le16_to_cpu(ip->hw_id); /* == ii */ 1287 ip_hw_instance->num_instance = ip->instance_number; 1288 ip_hw_instance->major = ip->major; 1289 ip_hw_instance->minor = ip->minor; 1290 ip_hw_instance->revision = ip->revision; 1291 ip_hw_instance->harvest = 1292 amdgpu_discovery_get_harvest_info( 1293 adev, ip_hw_instance->hw_id, 1294 ip_hw_instance->num_instance); 1295 ip_hw_instance->num_base_addresses = ip->num_base_address; 1296 1297 for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++) 1298 ip_hw_instance->base_addr[kk] = ip->base_address[kk]; 1299 1300 kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype); 1301 ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset; 1302 res = kobject_add(&ip_hw_instance->kobj, NULL, 1303 "%d", ip_hw_instance->num_instance); 1304 next_ip: 1305 if (reg_base_64) 1306 ip_offset += struct_size(ip, base_address_64, 1307 ip->num_base_address); 1308 else 1309 ip_offset += struct_size(ip, base_address, 1310 ip->num_base_address); 1311 } 1312 } 1313 1314 return 0; 1315 } 1316 1317 static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev, 1318 struct ip_discovery_top *ip_top) 1319 { 1320 uint8_t *discovery_bin = ip_top->standalone_mode ? 1321 ip_top->discovery_bin : 1322 adev->discovery.bin; 1323 struct table_info *info; 1324 struct ip_discovery_header *ihdr; 1325 struct die_header *dhdr; 1326 struct kset *die_kset = &ip_top->die_kset; 1327 u16 num_dies, die_offset, num_ips; 1328 size_t ip_offset; 1329 int ii, res; 1330 1331 info = amdgpu_discovery_get_table_info_from_bin(discovery_bin, 1332 IP_DISCOVERY); 1333 if (!info) 1334 return -EINVAL; 1335 ihdr = (struct ip_discovery_header 1336 *)(discovery_bin + 1337 le16_to_cpu(info->offset)); 1338 num_dies = le16_to_cpu(ihdr->num_dies); 1339 1340 DRM_DEBUG("number of dies: %d\n", num_dies); 1341 1342 for (ii = 0; ii < num_dies; ii++) { 1343 struct ip_die_entry *ip_die_entry; 1344 1345 die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset); 1346 dhdr = (struct die_header *)(discovery_bin + die_offset); 1347 num_ips = le16_to_cpu(dhdr->num_ips); 1348 ip_offset = die_offset + sizeof(*dhdr); 1349 1350 /* Add the die to the kset. 1351 * 1352 * dhdr->die_id == ii, which was checked in 1353 * amdgpu_discovery_reg_base_init(). 1354 */ 1355 1356 ip_die_entry = kzalloc_obj(*ip_die_entry); 1357 if (!ip_die_entry) 1358 return -ENOMEM; 1359 1360 ip_die_entry->num_ips = num_ips; 1361 1362 kobject_set_name(&ip_die_entry->ip_kset.kobj, "%d", le16_to_cpu(dhdr->die_id)); 1363 ip_die_entry->ip_kset.kobj.kset = die_kset; 1364 ip_die_entry->ip_kset.kobj.ktype = &ip_die_entry_ktype; 1365 res = kset_register(&ip_die_entry->ip_kset); 1366 if (res) { 1367 DRM_ERROR("Couldn't register ip_die_entry kset"); 1368 kfree(ip_die_entry); 1369 return res; 1370 } 1371 1372 amdgpu_discovery_sysfs_ips(adev, ip_top, ip_die_entry, ip_offset, 1373 num_ips, !!ihdr->base_addr_64_bit); 1374 } 1375 1376 return 0; 1377 } 1378 1379 static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev) 1380 { 1381 uint8_t *discovery_bin = adev->discovery.bin; 1382 struct ip_discovery_top *ip_top; 1383 struct kset *die_kset; 1384 int res, ii; 1385 1386 if (!discovery_bin) 1387 return -EINVAL; 1388 1389 /* If early init already created sysfs in standalone mode, skip normal init */ 1390 if (adev->discovery.ip_top && adev->discovery.ip_top->standalone_mode) 1391 return 0; 1392 1393 ip_top = kzalloc_obj(*ip_top); 1394 if (!ip_top) 1395 return -ENOMEM; 1396 1397 ip_top->adev = adev; 1398 1399 /* Check if ip_discovery already exists before creating. 1400 * This shouldn't normally happen but handle it gracefully. 1401 */ 1402 if (adev->dev->kobj.sd) { 1403 struct kernfs_node *existing; 1404 1405 existing = kernfs_find_and_get(adev->dev->kobj.sd, "ip_discovery"); 1406 if (existing) { 1407 kernfs_put(existing); 1408 kfree(ip_top); 1409 return 0; 1410 } 1411 } 1412 1413 res = kobject_init_and_add(&ip_top->kobj, &ip_discovery_ktype, 1414 &adev->dev->kobj, "ip_discovery"); 1415 if (res) { 1416 DRM_ERROR("Couldn't init and add ip_discovery/"); 1417 goto Err; 1418 } 1419 1420 adev->discovery.ip_top = ip_top; 1421 1422 die_kset = &ip_top->die_kset; 1423 kobject_set_name(&die_kset->kobj, "%s", "die"); 1424 die_kset->kobj.parent = &ip_top->kobj; 1425 die_kset->kobj.ktype = &die_kobj_ktype; 1426 res = kset_register(&ip_top->die_kset); 1427 if (res) { 1428 DRM_ERROR("Couldn't register die_kset"); 1429 goto Err; 1430 } 1431 1432 for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++) 1433 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr; 1434 ip_hw_instance_attrs[ii] = NULL; 1435 1436 res = amdgpu_discovery_sysfs_recurse(adev, ip_top); 1437 1438 return res; 1439 Err: 1440 kobject_put(&ip_top->kobj); 1441 return res; 1442 } 1443 1444 /* -------------------------------------------------- */ 1445 1446 #define list_to_kobj(el) container_of(el, struct kobject, entry) 1447 1448 static void amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id *ip_hw_id) 1449 { 1450 struct list_head *el, *tmp; 1451 struct kset *hw_id_kset; 1452 1453 hw_id_kset = &ip_hw_id->hw_id_kset; 1454 spin_lock(&hw_id_kset->list_lock); 1455 list_for_each_prev_safe(el, tmp, &hw_id_kset->list) { 1456 list_del_init(el); 1457 spin_unlock(&hw_id_kset->list_lock); 1458 /* kobject is embedded in ip_hw_instance */ 1459 kobject_put(list_to_kobj(el)); 1460 spin_lock(&hw_id_kset->list_lock); 1461 } 1462 spin_unlock(&hw_id_kset->list_lock); 1463 kobject_put(&ip_hw_id->hw_id_kset.kobj); 1464 } 1465 1466 static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry) 1467 { 1468 struct list_head *el, *tmp; 1469 struct kset *ip_kset; 1470 1471 ip_kset = &ip_die_entry->ip_kset; 1472 spin_lock(&ip_kset->list_lock); 1473 list_for_each_prev_safe(el, tmp, &ip_kset->list) { 1474 list_del_init(el); 1475 spin_unlock(&ip_kset->list_lock); 1476 amdgpu_discovery_sysfs_ip_hw_free(to_ip_hw_id(list_to_kobj(el))); 1477 spin_lock(&ip_kset->list_lock); 1478 } 1479 spin_unlock(&ip_kset->list_lock); 1480 kobject_put(&ip_die_entry->ip_kset.kobj); 1481 } 1482 1483 void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev) 1484 { 1485 struct ip_discovery_top *ip_top = adev->discovery.ip_top; 1486 struct list_head *el, *tmp; 1487 struct kset *die_kset; 1488 1489 if (!ip_top) 1490 return; 1491 1492 /* 1493 * In standalone mode the sysfs hierarchy is tied to the PCI device 1494 * lifetime and is torn down by amdgpu_discovery_sysfs_early_fini(). 1495 * Freeing it here would leave a dangling pointer in the early 1496 * discovery list, causing a use-after-free on driver unbind. 1497 */ 1498 if (ip_top->standalone_mode) 1499 return; 1500 1501 adev->discovery.ip_top = NULL; 1502 die_kset = &ip_top->die_kset; 1503 spin_lock(&die_kset->list_lock); 1504 list_for_each_prev_safe(el, tmp, &die_kset->list) { 1505 list_del_init(el); 1506 spin_unlock(&die_kset->list_lock); 1507 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el))); 1508 spin_lock(&die_kset->list_lock); 1509 } 1510 spin_unlock(&die_kset->list_lock); 1511 kobject_put(&ip_top->die_kset.kobj); 1512 kobject_put(&ip_top->kobj); 1513 } 1514 1515 /* devcoredump support */ 1516 void amdgpu_discovery_dump(struct amdgpu_device *adev, struct drm_printer *p) 1517 { 1518 struct ip_discovery_top *ip_top = adev->discovery.ip_top; 1519 struct ip_die_entry *ip_die_entry; 1520 struct list_head *el_die, *el_hw_id, *el_hw_inst; 1521 struct ip_hw_id *hw_id; 1522 struct kset *die_kset; 1523 struct ip_hw_instance *ip_inst; 1524 int i = 0, j; 1525 1526 if (!ip_top) 1527 return; 1528 1529 die_kset = &ip_top->die_kset; 1530 1531 drm_printf(p, "\nHW IP Discovery\n"); 1532 1533 spin_lock(&die_kset->list_lock); 1534 list_for_each(el_die, &die_kset->list) { 1535 drm_printf(p, "die %d\n", i++); 1536 ip_die_entry = to_ip_die_entry(list_to_kobj(el_die)); 1537 1538 list_for_each(el_hw_id, &ip_die_entry->ip_kset.list) { 1539 hw_id = to_ip_hw_id(list_to_kobj(el_hw_id)); 1540 drm_printf(p, "hw_id %d %s\n", hw_id->hw_id, hw_id_names[hw_id->hw_id]); 1541 1542 list_for_each(el_hw_inst, &hw_id->hw_id_kset.list) { 1543 ip_inst = to_ip_hw_instance(list_to_kobj(el_hw_inst)); 1544 drm_printf(p, "\tinstance %d\n", ip_inst->num_instance); 1545 drm_printf(p, "\tmajor %d\n", ip_inst->major); 1546 drm_printf(p, "\tminor %d\n", ip_inst->minor); 1547 drm_printf(p, "\trevision %d\n", ip_inst->revision); 1548 drm_printf(p, "\tharvest 0x%01X\n", ip_inst->harvest); 1549 drm_printf(p, "\tnum_base_addresses %d\n", 1550 ip_inst->num_base_addresses); 1551 for (j = 0; j < ip_inst->num_base_addresses; j++) 1552 drm_printf(p, "\tbase_addr[%d] 0x%08X\n", 1553 j, ip_inst->base_addr[j]); 1554 } 1555 } 1556 } 1557 spin_unlock(&die_kset->list_lock); 1558 } 1559 1560 int amdgpu_discovery_sysfs_early_init(struct amdgpu_device *adev, struct pci_dev *pdev) 1561 { 1562 struct ip_discovery_top *ip_top; 1563 struct early_ip_discovery *early_entry, *tmp; 1564 struct kset *die_kset; 1565 uint8_t *discovery_bin; 1566 int res, ii; 1567 1568 if (!adev || !adev->discovery.bin) 1569 return -EINVAL; 1570 1571 if (adev->discovery.ip_top) 1572 return 0; 1573 1574 mutex_lock(&early_ip_discovery_mutex); 1575 list_for_each_entry_safe(early_entry, tmp, &early_ip_discovery_list, list) { 1576 if (early_entry->pdev == pdev) { 1577 adev->discovery.ip_top = early_entry->ip_top; 1578 early_entry->ip_top->adev = adev; 1579 mutex_unlock(&early_ip_discovery_mutex); 1580 return 0; 1581 } 1582 } 1583 mutex_unlock(&early_ip_discovery_mutex); 1584 1585 discovery_bin = adev->discovery.bin; 1586 1587 early_entry = kzalloc(sizeof(*early_entry), GFP_KERNEL); 1588 if (!early_entry) 1589 return -ENOMEM; 1590 1591 ip_top = kzalloc(sizeof(*ip_top), GFP_KERNEL); 1592 if (!ip_top) { 1593 kfree(early_entry); 1594 return -ENOMEM; 1595 } 1596 1597 ip_top->discovery_bin = devm_kmemdup(&pdev->dev, discovery_bin, 1598 DISCOVERY_TMR_SIZE, GFP_KERNEL); 1599 if (!ip_top->discovery_bin) { 1600 kfree(ip_top); 1601 kfree(early_entry); 1602 return -ENOMEM; 1603 } 1604 1605 ip_top->bin_size = DISCOVERY_TMR_SIZE; 1606 ip_top->pdev = pdev; 1607 ip_top->adev = adev; 1608 ip_top->standalone_mode = true; 1609 1610 /* Check if ip_discovery already exists (from previous probe attempt). 1611 * This can happen if the module was unloaded and reloaded but the 1612 * sysfs persisted (tied to PCI device lifetime). 1613 */ 1614 if (pdev->dev.kobj.sd) { 1615 struct kernfs_node *existing; 1616 1617 existing = kernfs_find_and_get(pdev->dev.kobj.sd, "ip_discovery"); 1618 if (existing) { 1619 kernfs_put(existing); 1620 kfree(ip_top); 1621 kfree(early_entry); 1622 return 0; 1623 } 1624 } 1625 1626 res = kobject_init_and_add(&ip_top->kobj, &ip_discovery_ktype, 1627 &pdev->dev.kobj, "ip_discovery"); 1628 if (res) 1629 goto err_put_kobj; 1630 1631 adev->discovery.ip_top = ip_top; 1632 1633 die_kset = &ip_top->die_kset; 1634 kobject_set_name(&die_kset->kobj, "%s", "die"); 1635 die_kset->kobj.parent = &ip_top->kobj; 1636 die_kset->kobj.ktype = &die_kobj_ktype; 1637 res = kset_register(&ip_top->die_kset); 1638 if (res) 1639 goto err_put_die_kset; 1640 1641 for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++) 1642 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr; 1643 ip_hw_instance_attrs[ii] = NULL; 1644 1645 res = amdgpu_discovery_sysfs_recurse(NULL, ip_top); 1646 if (res) 1647 goto err_put_die_kset; 1648 1649 early_entry->pdev = pdev; 1650 early_entry->ip_top = ip_top; 1651 mutex_lock(&early_ip_discovery_mutex); 1652 list_add(&early_entry->list, &early_ip_discovery_list); 1653 mutex_unlock(&early_ip_discovery_mutex); 1654 1655 return 0; 1656 1657 err_put_die_kset: 1658 kobject_put(&ip_top->die_kset.kobj); 1659 err_put_kobj: 1660 kobject_put(&ip_top->kobj); 1661 kfree(early_entry); 1662 adev->discovery.ip_top = NULL; 1663 return res; 1664 } 1665 1666 void amdgpu_discovery_sysfs_early_fini(struct pci_dev *pdev) 1667 { 1668 struct early_ip_discovery *entry, *tmp_entry; 1669 struct ip_discovery_top *ip_top = NULL; 1670 struct list_head *el, *tmp; 1671 struct kset *die_kset; 1672 1673 /* Find the entry in our tracking list */ 1674 mutex_lock(&early_ip_discovery_mutex); 1675 list_for_each_entry_safe(entry, tmp_entry, &early_ip_discovery_list, list) { 1676 if (entry->pdev == pdev) { 1677 ip_top = entry->ip_top; 1678 list_del(&entry->list); 1679 kfree(entry); 1680 break; 1681 } 1682 } 1683 mutex_unlock(&early_ip_discovery_mutex); 1684 1685 if (!ip_top) 1686 return; 1687 1688 /* Clean up sysfs hierarchy */ 1689 die_kset = &ip_top->die_kset; 1690 1691 spin_lock(&die_kset->list_lock); 1692 list_for_each_prev_safe(el, tmp, &die_kset->list) { 1693 list_del_init(el); 1694 spin_unlock(&die_kset->list_lock); 1695 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el))); 1696 spin_lock(&die_kset->list_lock); 1697 } 1698 spin_unlock(&die_kset->list_lock); 1699 1700 kobject_put(&ip_top->die_kset.kobj); 1701 kobject_put(&ip_top->kobj); 1702 /* ip_top itself will be freed by kobject_put via ip_disc_release */ 1703 } 1704 1705 /* ================================================== */ 1706 1707 static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) 1708 { 1709 uint8_t num_base_address, subrev, variant; 1710 struct table_info *info; 1711 struct ip_discovery_header *ihdr; 1712 struct die_header *dhdr; 1713 uint8_t *discovery_bin; 1714 struct ip_v4 *ip; 1715 uint16_t die_offset; 1716 uint16_t ip_offset; 1717 uint16_t num_dies; 1718 uint32_t wafl_ver; 1719 uint16_t num_ips; 1720 uint16_t hw_id; 1721 uint8_t inst; 1722 int hw_ip; 1723 int i, j, k; 1724 int r; 1725 1726 r = amdgpu_discovery_init(adev); 1727 if (r) 1728 return r; 1729 1730 amdgpu_discovery_sysfs_early_init(adev, adev->pdev); 1731 1732 discovery_bin = adev->discovery.bin; 1733 wafl_ver = 0; 1734 adev->gfx.xcc_mask = 0; 1735 adev->sdma.sdma_mask = 0; 1736 adev->vcn.inst_mask = 0; 1737 adev->jpeg.inst_mask = 0; 1738 r = amdgpu_discovery_get_table_info(adev, &info, IP_DISCOVERY); 1739 if (r) 1740 return r; 1741 ihdr = (struct ip_discovery_header 1742 *)(discovery_bin + 1743 le16_to_cpu(info->offset)); 1744 num_dies = le16_to_cpu(ihdr->num_dies); 1745 1746 DRM_DEBUG("number of dies: %d\n", num_dies); 1747 1748 for (i = 0; i < num_dies; i++) { 1749 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 1750 dhdr = (struct die_header *)(discovery_bin + die_offset); 1751 num_ips = le16_to_cpu(dhdr->num_ips); 1752 ip_offset = die_offset + sizeof(*dhdr); 1753 1754 if (le16_to_cpu(dhdr->die_id) != i) { 1755 DRM_ERROR("invalid die id %d, expected %d\n", 1756 le16_to_cpu(dhdr->die_id), i); 1757 return -EINVAL; 1758 } 1759 1760 DRM_DEBUG("number of hardware IPs on die%d: %d\n", 1761 le16_to_cpu(dhdr->die_id), num_ips); 1762 1763 for (j = 0; j < num_ips; j++) { 1764 ip = (struct ip_v4 *)(discovery_bin + ip_offset); 1765 1766 inst = ip->instance_number; 1767 hw_id = le16_to_cpu(ip->hw_id); 1768 if (amdgpu_discovery_validate_ip(adev, inst, hw_id)) 1769 goto next_ip; 1770 1771 num_base_address = ip->num_base_address; 1772 1773 DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n", 1774 hw_id_names[le16_to_cpu(ip->hw_id)], 1775 le16_to_cpu(ip->hw_id), 1776 ip->instance_number, 1777 ip->major, ip->minor, 1778 ip->revision); 1779 1780 if (le16_to_cpu(ip->hw_id) == VCN_HWID) { 1781 /* Bit [5:0]: original revision value 1782 * Bit [7:6]: en/decode capability: 1783 * 0b00 : VCN function normally 1784 * 0b10 : encode is disabled 1785 * 0b01 : decode is disabled 1786 */ 1787 if (adev->vcn.num_vcn_inst < 1788 AMDGPU_MAX_VCN_INSTANCES) { 1789 adev->vcn.inst[adev->vcn.num_vcn_inst].vcn_config = 1790 ip->revision & 0xc0; 1791 adev->vcn.num_vcn_inst++; 1792 adev->vcn.inst_mask |= 1793 (1U << ip->instance_number); 1794 adev->jpeg.inst_mask |= 1795 (1U << ip->instance_number); 1796 } else { 1797 dev_err(adev->dev, "Too many VCN instances: %d vs %d\n", 1798 adev->vcn.num_vcn_inst + 1, 1799 AMDGPU_MAX_VCN_INSTANCES); 1800 } 1801 ip->revision &= ~0xc0; 1802 } 1803 if (le16_to_cpu(ip->hw_id) == SDMA0_HWID || 1804 le16_to_cpu(ip->hw_id) == SDMA1_HWID || 1805 le16_to_cpu(ip->hw_id) == SDMA2_HWID || 1806 le16_to_cpu(ip->hw_id) == SDMA3_HWID) { 1807 if (adev->sdma.num_instances < 1808 AMDGPU_MAX_SDMA_INSTANCES) { 1809 adev->sdma.num_instances++; 1810 adev->sdma.sdma_mask |= 1811 (1U << ip->instance_number); 1812 } else { 1813 dev_err(adev->dev, "Too many SDMA instances: %d vs %d\n", 1814 adev->sdma.num_instances + 1, 1815 AMDGPU_MAX_SDMA_INSTANCES); 1816 } 1817 } 1818 1819 if (le16_to_cpu(ip->hw_id) == VPE_HWID) { 1820 if (adev->vpe.num_instances < AMDGPU_MAX_VPE_INSTANCES) 1821 adev->vpe.num_instances++; 1822 else 1823 dev_err(adev->dev, "Too many VPE instances: %d vs %d\n", 1824 adev->vpe.num_instances + 1, 1825 AMDGPU_MAX_VPE_INSTANCES); 1826 } 1827 1828 if (le16_to_cpu(ip->hw_id) == UMC_HWID) { 1829 adev->gmc.num_umc++; 1830 adev->umc.node_inst_num++; 1831 } 1832 1833 if (le16_to_cpu(ip->hw_id) == GC_HWID) 1834 adev->gfx.xcc_mask |= 1835 (1U << ip->instance_number); 1836 1837 if (!wafl_ver && le16_to_cpu(ip->hw_id) == WAFLC_HWID) 1838 wafl_ver = IP_VERSION_FULL(ip->major, ip->minor, 1839 ip->revision, 0, 0); 1840 1841 for (k = 0; k < num_base_address; k++) { 1842 /* 1843 * convert the endianness of base addresses in place, 1844 * so that we don't need to convert them when accessing adev->reg_offset. 1845 */ 1846 if (ihdr->base_addr_64_bit) 1847 /* Truncate the 64bit base address from ip discovery 1848 * and only store lower 32bit ip base in reg_offset[]. 1849 * Bits > 32 follows ASIC specific format, thus just 1850 * discard them and handle it within specific ASIC. 1851 * By this way reg_offset[] and related helpers can 1852 * stay unchanged. 1853 * The base address is in dwords, thus clear the 1854 * highest 2 bits to store. 1855 */ 1856 ip->base_address[k] = 1857 lower_32_bits(le64_to_cpu(ip->base_address_64[k])) & 0x3FFFFFFF; 1858 else 1859 ip->base_address[k] = le32_to_cpu(ip->base_address[k]); 1860 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]); 1861 } 1862 1863 for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) { 1864 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id) && 1865 hw_id_map[hw_ip] != 0) { 1866 DRM_DEBUG("set register base offset for %s\n", 1867 hw_id_names[le16_to_cpu(ip->hw_id)]); 1868 adev->reg_offset[hw_ip][ip->instance_number] = 1869 ip->base_address; 1870 /* Instance support is somewhat inconsistent. 1871 * SDMA is a good example. Sienna cichlid has 4 total 1872 * SDMA instances, each enumerated separately (HWIDs 1873 * 42, 43, 68, 69). Arcturus has 8 total SDMA instances, 1874 * but they are enumerated as multiple instances of the 1875 * same HWIDs (4x HWID 42, 4x HWID 43). UMC is another 1876 * example. On most chips there are multiple instances 1877 * with the same HWID. 1878 */ 1879 1880 if (ihdr->version < 3) { 1881 subrev = 0; 1882 variant = 0; 1883 } else { 1884 subrev = ip->sub_revision; 1885 variant = ip->variant; 1886 } 1887 1888 adev->ip_versions[hw_ip] 1889 [ip->instance_number] = 1890 IP_VERSION_FULL(ip->major, 1891 ip->minor, 1892 ip->revision, 1893 variant, 1894 subrev); 1895 } 1896 } 1897 1898 next_ip: 1899 if (ihdr->base_addr_64_bit) 1900 ip_offset += struct_size(ip, base_address_64, ip->num_base_address); 1901 else 1902 ip_offset += struct_size(ip, base_address, ip->num_base_address); 1903 } 1904 } 1905 1906 if (wafl_ver && !adev->ip_versions[XGMI_HWIP][0]) 1907 adev->ip_versions[XGMI_HWIP][0] = wafl_ver; 1908 1909 return 0; 1910 } 1911 1912 static void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev) 1913 { 1914 uint8_t *discovery_bin = adev->discovery.bin; 1915 struct ip_discovery_header *ihdr; 1916 struct table_info *info; 1917 int vcn_harvest_count = 0; 1918 int umc_harvest_count = 0; 1919 uint16_t ihdr_ver; 1920 1921 if (amdgpu_discovery_get_table_info(adev, &info, IP_DISCOVERY)) 1922 return; 1923 ihdr = (struct ip_discovery_header *)(discovery_bin + 1924 le16_to_cpu(info->offset)); 1925 ihdr_ver = le16_to_cpu(ihdr->version); 1926 /* 1927 * Harvest table does not fit Navi1x and legacy GPUs, 1928 * so read harvest bit per IP data structure to set 1929 * harvest configuration. 1930 */ 1931 if (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 2, 0) && 1932 ihdr_ver <= 2) { 1933 if ((adev->pdev->device == 0x731E && 1934 (adev->pdev->revision == 0xC6 || 1935 adev->pdev->revision == 0xC7)) || 1936 (adev->pdev->device == 0x7340 && 1937 adev->pdev->revision == 0xC9) || 1938 (adev->pdev->device == 0x7360 && 1939 adev->pdev->revision == 0xC7)) 1940 amdgpu_discovery_read_harvest_bit_per_ip(adev, 1941 &vcn_harvest_count); 1942 } else { 1943 amdgpu_discovery_read_from_harvest_table(adev, 1944 &vcn_harvest_count, 1945 &umc_harvest_count); 1946 } 1947 1948 amdgpu_discovery_harvest_config_quirk(adev); 1949 1950 if (vcn_harvest_count == adev->vcn.num_vcn_inst) { 1951 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK; 1952 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK; 1953 } 1954 1955 if (umc_harvest_count < adev->gmc.num_umc) { 1956 adev->gmc.num_umc -= umc_harvest_count; 1957 } 1958 } 1959 1960 union gc_info { 1961 struct gc_info_v1_0 v1; 1962 struct gc_info_v1_1 v1_1; 1963 struct gc_info_v1_2 v1_2; 1964 struct gc_info_v1_3 v1_3; 1965 struct gc_info_v2_0 v2; 1966 struct gc_info_v2_1 v2_1; 1967 }; 1968 1969 static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) 1970 { 1971 uint8_t *discovery_bin = adev->discovery.bin; 1972 struct table_info *info; 1973 union gc_info *gc_info; 1974 u16 offset; 1975 1976 if (!discovery_bin) { 1977 DRM_ERROR("ip discovery uninitialized\n"); 1978 return -EINVAL; 1979 } 1980 1981 if (amdgpu_discovery_get_table_info(adev, &info, GC)) 1982 return -EINVAL; 1983 offset = le16_to_cpu(info->offset); 1984 1985 if (!offset) 1986 return 0; 1987 1988 gc_info = (union gc_info *)(discovery_bin + offset); 1989 1990 switch (le16_to_cpu(gc_info->v1.header.version_major)) { 1991 case 1: 1992 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se); 1993 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) + 1994 le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa)); 1995 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1996 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se); 1997 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c); 1998 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs); 1999 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds); 2000 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth); 2001 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth); 2002 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer); 2003 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size); 2004 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd); 2005 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu); 2006 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size); 2007 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) / 2008 le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 2009 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc); 2010 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 1) { 2011 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v1_1.gc_num_tcp_per_sa); 2012 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v1_1.gc_num_sdp_interface); 2013 adev->gfx.config.gc_num_tcps = le32_to_cpu(gc_info->v1_1.gc_num_tcps); 2014 } 2015 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 2) { 2016 adev->gfx.config.gc_num_tcp_per_wpg = le32_to_cpu(gc_info->v1_2.gc_num_tcp_per_wpg); 2017 adev->gfx.config.gc_tcp_l1_size = le32_to_cpu(gc_info->v1_2.gc_tcp_l1_size); 2018 adev->gfx.config.gc_num_sqc_per_wgp = le32_to_cpu(gc_info->v1_2.gc_num_sqc_per_wgp); 2019 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_instruction_cache_size_per_sqc); 2020 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_data_cache_size_per_sqc); 2021 adev->gfx.config.gc_gl1c_per_sa = le32_to_cpu(gc_info->v1_2.gc_gl1c_per_sa); 2022 adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance); 2023 adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu); 2024 } 2025 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 3) { 2026 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v1_3.gc_tcp_size_per_cu); 2027 adev->gfx.config.gc_tcp_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcp_cache_line_size); 2028 adev->gfx.config.gc_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_size_per_sqc); 2029 adev->gfx.config.gc_instruction_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_line_size); 2030 adev->gfx.config.gc_scalar_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_size_per_sqc); 2031 adev->gfx.config.gc_scalar_data_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_line_size); 2032 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v1_3.gc_tcc_size); 2033 adev->gfx.config.gc_tcc_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcc_cache_line_size); 2034 } 2035 break; 2036 case 2: 2037 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se); 2038 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh); 2039 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 2040 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se); 2041 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs); 2042 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs); 2043 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds); 2044 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth); 2045 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth); 2046 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer); 2047 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size); 2048 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd); 2049 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu); 2050 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size); 2051 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) / 2052 le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 2053 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc); 2054 if (le16_to_cpu(gc_info->v2.header.version_minor) == 1) { 2055 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v2_1.gc_num_tcp_per_sh); 2056 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v2_1.gc_tcp_size_per_cu); 2057 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v2_1.gc_num_sdp_interface); /* per XCD */ 2058 adev->gfx.config.gc_num_cu_per_sqc = le32_to_cpu(gc_info->v2_1.gc_num_cu_per_sqc); 2059 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_instruction_cache_size_per_sqc); 2060 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_scalar_data_cache_size_per_sqc); 2061 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v2_1.gc_tcc_size); /* per XCD */ 2062 } 2063 break; 2064 default: 2065 dev_err(adev->dev, 2066 "Unhandled GC info table %d.%d\n", 2067 le16_to_cpu(gc_info->v1.header.version_major), 2068 le16_to_cpu(gc_info->v1.header.version_minor)); 2069 return -EINVAL; 2070 } 2071 return 0; 2072 } 2073 2074 union mall_info { 2075 struct mall_info_v1_0 v1; 2076 struct mall_info_v2_0 v2; 2077 }; 2078 2079 static int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev) 2080 { 2081 uint8_t *discovery_bin = adev->discovery.bin; 2082 struct table_info *info; 2083 union mall_info *mall_info; 2084 u32 u, mall_size_per_umc, m_s_present, half_use; 2085 u64 mall_size; 2086 u16 offset; 2087 2088 if (!discovery_bin) { 2089 DRM_ERROR("ip discovery uninitialized\n"); 2090 return -EINVAL; 2091 } 2092 2093 if (amdgpu_discovery_get_table_info(adev, &info, MALL_INFO)) 2094 return -EINVAL; 2095 offset = le16_to_cpu(info->offset); 2096 2097 if (!offset) 2098 return 0; 2099 2100 mall_info = (union mall_info *)(discovery_bin + offset); 2101 2102 switch (le16_to_cpu(mall_info->v1.header.version_major)) { 2103 case 1: 2104 mall_size = 0; 2105 mall_size_per_umc = le32_to_cpu(mall_info->v1.mall_size_per_m); 2106 m_s_present = le32_to_cpu(mall_info->v1.m_s_present); 2107 half_use = le32_to_cpu(mall_info->v1.m_half_use); 2108 for (u = 0; u < adev->gmc.num_umc; u++) { 2109 if (m_s_present & (1 << u)) 2110 mall_size += mall_size_per_umc * 2; 2111 else if (half_use & (1 << u)) 2112 mall_size += mall_size_per_umc / 2; 2113 else 2114 mall_size += mall_size_per_umc; 2115 } 2116 adev->gmc.mall_size = mall_size; 2117 adev->gmc.m_half_use = half_use; 2118 break; 2119 case 2: 2120 mall_size_per_umc = le32_to_cpu(mall_info->v2.mall_size_per_umc); 2121 adev->gmc.mall_size = (uint64_t)mall_size_per_umc * adev->gmc.num_umc; 2122 break; 2123 default: 2124 dev_err(adev->dev, 2125 "Unhandled MALL info table %d.%d\n", 2126 le16_to_cpu(mall_info->v1.header.version_major), 2127 le16_to_cpu(mall_info->v1.header.version_minor)); 2128 return -EINVAL; 2129 } 2130 return 0; 2131 } 2132 2133 union vcn_info { 2134 struct vcn_info_v1_0 v1; 2135 }; 2136 2137 static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev) 2138 { 2139 uint8_t *discovery_bin = adev->discovery.bin; 2140 struct table_info *info; 2141 union vcn_info *vcn_info; 2142 u16 offset; 2143 int v; 2144 2145 if (!discovery_bin) { 2146 DRM_ERROR("ip discovery uninitialized\n"); 2147 return -EINVAL; 2148 } 2149 2150 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES 2151 * which is smaller than VCN_INFO_TABLE_MAX_NUM_INSTANCES 2152 * but that may change in the future with new GPUs so keep this 2153 * check for defensive purposes. 2154 */ 2155 if (adev->vcn.num_vcn_inst > VCN_INFO_TABLE_MAX_NUM_INSTANCES) { 2156 dev_err(adev->dev, "invalid vcn instances\n"); 2157 return -EINVAL; 2158 } 2159 2160 if (amdgpu_discovery_get_table_info(adev, &info, VCN_INFO)) 2161 return -EINVAL; 2162 offset = le16_to_cpu(info->offset); 2163 2164 if (!offset) 2165 return 0; 2166 2167 vcn_info = (union vcn_info *)(discovery_bin + offset); 2168 2169 switch (le16_to_cpu(vcn_info->v1.header.version_major)) { 2170 case 1: 2171 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES 2172 * so this won't overflow. 2173 */ 2174 for (v = 0; v < adev->vcn.num_vcn_inst; v++) { 2175 adev->vcn.inst[v].vcn_codec_disable_mask = 2176 le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits); 2177 } 2178 break; 2179 default: 2180 dev_err(adev->dev, 2181 "Unhandled VCN info table %d.%d\n", 2182 le16_to_cpu(vcn_info->v1.header.version_major), 2183 le16_to_cpu(vcn_info->v1.header.version_minor)); 2184 return -EINVAL; 2185 } 2186 return 0; 2187 } 2188 2189 union nps_info { 2190 struct nps_info_v1_0 v1; 2191 }; 2192 2193 static int amdgpu_discovery_refresh_nps_info(struct amdgpu_device *adev, 2194 union nps_info *nps_data) 2195 { 2196 uint64_t vram_size, pos, offset; 2197 struct nps_info_header *nhdr; 2198 struct binary_header bhdr; 2199 struct binary_header_v2 bhdrv2; 2200 uint16_t checksum; 2201 2202 vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20; 2203 pos = vram_size - DISCOVERY_TMR_OFFSET; 2204 amdgpu_device_vram_access(adev, pos, &bhdr, sizeof(bhdr), false); 2205 2206 switch (bhdr.version_major) { 2207 case 2: 2208 amdgpu_device_vram_access(adev, pos, &bhdrv2, sizeof(bhdrv2), false); 2209 offset = le16_to_cpu(bhdrv2.table_list[NPS_INFO].offset); 2210 checksum = le16_to_cpu(bhdrv2.table_list[NPS_INFO].checksum); 2211 break; 2212 case 1: 2213 offset = le16_to_cpu(bhdr.table_list[NPS_INFO].offset); 2214 checksum = le16_to_cpu(bhdr.table_list[NPS_INFO].checksum); 2215 break; 2216 default: 2217 return -EINVAL; 2218 } 2219 2220 amdgpu_device_vram_access(adev, (pos + offset), nps_data, 2221 sizeof(*nps_data), false); 2222 2223 nhdr = (struct nps_info_header *)(nps_data); 2224 if (!amdgpu_discovery_verify_checksum(adev, (uint8_t *)nps_data, 2225 le32_to_cpu(nhdr->size_bytes), 2226 checksum)) { 2227 dev_err(adev->dev, "nps data refresh, checksum mismatch\n"); 2228 return -EINVAL; 2229 } 2230 2231 return 0; 2232 } 2233 2234 int amdgpu_discovery_get_nps_info(struct amdgpu_device *adev, 2235 uint32_t *nps_type, 2236 struct amdgpu_gmc_memrange *ranges, 2237 int *range_cnt, bool refresh) 2238 { 2239 uint8_t *discovery_bin = adev->discovery.bin; 2240 struct table_info *info; 2241 union nps_info *nps_info; 2242 union nps_info nps_data; 2243 u16 offset; 2244 int i, r; 2245 2246 if (!nps_type || !range_cnt || !ranges) 2247 return -EINVAL; 2248 2249 if (refresh) { 2250 r = amdgpu_discovery_refresh_nps_info(adev, &nps_data); 2251 if (r) 2252 return r; 2253 nps_info = &nps_data; 2254 } else { 2255 if (!discovery_bin) { 2256 dev_err(adev->dev, 2257 "fetch mem range failed, ip discovery uninitialized\n"); 2258 return -EINVAL; 2259 } 2260 2261 if (amdgpu_discovery_get_table_info(adev, &info, NPS_INFO)) 2262 return -EINVAL; 2263 offset = le16_to_cpu(info->offset); 2264 2265 if (!offset) 2266 return -ENOENT; 2267 2268 /* If verification fails, return as if NPS table doesn't exist */ 2269 if (amdgpu_discovery_verify_npsinfo(adev, info)) 2270 return -ENOENT; 2271 2272 nps_info = (union nps_info *)(discovery_bin + offset); 2273 } 2274 2275 switch (le16_to_cpu(nps_info->v1.header.version_major)) { 2276 case 1: 2277 *nps_type = nps_info->v1.nps_type; 2278 if (*range_cnt < nps_info->v1.count) { 2279 dev_dbg(adev->dev, 2280 "not enough space for nps ranges: %d < %d\n", 2281 *range_cnt, nps_info->v1.count); 2282 return -ENOSPC; 2283 } 2284 *range_cnt = nps_info->v1.count; 2285 for (i = 0; i < *range_cnt; i++) { 2286 ranges[i].base_address = 2287 nps_info->v1.instance_info[i].base_address; 2288 ranges[i].limit_address = 2289 nps_info->v1.instance_info[i].limit_address; 2290 ranges[i].nid_mask = -1; 2291 ranges[i].flags = 0; 2292 } 2293 break; 2294 default: 2295 dev_err(adev->dev, "Unhandled NPS info table %d.%d\n", 2296 le16_to_cpu(nps_info->v1.header.version_major), 2297 le16_to_cpu(nps_info->v1.header.version_minor)); 2298 return -EINVAL; 2299 } 2300 2301 return 0; 2302 } 2303 2304 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev) 2305 { 2306 /* what IP to use for this? */ 2307 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2308 case IP_VERSION(9, 0, 1): 2309 case IP_VERSION(9, 1, 0): 2310 case IP_VERSION(9, 2, 1): 2311 case IP_VERSION(9, 2, 2): 2312 case IP_VERSION(9, 3, 0): 2313 case IP_VERSION(9, 4, 0): 2314 case IP_VERSION(9, 4, 1): 2315 case IP_VERSION(9, 4, 2): 2316 case IP_VERSION(9, 4, 3): 2317 case IP_VERSION(9, 4, 4): 2318 case IP_VERSION(9, 5, 0): 2319 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 2320 break; 2321 case IP_VERSION(10, 1, 10): 2322 case IP_VERSION(10, 1, 1): 2323 case IP_VERSION(10, 1, 2): 2324 case IP_VERSION(10, 1, 3): 2325 case IP_VERSION(10, 1, 4): 2326 case IP_VERSION(10, 3, 0): 2327 case IP_VERSION(10, 3, 1): 2328 case IP_VERSION(10, 3, 2): 2329 case IP_VERSION(10, 3, 3): 2330 case IP_VERSION(10, 3, 4): 2331 case IP_VERSION(10, 3, 5): 2332 case IP_VERSION(10, 3, 6): 2333 case IP_VERSION(10, 3, 7): 2334 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 2335 break; 2336 case IP_VERSION(11, 0, 0): 2337 case IP_VERSION(11, 0, 1): 2338 case IP_VERSION(11, 0, 2): 2339 case IP_VERSION(11, 0, 3): 2340 case IP_VERSION(11, 0, 4): 2341 case IP_VERSION(11, 5, 0): 2342 case IP_VERSION(11, 5, 1): 2343 case IP_VERSION(11, 5, 2): 2344 case IP_VERSION(11, 5, 3): 2345 case IP_VERSION(11, 5, 4): 2346 case IP_VERSION(11, 5, 6): 2347 case IP_VERSION(11, 7, 0): 2348 case IP_VERSION(11, 7, 1): 2349 amdgpu_device_ip_block_add(adev, &soc21_common_ip_block); 2350 break; 2351 case IP_VERSION(12, 0, 0): 2352 case IP_VERSION(12, 0, 1): 2353 amdgpu_device_ip_block_add(adev, &soc24_common_ip_block); 2354 break; 2355 case IP_VERSION(12, 1, 0): 2356 amdgpu_device_ip_block_add(adev, &soc_v1_0_common_ip_block); 2357 break; 2358 default: 2359 dev_err(adev->dev, 2360 "Failed to add common ip block(GC_HWIP:0x%x)\n", 2361 amdgpu_ip_version(adev, GC_HWIP, 0)); 2362 return -EINVAL; 2363 } 2364 return 0; 2365 } 2366 2367 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev) 2368 { 2369 /* use GC or MMHUB IP version */ 2370 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2371 case IP_VERSION(9, 0, 1): 2372 case IP_VERSION(9, 1, 0): 2373 case IP_VERSION(9, 2, 1): 2374 case IP_VERSION(9, 2, 2): 2375 case IP_VERSION(9, 3, 0): 2376 case IP_VERSION(9, 4, 0): 2377 case IP_VERSION(9, 4, 1): 2378 case IP_VERSION(9, 4, 2): 2379 case IP_VERSION(9, 4, 3): 2380 case IP_VERSION(9, 4, 4): 2381 case IP_VERSION(9, 5, 0): 2382 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 2383 break; 2384 case IP_VERSION(10, 1, 10): 2385 case IP_VERSION(10, 1, 1): 2386 case IP_VERSION(10, 1, 2): 2387 case IP_VERSION(10, 1, 3): 2388 case IP_VERSION(10, 1, 4): 2389 case IP_VERSION(10, 3, 0): 2390 case IP_VERSION(10, 3, 1): 2391 case IP_VERSION(10, 3, 2): 2392 case IP_VERSION(10, 3, 3): 2393 case IP_VERSION(10, 3, 4): 2394 case IP_VERSION(10, 3, 5): 2395 case IP_VERSION(10, 3, 6): 2396 case IP_VERSION(10, 3, 7): 2397 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 2398 break; 2399 case IP_VERSION(11, 0, 0): 2400 case IP_VERSION(11, 0, 1): 2401 case IP_VERSION(11, 0, 2): 2402 case IP_VERSION(11, 0, 3): 2403 case IP_VERSION(11, 0, 4): 2404 case IP_VERSION(11, 5, 0): 2405 case IP_VERSION(11, 5, 1): 2406 case IP_VERSION(11, 5, 2): 2407 case IP_VERSION(11, 5, 3): 2408 case IP_VERSION(11, 5, 4): 2409 case IP_VERSION(11, 5, 6): 2410 case IP_VERSION(11, 7, 0): 2411 case IP_VERSION(11, 7, 1): 2412 amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block); 2413 break; 2414 case IP_VERSION(12, 0, 0): 2415 case IP_VERSION(12, 0, 1): 2416 case IP_VERSION(12, 1, 0): 2417 amdgpu_device_ip_block_add(adev, &gmc_v12_0_ip_block); 2418 break; 2419 default: 2420 dev_err(adev->dev, "Failed to add gmc ip block(GC_HWIP:0x%x)\n", 2421 amdgpu_ip_version(adev, GC_HWIP, 0)); 2422 return -EINVAL; 2423 } 2424 return 0; 2425 } 2426 2427 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev) 2428 { 2429 switch (amdgpu_ip_version(adev, OSSSYS_HWIP, 0)) { 2430 case IP_VERSION(4, 0, 0): 2431 case IP_VERSION(4, 0, 1): 2432 case IP_VERSION(4, 1, 0): 2433 case IP_VERSION(4, 1, 1): 2434 case IP_VERSION(4, 3, 0): 2435 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 2436 break; 2437 case IP_VERSION(4, 2, 0): 2438 case IP_VERSION(4, 2, 1): 2439 case IP_VERSION(4, 4, 0): 2440 case IP_VERSION(4, 4, 2): 2441 case IP_VERSION(4, 4, 5): 2442 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 2443 break; 2444 case IP_VERSION(5, 0, 0): 2445 case IP_VERSION(5, 0, 1): 2446 case IP_VERSION(5, 0, 2): 2447 case IP_VERSION(5, 0, 3): 2448 case IP_VERSION(5, 2, 0): 2449 case IP_VERSION(5, 2, 1): 2450 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 2451 break; 2452 case IP_VERSION(6, 0, 0): 2453 case IP_VERSION(6, 0, 1): 2454 case IP_VERSION(6, 0, 2): 2455 amdgpu_device_ip_block_add(adev, &ih_v6_0_ip_block); 2456 break; 2457 case IP_VERSION(6, 1, 0): 2458 case IP_VERSION(6, 1, 1): 2459 case IP_VERSION(6, 4, 0): 2460 amdgpu_device_ip_block_add(adev, &ih_v6_1_ip_block); 2461 break; 2462 case IP_VERSION(7, 0, 0): 2463 case IP_VERSION(7, 1, 0): 2464 amdgpu_device_ip_block_add(adev, &ih_v7_0_ip_block); 2465 break; 2466 default: 2467 dev_err(adev->dev, 2468 "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n", 2469 amdgpu_ip_version(adev, OSSSYS_HWIP, 0)); 2470 return -EINVAL; 2471 } 2472 return 0; 2473 } 2474 2475 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev) 2476 { 2477 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 2478 case IP_VERSION(9, 0, 0): 2479 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 2480 break; 2481 case IP_VERSION(10, 0, 0): 2482 case IP_VERSION(10, 0, 1): 2483 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); 2484 break; 2485 case IP_VERSION(11, 0, 0): 2486 case IP_VERSION(11, 0, 2): 2487 case IP_VERSION(11, 0, 4): 2488 case IP_VERSION(11, 0, 5): 2489 case IP_VERSION(11, 0, 9): 2490 case IP_VERSION(11, 0, 7): 2491 case IP_VERSION(11, 0, 11): 2492 case IP_VERSION(11, 0, 12): 2493 case IP_VERSION(11, 0, 13): 2494 case IP_VERSION(11, 5, 0): 2495 case IP_VERSION(11, 5, 2): 2496 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 2497 break; 2498 case IP_VERSION(11, 0, 8): 2499 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block); 2500 break; 2501 case IP_VERSION(11, 0, 3): 2502 case IP_VERSION(12, 0, 1): 2503 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); 2504 break; 2505 case IP_VERSION(13, 0, 0): 2506 case IP_VERSION(13, 0, 1): 2507 case IP_VERSION(13, 0, 2): 2508 case IP_VERSION(13, 0, 3): 2509 case IP_VERSION(13, 0, 5): 2510 case IP_VERSION(13, 0, 6): 2511 case IP_VERSION(13, 0, 7): 2512 case IP_VERSION(13, 0, 8): 2513 case IP_VERSION(13, 0, 10): 2514 case IP_VERSION(13, 0, 11): 2515 case IP_VERSION(13, 0, 12): 2516 case IP_VERSION(13, 0, 14): 2517 case IP_VERSION(13, 0, 15): 2518 case IP_VERSION(14, 0, 0): 2519 case IP_VERSION(14, 0, 1): 2520 case IP_VERSION(14, 0, 4): 2521 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); 2522 break; 2523 case IP_VERSION(13, 0, 4): 2524 amdgpu_device_ip_block_add(adev, &psp_v13_0_4_ip_block); 2525 break; 2526 case IP_VERSION(14, 0, 2): 2527 case IP_VERSION(14, 0, 3): 2528 case IP_VERSION(14, 0, 5): 2529 amdgpu_device_ip_block_add(adev, &psp_v14_0_ip_block); 2530 break; 2531 case IP_VERSION(15, 0, 0): 2532 case IP_VERSION(15, 0, 5): 2533 case IP_VERSION(15, 0, 9): 2534 amdgpu_device_ip_block_add(adev, &psp_v15_0_ip_block); 2535 break; 2536 case IP_VERSION(15, 0, 8): 2537 amdgpu_device_ip_block_add(adev, &psp_v15_0_8_ip_block); 2538 break; 2539 default: 2540 dev_err(adev->dev, 2541 "Failed to add psp ip block(MP0_HWIP:0x%x)\n", 2542 amdgpu_ip_version(adev, MP0_HWIP, 0)); 2543 return -EINVAL; 2544 } 2545 return 0; 2546 } 2547 2548 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev) 2549 { 2550 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2551 case IP_VERSION(9, 0, 0): 2552 case IP_VERSION(10, 0, 0): 2553 case IP_VERSION(10, 0, 1): 2554 case IP_VERSION(11, 0, 2): 2555 if (adev->asic_type == CHIP_ARCTURUS) 2556 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 2557 else 2558 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 2559 break; 2560 case IP_VERSION(11, 0, 0): 2561 case IP_VERSION(11, 0, 5): 2562 case IP_VERSION(11, 0, 9): 2563 case IP_VERSION(11, 0, 7): 2564 case IP_VERSION(11, 0, 11): 2565 case IP_VERSION(11, 0, 12): 2566 case IP_VERSION(11, 0, 13): 2567 case IP_VERSION(11, 5, 0): 2568 case IP_VERSION(11, 5, 2): 2569 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 2570 break; 2571 case IP_VERSION(11, 0, 8): 2572 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) 2573 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 2574 break; 2575 case IP_VERSION(12, 0, 0): 2576 case IP_VERSION(12, 0, 1): 2577 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); 2578 break; 2579 case IP_VERSION(13, 0, 0): 2580 case IP_VERSION(13, 0, 1): 2581 case IP_VERSION(13, 0, 2): 2582 case IP_VERSION(13, 0, 3): 2583 case IP_VERSION(13, 0, 4): 2584 case IP_VERSION(13, 0, 5): 2585 case IP_VERSION(13, 0, 6): 2586 case IP_VERSION(13, 0, 7): 2587 case IP_VERSION(13, 0, 8): 2588 case IP_VERSION(13, 0, 10): 2589 case IP_VERSION(13, 0, 11): 2590 case IP_VERSION(13, 0, 14): 2591 case IP_VERSION(13, 0, 12): 2592 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); 2593 break; 2594 case IP_VERSION(14, 0, 0): 2595 case IP_VERSION(14, 0, 1): 2596 case IP_VERSION(14, 0, 2): 2597 case IP_VERSION(14, 0, 3): 2598 case IP_VERSION(14, 0, 4): 2599 case IP_VERSION(14, 0, 5): 2600 amdgpu_device_ip_block_add(adev, &smu_v14_0_ip_block); 2601 break; 2602 case IP_VERSION(15, 0, 0): 2603 case IP_VERSION(15, 0, 5): 2604 case IP_VERSION(15, 0, 8): 2605 case IP_VERSION(15, 0, 9): 2606 amdgpu_device_ip_block_add(adev, &smu_v15_0_ip_block); 2607 break; 2608 default: 2609 dev_err(adev->dev, 2610 "Failed to add smu ip block(MP1_HWIP:0x%x)\n", 2611 amdgpu_ip_version(adev, MP1_HWIP, 0)); 2612 return -EINVAL; 2613 } 2614 return 0; 2615 } 2616 2617 #if defined(CONFIG_DRM_AMD_DC) 2618 static void amdgpu_discovery_set_sriov_display(struct amdgpu_device *adev) 2619 { 2620 amdgpu_device_set_sriov_virtual_display(adev); 2621 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2622 } 2623 #endif 2624 2625 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev) 2626 { 2627 if (adev->enable_virtual_display) { 2628 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2629 return 0; 2630 } 2631 2632 if (!amdgpu_device_has_dc_support(adev)) 2633 return 0; 2634 2635 #if defined(CONFIG_DRM_AMD_DC) 2636 if (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2637 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2638 case IP_VERSION(1, 0, 0): 2639 case IP_VERSION(1, 0, 1): 2640 case IP_VERSION(2, 0, 2): 2641 case IP_VERSION(2, 0, 0): 2642 case IP_VERSION(2, 0, 3): 2643 case IP_VERSION(2, 1, 0): 2644 case IP_VERSION(3, 0, 0): 2645 case IP_VERSION(3, 0, 2): 2646 case IP_VERSION(3, 0, 3): 2647 case IP_VERSION(3, 0, 1): 2648 case IP_VERSION(3, 1, 2): 2649 case IP_VERSION(3, 1, 3): 2650 case IP_VERSION(3, 1, 4): 2651 case IP_VERSION(3, 1, 5): 2652 case IP_VERSION(3, 1, 6): 2653 case IP_VERSION(3, 2, 0): 2654 case IP_VERSION(3, 2, 1): 2655 case IP_VERSION(3, 5, 0): 2656 case IP_VERSION(3, 5, 1): 2657 case IP_VERSION(3, 6, 0): 2658 case IP_VERSION(4, 1, 0): 2659 case IP_VERSION(4, 2, 0): 2660 case IP_VERSION(4, 2, 1): 2661 /* TODO: Fix IP version. DC code expects version 4.0.1 */ 2662 if (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(4, 1, 0)) 2663 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(4, 0, 1); 2664 2665 if (amdgpu_sriov_vf(adev)) 2666 amdgpu_discovery_set_sriov_display(adev); 2667 else 2668 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2669 break; 2670 default: 2671 dev_err(adev->dev, 2672 "Failed to add dm ip block(DCE_HWIP:0x%x)\n", 2673 amdgpu_ip_version(adev, DCE_HWIP, 0)); 2674 return -EINVAL; 2675 } 2676 } else if (amdgpu_ip_version(adev, DCI_HWIP, 0)) { 2677 switch (amdgpu_ip_version(adev, DCI_HWIP, 0)) { 2678 case IP_VERSION(12, 0, 0): 2679 case IP_VERSION(12, 0, 1): 2680 case IP_VERSION(12, 1, 0): 2681 if (amdgpu_sriov_vf(adev)) 2682 amdgpu_discovery_set_sriov_display(adev); 2683 else 2684 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2685 break; 2686 default: 2687 dev_err(adev->dev, 2688 "Failed to add dm ip block(DCI_HWIP:0x%x)\n", 2689 amdgpu_ip_version(adev, DCI_HWIP, 0)); 2690 return -EINVAL; 2691 } 2692 } 2693 #endif 2694 return 0; 2695 } 2696 2697 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) 2698 { 2699 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2700 case IP_VERSION(9, 0, 1): 2701 case IP_VERSION(9, 1, 0): 2702 case IP_VERSION(9, 2, 1): 2703 case IP_VERSION(9, 2, 2): 2704 case IP_VERSION(9, 3, 0): 2705 case IP_VERSION(9, 4, 0): 2706 case IP_VERSION(9, 4, 1): 2707 case IP_VERSION(9, 4, 2): 2708 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 2709 break; 2710 case IP_VERSION(9, 4, 3): 2711 case IP_VERSION(9, 4, 4): 2712 case IP_VERSION(9, 5, 0): 2713 amdgpu_device_ip_block_add(adev, &gfx_v9_4_3_ip_block); 2714 break; 2715 case IP_VERSION(10, 1, 10): 2716 case IP_VERSION(10, 1, 2): 2717 case IP_VERSION(10, 1, 1): 2718 case IP_VERSION(10, 1, 3): 2719 case IP_VERSION(10, 1, 4): 2720 case IP_VERSION(10, 3, 0): 2721 case IP_VERSION(10, 3, 2): 2722 case IP_VERSION(10, 3, 1): 2723 case IP_VERSION(10, 3, 4): 2724 case IP_VERSION(10, 3, 5): 2725 case IP_VERSION(10, 3, 6): 2726 case IP_VERSION(10, 3, 3): 2727 case IP_VERSION(10, 3, 7): 2728 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 2729 break; 2730 case IP_VERSION(11, 0, 0): 2731 case IP_VERSION(11, 0, 1): 2732 case IP_VERSION(11, 0, 2): 2733 case IP_VERSION(11, 0, 3): 2734 case IP_VERSION(11, 0, 4): 2735 case IP_VERSION(11, 5, 0): 2736 case IP_VERSION(11, 5, 1): 2737 case IP_VERSION(11, 5, 2): 2738 case IP_VERSION(11, 5, 3): 2739 case IP_VERSION(11, 5, 4): 2740 case IP_VERSION(11, 5, 6): 2741 case IP_VERSION(11, 7, 0): 2742 case IP_VERSION(11, 7, 1): 2743 amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block); 2744 break; 2745 case IP_VERSION(12, 0, 0): 2746 case IP_VERSION(12, 0, 1): 2747 amdgpu_device_ip_block_add(adev, &gfx_v12_0_ip_block); 2748 break; 2749 case IP_VERSION(12, 1, 0): 2750 amdgpu_device_ip_block_add(adev, &gfx_v12_1_ip_block); 2751 break; 2752 default: 2753 dev_err(adev->dev, "Failed to add gfx ip block(GC_HWIP:0x%x)\n", 2754 amdgpu_ip_version(adev, GC_HWIP, 0)); 2755 return -EINVAL; 2756 } 2757 return 0; 2758 } 2759 2760 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev) 2761 { 2762 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 2763 case IP_VERSION(4, 0, 0): 2764 case IP_VERSION(4, 0, 1): 2765 case IP_VERSION(4, 1, 0): 2766 case IP_VERSION(4, 1, 1): 2767 case IP_VERSION(4, 1, 2): 2768 case IP_VERSION(4, 2, 0): 2769 case IP_VERSION(4, 2, 2): 2770 case IP_VERSION(4, 4, 0): 2771 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 2772 break; 2773 case IP_VERSION(4, 4, 2): 2774 case IP_VERSION(4, 4, 5): 2775 case IP_VERSION(4, 4, 4): 2776 amdgpu_device_ip_block_add(adev, &sdma_v4_4_2_ip_block); 2777 break; 2778 case IP_VERSION(5, 0, 0): 2779 case IP_VERSION(5, 0, 1): 2780 case IP_VERSION(5, 0, 2): 2781 case IP_VERSION(5, 0, 5): 2782 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 2783 break; 2784 case IP_VERSION(5, 2, 0): 2785 case IP_VERSION(5, 2, 2): 2786 case IP_VERSION(5, 2, 4): 2787 case IP_VERSION(5, 2, 5): 2788 case IP_VERSION(5, 2, 6): 2789 case IP_VERSION(5, 2, 3): 2790 case IP_VERSION(5, 2, 1): 2791 case IP_VERSION(5, 2, 7): 2792 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 2793 break; 2794 case IP_VERSION(6, 0, 0): 2795 case IP_VERSION(6, 0, 1): 2796 case IP_VERSION(6, 0, 2): 2797 case IP_VERSION(6, 0, 3): 2798 case IP_VERSION(6, 1, 0): 2799 case IP_VERSION(6, 1, 1): 2800 case IP_VERSION(6, 1, 2): 2801 case IP_VERSION(6, 1, 3): 2802 case IP_VERSION(6, 1, 4): 2803 case IP_VERSION(6, 4, 0): 2804 amdgpu_device_ip_block_add(adev, &sdma_v6_0_ip_block); 2805 break; 2806 case IP_VERSION(7, 0, 0): 2807 case IP_VERSION(7, 0, 1): 2808 amdgpu_device_ip_block_add(adev, &sdma_v7_0_ip_block); 2809 break; 2810 case IP_VERSION(7, 1, 0): 2811 amdgpu_device_ip_block_add(adev, &sdma_v7_1_ip_block); 2812 break; 2813 default: 2814 dev_err(adev->dev, 2815 "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n", 2816 amdgpu_ip_version(adev, SDMA0_HWIP, 0)); 2817 return -EINVAL; 2818 } 2819 2820 return 0; 2821 } 2822 2823 static int amdgpu_discovery_set_ras_ip_blocks(struct amdgpu_device *adev) 2824 { 2825 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 2826 case IP_VERSION(13, 0, 6): 2827 case IP_VERSION(13, 0, 12): 2828 case IP_VERSION(13, 0, 14): 2829 amdgpu_device_ip_block_add(adev, &ras_v1_0_ip_block); 2830 break; 2831 default: 2832 break; 2833 } 2834 return 0; 2835 } 2836 2837 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) 2838 { 2839 if (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 2840 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 2841 case IP_VERSION(7, 0, 0): 2842 case IP_VERSION(7, 2, 0): 2843 /* UVD is not supported on vega20 SR-IOV */ 2844 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 2845 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); 2846 break; 2847 default: 2848 dev_err(adev->dev, 2849 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n", 2850 amdgpu_ip_version(adev, UVD_HWIP, 0)); 2851 return -EINVAL; 2852 } 2853 switch (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 2854 case IP_VERSION(4, 0, 0): 2855 case IP_VERSION(4, 1, 0): 2856 /* VCE is not supported on vega20 SR-IOV */ 2857 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 2858 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); 2859 break; 2860 default: 2861 dev_err(adev->dev, 2862 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n", 2863 amdgpu_ip_version(adev, VCE_HWIP, 0)); 2864 return -EINVAL; 2865 } 2866 } else { 2867 uint32_t vcn_version = amdgpu_ip_version(adev, UVD_HWIP, 0); 2868 2869 /* no VCN discovered; nothing to add */ 2870 if (!vcn_version) 2871 return 0; 2872 switch (vcn_version) { 2873 case IP_VERSION(1, 0, 0): 2874 case IP_VERSION(1, 0, 1): 2875 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); 2876 break; 2877 case IP_VERSION(2, 0, 0): 2878 case IP_VERSION(2, 0, 2): 2879 case IP_VERSION(2, 2, 0): 2880 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 2881 if (!amdgpu_sriov_vf(adev)) 2882 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 2883 break; 2884 case IP_VERSION(2, 0, 3): 2885 break; 2886 case IP_VERSION(2, 5, 0): 2887 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 2888 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block); 2889 break; 2890 case IP_VERSION(2, 6, 0): 2891 amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block); 2892 amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block); 2893 break; 2894 case IP_VERSION(3, 0, 0): 2895 case IP_VERSION(3, 0, 16): 2896 case IP_VERSION(3, 1, 1): 2897 case IP_VERSION(3, 1, 2): 2898 case IP_VERSION(3, 0, 2): 2899 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 2900 if (!amdgpu_sriov_vf(adev)) 2901 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 2902 break; 2903 case IP_VERSION(3, 0, 33): 2904 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 2905 break; 2906 case IP_VERSION(4, 0, 0): 2907 case IP_VERSION(4, 0, 2): 2908 case IP_VERSION(4, 0, 4): 2909 amdgpu_device_ip_block_add(adev, &vcn_v4_0_ip_block); 2910 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block); 2911 break; 2912 case IP_VERSION(4, 0, 3): 2913 amdgpu_device_ip_block_add(adev, &vcn_v4_0_3_ip_block); 2914 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_3_ip_block); 2915 break; 2916 case IP_VERSION(4, 0, 5): 2917 case IP_VERSION(4, 0, 6): 2918 amdgpu_device_ip_block_add(adev, &vcn_v4_0_5_ip_block); 2919 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_5_ip_block); 2920 break; 2921 case IP_VERSION(5, 0, 0): 2922 amdgpu_device_ip_block_add(adev, &vcn_v5_0_0_ip_block); 2923 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_0_ip_block); 2924 break; 2925 case IP_VERSION(5, 3, 0): 2926 amdgpu_device_ip_block_add(adev, &vcn_v5_0_0_ip_block); 2927 amdgpu_device_ip_block_add(adev, &jpeg_v5_3_0_ip_block); 2928 break; 2929 case IP_VERSION(5, 0, 1): 2930 amdgpu_device_ip_block_add(adev, &vcn_v5_0_1_ip_block); 2931 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_1_ip_block); 2932 break; 2933 case IP_VERSION(5, 0, 2): 2934 amdgpu_device_ip_block_add(adev, &vcn_v5_0_2_ip_block); 2935 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_2_ip_block); 2936 break; 2937 default: 2938 dev_err(adev->dev, 2939 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n", 2940 vcn_version); 2941 return -EINVAL; 2942 } 2943 } 2944 return 0; 2945 } 2946 2947 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev) 2948 { 2949 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2950 case IP_VERSION(11, 0, 0): 2951 case IP_VERSION(11, 0, 1): 2952 case IP_VERSION(11, 0, 2): 2953 case IP_VERSION(11, 0, 3): 2954 case IP_VERSION(11, 0, 4): 2955 case IP_VERSION(11, 5, 0): 2956 case IP_VERSION(11, 5, 1): 2957 case IP_VERSION(11, 5, 2): 2958 case IP_VERSION(11, 5, 3): 2959 case IP_VERSION(11, 5, 4): 2960 case IP_VERSION(11, 5, 6): 2961 case IP_VERSION(11, 7, 0): 2962 case IP_VERSION(11, 7, 1): 2963 amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block); 2964 adev->enable_mes = true; 2965 adev->enable_mes_kiq = true; 2966 break; 2967 case IP_VERSION(12, 0, 0): 2968 case IP_VERSION(12, 0, 1): 2969 amdgpu_device_ip_block_add(adev, &mes_v12_0_ip_block); 2970 adev->enable_mes = true; 2971 adev->enable_mes_kiq = true; 2972 if (amdgpu_uni_mes) 2973 adev->enable_uni_mes = true; 2974 break; 2975 case IP_VERSION(12, 1, 0): 2976 amdgpu_device_ip_block_add(adev, &mes_v12_1_ip_block); 2977 adev->enable_mes = true; 2978 adev->enable_mes_kiq = true; 2979 if (amdgpu_uni_mes) 2980 adev->enable_uni_mes = true; 2981 break; 2982 default: 2983 break; 2984 } 2985 return 0; 2986 } 2987 2988 static void amdgpu_discovery_init_soc_config(struct amdgpu_device *adev) 2989 { 2990 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2991 case IP_VERSION(9, 4, 3): 2992 case IP_VERSION(9, 4, 4): 2993 case IP_VERSION(9, 5, 0): 2994 aqua_vanjaram_init_soc_config(adev); 2995 break; 2996 case IP_VERSION(12, 1, 0): 2997 soc_v1_0_init_soc_config(adev); 2998 break; 2999 default: 3000 break; 3001 } 3002 } 3003 3004 static int amdgpu_discovery_set_vpe_ip_blocks(struct amdgpu_device *adev) 3005 { 3006 switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) { 3007 case IP_VERSION(6, 1, 0): 3008 case IP_VERSION(6, 1, 1): 3009 case IP_VERSION(6, 1, 3): 3010 amdgpu_device_ip_block_add(adev, &vpe_v6_1_ip_block); 3011 break; 3012 case IP_VERSION(2, 0, 0): 3013 case IP_VERSION(2, 2, 0): 3014 amdgpu_device_ip_block_add(adev, &vpe_v2_0_ip_block); 3015 break; 3016 default: 3017 break; 3018 } 3019 3020 return 0; 3021 } 3022 3023 static int amdgpu_discovery_set_umsch_mm_ip_blocks(struct amdgpu_device *adev) 3024 { 3025 switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) { 3026 case IP_VERSION(4, 0, 5): 3027 case IP_VERSION(4, 0, 6): 3028 if (amdgpu_umsch_mm & 0x1) { 3029 amdgpu_device_ip_block_add(adev, &umsch_mm_v4_0_ip_block); 3030 adev->enable_umsch_mm = true; 3031 } 3032 break; 3033 default: 3034 break; 3035 } 3036 3037 return 0; 3038 } 3039 3040 static int amdgpu_discovery_set_isp_ip_blocks(struct amdgpu_device *adev) 3041 { 3042 #if defined(CONFIG_DRM_AMD_ISP) 3043 switch (amdgpu_ip_version(adev, ISP_HWIP, 0)) { 3044 case IP_VERSION(4, 1, 0): 3045 amdgpu_device_ip_block_add(adev, &isp_v4_1_0_ip_block); 3046 break; 3047 case IP_VERSION(4, 1, 1): 3048 amdgpu_device_ip_block_add(adev, &isp_v4_1_1_ip_block); 3049 break; 3050 default: 3051 break; 3052 } 3053 #endif 3054 3055 return 0; 3056 } 3057 3058 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 3059 { 3060 int r; 3061 3062 switch (adev->asic_type) { 3063 case CHIP_VEGA10: 3064 /* This is not fatal. We only need the discovery 3065 * binary for sysfs. We don't need it for a 3066 * functional system. 3067 */ 3068 amdgpu_discovery_init(adev); 3069 vega10_reg_base_init(adev); 3070 adev->sdma.num_instances = 2; 3071 adev->sdma.sdma_mask = 3; 3072 adev->gmc.num_umc = 4; 3073 adev->gfx.xcc_mask = 1; 3074 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0); 3075 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0); 3076 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0); 3077 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0); 3078 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0); 3079 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0); 3080 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 3081 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0); 3082 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0); 3083 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 3084 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 3085 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 3086 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0); 3087 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1); 3088 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 3089 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 3090 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0); 3091 break; 3092 case CHIP_VEGA12: 3093 /* This is not fatal. We only need the discovery 3094 * binary for sysfs. We don't need it for a 3095 * functional system. 3096 */ 3097 amdgpu_discovery_init(adev); 3098 vega10_reg_base_init(adev); 3099 adev->sdma.num_instances = 2; 3100 adev->sdma.sdma_mask = 3; 3101 adev->gmc.num_umc = 4; 3102 adev->gfx.xcc_mask = 1; 3103 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0); 3104 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0); 3105 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1); 3106 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1); 3107 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1); 3108 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1); 3109 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0); 3110 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0); 3111 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0); 3112 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 3113 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 3114 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 3115 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1); 3116 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1); 3117 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 3118 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 3119 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1); 3120 break; 3121 case CHIP_RAVEN: 3122 /* This is not fatal. We only need the discovery 3123 * binary for sysfs. We don't need it for a 3124 * functional system. 3125 */ 3126 amdgpu_discovery_init(adev); 3127 vega10_reg_base_init(adev); 3128 adev->sdma.num_instances = 1; 3129 adev->sdma.sdma_mask = 1; 3130 adev->vcn.num_vcn_inst = 1; 3131 adev->gmc.num_umc = 2; 3132 adev->gfx.xcc_mask = 1; 3133 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { 3134 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0); 3135 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0); 3136 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1); 3137 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1); 3138 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1); 3139 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1); 3140 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1); 3141 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0); 3142 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1); 3143 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1); 3144 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0); 3145 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1); 3146 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2); 3147 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1); 3148 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1); 3149 adev->ip_versions[ISP_HWIP][0] = IP_VERSION(2, 0, 0); 3150 } else { 3151 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0); 3152 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0); 3153 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0); 3154 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0); 3155 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0); 3156 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 3157 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0); 3158 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0); 3159 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0); 3160 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0); 3161 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0); 3162 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0); 3163 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0); 3164 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0); 3165 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0); 3166 adev->ip_versions[ISP_HWIP][0] = IP_VERSION(2, 0, 0); 3167 } 3168 break; 3169 case CHIP_VEGA20: 3170 /* This is not fatal. We only need the discovery 3171 * binary for sysfs. We don't need it for a 3172 * functional system. 3173 */ 3174 amdgpu_discovery_init(adev); 3175 vega20_reg_base_init(adev); 3176 adev->sdma.num_instances = 2; 3177 adev->sdma.sdma_mask = 3; 3178 adev->gmc.num_umc = 8; 3179 adev->gfx.xcc_mask = 1; 3180 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0); 3181 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0); 3182 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0); 3183 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0); 3184 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0); 3185 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0); 3186 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0); 3187 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0); 3188 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1); 3189 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2); 3190 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 3191 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2); 3192 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2); 3193 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0); 3194 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0); 3195 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0); 3196 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0); 3197 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0); 3198 break; 3199 case CHIP_ARCTURUS: 3200 /* This is not fatal. We only need the discovery 3201 * binary for sysfs. We don't need it for a 3202 * functional system. 3203 */ 3204 amdgpu_discovery_init(adev); 3205 arct_reg_base_init(adev); 3206 adev->sdma.num_instances = 8; 3207 adev->sdma.sdma_mask = 0xff; 3208 adev->vcn.num_vcn_inst = 2; 3209 adev->gmc.num_umc = 8; 3210 adev->gfx.xcc_mask = 1; 3211 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1); 3212 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1); 3213 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1); 3214 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1); 3215 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2); 3216 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2); 3217 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2); 3218 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2); 3219 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2); 3220 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2); 3221 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2); 3222 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2); 3223 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1); 3224 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1); 3225 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2); 3226 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4); 3227 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 3228 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3); 3229 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3); 3230 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1); 3231 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0); 3232 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0); 3233 break; 3234 case CHIP_ALDEBARAN: 3235 /* This is not fatal. We only need the discovery 3236 * binary for sysfs. We don't need it for a 3237 * functional system. 3238 */ 3239 amdgpu_discovery_init(adev); 3240 aldebaran_reg_base_init(adev); 3241 adev->sdma.num_instances = 5; 3242 adev->sdma.sdma_mask = 0x1f; 3243 adev->vcn.num_vcn_inst = 2; 3244 adev->gmc.num_umc = 4; 3245 adev->gfx.xcc_mask = 1; 3246 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2); 3247 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2); 3248 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0); 3249 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0); 3250 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0); 3251 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0); 3252 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0); 3253 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0); 3254 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0); 3255 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2); 3256 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4); 3257 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0); 3258 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2); 3259 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2); 3260 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2); 3261 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2); 3262 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2); 3263 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0); 3264 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0); 3265 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0); 3266 break; 3267 case CHIP_CYAN_SKILLFISH: 3268 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 3269 r = amdgpu_discovery_reg_base_init(adev); 3270 if (r) 3271 return -EINVAL; 3272 3273 amdgpu_discovery_harvest_ip(adev); 3274 amdgpu_discovery_get_gfx_info(adev); 3275 amdgpu_discovery_get_mall_info(adev); 3276 amdgpu_discovery_get_vcn_info(adev); 3277 } else { 3278 cyan_skillfish_reg_base_init(adev); 3279 adev->sdma.num_instances = 2; 3280 adev->sdma.sdma_mask = 3; 3281 adev->gfx.xcc_mask = 1; 3282 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(2, 0, 3); 3283 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(2, 0, 3); 3284 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(5, 0, 1); 3285 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(5, 0, 1); 3286 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(5, 0, 1); 3287 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(5, 0, 1); 3288 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 5, 0); 3289 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(2, 1, 1); 3290 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(8, 1, 1); 3291 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 8); 3292 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 8); 3293 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 1); 3294 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 8); 3295 adev->ip_versions[GC_HWIP][0] = IP_VERSION(10, 1, 3); 3296 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 0, 3); 3297 } 3298 break; 3299 default: 3300 r = amdgpu_discovery_reg_base_init(adev); 3301 if (r) { 3302 drm_err(&adev->ddev, "discovery failed: %d\n", r); 3303 return r; 3304 } 3305 3306 amdgpu_discovery_harvest_ip(adev); 3307 amdgpu_discovery_get_gfx_info(adev); 3308 amdgpu_discovery_get_mall_info(adev); 3309 amdgpu_discovery_get_vcn_info(adev); 3310 break; 3311 } 3312 3313 amdgpu_discovery_init_soc_config(adev); 3314 amdgpu_discovery_sysfs_init(adev); 3315 3316 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3317 case IP_VERSION(9, 0, 1): 3318 case IP_VERSION(9, 2, 1): 3319 case IP_VERSION(9, 4, 0): 3320 case IP_VERSION(9, 4, 1): 3321 case IP_VERSION(9, 4, 2): 3322 case IP_VERSION(9, 4, 3): 3323 case IP_VERSION(9, 4, 4): 3324 case IP_VERSION(9, 5, 0): 3325 adev->family = AMDGPU_FAMILY_AI; 3326 break; 3327 case IP_VERSION(9, 1, 0): 3328 case IP_VERSION(9, 2, 2): 3329 case IP_VERSION(9, 3, 0): 3330 adev->family = AMDGPU_FAMILY_RV; 3331 break; 3332 case IP_VERSION(10, 1, 10): 3333 case IP_VERSION(10, 1, 1): 3334 case IP_VERSION(10, 1, 2): 3335 case IP_VERSION(10, 1, 3): 3336 case IP_VERSION(10, 1, 4): 3337 case IP_VERSION(10, 3, 0): 3338 case IP_VERSION(10, 3, 2): 3339 case IP_VERSION(10, 3, 4): 3340 case IP_VERSION(10, 3, 5): 3341 adev->family = AMDGPU_FAMILY_NV; 3342 break; 3343 case IP_VERSION(10, 3, 1): 3344 adev->family = AMDGPU_FAMILY_VGH; 3345 adev->apu_flags |= AMD_APU_IS_VANGOGH; 3346 break; 3347 case IP_VERSION(10, 3, 3): 3348 adev->family = AMDGPU_FAMILY_YC; 3349 break; 3350 case IP_VERSION(10, 3, 6): 3351 adev->family = AMDGPU_FAMILY_GC_10_3_6; 3352 break; 3353 case IP_VERSION(10, 3, 7): 3354 adev->family = AMDGPU_FAMILY_GC_10_3_7; 3355 break; 3356 case IP_VERSION(11, 0, 0): 3357 case IP_VERSION(11, 0, 2): 3358 case IP_VERSION(11, 0, 3): 3359 adev->family = AMDGPU_FAMILY_GC_11_0_0; 3360 break; 3361 case IP_VERSION(11, 0, 1): 3362 case IP_VERSION(11, 0, 4): 3363 adev->family = AMDGPU_FAMILY_GC_11_0_1; 3364 break; 3365 case IP_VERSION(11, 5, 0): 3366 case IP_VERSION(11, 5, 1): 3367 case IP_VERSION(11, 5, 2): 3368 case IP_VERSION(11, 5, 3): 3369 case IP_VERSION(11, 5, 4): 3370 case IP_VERSION(11, 5, 6): 3371 adev->family = AMDGPU_FAMILY_GC_11_5_0; 3372 break; 3373 case IP_VERSION(11, 7, 0): 3374 case IP_VERSION(11, 7, 1): 3375 adev->family = AMDGPU_FAMILY_GC_11_5_4; 3376 break; 3377 case IP_VERSION(12, 0, 0): 3378 case IP_VERSION(12, 0, 1): 3379 case IP_VERSION(12, 1, 0): 3380 adev->family = AMDGPU_FAMILY_GC_12_0_0; 3381 break; 3382 default: 3383 return -EINVAL; 3384 } 3385 3386 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3387 case IP_VERSION(9, 1, 0): 3388 case IP_VERSION(9, 2, 2): 3389 case IP_VERSION(9, 3, 0): 3390 case IP_VERSION(10, 1, 3): 3391 case IP_VERSION(10, 1, 4): 3392 case IP_VERSION(10, 3, 1): 3393 case IP_VERSION(10, 3, 3): 3394 case IP_VERSION(10, 3, 6): 3395 case IP_VERSION(10, 3, 7): 3396 case IP_VERSION(11, 0, 1): 3397 case IP_VERSION(11, 0, 4): 3398 case IP_VERSION(11, 5, 0): 3399 case IP_VERSION(11, 5, 1): 3400 case IP_VERSION(11, 5, 2): 3401 case IP_VERSION(11, 5, 3): 3402 case IP_VERSION(11, 5, 4): 3403 case IP_VERSION(11, 5, 6): 3404 case IP_VERSION(11, 7, 0): 3405 case IP_VERSION(11, 7, 1): 3406 adev->flags |= AMD_IS_APU; 3407 break; 3408 default: 3409 break; 3410 } 3411 3412 /* set NBIO version */ 3413 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { 3414 case IP_VERSION(6, 1, 0): 3415 case IP_VERSION(6, 2, 0): 3416 adev->nbio.funcs = &nbio_v6_1_funcs; 3417 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; 3418 break; 3419 case IP_VERSION(7, 0, 0): 3420 case IP_VERSION(7, 0, 1): 3421 case IP_VERSION(2, 5, 0): 3422 adev->nbio.funcs = &nbio_v7_0_funcs; 3423 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; 3424 break; 3425 case IP_VERSION(7, 4, 0): 3426 case IP_VERSION(7, 4, 1): 3427 case IP_VERSION(7, 4, 4): 3428 adev->nbio.funcs = &nbio_v7_4_funcs; 3429 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; 3430 break; 3431 case IP_VERSION(7, 9, 0): 3432 case IP_VERSION(7, 9, 1): 3433 adev->nbio.funcs = &nbio_v7_9_funcs; 3434 adev->nbio.hdp_flush_reg = &nbio_v7_9_hdp_flush_reg; 3435 break; 3436 case IP_VERSION(7, 11, 0): 3437 case IP_VERSION(7, 11, 1): 3438 case IP_VERSION(7, 11, 2): 3439 case IP_VERSION(7, 11, 3): 3440 adev->nbio.funcs = &nbio_v7_11_funcs; 3441 adev->nbio.hdp_flush_reg = &nbio_v7_11_hdp_flush_reg; 3442 break; 3443 case IP_VERSION(7, 2, 0): 3444 case IP_VERSION(7, 2, 1): 3445 case IP_VERSION(7, 3, 0): 3446 case IP_VERSION(7, 5, 0): 3447 case IP_VERSION(7, 5, 1): 3448 adev->nbio.funcs = &nbio_v7_2_funcs; 3449 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; 3450 break; 3451 case IP_VERSION(2, 1, 1): 3452 case IP_VERSION(2, 3, 0): 3453 case IP_VERSION(2, 3, 1): 3454 case IP_VERSION(2, 3, 2): 3455 case IP_VERSION(3, 3, 0): 3456 case IP_VERSION(3, 3, 1): 3457 case IP_VERSION(3, 3, 2): 3458 case IP_VERSION(3, 3, 3): 3459 adev->nbio.funcs = &nbio_v2_3_funcs; 3460 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 3461 break; 3462 case IP_VERSION(4, 3, 0): 3463 case IP_VERSION(4, 3, 1): 3464 if (amdgpu_sriov_vf(adev)) 3465 adev->nbio.funcs = &nbio_v4_3_sriov_funcs; 3466 else 3467 adev->nbio.funcs = &nbio_v4_3_funcs; 3468 adev->nbio.hdp_flush_reg = &nbio_v4_3_hdp_flush_reg; 3469 break; 3470 case IP_VERSION(7, 7, 0): 3471 case IP_VERSION(7, 7, 1): 3472 adev->nbio.funcs = &nbio_v7_7_funcs; 3473 adev->nbio.hdp_flush_reg = &nbio_v7_7_hdp_flush_reg; 3474 break; 3475 case IP_VERSION(6, 3, 1): 3476 case IP_VERSION(7, 11, 4): 3477 case IP_VERSION(7, 11, 5): 3478 adev->nbio.funcs = &nbif_v6_3_1_funcs; 3479 adev->nbio.hdp_flush_reg = &nbif_v6_3_1_hdp_flush_reg; 3480 break; 3481 case IP_VERSION(6, 3, 2): 3482 adev->nbio.funcs = &nbio_v6_3_2_funcs; 3483 break; 3484 default: 3485 break; 3486 } 3487 3488 switch (amdgpu_ip_version(adev, HDP_HWIP, 0)) { 3489 case IP_VERSION(4, 0, 0): 3490 case IP_VERSION(4, 0, 1): 3491 case IP_VERSION(4, 1, 0): 3492 case IP_VERSION(4, 1, 1): 3493 case IP_VERSION(4, 1, 2): 3494 case IP_VERSION(4, 2, 0): 3495 case IP_VERSION(4, 2, 1): 3496 case IP_VERSION(4, 4, 0): 3497 case IP_VERSION(4, 4, 2): 3498 case IP_VERSION(4, 4, 5): 3499 adev->hdp.funcs = &hdp_v4_0_funcs; 3500 break; 3501 case IP_VERSION(5, 0, 0): 3502 case IP_VERSION(5, 0, 1): 3503 case IP_VERSION(5, 0, 2): 3504 case IP_VERSION(5, 0, 3): 3505 case IP_VERSION(5, 0, 4): 3506 case IP_VERSION(5, 2, 0): 3507 adev->hdp.funcs = &hdp_v5_0_funcs; 3508 break; 3509 case IP_VERSION(5, 2, 1): 3510 adev->hdp.funcs = &hdp_v5_2_funcs; 3511 break; 3512 case IP_VERSION(6, 0, 0): 3513 case IP_VERSION(6, 0, 1): 3514 case IP_VERSION(6, 1, 0): 3515 case IP_VERSION(6, 1, 1): 3516 case IP_VERSION(6, 4, 0): 3517 adev->hdp.funcs = &hdp_v6_0_funcs; 3518 break; 3519 case IP_VERSION(7, 0, 0): 3520 adev->hdp.funcs = &hdp_v7_0_funcs; 3521 break; 3522 default: 3523 break; 3524 } 3525 3526 switch (amdgpu_ip_version(adev, DF_HWIP, 0)) { 3527 case IP_VERSION(3, 6, 0): 3528 case IP_VERSION(3, 6, 1): 3529 case IP_VERSION(3, 6, 2): 3530 adev->df.funcs = &df_v3_6_funcs; 3531 break; 3532 case IP_VERSION(2, 1, 0): 3533 case IP_VERSION(2, 1, 1): 3534 case IP_VERSION(2, 5, 0): 3535 case IP_VERSION(3, 5, 1): 3536 case IP_VERSION(3, 5, 2): 3537 adev->df.funcs = &df_v1_7_funcs; 3538 break; 3539 case IP_VERSION(4, 3, 0): 3540 adev->df.funcs = &df_v4_3_funcs; 3541 break; 3542 case IP_VERSION(4, 6, 2): 3543 adev->df.funcs = &df_v4_6_2_funcs; 3544 break; 3545 case IP_VERSION(4, 15, 0): 3546 case IP_VERSION(4, 15, 1): 3547 adev->df.funcs = &df_v4_15_funcs; 3548 break; 3549 default: 3550 break; 3551 } 3552 3553 switch (amdgpu_ip_version(adev, SMUIO_HWIP, 0)) { 3554 case IP_VERSION(9, 0, 0): 3555 case IP_VERSION(9, 0, 1): 3556 case IP_VERSION(10, 0, 0): 3557 case IP_VERSION(10, 0, 1): 3558 case IP_VERSION(10, 0, 2): 3559 adev->smuio.funcs = &smuio_v9_0_funcs; 3560 break; 3561 case IP_VERSION(11, 0, 0): 3562 case IP_VERSION(11, 0, 2): 3563 case IP_VERSION(11, 0, 3): 3564 case IP_VERSION(11, 0, 4): 3565 case IP_VERSION(11, 0, 7): 3566 case IP_VERSION(11, 0, 8): 3567 adev->smuio.funcs = &smuio_v11_0_funcs; 3568 break; 3569 case IP_VERSION(11, 0, 6): 3570 case IP_VERSION(11, 0, 10): 3571 case IP_VERSION(11, 0, 11): 3572 case IP_VERSION(11, 5, 0): 3573 case IP_VERSION(11, 5, 2): 3574 case IP_VERSION(13, 0, 1): 3575 case IP_VERSION(13, 0, 9): 3576 case IP_VERSION(13, 0, 10): 3577 adev->smuio.funcs = &smuio_v11_0_6_funcs; 3578 break; 3579 case IP_VERSION(13, 0, 2): 3580 adev->smuio.funcs = &smuio_v13_0_funcs; 3581 break; 3582 case IP_VERSION(13, 0, 3): 3583 case IP_VERSION(13, 0, 11): 3584 adev->smuio.funcs = &smuio_v13_0_3_funcs; 3585 if (adev->smuio.funcs->get_pkg_type(adev) == AMDGPU_PKG_TYPE_APU) { 3586 adev->flags |= AMD_IS_APU; 3587 } 3588 break; 3589 case IP_VERSION(13, 0, 6): 3590 case IP_VERSION(13, 0, 8): 3591 case IP_VERSION(14, 0, 0): 3592 case IP_VERSION(14, 0, 1): 3593 adev->smuio.funcs = &smuio_v13_0_6_funcs; 3594 break; 3595 case IP_VERSION(14, 0, 2): 3596 adev->smuio.funcs = &smuio_v14_0_2_funcs; 3597 break; 3598 case IP_VERSION(15, 0, 0): 3599 case IP_VERSION(15, 0, 5): 3600 adev->smuio.funcs = &smuio_v15_0_0_funcs; 3601 break; 3602 case IP_VERSION(15, 0, 8): 3603 adev->smuio.funcs = &smuio_v15_0_8_funcs; 3604 break; 3605 default: 3606 break; 3607 } 3608 3609 switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) { 3610 case IP_VERSION(6, 0, 0): 3611 case IP_VERSION(6, 0, 1): 3612 case IP_VERSION(6, 0, 2): 3613 case IP_VERSION(6, 0, 3): 3614 adev->lsdma.funcs = &lsdma_v6_0_funcs; 3615 break; 3616 case IP_VERSION(7, 0, 0): 3617 case IP_VERSION(7, 0, 1): 3618 adev->lsdma.funcs = &lsdma_v7_0_funcs; 3619 break; 3620 case IP_VERSION(7, 1, 0): 3621 adev->lsdma.funcs = &lsdma_v7_1_funcs; 3622 break; 3623 default: 3624 break; 3625 } 3626 3627 r = amdgpu_discovery_set_common_ip_blocks(adev); 3628 if (r) 3629 return r; 3630 3631 r = amdgpu_discovery_set_gmc_ip_blocks(adev); 3632 if (r) 3633 return r; 3634 3635 /* For SR-IOV, PSP needs to be initialized before IH */ 3636 if (amdgpu_sriov_vf(adev)) { 3637 r = amdgpu_discovery_set_psp_ip_blocks(adev); 3638 if (r) 3639 return r; 3640 r = amdgpu_discovery_set_ih_ip_blocks(adev); 3641 if (r) 3642 return r; 3643 } else { 3644 r = amdgpu_discovery_set_ih_ip_blocks(adev); 3645 if (r) 3646 return r; 3647 3648 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 3649 r = amdgpu_discovery_set_psp_ip_blocks(adev); 3650 if (r) 3651 return r; 3652 } 3653 } 3654 3655 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 3656 r = amdgpu_discovery_set_smu_ip_blocks(adev); 3657 if (r) 3658 return r; 3659 } 3660 3661 r = amdgpu_discovery_set_display_ip_blocks(adev); 3662 if (r) 3663 return r; 3664 3665 r = amdgpu_discovery_set_gc_ip_blocks(adev); 3666 if (r) 3667 return r; 3668 3669 r = amdgpu_discovery_set_sdma_ip_blocks(adev); 3670 if (r) 3671 return r; 3672 3673 r = amdgpu_discovery_set_ras_ip_blocks(adev); 3674 if (r) 3675 return r; 3676 3677 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 3678 !amdgpu_sriov_vf(adev) && 3679 amdgpu_dpm == 1) || 3680 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && 3681 amdgpu_dpm == 1)) { 3682 r = amdgpu_discovery_set_smu_ip_blocks(adev); 3683 if (r) 3684 return r; 3685 } 3686 3687 r = amdgpu_discovery_set_mm_ip_blocks(adev); 3688 if (r) 3689 return r; 3690 3691 r = amdgpu_discovery_set_mes_ip_blocks(adev); 3692 if (r) 3693 return r; 3694 3695 r = amdgpu_discovery_set_vpe_ip_blocks(adev); 3696 if (r) 3697 return r; 3698 3699 r = amdgpu_discovery_set_umsch_mm_ip_blocks(adev); 3700 if (r) 3701 return r; 3702 3703 r = amdgpu_discovery_set_isp_ip_blocks(adev); 3704 if (r) 3705 return r; 3706 return 0; 3707 } 3708 3709 int amdgpu_discovery_get_gc_major_minor_version(struct amdgpu_device *adev, 3710 uint16_t *major, uint16_t *minor) 3711 { 3712 uint8_t *discovery_bin = adev->discovery.bin; 3713 struct table_info *info; 3714 union gc_info *gc_info; 3715 u16 offset; 3716 3717 if (!discovery_bin) 3718 return -EINVAL; 3719 if (amdgpu_discovery_get_table_info(adev, &info, GC)) 3720 return -EINVAL; 3721 3722 offset = le16_to_cpu(info->offset); 3723 if (!offset) 3724 return -EINVAL; 3725 3726 gc_info = (union gc_info *)(discovery_bin + offset); 3727 3728 if (major) 3729 *major = le16_to_cpu(gc_info->v1.header.version_major); 3730 if (minor) 3731 *minor = le16_to_cpu(gc_info->v1.header.version_minor); 3732 return 0; 3733 } 3734